[mirror_ubuntu-artful-kernel.git] / arch / xtensa / kernel / setup.c

/*
 * arch/xtensa/kernel/setup.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 2001 - 2005  Tensilica Inc.
 *
 * Chris Zankel	<chris@zankel.net>
 * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
 * Kevin Chea
 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/screen_info.h>
#include <linux/bootmem.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_fdt.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
# include <linux/console.h>
#endif

#ifdef CONFIG_RTC
# include <linux/timex.h>
#endif

#ifdef CONFIG_PROC_FS
# include <linux/seq_file.h>
#endif

#include <asm/bootparam.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/timex.h>
#include <asm/platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/param.h>
#include <asm/traps.h>
#include <asm/smp.h>
#include <asm/sysmem.h>

#include <platform/hardware.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
#endif

#ifdef CONFIG_BLK_DEV_FD
extern struct fd_ops no_fd_ops;
struct fd_ops *fd_ops;
#endif

extern struct rtc_ops no_rtc_ops;
struct rtc_ops *rtc_ops;

#ifdef CONFIG_BLK_DEV_INITRD
extern unsigned long initrd_start;
extern unsigned long initrd_end;
int initrd_is_mapped = 0;
extern int initrd_below_start_ok;
#endif

#ifdef CONFIG_OF
void *dtb_start = __dtb_start;
#endif

unsigned char aux_device_present;
extern unsigned long loops_per_jiffy;

/* Command line specified as configuration option. */

static char __initdata command_line[COMMAND_LINE_SIZE];

#ifdef CONFIG_CMDLINE_BOOL
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
#endif

/*
 * Boot parameter parsing.
 *
 * The Xtensa port uses a list of variable-sized tags to pass data to
 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
 * to be recognised. The list is terminated with a zero-sized
 * BP_TAG_LAST tag.
 */

typedef struct tagtable {
	u32 tag;
	int (*parse)(const bp_tag_t*);
} tagtable_t;

#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
	__attribute__((used, section(".taglist"))) = { tag, fn }

/* parse current tag */

static int __init parse_tag_mem(const bp_tag_t *tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
		return -1;

	return add_sysmem_bank(mi->start, mi->end);
}

__tagtable(BP_TAG_MEMORY, parse_tag_mem);

#ifdef CONFIG_BLK_DEV_INITRD

static int __init parse_tag_initrd(const bp_tag_t* tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	initrd_start = (unsigned long)__va(mi->start);
	initrd_end = (unsigned long)__va(mi->end);

	return 0;
}

__tagtable(BP_TAG_INITRD, parse_tag_initrd);

#ifdef CONFIG_OF

static int __init parse_tag_fdt(const bp_tag_t *tag)
{
	dtb_start = __va(tag->data[0]);
	return 0;
}

__tagtable(BP_TAG_FDT, parse_tag_fdt);

#endif /* CONFIG_OF */

#endif /* CONFIG_BLK_DEV_INITRD */

static int __init parse_tag_cmdline(const bp_tag_t* tag)
{
	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
	return 0;
}

__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);

static int __init parse_bootparam(const bp_tag_t* tag)
{
	extern tagtable_t __tagtable_begin, __tagtable_end;
	tagtable_t *t;

	/* Boot parameters must start with a BP_TAG_FIRST tag. */

	if (tag->id != BP_TAG_FIRST) {
		printk(KERN_WARNING "Invalid boot parameters!\n");
		return 0;
	}

	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);

	/* Parse all tags. */

	while (tag != NULL && tag->id != BP_TAG_LAST) {
	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
			if (tag->id == t->tag) {
				t->parse(tag);
				break;
			}
		}
		if (t == &__tagtable_end)
			printk(KERN_WARNING "Ignoring tag "
			       "0x%08x\n", tag->id);
		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	}

	return 0;
}

#ifdef CONFIG_OF
bool __initdata dt_memory_scan = false;

#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
EXPORT_SYMBOL(xtensa_kio_paddr);

static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	const __be32 *ranges;
	int len;

	if (depth > 1)
		return 0;

	if (!of_flat_dt_is_compatible(node, "simple-bus"))
		return 0;

	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	if (!ranges)
		return 1;
	if (len == 0)
		return 1;

	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	/* round down to nearest 256MB boundary */
	xtensa_kio_paddr &= 0xf0000000;

	return 1;
}
#else
static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	return 1;
}
#endif

void __init early_init_dt_add_memory_arch(u64 base, u64 size)
{
	if (!dt_memory_scan)
		return;

	size &= PAGE_MASK;
	add_sysmem_bank(base, base + size);
}

void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
{
	return __alloc_bootmem(size, align, 0);
}

void __init early_init_devtree(void *params)
{
	if (sysmem.nr_banks == 0)
		dt_memory_scan = true;

	early_init_dt_scan(params);
	of_scan_flat_dt(xtensa_dt_io_area, NULL);

	if (!command_line[0])
		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
}

#endif /* CONFIG_OF */

/*
 * Initialize architecture. (Early stage)
 */

void __init init_arch(bp_tag_t *bp_start)
{
	/* Parse boot parameters */

	if (bp_start)
		parse_bootparam(bp_start);

#ifdef CONFIG_OF
	early_init_devtree(dtb_start);
#endif

	if (sysmem.nr_banks == 0) {
		add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
				PLATFORM_DEFAULT_MEM_START +
				PLATFORM_DEFAULT_MEM_SIZE);
	}

#ifdef CONFIG_CMDLINE_BOOL
	if (!command_line[0])
		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
#endif

	/* Early hook for platforms */

	platform_init(bp_start);

	/* Initialize MMU. */

	init_mmu();
}

/*
 * Initialize system. Setup memory and reserve regions.
 */

extern char _end;
extern char _stext;
extern char _WindowVectors_text_start;
extern char _WindowVectors_text_end;
extern char _DebugInterruptVector_literal_start;
extern char _DebugInterruptVector_text_end;
extern char _KernelExceptionVector_literal_start;
extern char _KernelExceptionVector_text_end;
extern char _UserExceptionVector_literal_start;
extern char _UserExceptionVector_text_end;
extern char _DoubleExceptionVector_literal_start;
extern char _DoubleExceptionVector_text_end;
#if XCHAL_EXCM_LEVEL >= 2
extern char _Level2InterruptVector_text_start;
extern char _Level2InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 3
extern char _Level3InterruptVector_text_start;
extern char _Level3InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 4
extern char _Level4InterruptVector_text_start;
extern char _Level4InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 5
extern char _Level5InterruptVector_text_start;
extern char _Level5InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 6
extern char _Level6InterruptVector_text_start;
extern char _Level6InterruptVector_text_end;
#endif
#ifdef CONFIG_SMP
extern char _SecondaryResetVector_text_start;
extern char _SecondaryResetVector_text_end;
#endif


#ifdef CONFIG_S32C1I_SELFTEST
#if XCHAL_HAVE_S32C1I

static int __initdata rcw_word, rcw_probe_pc, rcw_exc;

/*
 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
 *
 * If *v == cmp, set *v = set.  Return previous *v.
 */
static inline int probed_compare_swap(int *v, int cmp, int set)
{
	int tmp;

	__asm__ __volatile__(
			"	movi	%1, 1f\n"
			"	s32i	%1, %4, 0\n"
			"	wsr	%2, scompare1\n"
			"1:	s32c1i	%0, %3, 0\n"
			: "=a" (set), "=&a" (tmp)
			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
			: "memory"
			);
	return set;
}

/* Handle probed exception */

static void __init do_probed_exception(struct pt_regs *regs,
		unsigned long exccause)
{
	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
		regs->pc += 3;		/* skip the s32c1i instruction */
		rcw_exc = exccause;
	} else {
		do_unhandled(regs, exccause);
	}
}

/* Simple test of S32C1I (soc bringup assist) */

static int __init check_s32c1i(void)
{
	int n, cause1, cause2;
	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */

	rcw_probe_pc = 0;
	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
			do_probed_exception);
	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
			do_probed_exception);
	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
			do_probed_exception);

	/* First try an S32C1I that does not store: */
	rcw_exc = 0;
	rcw_word = 1;
	n = probed_compare_swap(&rcw_word, 0, 2);
	cause1 = rcw_exc;

	/* took exception? */
	if (cause1 != 0) {
		/* unclean exception? */
		if (n != 2 || rcw_word != 1)
			panic("S32C1I exception error");
	} else if (rcw_word != 1 || n != 1) {
		panic("S32C1I compare error");
	}

	/* Then an S32C1I that stores: */
	rcw_exc = 0;
	rcw_word = 0x1234567;
	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
	cause2 = rcw_exc;

	if (cause2 != 0) {
		/* unclean exception? */
		if (n != 0xabcde || rcw_word != 0x1234567)
			panic("S32C1I exception error (b)");
	} else if (rcw_word != 0xabcde || n != 0x1234567) {
		panic("S32C1I store error");
	}

	/* Verify consistency of exceptions: */
	if (cause1 || cause2) {
		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
		/* If emulation of S32C1I upon bus error gets implemented,
		   we can get rid of this panic for single core (not SMP) */
		panic("S32C1I exceptions not currently supported");
	}
	if (cause1 != cause2)
		panic("inconsistent S32C1I exceptions");

	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
	return 0;
}

#else /* XCHAL_HAVE_S32C1I */

/* This condition should not occur with a commercially deployed processor.
   Display reminder for early engr test or demo chips / FPGA bitstreams */
static int __init check_s32c1i(void)
{
	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
	return 0;
}

#endif /* XCHAL_HAVE_S32C1I */
early_initcall(check_s32c1i);
#endif /* CONFIG_S32C1I_SELFTEST */


void __init setup_arch(char **cmdline_p)
{
	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
	*cmdline_p = command_line;

	/* Reserve some memory regions */

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start < initrd_end) {
		initrd_is_mapped = mem_reserve(__pa(initrd_start),
					       __pa(initrd_end), 0) == 0;
		initrd_below_start_ok = 1;
	} else {
		initrd_start = 0;
	}
#endif

	mem_reserve(__pa(&_stext),__pa(&_end), 1);

	mem_reserve(__pa(&_WindowVectors_text_start),
		    __pa(&_WindowVectors_text_end), 0);

	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
		    __pa(&_DebugInterruptVector_text_end), 0);

	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
		    __pa(&_KernelExceptionVector_text_end), 0);

	mem_reserve(__pa(&_UserExceptionVector_literal_start),
		    __pa(&_UserExceptionVector_text_end), 0);

	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
		    __pa(&_DoubleExceptionVector_text_end), 0);

#if XCHAL_EXCM_LEVEL >= 2
	mem_reserve(__pa(&_Level2InterruptVector_text_start),
		    __pa(&_Level2InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 3
	mem_reserve(__pa(&_Level3InterruptVector_text_start),
		    __pa(&_Level3InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 4
	mem_reserve(__pa(&_Level4InterruptVector_text_start),
		    __pa(&_Level4InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 5
	mem_reserve(__pa(&_Level5InterruptVector_text_start),
		    __pa(&_Level5InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 6
	mem_reserve(__pa(&_Level6InterruptVector_text_start),
		    __pa(&_Level6InterruptVector_text_end), 0);
#endif

#ifdef CONFIG_SMP
	mem_reserve(__pa(&_SecondaryResetVector_text_start),
		    __pa(&_SecondaryResetVector_text_end), 0);
#endif
	parse_early_param();
	bootmem_init();

	unflatten_and_copy_device_tree();

	platform_setup(cmdline_p);

#ifdef CONFIG_SMP
	smp_init_cpus();
#endif

	paging_init();
	zones_init();

#ifdef CONFIG_VT
# if defined(CONFIG_VGA_CONSOLE)
	conswitchp = &vga_con;
# elif defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
# endif
#endif

#ifdef CONFIG_PCI
	platform_pcibios_init();
#endif
}

static DEFINE_PER_CPU(struct cpu, cpu_data);

static int __init topology_init(void)
{
	int i;

	for_each_possible_cpu(i) {
		struct cpu *cpu = &per_cpu(cpu_data, i);
		cpu->hotpluggable = !!i;
		register_cpu(cpu, i);
	}

	return 0;
}
subsys_initcall(topology_init);

void machine_restart(char * cmd)
{
	platform_restart();
}

void machine_halt(void)
{
	platform_halt();
	while (1);
}

void machine_power_off(void)
{
	platform_power_off();
	while (1);
}
#ifdef CONFIG_PROC_FS

/*
 * Display some core information through /proc/cpuinfo.
 */

static int
c_show(struct seq_file *f, void *slot)
{
	/* high-level stuff */
	seq_printf(f, "CPU count\t: %u\n"
		      "CPU list\t: %*pbl\n"
		      "vendor_id\t: Tensilica\n"
		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
		      "core ID\t\t: " XCHAL_CORE_ID "\n"
		      "build ID\t: 0x%x\n"
		      "byte order\t: %s\n"
		      "cpu MHz\t\t: %lu.%02lu\n"
		      "bogomips\t: %lu.%02lu\n",
		      num_online_cpus(),
		      cpumask_pr_args(cpu_online_mask),
		      XCHAL_BUILD_UNIQUE_ID,
		      XCHAL_HAVE_BE ?  "big" : "little",
		      ccount_freq/1000000,
		      (ccount_freq/10000) % 100,
		      loops_per_jiffy/(500000/HZ),
		      (loops_per_jiffy/(5000/HZ)) % 100);

	seq_printf(f,"flags\t\t: "
#if XCHAL_HAVE_NMI
		     "nmi "
#endif
#if XCHAL_HAVE_DEBUG
		     "debug "
# if XCHAL_HAVE_OCD
		     "ocd "
# endif
#endif
#if XCHAL_HAVE_DENSITY
	    	     "density "
#endif
#if XCHAL_HAVE_BOOLEANS
		     "boolean "
#endif
#if XCHAL_HAVE_LOOPS
		     "loop "
#endif
#if XCHAL_HAVE_NSA
		     "nsa "
#endif
#if XCHAL_HAVE_MINMAX
		     "minmax "
#endif
#if XCHAL_HAVE_SEXT
		     "sext "
#endif
#if XCHAL_HAVE_CLAMPS
		     "clamps "
#endif
#if XCHAL_HAVE_MAC16
		     "mac16 "
#endif
#if XCHAL_HAVE_MUL16
		     "mul16 "
#endif
#if XCHAL_HAVE_MUL32
		     "mul32 "
#endif
#if XCHAL_HAVE_MUL32_HIGH
		     "mul32h "
#endif
#if XCHAL_HAVE_FP
		     "fpu "
#endif
#if XCHAL_HAVE_S32C1I
		     "s32c1i "
#endif
		     "\n");

	/* Registers. */
	seq_printf(f,"physical aregs\t: %d\n"
		     "misc regs\t: %d\n"
		     "ibreak\t\t: %d\n"
		     "dbreak\t\t: %d\n",
		     XCHAL_NUM_AREGS,
		     XCHAL_NUM_MISC_REGS,
		     XCHAL_NUM_IBREAK,
		     XCHAL_NUM_DBREAK);


	/* Interrupt. */
	seq_printf(f,"num ints\t: %d\n"
		     "ext ints\t: %d\n"
		     "int levels\t: %d\n"
		     "timers\t\t: %d\n"
		     "debug level\t: %d\n",
		     XCHAL_NUM_INTERRUPTS,
		     XCHAL_NUM_EXTINTERRUPTS,
		     XCHAL_NUM_INTLEVELS,
		     XCHAL_NUM_TIMERS,
		     XCHAL_DEBUGLEVEL);

	/* Cache */
	seq_printf(f,"icache line size: %d\n"
		     "icache ways\t: %d\n"
		     "icache size\t: %d\n"
		     "icache flags\t: "
#if XCHAL_ICACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n"
		     "dcache line size: %d\n"
		     "dcache ways\t: %d\n"
		     "dcache size\t: %d\n"
		     "dcache flags\t: "
#if XCHAL_DCACHE_IS_WRITEBACK
		     "writeback "
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n",
		     XCHAL_ICACHE_LINESIZE,
		     XCHAL_ICACHE_WAYS,
		     XCHAL_ICACHE_SIZE,
		     XCHAL_DCACHE_LINESIZE,
		     XCHAL_DCACHE_WAYS,
		     XCHAL_DCACHE_SIZE);

	return 0;
}

/*
 * We show only CPU #0 info.
 */
static void *
c_start(struct seq_file *f, loff_t *pos)
{
	return (*pos == 0) ? (void *)1 : NULL;
}

static void *
c_next(struct seq_file *f, void *v, loff_t *pos)
{
	return NULL;
}

static void
c_stop(struct seq_file *f, void *v)
{
}

const struct seq_operations cpuinfo_op =
{
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show,
};

#endif /* CONFIG_PROC_FS */
Commit	Line	Data
5a0015d6	1	/*
f30c2269	2	* arch/xtensa/kernel/setup.c
5a0015d6 CZ	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1995 Linus Torvalds
	9	* Copyright (C) 2001 - 2005 Tensilica Inc.
	10	*
	11	* Chris Zankel <chris@zankel.net>
	12	* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
	13	* Kevin Chea
	14	* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
	15	*/
	16
5a0015d6 CZ	17	#include <linux/errno.h>
5a0015d6 CZ	18	#include <linux/init.h>
27ac792c	19	#include <linux/mm.h>
5a0015d6	20	#include <linux/proc_fs.h>
894673ee	21	#include <linux/screen_info.h>
5a0015d6 CZ	22	#include <linux/bootmem.h>
5a0015d6 CZ	23	#include <linux/kernel.h>
f615136c MF	24	#include <linux/percpu.h>
f615136c MF	25	#include <linux/cpu.h>
d02014b2	26	#include <linux/of.h>
da844a81	27	#include <linux/of_fdt.h>
da844a81	28
5a0015d6 CZ	29	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
	30	# include <linux/console.h>
	31	#endif
	32
	33	#ifdef CONFIG_RTC
	34	# include <linux/timex.h>
	35	#endif
	36
	37	#ifdef CONFIG_PROC_FS
	38	# include <linux/seq_file.h>
	39	#endif
	40
5a0015d6	41	#include <asm/bootparam.h>
c8f3a7dc	42	#include <asm/mmu_context.h>
5a0015d6 CZ	43	#include <asm/pgtable.h>
	44	#include <asm/processor.h>
	45	#include <asm/timex.h>
	46	#include <asm/platform.h>
	47	#include <asm/page.h>
	48	#include <asm/setup.h>
de4f6e5b	49	#include <asm/param.h>
00273125	50	#include <asm/traps.h>
f615136c	51	#include <asm/smp.h>
9ba067f9	52	#include <asm/sysmem.h>
5a0015d6	53
5a891ed5 AD	54	#include <platform/hardware.h>
5a891ed5 AD	55
5a0015d6 CZ	56	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
	57	struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
	58	#endif
	59
	60	#ifdef CONFIG_BLK_DEV_FD
	61	extern struct fd_ops no_fd_ops;
	62	struct fd_ops *fd_ops;
	63	#endif
	64
5a0015d6 CZ	65	extern struct rtc_ops no_rtc_ops;
	66	struct rtc_ops *rtc_ops;
	67
5a0015d6	68	#ifdef CONFIG_BLK_DEV_INITRD
29eb45a9 RH	69	extern unsigned long initrd_start;
29eb45a9 RH	70	extern unsigned long initrd_end;
5a0015d6 CZ	71	int initrd_is_mapped = 0;
	72	extern int initrd_below_start_ok;
	73	#endif
	74
da844a81	75	#ifdef CONFIG_OF
da844a81 MF	76	void *dtb_start = __dtb_start;
	77	#endif
	78
5a0015d6 CZ	79	unsigned char aux_device_present;
	80	extern unsigned long loops_per_jiffy;
	81
	82	/* Command line specified as configuration option. */
	83
d3e9ccea	84	static char __initdata command_line[COMMAND_LINE_SIZE];
5a0015d6 CZ	85
	86	#ifdef CONFIG_CMDLINE_BOOL
	87	static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
	88	#endif
	89
5a0015d6 CZ	90	/*
	91	* Boot parameter parsing.
	92	*
	93	* The Xtensa port uses a list of variable-sized tags to pass data to
	94	* the kernel. The first tag must be a BP_TAG_FIRST tag for the list
	95	* to be recognised. The list is terminated with a zero-sized
	96	* BP_TAG_LAST tag.
	97	*/
	98
	99	typedef struct tagtable {
	100	u32 tag;
	101	int (parse)(const bp_tag_t);
	102	} tagtable_t;
	103
	104	#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
f4349b6e	105	__attribute__((used, section(".taglist"))) = { tag, fn }
5a0015d6 CZ	106
	107	/* parse current tag */
	108
da844a81 MF	109	static int __init parse_tag_mem(const bp_tag_t *tag)
da844a81 MF	110	{
9ba067f9	111	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
da844a81 MF	112
	113	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
	114	return -1;
	115
9ba067f9	116	return add_sysmem_bank(mi->start, mi->end);
da844a81 MF	117	}
da844a81 MF	118
5a0015d6 CZ	119	__tagtable(BP_TAG_MEMORY, parse_tag_mem);
	120
	121	#ifdef CONFIG_BLK_DEV_INITRD
	122
	123	static int __init parse_tag_initrd(const bp_tag_t* tag)
	124	{
9ba067f9 MF	125	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
9ba067f9 MF	126
29eb45a9 RH	127	initrd_start = (unsigned long)__va(mi->start);
29eb45a9 RH	128	initrd_end = (unsigned long)__va(mi->end);
5a0015d6 CZ	129
	130	return 0;
	131	}
	132
	133	__tagtable(BP_TAG_INITRD, parse_tag_initrd);
	134
da844a81 MF	135	#ifdef CONFIG_OF
	136
	137	static int __init parse_tag_fdt(const bp_tag_t *tag)
	138	{
c5a771d0	139	dtb_start = __va(tag->data[0]);
da844a81 MF	140	return 0;
	141	}
	142
	143	__tagtable(BP_TAG_FDT, parse_tag_fdt);
	144
da844a81 MF	145	#endif /* CONFIG_OF */
da844a81 MF	146
5a0015d6 CZ	147	#endif /* CONFIG_BLK_DEV_INITRD */
	148
	149	static int __init parse_tag_cmdline(const bp_tag_t* tag)
	150	{
da844a81	151	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
5a0015d6 CZ	152	return 0;
	153	}
	154
	155	__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
	156
	157	static int __init parse_bootparam(const bp_tag_t* tag)
	158	{
	159	extern tagtable_t __tagtable_begin, __tagtable_end;
	160	tagtable_t *t;
	161
	162	/* Boot parameters must start with a BP_TAG_FIRST tag. */
	163
	164	if (tag->id != BP_TAG_FIRST) {
	165	printk(KERN_WARNING "Invalid boot parameters!\n");
	166	return 0;
	167	}
	168
	169	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
	170
	171	/* Parse all tags. */
	172
	173	while (tag != NULL && tag->id != BP_TAG_LAST) {
	174	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
	175	if (tag->id == t->tag) {
	176	t->parse(tag);
	177	break;
	178	}
	179	}
	180	if (t == &__tagtable_end)
	181	printk(KERN_WARNING "Ignoring tag "
	182	"0x%08x\n", tag->id);
	183	tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	184	}
	185
	186	return 0;
	187	}
	188
da844a81	189	#ifdef CONFIG_OF
7745fc1f	190	bool __initdata dt_memory_scan = false;
da844a81	191
260c64bb	192	#if !XCHAL_HAVE_PTP_MMU \|\| XCHAL_HAVE_SPANNING_WAY
6cb97111 BS	193	unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
	194	EXPORT_SYMBOL(xtensa_kio_paddr);
	195
	196	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	197	int depth, void *data)
	198	{
	199	const __be32 *ranges;
9d0c4dfe	200	int len;
6cb97111 BS	201
	202	if (depth > 1)
	203	return 0;
	204
	205	if (!of_flat_dt_is_compatible(node, "simple-bus"))
	206	return 0;
	207
	208	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	209	if (!ranges)
	210	return 1;
	211	if (len == 0)
	212	return 1;
	213
	214	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	215	/* round down to nearest 256MB boundary */
	216	xtensa_kio_paddr &= 0xf0000000;
	217
	218	return 1;
	219	}
	220	#else
	221	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	222	int depth, void *data)
	223	{
	224	return 1;
	225	}
	226	#endif
	227
da844a81 MF	228	void __init early_init_dt_add_memory_arch(u64 base, u64 size)
da844a81 MF	229	{
7745fc1f RH	230	if (!dt_memory_scan)
	231	return;
	232
da844a81	233	size &= PAGE_MASK;
9ba067f9	234	add_sysmem_bank(base, base + size);
da844a81 MF	235	}
	236
	237	void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
	238	{
	239	return __alloc_bootmem(size, align, 0);
	240	}
	241
	242	void __init early_init_devtree(void *params)
	243	{
7745fc1f RH	244	if (sysmem.nr_banks == 0)
7745fc1f RH	245	dt_memory_scan = true;
da844a81	246
7745fc1f	247	early_init_dt_scan(params);
6cb97111	248	of_scan_flat_dt(xtensa_dt_io_area, NULL);
da844a81	249
7745fc1f RH	250	if (!command_line[0])
7745fc1f RH	251	strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
da844a81 MF	252	}
da844a81 MF	253
da844a81 MF	254	#endif /* CONFIG_OF */
da844a81 MF	255
5a0015d6 CZ	256	/*
	257	* Initialize architecture. (Early stage)
	258	*/
	259
	260	void __init init_arch(bp_tag_t *bp_start)
	261	{
5a0015d6 CZ	262	/* Parse boot parameters */
5a0015d6 CZ	263
c4c4594b	264	if (bp_start)
da844a81 MF	265	parse_bootparam(bp_start);
	266
	267	#ifdef CONFIG_OF
	268	early_init_devtree(dtb_start);
	269	#endif
5a0015d6 CZ	270
5a0015d6 CZ	271	if (sysmem.nr_banks == 0) {
9ba067f9 MF	272	add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
	273	PLATFORM_DEFAULT_MEM_START +
	274	PLATFORM_DEFAULT_MEM_SIZE);
5a0015d6 CZ	275	}
5a0015d6 CZ	276
da844a81 MF	277	#ifdef CONFIG_CMDLINE_BOOL
	278	if (!command_line[0])
	279	strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
	280	#endif
	281
5a0015d6 CZ	282	/* Early hook for platforms */
	283
	284	platform_init(bp_start);
	285
	286	/* Initialize MMU. */
	287
	288	init_mmu();
	289	}
	290
	291	/*
	292	* Initialize system. Setup memory and reserve regions.
	293	*/
	294
	295	extern char _end;
	296	extern char _stext;
	297	extern char _WindowVectors_text_start;
	298	extern char _WindowVectors_text_end;
	299	extern char _DebugInterruptVector_literal_start;
	300	extern char _DebugInterruptVector_text_end;
	301	extern char _KernelExceptionVector_literal_start;
	302	extern char _KernelExceptionVector_text_end;
	303	extern char _UserExceptionVector_literal_start;
	304	extern char _UserExceptionVector_text_end;
	305	extern char _DoubleExceptionVector_literal_start;
	306	extern char _DoubleExceptionVector_text_end;
2d1c645c MG	307	#if XCHAL_EXCM_LEVEL >= 2
	308	extern char _Level2InterruptVector_text_start;
	309	extern char _Level2InterruptVector_text_end;
	310	#endif
	311	#if XCHAL_EXCM_LEVEL >= 3
	312	extern char _Level3InterruptVector_text_start;
	313	extern char _Level3InterruptVector_text_end;
	314	#endif
	315	#if XCHAL_EXCM_LEVEL >= 4
	316	extern char _Level4InterruptVector_text_start;
	317	extern char _Level4InterruptVector_text_end;
	318	#endif
	319	#if XCHAL_EXCM_LEVEL >= 5
	320	extern char _Level5InterruptVector_text_start;
	321	extern char _Level5InterruptVector_text_end;
	322	#endif
	323	#if XCHAL_EXCM_LEVEL >= 6
	324	extern char _Level6InterruptVector_text_start;
	325	extern char _Level6InterruptVector_text_end;
	326	#endif
ab45fb14 MF	327	#ifdef CONFIG_SMP
	328	extern char _SecondaryResetVector_text_start;
	329	extern char _SecondaryResetVector_text_end;
	330	#endif
5a0015d6	331
00273125 MF	332
	333	#ifdef CONFIG_S32C1I_SELFTEST
	334	#if XCHAL_HAVE_S32C1I
	335
	336	static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
	337
	338	/*
	339	* Basic atomic compare-and-swap, that records PC of S32C1I for probing.
	340	*
	341	* If v == cmp, set v = set. Return previous *v.
	342	*/
	343	static inline int probed_compare_swap(int *v, int cmp, int set)
	344	{
	345	int tmp;
	346
	347	__asm__ __volatile__(
	348	" movi %1, 1f\n"
	349	" s32i %1, %4, 0\n"
	350	" wsr %2, scompare1\n"
	351	"1: s32c1i %0, %3, 0\n"
	352	: "=a" (set), "=&a" (tmp)
	353	: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
	354	: "memory"
	355	);
	356	return set;
	357	}
	358
	359	/* Handle probed exception */
	360
59970753 MF	361	static void __init do_probed_exception(struct pt_regs *regs,
59970753 MF	362	unsigned long exccause)
00273125 MF	363	{
	364	if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
	365	regs->pc += 3; /* skip the s32c1i instruction */
	366	rcw_exc = exccause;
	367	} else {
	368	do_unhandled(regs, exccause);
	369	}
	370	}
	371
	372	/* Simple test of S32C1I (soc bringup assist) */
	373
59970753	374	static int __init check_s32c1i(void)
00273125 MF	375	{
	376	int n, cause1, cause2;
	377	void handbus, handdata, handaddr; / temporarily saved handlers */
	378
	379	rcw_probe_pc = 0;
	380	handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
	381	do_probed_exception);
	382	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
	383	do_probed_exception);
	384	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
	385	do_probed_exception);
	386
	387	/* First try an S32C1I that does not store: */
	388	rcw_exc = 0;
	389	rcw_word = 1;
	390	n = probed_compare_swap(&rcw_word, 0, 2);
	391	cause1 = rcw_exc;
	392
	393	/* took exception? */
	394	if (cause1 != 0) {
	395	/* unclean exception? */
	396	if (n != 2 \|\| rcw_word != 1)
	397	panic("S32C1I exception error");
	398	} else if (rcw_word != 1 \|\| n != 1) {
	399	panic("S32C1I compare error");
	400	}
	401
	402	/* Then an S32C1I that stores: */
	403	rcw_exc = 0;
	404	rcw_word = 0x1234567;
	405	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
	406	cause2 = rcw_exc;
	407
	408	if (cause2 != 0) {
	409	/* unclean exception? */
	410	if (n != 0xabcde \|\| rcw_word != 0x1234567)
	411	panic("S32C1I exception error (b)");
	412	} else if (rcw_word != 0xabcde \|\| n != 0x1234567) {
	413	panic("S32C1I store error");
	414	}
	415
	416	/* Verify consistency of exceptions: */
	417	if (cause1 \|\| cause2) {
	418	pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
	419	/* If emulation of S32C1I upon bus error gets implemented,
	420	we can get rid of this panic for single core (not SMP) */
	421	panic("S32C1I exceptions not currently supported");
	422	}
	423	if (cause1 != cause2)
	424	panic("inconsistent S32C1I exceptions");
	425
	426	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
	427	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
	428	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
59970753	429	return 0;
00273125 MF	430	}
	431
	432	#else /* XCHAL_HAVE_S32C1I */
	433
	434	/* This condition should not occur with a commercially deployed processor.
	435	Display reminder for early engr test or demo chips / FPGA bitstreams */
59970753	436	static int __init check_s32c1i(void)
00273125 MF	437	{
00273125 MF	438	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
59970753	439	return 0;
00273125 MF	440	}
	441
	442	#endif /* XCHAL_HAVE_S32C1I */
59970753	443	early_initcall(check_s32c1i);
00273125 MF	444	#endif /* CONFIG_S32C1I_SELFTEST */
	445
	446
5a0015d6 CZ	447	void __init setup_arch(char **cmdline_p)
5a0015d6 CZ	448	{
da844a81	449	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
5a0015d6 CZ	450	*cmdline_p = command_line;
	451
	452	/* Reserve some memory regions */
	453
	454	#ifdef CONFIG_BLK_DEV_INITRD
	455	if (initrd_start < initrd_end) {
	456	initrd_is_mapped = mem_reserve(__pa(initrd_start),
62327918	457	__pa(initrd_end), 0) == 0;
5a0015d6	458	initrd_below_start_ok = 1;
c4c4594b	459	} else {
5a0015d6 CZ	460	initrd_start = 0;
	461	}
	462	#endif
	463
	464	mem_reserve(__pa(&_stext),__pa(&_end), 1);
	465
	466	mem_reserve(__pa(&_WindowVectors_text_start),
	467	__pa(&_WindowVectors_text_end), 0);
	468
	469	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
	470	__pa(&_DebugInterruptVector_text_end), 0);
	471
	472	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
	473	__pa(&_KernelExceptionVector_text_end), 0);
	474
	475	mem_reserve(__pa(&_UserExceptionVector_literal_start),
	476	__pa(&_UserExceptionVector_text_end), 0);
	477
	478	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
	479	__pa(&_DoubleExceptionVector_text_end), 0);
	480
2d1c645c MG	481	#if XCHAL_EXCM_LEVEL >= 2
	482	mem_reserve(__pa(&_Level2InterruptVector_text_start),
	483	__pa(&_Level2InterruptVector_text_end), 0);
	484	#endif
	485	#if XCHAL_EXCM_LEVEL >= 3
	486	mem_reserve(__pa(&_Level3InterruptVector_text_start),
	487	__pa(&_Level3InterruptVector_text_end), 0);
	488	#endif
	489	#if XCHAL_EXCM_LEVEL >= 4
	490	mem_reserve(__pa(&_Level4InterruptVector_text_start),
	491	__pa(&_Level4InterruptVector_text_end), 0);
	492	#endif
	493	#if XCHAL_EXCM_LEVEL >= 5
	494	mem_reserve(__pa(&_Level5InterruptVector_text_start),
	495	__pa(&_Level5InterruptVector_text_end), 0);
	496	#endif
	497	#if XCHAL_EXCM_LEVEL >= 6
	498	mem_reserve(__pa(&_Level6InterruptVector_text_start),
	499	__pa(&_Level6InterruptVector_text_end), 0);
	500	#endif
	501
ab45fb14 MF	502	#ifdef CONFIG_SMP
	503	mem_reserve(__pa(&_SecondaryResetVector_text_start),
	504	__pa(&_SecondaryResetVector_text_end), 0);
	505	#endif
06bd2824	506	parse_early_param();
5a0015d6 CZ	507	bootmem_init();
5a0015d6 CZ	508
3104021c	509	unflatten_and_copy_device_tree();
5a0015d6	510
da844a81	511	platform_setup(cmdline_p);
5a0015d6	512
f615136c MF	513	#ifdef CONFIG_SMP
	514	smp_init_cpus();
	515	#endif
	516
5a0015d6	517	paging_init();
e5083a63	518	zones_init();
5a0015d6 CZ	519
	520	#ifdef CONFIG_VT
	521	# if defined(CONFIG_VGA_CONSOLE)
	522	conswitchp = &vga_con;
	523	# elif defined(CONFIG_DUMMY_CONSOLE)
	524	conswitchp = &dummy_con;
	525	# endif
	526	#endif
	527
288a60cf	528	#ifdef CONFIG_PCI
5a0015d6 CZ	529	platform_pcibios_init();
	530	#endif
	531	}
	532
f615136c MF	533	static DEFINE_PER_CPU(struct cpu, cpu_data);
	534
	535	static int __init topology_init(void)
	536	{
	537	int i;
	538
	539	for_each_possible_cpu(i) {
	540	struct cpu *cpu = &per_cpu(cpu_data, i);
49b424fe	541	cpu->hotpluggable = !!i;
f615136c MF	542	register_cpu(cpu, i);
	543	}
	544
	545	return 0;
	546	}
	547	subsys_initcall(topology_init);
	548
5a0015d6 CZ	549	void machine_restart(char * cmd)
	550	{
	551	platform_restart();
	552	}
	553
	554	void machine_halt(void)
	555	{
	556	platform_halt();
	557	while (1);
	558	}
	559
	560	void machine_power_off(void)
	561	{
	562	platform_power_off();
	563	while (1);
	564	}
	565	#ifdef CONFIG_PROC_FS
	566
	567	/*
	568	* Display some core information through /proc/cpuinfo.
	569	*/
	570
	571	static int
	572	c_show(struct seq_file f, void slot)
	573	{
	574	/* high-level stuff */
f615136c	575	seq_printf(f, "CPU count\t: %u\n"
62518994	576	"CPU list\t: %*pbl\n"
f615136c MF	577	"vendor_id\t: Tensilica\n"
	578	"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
	579	"core ID\t\t: " XCHAL_CORE_ID "\n"
	580	"build ID\t: 0x%x\n"
	581	"byte order\t: %s\n"
	582	"cpu MHz\t\t: %lu.%02lu\n"
	583	"bogomips\t: %lu.%02lu\n",
	584	num_online_cpus(),
62518994	585	cpumask_pr_args(cpu_online_mask),
f615136c MF	586	XCHAL_BUILD_UNIQUE_ID,
	587	XCHAL_HAVE_BE ? "big" : "little",
	588	ccount_freq/1000000,
	589	(ccount_freq/10000) % 100,
	590	loops_per_jiffy/(500000/HZ),
	591	(loops_per_jiffy/(5000/HZ)) % 100);
5a0015d6 CZ	592
	593	seq_printf(f,"flags\t\t: "
	594	#if XCHAL_HAVE_NMI
	595	"nmi "
	596	#endif
	597	#if XCHAL_HAVE_DEBUG
	598	"debug "
	599	# if XCHAL_HAVE_OCD
	600	"ocd "
	601	# endif
	602	#endif
	603	#if XCHAL_HAVE_DENSITY
	604	"density "
	605	#endif
	606	#if XCHAL_HAVE_BOOLEANS
	607	"boolean "
	608	#endif
	609	#if XCHAL_HAVE_LOOPS
	610	"loop "
	611	#endif
	612	#if XCHAL_HAVE_NSA
	613	"nsa "
	614	#endif
	615	#if XCHAL_HAVE_MINMAX
	616	"minmax "
	617	#endif
	618	#if XCHAL_HAVE_SEXT
	619	"sext "
	620	#endif
	621	#if XCHAL_HAVE_CLAMPS
	622	"clamps "
	623	#endif
	624	#if XCHAL_HAVE_MAC16
	625	"mac16 "
	626	#endif
	627	#if XCHAL_HAVE_MUL16
	628	"mul16 "
	629	#endif
	630	#if XCHAL_HAVE_MUL32
	631	"mul32 "
	632	#endif
	633	#if XCHAL_HAVE_MUL32_HIGH
	634	"mul32h "
	635	#endif
	636	#if XCHAL_HAVE_FP
	637	"fpu "
2f6ea6a7 MF	638	#endif
	639	#if XCHAL_HAVE_S32C1I
	640	"s32c1i "
5a0015d6 CZ	641	#endif
	642	"\n");
	643
	644	/* Registers. */
	645	seq_printf(f,"physical aregs\t: %d\n"
	646	"misc regs\t: %d\n"
	647	"ibreak\t\t: %d\n"
	648	"dbreak\t\t: %d\n",
	649	XCHAL_NUM_AREGS,
	650	XCHAL_NUM_MISC_REGS,
	651	XCHAL_NUM_IBREAK,
	652	XCHAL_NUM_DBREAK);
	653
	654
	655	/* Interrupt. */
	656	seq_printf(f,"num ints\t: %d\n"
	657	"ext ints\t: %d\n"
	658	"int levels\t: %d\n"
	659	"timers\t\t: %d\n"
	660	"debug level\t: %d\n",
	661	XCHAL_NUM_INTERRUPTS,
	662	XCHAL_NUM_EXTINTERRUPTS,
	663	XCHAL_NUM_INTLEVELS,
	664	XCHAL_NUM_TIMERS,
	665	XCHAL_DEBUGLEVEL);
	666
5a0015d6 CZ	667	/* Cache */
	668	seq_printf(f,"icache line size: %d\n"
	669	"icache ways\t: %d\n"
	670	"icache size\t: %d\n"
	671	"icache flags\t: "
	672	#if XCHAL_ICACHE_LINE_LOCKABLE
415217ef	673	"lock "
5a0015d6 CZ	674	#endif
	675	"\n"
	676	"dcache line size: %d\n"
	677	"dcache ways\t: %d\n"
	678	"dcache size\t: %d\n"
	679	"dcache flags\t: "
	680	#if XCHAL_DCACHE_IS_WRITEBACK
415217ef	681	"writeback "
5a0015d6 CZ	682	#endif
5a0015d6 CZ	683	#if XCHAL_DCACHE_LINE_LOCKABLE
415217ef	684	"lock "
5a0015d6 CZ	685	#endif
	686	"\n",
	687	XCHAL_ICACHE_LINESIZE,
	688	XCHAL_ICACHE_WAYS,
	689	XCHAL_ICACHE_SIZE,
	690	XCHAL_DCACHE_LINESIZE,
	691	XCHAL_DCACHE_WAYS,
	692	XCHAL_DCACHE_SIZE);
	693
5a0015d6 CZ	694	return 0;
	695	}
	696
	697	/*
	698	* We show only CPU #0 info.
	699	*/
	700	static void *
	701	c_start(struct seq_file f, loff_t pos)
	702	{
f615136c	703	return (pos == 0) ? (void )1 : NULL;
5a0015d6 CZ	704	}
	705
	706	static void *
	707	c_next(struct seq_file f, void v, loff_t *pos)
	708	{
	709	return NULL;
	710	}
	711
	712	static void
	713	c_stop(struct seq_file f, void v)
	714	{
	715	}
	716
03a44825	717	const struct seq_operations cpuinfo_op =
5a0015d6	718	{
f615136c MF	719	.start = c_start,
	720	.next = c_next,
	721	.stop = c_stop,
	722	.show = c_show,
5a0015d6 CZ	723	};
	724
	725	#endif /* CONFIG_PROC_FS */