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1 | /* |
2 | * arch/xtensa/platform/xtavnet/include/platform/hardware.h | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2006 Tensilica Inc. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * This file contains the hardware configuration of the XTAVNET boards. | |
13 | */ | |
14 | ||
15 | #ifndef __XTENSA_XTAVNET_HARDWARE_H | |
16 | #define __XTENSA_XTAVNET_HARDWARE_H | |
17 | ||
0d456bad MF |
18 | /* Memory configuration. */ |
19 | ||
20 | #define PLATFORM_DEFAULT_MEM_START 0x00000000 | |
21 | #define PLATFORM_DEFAULT_MEM_SIZE 0x04000000 | |
22 | ||
23 | /* Interrupt configuration. */ | |
24 | ||
25 | #define PLATFORM_NR_IRQS 10 | |
26 | ||
27 | /* Default assignment of LX60 devices to external interrupts. */ | |
28 | ||
29 | #ifdef CONFIG_ARCH_HAS_SMP | |
30 | #define DUART16552_INTNUM XCHAL_EXTINT3_NUM | |
31 | #define OETH_IRQ XCHAL_EXTINT4_NUM | |
32 | #else | |
33 | #define DUART16552_INTNUM XCHAL_EXTINT0_NUM | |
34 | #define OETH_IRQ XCHAL_EXTINT1_NUM | |
35 | #endif | |
36 | ||
37 | /* | |
38 | * Device addresses and parameters. | |
39 | */ | |
40 | ||
41 | /* UART */ | |
42 | #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020) | |
43 | /* LCD instruction and data addresses. */ | |
44 | #define LCD_INSTR_ADDR ((char *)IOADDR(0x0D040000)) | |
45 | #define LCD_DATA_ADDR ((char *)IOADDR(0x0D040004)) | |
46 | ||
47 | /* Misc. */ | |
48 | #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000) | |
49 | /* Clock frequency in Hz (read-only): */ | |
50 | #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) | |
51 | /* Setting of 8 DIP switches: */ | |
52 | #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C) | |
53 | /* Software reset (write 0xdead): */ | |
54 | #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10) | |
55 | ||
56 | /* OpenCores Ethernet controller: */ | |
57 | /* regs + RX/TX descriptors */ | |
58 | #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000) | |
59 | #define OETH_REGS_SIZE 0x1000 | |
60 | #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000) | |
61 | ||
62 | /* 5*rx buffs + 5*tx buffs */ | |
63 | #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600) | |
64 | ||
65 | #endif /* __XTENSA_XTAVNET_HARDWARE_H */ |