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ca5d32a3 WL |
1 | /* |
2 | * arm cpu init and loop | |
3 | * | |
4 | * Copyright (c) 2013 Stacey D. Son | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef _TARGET_ARCH_CPU_H_ | |
21 | #define _TARGET_ARCH_CPU_H_ | |
22 | ||
23 | #include "target_arch.h" | |
24 | ||
25 | #define TARGET_DEFAULT_CPU_MODEL "any" | |
26 | ||
27 | static inline void target_cpu_init(CPUARMState *env, | |
28 | struct target_pt_regs *regs) | |
29 | { | |
30 | int i; | |
31 | ||
32 | cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, | |
33 | CPSRWriteByInstr); | |
34 | for (i = 0; i < 16; i++) { | |
35 | env->regs[i] = regs->uregs[i]; | |
36 | } | |
37 | } | |
38 | ||
06efe3bf WL |
39 | static inline void target_cpu_loop(CPUARMState *env) |
40 | { | |
41 | int trapnr; | |
42 | target_siginfo_t info; | |
43 | CPUState *cs = env_cpu(env); | |
44 | ||
45 | for (;;) { | |
46 | cpu_exec_start(cs); | |
47 | trapnr = cpu_exec(cs); | |
48 | cpu_exec_end(cs); | |
49 | process_queued_cpu_work(cs); | |
50 | switch (trapnr) { | |
70985aec WL |
51 | case EXCP_UDEF: |
52 | { | |
53 | /* See arm/arm/undefined.c undefinedinstruction(); */ | |
54 | info.si_addr = env->regs[15]; | |
55 | ||
56 | /* illegal instruction */ | |
57 | info.si_signo = TARGET_SIGILL; | |
58 | info.si_errno = 0; | |
59 | info.si_code = TARGET_ILL_ILLOPC; | |
60 | queue_signal(env, info.si_signo, &info); | |
61 | ||
62 | /* TODO: What about instruction emulation? */ | |
63 | } | |
64 | break; | |
65 | case EXCP_INTERRUPT: | |
66 | /* just indicate that signals should be handled asap */ | |
67 | break; | |
68 | case EXCP_DEBUG: | |
69 | { | |
70 | ||
71 | info.si_signo = TARGET_SIGTRAP; | |
72 | info.si_errno = 0; | |
73 | info.si_code = TARGET_TRAP_BRKPT; | |
74 | info.si_addr = env->exception.vaddress; | |
75 | queue_signal(env, info.si_signo, &info); | |
76 | } | |
77 | break; | |
78 | case EXCP_ATOMIC: | |
79 | cpu_exec_step_atomic(cs); | |
80 | break; | |
81 | case EXCP_YIELD: | |
82 | /* nothing to do here for user-mode, just resume guest code */ | |
83 | break; | |
06efe3bf WL |
84 | default: |
85 | fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", | |
86 | trapnr); | |
87 | cpu_dump_state(cs, stderr, 0); | |
88 | abort(); | |
89 | } /* switch() */ | |
90 | process_pending_signals(env); | |
91 | } /* for (;;) */ | |
92 | } | |
93 | ||
e17d4c9a WL |
94 | static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong newsp) |
95 | { | |
96 | if (newsp) { | |
97 | env->regs[13] = newsp; | |
98 | } | |
99 | env->regs[0] = 0; | |
100 | } | |
101 | ||
ca5d32a3 WL |
102 | static inline void target_cpu_reset(CPUArchState *cpu) |
103 | { | |
104 | } | |
105 | ||
106 | #endif /* !_TARGET_ARCH_CPU_H */ |