[mirror_qemu.git] / bsd-user / i386 / target_arch_cpu.h

/*
 *  i386 cpu init and loop
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef TARGET_ARCH_CPU_H
#define TARGET_ARCH_CPU_H

#include "target_arch.h"
#include "signal-common.h"

#define TARGET_DEFAULT_CPU_MODEL "qemu32"

static inline void target_cpu_init(CPUX86State *env,
        struct target_pt_regs *regs)
{
    uint64_t *gdt_table;

    env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
    env->hflags |= HF_PE_MASK | HF_CPL_MASK;
    if (env->features[FEAT_1_EDX] & CPUID_SSE) {
        env->cr[4] |= CR4_OSFXSR_MASK;
        env->hflags |= HF_OSFXSR_MASK;
    }

    /* flags setup : we activate the IRQs by default as in user mode */
    env->eflags |= IF_MASK;

    /* register setup */
    env->regs[R_EAX] = regs->eax;
    env->regs[R_EBX] = regs->ebx;
    env->regs[R_ECX] = regs->ecx;
    env->regs[R_EDX] = regs->edx;
    env->regs[R_ESI] = regs->esi;
    env->regs[R_EDI] = regs->edi;
    env->regs[R_EBP] = regs->ebp;
    env->regs[R_ESP] = regs->esp;
    env->eip = regs->eip;

    /* interrupt setup */
    env->idt.limit = 255;

    env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
        PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
    bsd_i386_set_idt_base(env->idt.base);
    bsd_i386_set_idt(0, 0);
    bsd_i386_set_idt(1, 0);
    bsd_i386_set_idt(2, 0);
    bsd_i386_set_idt(3, 3);
    bsd_i386_set_idt(4, 3);
    bsd_i386_set_idt(5, 0);
    bsd_i386_set_idt(6, 0);
    bsd_i386_set_idt(7, 0);
    bsd_i386_set_idt(8, 0);
    bsd_i386_set_idt(9, 0);
    bsd_i386_set_idt(10, 0);
    bsd_i386_set_idt(11, 0);
    bsd_i386_set_idt(12, 0);
    bsd_i386_set_idt(13, 0);
    bsd_i386_set_idt(14, 0);
    bsd_i386_set_idt(15, 0);
    bsd_i386_set_idt(16, 0);
    bsd_i386_set_idt(17, 0);
    bsd_i386_set_idt(18, 0);
    bsd_i386_set_idt(19, 0);
    bsd_i386_set_idt(0x80, 3);

    /* segment setup */
    env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
            PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
    env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
    gdt_table = g2h_untagged(env->gdt.base);

    bsd_i386_write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
            (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));

    bsd_i386_write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
            (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));

    cpu_x86_load_seg(env, R_CS, __USER_CS);
    cpu_x86_load_seg(env, R_SS, __USER_DS);
    cpu_x86_load_seg(env, R_DS, __USER_DS);
    cpu_x86_load_seg(env, R_ES, __USER_DS);
    cpu_x86_load_seg(env, R_FS, __USER_DS);
    cpu_x86_load_seg(env, R_GS, __USER_DS);
    /* This hack makes Wine work... */
    env->segs[R_FS].selector = 0;
}

static inline void target_cpu_loop(CPUX86State *env)
{
    CPUState *cs = env_cpu(env);
    int trapnr;
    abi_ulong pc;
    /* target_siginfo_t info; */

    for (;;) {
        cpu_exec_start(cs);
        trapnr = cpu_exec(cs);
        cpu_exec_end(cs);
        process_queued_cpu_work(cs);

        switch (trapnr) {
        case 0x80: {
            /* syscall from int $0x80 */
            abi_ulong params = (abi_ulong) env->regs[R_ESP] +
                sizeof(int32_t);
            int32_t syscall_nr = env->regs[R_EAX];
            int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;

            if (syscall_nr == TARGET_FREEBSD_NR_syscall) {
                get_user_s32(syscall_nr, params);
                params += sizeof(int32_t);
            } else if (syscall_nr == TARGET_FREEBSD_NR___syscall) {
                get_user_s32(syscall_nr, params);
                params += sizeof(int64_t);
            }
            get_user_s32(arg1, params);
            params += sizeof(int32_t);
            get_user_s32(arg2, params);
            params += sizeof(int32_t);
            get_user_s32(arg3, params);
            params += sizeof(int32_t);
            get_user_s32(arg4, params);
            params += sizeof(int32_t);
            get_user_s32(arg5, params);
            params += sizeof(int32_t);
            get_user_s32(arg6, params);
            params += sizeof(int32_t);
            get_user_s32(arg7, params);
            params += sizeof(int32_t);
            get_user_s32(arg8, params);
            env->regs[R_EAX] = do_freebsd_syscall(env,
                                                  syscall_nr,
                                                  arg1,
                                                  arg2,
                                                  arg3,
                                                  arg4,
                                                  arg5,
                                                  arg6,
                                                  arg7,
                                                  arg8);
            }
            if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) {
                env->regs[R_EAX] = -env->regs[R_EAX];
                env->eflags |= CC_C;
            } else {
                env->eflags &= ~CC_C;
            }
            break;

        case EXCP_SYSCALL:
            /* doesn't do anything */
            break;

        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;

        case EXCP_ATOMIC:
            cpu_exec_step_atomic(cs);
            break;

        default:
            pc = env->segs[R_CS].base + env->eip;
            fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - "
                    "aborting\n", (long)pc, trapnr);
            abort();
        }
        process_pending_signals(env);
    }
}

static inline void target_cpu_clone_regs(CPUX86State *env, target_ulong newsp)
{
    if (newsp) {
        env->regs[R_ESP] = newsp;
    }
    env->regs[R_EAX] = 0;
}

static inline void target_cpu_reset(CPUArchState *env)
{
    cpu_reset(env_cpu(env));
}

#endif /* TARGET_ARCH_CPU_H */
Commit	Line	Data
031fe7af WL	1	/*
	2	* i386 cpu init and loop
	3	*
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
9c092804 MA	19	#ifndef TARGET_ARCH_CPU_H
9c092804 MA	20	#define TARGET_ARCH_CPU_H
031fe7af WL	21
031fe7af WL	22	#include "target_arch.h"
2bd010c4	23	#include "signal-common.h"
031fe7af WL	24
	25	#define TARGET_DEFAULT_CPU_MODEL "qemu32"
	26
031fe7af WL	27	static inline void target_cpu_init(CPUX86State *env,
	28	struct target_pt_regs *regs)
	29	{
	30	uint64_t *gdt_table;
	31
	32	env->cr[0] = CR0_PG_MASK \| CR0_WP_MASK \| CR0_PE_MASK;
	33	env->hflags \|= HF_PE_MASK \| HF_CPL_MASK;
	34	if (env->features[FEAT_1_EDX] & CPUID_SSE) {
	35	env->cr[4] \|= CR4_OSFXSR_MASK;
	36	env->hflags \|= HF_OSFXSR_MASK;
	37	}
	38
	39	/* flags setup : we activate the IRQs by default as in user mode */
	40	env->eflags \|= IF_MASK;
	41
	42	/* register setup */
	43	env->regs[R_EAX] = regs->eax;
	44	env->regs[R_EBX] = regs->ebx;
	45	env->regs[R_ECX] = regs->ecx;
	46	env->regs[R_EDX] = regs->edx;
	47	env->regs[R_ESI] = regs->esi;
	48	env->regs[R_EDI] = regs->edi;
	49	env->regs[R_EBP] = regs->ebp;
	50	env->regs[R_ESP] = regs->esp;
	51	env->eip = regs->eip;
	52
	53	/* interrupt setup */
	54	env->idt.limit = 255;
	55
	56	env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
	57	PROT_READ \| PROT_WRITE, MAP_ANONYMOUS \| MAP_PRIVATE, -1, 0);
	58	bsd_i386_set_idt_base(env->idt.base);
	59	bsd_i386_set_idt(0, 0);
	60	bsd_i386_set_idt(1, 0);
	61	bsd_i386_set_idt(2, 0);
	62	bsd_i386_set_idt(3, 3);
	63	bsd_i386_set_idt(4, 3);
	64	bsd_i386_set_idt(5, 0);
	65	bsd_i386_set_idt(6, 0);
	66	bsd_i386_set_idt(7, 0);
	67	bsd_i386_set_idt(8, 0);
	68	bsd_i386_set_idt(9, 0);
	69	bsd_i386_set_idt(10, 0);
	70	bsd_i386_set_idt(11, 0);
	71	bsd_i386_set_idt(12, 0);
	72	bsd_i386_set_idt(13, 0);
	73	bsd_i386_set_idt(14, 0);
	74	bsd_i386_set_idt(15, 0);
	75	bsd_i386_set_idt(16, 0);
	76	bsd_i386_set_idt(17, 0);
	77	bsd_i386_set_idt(18, 0);
	78	bsd_i386_set_idt(19, 0);
	79	bsd_i386_set_idt(0x80, 3);
	80
	81	/* segment setup */
	82	env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
	83	PROT_READ \| PROT_WRITE, MAP_ANONYMOUS \| MAP_PRIVATE, -1, 0);
	84	env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
	85	gdt_table = g2h_untagged(env->gdt.base);
	86
	87	bsd_i386_write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
	88	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \| DESC_S_MASK \|
	89	(3 << DESC_DPL_SHIFT) \| (0xa << DESC_TYPE_SHIFT));
	90
91	bsd_i386_write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
92	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \| DESC_S_MASK \|
93	(3 << DESC_DPL_SHIFT) \| (0x2 << DESC_TYPE_SHIFT));
94
95	cpu_x86_load_seg(env, R_CS, __USER_CS);
96	cpu_x86_load_seg(env, R_SS, __USER_DS);
97	cpu_x86_load_seg(env, R_DS, __USER_DS);
98	cpu_x86_load_seg(env, R_ES, __USER_DS);
99	cpu_x86_load_seg(env, R_FS, __USER_DS);
100	cpu_x86_load_seg(env, R_GS, __USER_DS);
101	/* This hack makes Wine work... */
102	env->segs[R_FS].selector = 0;
103	}
104
105	static inline void target_cpu_loop(CPUX86State *env)
106	{
107	CPUState *cs = env_cpu(env);
108	int trapnr;
109	abi_ulong pc;
110	/* target_siginfo_t info; */
111
112	for (;;) {
113	cpu_exec_start(cs);
114	trapnr = cpu_exec(cs);
115	cpu_exec_end(cs);
116	process_queued_cpu_work(cs);
117
118	switch (trapnr) {
8f4b4816	119	case 0x80: {
031fe7af	120	/* syscall from int $0x80 */
8f4b4816 WL	121	abi_ulong params = (abi_ulong) env->regs[R_ESP] +
	122	sizeof(int32_t);
	123	int32_t syscall_nr = env->regs[R_EAX];
	124	int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
	125
	126	if (syscall_nr == TARGET_FREEBSD_NR_syscall) {
	127	get_user_s32(syscall_nr, params);
031fe7af	128	params += sizeof(int32_t);
8f4b4816 WL	129	} else if (syscall_nr == TARGET_FREEBSD_NR___syscall) {
	130	get_user_s32(syscall_nr, params);
	131	params += sizeof(int64_t);
	132	}
	133	get_user_s32(arg1, params);
	134	params += sizeof(int32_t);
	135	get_user_s32(arg2, params);
	136	params += sizeof(int32_t);
	137	get_user_s32(arg3, params);
	138	params += sizeof(int32_t);
	139	get_user_s32(arg4, params);
	140	params += sizeof(int32_t);
	141	get_user_s32(arg5, params);
	142	params += sizeof(int32_t);
	143	get_user_s32(arg6, params);
	144	params += sizeof(int32_t);
	145	get_user_s32(arg7, params);
	146	params += sizeof(int32_t);
	147	get_user_s32(arg8, params);
	148	env->regs[R_EAX] = do_freebsd_syscall(env,
	149	syscall_nr,
	150	arg1,
	151	arg2,
	152	arg3,
	153	arg4,
	154	arg5,
	155	arg6,
	156	arg7,
	157	arg8);
031fe7af WL	158	}
	159	if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) {
	160	env->regs[R_EAX] = -env->regs[R_EAX];
	161	env->eflags \|= CC_C;
	162	} else {
	163	env->eflags &= ~CC_C;
	164	}
	165	break;
	166
63fd8ef0 PB	167	case EXCP_SYSCALL:
	168	/* doesn't do anything */
	169	break;
	170
031fe7af WL	171	case EXCP_INTERRUPT:
	172	/* just indicate that signals should be handled asap */
	173	break;
	174
	175	case EXCP_ATOMIC:
	176	cpu_exec_step_atomic(cs);
	177	break;
	178
	179	default:
	180	pc = env->segs[R_CS].base + env->eip;
	181	fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - "
	182	"aborting\n", (long)pc, trapnr);
	183	abort();
	184	}
	185	process_pending_signals(env);
	186	}
	187	}
	188
	189	static inline void target_cpu_clone_regs(CPUX86State *env, target_ulong newsp)
	190	{
	191	if (newsp) {
	192	env->regs[R_ESP] = newsp;
	193	}
	194	env->regs[R_EAX] = 0;
	195	}
	196
bab6ccc5	197	static inline void target_cpu_reset(CPUArchState *env)
031fe7af	198	{
bab6ccc5	199	cpu_reset(env_cpu(env));
031fe7af WL	200	}
031fe7af WL	201
9c092804	202	#endif /* TARGET_ARCH_CPU_H */