[rustc.git] / compiler / rustc_ast_lowering / src / asm.rs

use super::LoweringContext;

use rustc_ast::*;
use rustc_data_structures::fx::FxHashMap;
use rustc_data_structures::stable_set::FxHashSet;
use rustc_errors::struct_span_err;
use rustc_hir as hir;
use rustc_session::parse::feature_err;
use rustc_span::{sym, Span};
use rustc_target::asm;
use std::collections::hash_map::Entry;
use std::fmt::Write;

impl<'a, 'hir> LoweringContext<'a, 'hir> {
    crate fn lower_inline_asm(&mut self, sp: Span, asm: &InlineAsm) -> &'hir hir::InlineAsm<'hir> {
        // Rustdoc needs to support asm! from foreign architectures: don't try
        // lowering the register constraints in this case.
        let asm_arch = if self.sess.opts.actually_rustdoc { None } else { self.sess.asm_arch };
        if asm_arch.is_none() && !self.sess.opts.actually_rustdoc {
            struct_span_err!(self.sess, sp, E0472, "inline assembly is unsupported on this target")
                .emit();
        }
        if let Some(asm_arch) = asm_arch {
            // Inline assembly is currently only stable for these architectures.
            let is_stable = matches!(
                asm_arch,
                asm::InlineAsmArch::X86
                    | asm::InlineAsmArch::X86_64
                    | asm::InlineAsmArch::Arm
                    | asm::InlineAsmArch::AArch64
                    | asm::InlineAsmArch::RiscV32
                    | asm::InlineAsmArch::RiscV64
            );
            if !is_stable && !self.sess.features_untracked().asm_experimental_arch {
                feature_err(
                    &self.sess.parse_sess,
                    sym::asm_experimental_arch,
                    sp,
                    "inline assembly is not stable yet on this architecture",
                )
                .emit();
            }
        }
        if asm.options.contains(InlineAsmOptions::ATT_SYNTAX)
            && !matches!(asm_arch, Some(asm::InlineAsmArch::X86 | asm::InlineAsmArch::X86_64))
            && !self.sess.opts.actually_rustdoc
        {
            self.sess
                .struct_span_err(sp, "the `att_syntax` option is only supported on x86")
                .emit();
        }
        if asm.options.contains(InlineAsmOptions::MAY_UNWIND)
            && !self.sess.features_untracked().asm_unwind
        {
            feature_err(
                &self.sess.parse_sess,
                sym::asm_unwind,
                sp,
                "the `may_unwind` option is unstable",
            )
            .emit();
        }

        let mut clobber_abis = FxHashMap::default();
        if let Some(asm_arch) = asm_arch {
            for (abi_name, abi_span) in &asm.clobber_abis {
                match asm::InlineAsmClobberAbi::parse(
                    asm_arch,
                    &self.sess.target_features,
                    &self.sess.target,
                    *abi_name,
                ) {
                    Ok(abi) => {
                        // If the abi was already in the list, emit an error
                        match clobber_abis.get(&abi) {
                            Some((prev_name, prev_sp)) => {
                                let mut err = self.sess.struct_span_err(
                                    *abi_span,
                                    &format!("`{}` ABI specified multiple times", prev_name),
                                );
                                err.span_label(*prev_sp, "previously specified here");

                                // Multiple different abi names may actually be the same ABI
                                // If the specified ABIs are not the same name, alert the user that they resolve to the same ABI
                                let source_map = self.sess.source_map();
                                if source_map.span_to_snippet(*prev_sp)
                                    != source_map.span_to_snippet(*abi_span)
                                {
                                    err.note("these ABIs are equivalent on the current target");
                                }

                                err.emit();
                            }
                            None => {
                                clobber_abis.insert(abi, (abi_name, *abi_span));
                            }
                        }
                    }
                    Err(&[]) => {
                        self.sess
                            .struct_span_err(
                                *abi_span,
                                "`clobber_abi` is not supported on this target",
                            )
                            .emit();
                    }
                    Err(supported_abis) => {
                        let mut err =
                            self.sess.struct_span_err(*abi_span, "invalid ABI for `clobber_abi`");
                        let mut abis = format!("`{}`", supported_abis[0]);
                        for m in &supported_abis[1..] {
                            let _ = write!(abis, ", `{}`", m);
                        }
                        err.note(&format!(
                            "the following ABIs are supported on this target: {}",
                            abis
                        ));
                        err.emit();
                    }
                }
            }
        }

        // Lower operands to HIR. We use dummy register classes if an error
        // occurs during lowering because we still need to be able to produce a
        // valid HIR.
        let sess = self.sess;
        let mut operands: Vec<_> = asm
            .operands
            .iter()
            .map(|(op, op_sp)| {
                let lower_reg = |reg, is_clobber| match reg {
                    InlineAsmRegOrRegClass::Reg(s) => {
                        asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
                            asm::InlineAsmReg::parse(
                                asm_arch,
                                &sess.target_features,
                                &sess.target,
                                is_clobber,
                                s,
                            )
                            .unwrap_or_else(|e| {
                                let msg = format!("invalid register `{}`: {}", s.as_str(), e);
                                sess.struct_span_err(*op_sp, &msg).emit();
                                asm::InlineAsmReg::Err
                            })
                        } else {
                            asm::InlineAsmReg::Err
                        })
                    }
                    InlineAsmRegOrRegClass::RegClass(s) => {
                        asm::InlineAsmRegOrRegClass::RegClass(if let Some(asm_arch) = asm_arch {
                            asm::InlineAsmRegClass::parse(asm_arch, s).unwrap_or_else(|e| {
                                let msg = format!("invalid register class `{}`: {}", s.as_str(), e);
                                sess.struct_span_err(*op_sp, &msg).emit();
                                asm::InlineAsmRegClass::Err
                            })
                        } else {
                            asm::InlineAsmRegClass::Err
                        })
                    }
                };

                let op = match *op {
                    InlineAsmOperand::In { reg, ref expr } => hir::InlineAsmOperand::In {
                        reg: lower_reg(reg, false),
                        expr: self.lower_expr_mut(expr),
                    },
                    InlineAsmOperand::Out { reg, late, ref expr } => hir::InlineAsmOperand::Out {
                        reg: lower_reg(reg, expr.is_none()),
                        late,
                        expr: expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
                    },
                    InlineAsmOperand::InOut { reg, late, ref expr } => {
                        hir::InlineAsmOperand::InOut {
                            reg: lower_reg(reg, false),
                            late,
                            expr: self.lower_expr_mut(expr),
                        }
                    }
                    InlineAsmOperand::SplitInOut { reg, late, ref in_expr, ref out_expr } => {
                        hir::InlineAsmOperand::SplitInOut {
                            reg: lower_reg(reg, false),
                            late,
                            in_expr: self.lower_expr_mut(in_expr),
                            out_expr: out_expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
                        }
                    }
                    InlineAsmOperand::Const { ref anon_const } => {
                        if !self.sess.features_untracked().asm_const {
                            feature_err(
                                &self.sess.parse_sess,
                                sym::asm_const,
                                *op_sp,
                                "const operands for inline assembly are unstable",
                            )
                            .emit();
                        }
                        hir::InlineAsmOperand::Const {
                            anon_const: self.lower_anon_const(anon_const),
                        }
                    }
                    InlineAsmOperand::Sym { ref expr } => {
                        if !self.sess.features_untracked().asm_sym {
                            feature_err(
                                &self.sess.parse_sess,
                                sym::asm_sym,
                                *op_sp,
                                "sym operands for inline assembly are unstable",
                            )
                            .emit();
                        }
                        hir::InlineAsmOperand::Sym { expr: self.lower_expr_mut(expr) }
                    }
                };
                (op, self.lower_span(*op_sp))
            })
            .collect();

        // Validate template modifiers against the register classes for the operands
        for p in &asm.template {
            if let InlineAsmTemplatePiece::Placeholder {
                operand_idx,
                modifier: Some(modifier),
                span: placeholder_span,
            } = *p
            {
                let op_sp = asm.operands[operand_idx].1;
                match &operands[operand_idx].0 {
                    hir::InlineAsmOperand::In { reg, .. }
                    | hir::InlineAsmOperand::Out { reg, .. }
                    | hir::InlineAsmOperand::InOut { reg, .. }
                    | hir::InlineAsmOperand::SplitInOut { reg, .. } => {
                        let class = reg.reg_class();
                        if class == asm::InlineAsmRegClass::Err {
                            continue;
                        }
                        let valid_modifiers = class.valid_modifiers(asm_arch.unwrap());
                        if !valid_modifiers.contains(&modifier) {
                            let mut err = sess.struct_span_err(
                                placeholder_span,
                                "invalid asm template modifier for this register class",
                            );
                            err.span_label(placeholder_span, "template modifier");
                            err.span_label(op_sp, "argument");
                            if !valid_modifiers.is_empty() {
                                let mut mods = format!("`{}`", valid_modifiers[0]);
                                for m in &valid_modifiers[1..] {
                                    let _ = write!(mods, ", `{}`", m);
                                }
                                err.note(&format!(
                                    "the `{}` register class supports \
                                     the following template modifiers: {}",
                                    class.name(),
                                    mods
                                ));
                            } else {
                                err.note(&format!(
                                    "the `{}` register class does not support template modifiers",
                                    class.name()
                                ));
                            }
                            err.emit();
                        }
                    }
                    hir::InlineAsmOperand::Const { .. } => {
                        let mut err = sess.struct_span_err(
                            placeholder_span,
                            "asm template modifiers are not allowed for `const` arguments",
                        );
                        err.span_label(placeholder_span, "template modifier");
                        err.span_label(op_sp, "argument");
                        err.emit();
                    }
                    hir::InlineAsmOperand::Sym { .. } => {
                        let mut err = sess.struct_span_err(
                            placeholder_span,
                            "asm template modifiers are not allowed for `sym` arguments",
                        );
                        err.span_label(placeholder_span, "template modifier");
                        err.span_label(op_sp, "argument");
                        err.emit();
                    }
                }
            }
        }

        let mut used_input_regs = FxHashMap::default();
        let mut used_output_regs = FxHashMap::default();

        for (idx, &(ref op, op_sp)) in operands.iter().enumerate() {
            if let Some(reg) = op.reg() {
                let reg_class = reg.reg_class();
                if reg_class == asm::InlineAsmRegClass::Err {
                    continue;
                }

                // Some register classes can only be used as clobbers. This
                // means that we disallow passing a value in/out of the asm and
                // require that the operand name an explicit register, not a
                // register class.
                if reg_class.is_clobber_only(asm_arch.unwrap()) && !op.is_clobber() {
                    let msg = format!(
                        "register class `{}` can only be used as a clobber, \
                             not as an input or output",
                        reg_class.name()
                    );
                    sess.struct_span_err(op_sp, &msg).emit();
                    continue;
                }

                // Check for conflicts between explicit register operands.
                if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
                    let (input, output) = match op {
                        hir::InlineAsmOperand::In { .. } => (true, false),

                        // Late output do not conflict with inputs, but normal outputs do
                        hir::InlineAsmOperand::Out { late, .. } => (!late, true),

                        hir::InlineAsmOperand::InOut { .. }
                        | hir::InlineAsmOperand::SplitInOut { .. } => (true, true),

                        hir::InlineAsmOperand::Const { .. } | hir::InlineAsmOperand::Sym { .. } => {
                            unreachable!()
                        }
                    };

                    // Flag to output the error only once per operand
                    let mut skip = false;
                    reg.overlapping_regs(|r| {
                        let mut check = |used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
                                         input| {
                            match used_regs.entry(r) {
                                Entry::Occupied(o) => {
                                    if skip {
                                        return;
                                    }
                                    skip = true;

                                    let idx2 = *o.get();
                                    let &(ref op2, op_sp2) = &operands[idx2];
                                    let reg2 = match op2.reg() {
                                        Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
                                        _ => unreachable!(),
                                    };

                                    let msg = format!(
                                        "register `{}` conflicts with register `{}`",
                                        reg.name(),
                                        reg2.name()
                                    );
                                    let mut err = sess.struct_span_err(op_sp, &msg);
                                    err.span_label(op_sp, &format!("register `{}`", reg.name()));
                                    err.span_label(op_sp2, &format!("register `{}`", reg2.name()));

                                    match (op, op2) {
                                        (
                                            hir::InlineAsmOperand::In { .. },
                                            hir::InlineAsmOperand::Out { late, .. },
                                        )
                                        | (
                                            hir::InlineAsmOperand::Out { late, .. },
                                            hir::InlineAsmOperand::In { .. },
                                        ) => {
                                            assert!(!*late);
                                            let out_op_sp = if input { op_sp2 } else { op_sp };
                                            let msg = "use `lateout` instead of \
                                                       `out` to avoid conflict";
                                            err.span_help(out_op_sp, msg);
                                        }
                                        _ => {}
                                    }

                                    err.emit();
                                }
                                Entry::Vacant(v) => {
                                    if r == reg {
                                        v.insert(idx);
                                    }
                                }
                            }
                        };
                        if input {
                            check(&mut used_input_regs, true);
                        }
                        if output {
                            check(&mut used_output_regs, false);
                        }
                    });
                }
            }
        }

        // If a clobber_abi is specified, add the necessary clobbers to the
        // operands list.
        let mut clobbered = FxHashSet::default();
        for (abi, (_, abi_span)) in clobber_abis {
            for &clobber in abi.clobbered_regs() {
                // Don't emit a clobber for a register already clobbered
                if clobbered.contains(&clobber) {
                    continue;
                }

                let mut output_used = false;
                clobber.overlapping_regs(|reg| {
                    if used_output_regs.contains_key(&reg) {
                        output_used = true;
                    }
                });

                if !output_used {
                    operands.push((
                        hir::InlineAsmOperand::Out {
                            reg: asm::InlineAsmRegOrRegClass::Reg(clobber),
                            late: true,
                            expr: None,
                        },
                        self.lower_span(abi_span),
                    ));
                    clobbered.insert(clobber);
                }
            }
        }

        let operands = self.arena.alloc_from_iter(operands);
        let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
        let template_strs = self.arena.alloc_from_iter(
            asm.template_strs
                .iter()
                .map(|(sym, snippet, span)| (*sym, *snippet, self.lower_span(*span))),
        );
        let line_spans =
            self.arena.alloc_from_iter(asm.line_spans.iter().map(|span| self.lower_span(*span)));
        let hir_asm =
            hir::InlineAsm { template, template_strs, operands, options: asm.options, line_spans };
        self.arena.alloc(hir_asm)
    }
}
Commit	Line	Data
17df50a5 XL	1	use super::LoweringContext;
	2
	3	use rustc_ast::*;
	4	use rustc_data_structures::fx::FxHashMap;
3c0e092e	5	use rustc_data_structures::stable_set::FxHashSet;
17df50a5 XL	6	use rustc_errors::struct_span_err;
17df50a5 XL	7	use rustc_hir as hir;
3c0e092e	8	use rustc_session::parse::feature_err;
5099ac24	9	use rustc_span::{sym, Span};
17df50a5 XL	10	use rustc_target::asm;
	11	use std::collections::hash_map::Entry;
	12	use std::fmt::Write;
	13
	14	impl<'a, 'hir> LoweringContext<'a, 'hir> {
	15	crate fn lower_inline_asm(&mut self, sp: Span, asm: &InlineAsm) -> &'hir hir::InlineAsm<'hir> {
3c0e092e XL	16	// Rustdoc needs to support asm! from foreign architectures: don't try
3c0e092e XL	17	// lowering the register constraints in this case.
17df50a5 XL	18	let asm_arch = if self.sess.opts.actually_rustdoc { None } else { self.sess.asm_arch };
	19	if asm_arch.is_none() && !self.sess.opts.actually_rustdoc {
	20	struct_span_err!(self.sess, sp, E0472, "inline assembly is unsupported on this target")
	21	.emit();
	22	}
3c0e092e XL	23	if let Some(asm_arch) = asm_arch {
	24	// Inline assembly is currently only stable for these architectures.
	25	let is_stable = matches!(
	26	asm_arch,
	27	asm::InlineAsmArch::X86
	28	\| asm::InlineAsmArch::X86_64
	29	\| asm::InlineAsmArch::Arm
	30	\| asm::InlineAsmArch::AArch64
	31	\| asm::InlineAsmArch::RiscV32
	32	\| asm::InlineAsmArch::RiscV64
	33	);
	34	if !is_stable && !self.sess.features_untracked().asm_experimental_arch {
	35	feature_err(
	36	&self.sess.parse_sess,
	37	sym::asm_experimental_arch,
	38	sp,
	39	"inline assembly is not stable yet on this architecture",
	40	)
	41	.emit();
	42	}
	43	}
17df50a5 XL	44	if asm.options.contains(InlineAsmOptions::ATT_SYNTAX)
	45	&& !matches!(asm_arch, Some(asm::InlineAsmArch::X86 \| asm::InlineAsmArch::X86_64))
	46	&& !self.sess.opts.actually_rustdoc
	47	{
	48	self.sess
	49	.struct_span_err(sp, "the `att_syntax` option is only supported on x86")
	50	.emit();
	51	}
a2a8927a XL	52	if asm.options.contains(InlineAsmOptions::MAY_UNWIND)
	53	&& !self.sess.features_untracked().asm_unwind
	54	{
	55	feature_err(
	56	&self.sess.parse_sess,
	57	sym::asm_unwind,
	58	sp,
	59	"the `may_unwind` option is unstable",
	60	)
	61	.emit();
	62	}
17df50a5	63
3c0e092e	64	let mut clobber_abis = FxHashMap::default();
94222f64	65	if let Some(asm_arch) = asm_arch {
3c0e092e	66	for (abi_name, abi_span) in &asm.clobber_abis {
a2a8927a XL	67	match asm::InlineAsmClobberAbi::parse(
a2a8927a XL	68	asm_arch,
5099ac24	69	&self.sess.target_features,
a2a8927a XL	70	&self.sess.target,
	71	*abi_name,
	72	) {
3c0e092e XL	73	Ok(abi) => {
	74	// If the abi was already in the list, emit an error
	75	match clobber_abis.get(&abi) {
	76	Some((prev_name, prev_sp)) => {
	77	let mut err = self.sess.struct_span_err(
	78	*abi_span,
	79	&format!("`{}` ABI specified multiple times", prev_name),
	80	);
	81	err.span_label(*prev_sp, "previously specified here");
	82
	83	// Multiple different abi names may actually be the same ABI
	84	// If the specified ABIs are not the same name, alert the user that they resolve to the same ABI
	85	let source_map = self.sess.source_map();
	86	if source_map.span_to_snippet(*prev_sp)
	87	!= source_map.span_to_snippet(*abi_span)
	88	{
	89	err.note("these ABIs are equivalent on the current target");
	90	}
	91
	92	err.emit();
	93	}
	94	None => {
	95	clobber_abis.insert(abi, (abi_name, *abi_span));
	96	}
	97	}
	98	}
94222f64 XL	99	Err(&[]) => {
	100	self.sess
	101	.struct_span_err(
3c0e092e	102	*abi_span,
94222f64 XL	103	"`clobber_abi` is not supported on this target",
	104	)
	105	.emit();
	106	}
	107	Err(supported_abis) => {
	108	let mut err =
3c0e092e	109	self.sess.struct_span_err(*abi_span, "invalid ABI for `clobber_abi`");
94222f64 XL	110	let mut abis = format!("`{}`", supported_abis[0]);
	111	for m in &supported_abis[1..] {
	112	let _ = write!(abis, ", `{}`", m);
	113	}
	114	err.note(&format!(
	115	"the following ABIs are supported on this target: {}",
	116	abis
	117	));
	118	err.emit();
	119	}
	120	}
	121	}
	122	}
	123
17df50a5 XL	124	// Lower operands to HIR. We use dummy register classes if an error
	125	// occurs during lowering because we still need to be able to produce a
	126	// valid HIR.
	127	let sess = self.sess;
94222f64	128	let mut operands: Vec<_> = asm
17df50a5 XL	129	.operands
	130	.iter()
	131	.map(\|(op, op_sp)\| {
5099ac24	132	let lower_reg = \|reg, is_clobber\| match reg {
17df50a5 XL	133	InlineAsmRegOrRegClass::Reg(s) => {
	134	asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
	135	asm::InlineAsmReg::parse(
	136	asm_arch,
5099ac24	137	&sess.target_features,
17df50a5	138	&sess.target,
5099ac24	139	is_clobber,
17df50a5 XL	140	s,
	141	)
	142	.unwrap_or_else(\|e\| {
	143	let msg = format!("invalid register `{}`: {}", s.as_str(), e);
	144	sess.struct_span_err(*op_sp, &msg).emit();
	145	asm::InlineAsmReg::Err
	146	})
	147	} else {
	148	asm::InlineAsmReg::Err
	149	})
	150	}
	151	InlineAsmRegOrRegClass::RegClass(s) => {
	152	asm::InlineAsmRegOrRegClass::RegClass(if let Some(asm_arch) = asm_arch {
	153	asm::InlineAsmRegClass::parse(asm_arch, s).unwrap_or_else(\|e\| {
	154	let msg = format!("invalid register class `{}`: {}", s.as_str(), e);
	155	sess.struct_span_err(*op_sp, &msg).emit();
	156	asm::InlineAsmRegClass::Err
	157	})
	158	} else {
	159	asm::InlineAsmRegClass::Err
	160	})
	161	}
	162	};
	163
	164	let op = match *op {
	165	InlineAsmOperand::In { reg, ref expr } => hir::InlineAsmOperand::In {
5099ac24	166	reg: lower_reg(reg, false),
17df50a5 XL	167	expr: self.lower_expr_mut(expr),
	168	},
	169	InlineAsmOperand::Out { reg, late, ref expr } => hir::InlineAsmOperand::Out {
5099ac24	170	reg: lower_reg(reg, expr.is_none()),
17df50a5 XL	171	late,
	172	expr: expr.as_ref().map(\|expr\| self.lower_expr_mut(expr)),
	173	},
	174	InlineAsmOperand::InOut { reg, late, ref expr } => {
	175	hir::InlineAsmOperand::InOut {
5099ac24	176	reg: lower_reg(reg, false),
17df50a5 XL	177	late,
	178	expr: self.lower_expr_mut(expr),
	179	}
	180	}
	181	InlineAsmOperand::SplitInOut { reg, late, ref in_expr, ref out_expr } => {
	182	hir::InlineAsmOperand::SplitInOut {
5099ac24	183	reg: lower_reg(reg, false),
17df50a5 XL	184	late,
	185	in_expr: self.lower_expr_mut(in_expr),
	186	out_expr: out_expr.as_ref().map(\|expr\| self.lower_expr_mut(expr)),
	187	}
	188	}
3c0e092e XL	189	InlineAsmOperand::Const { ref anon_const } => {
	190	if !self.sess.features_untracked().asm_const {
	191	feature_err(
	192	&self.sess.parse_sess,
	193	sym::asm_const,
	194	*op_sp,
	195	"const operands for inline assembly are unstable",
	196	)
	197	.emit();
	198	}
	199	hir::InlineAsmOperand::Const {
	200	anon_const: self.lower_anon_const(anon_const),
	201	}
	202	}
17df50a5	203	InlineAsmOperand::Sym { ref expr } => {
3c0e092e XL	204	if !self.sess.features_untracked().asm_sym {
	205	feature_err(
	206	&self.sess.parse_sess,
	207	sym::asm_sym,
	208	*op_sp,
	209	"sym operands for inline assembly are unstable",
	210	)
	211	.emit();
	212	}
17df50a5 XL	213	hir::InlineAsmOperand::Sym { expr: self.lower_expr_mut(expr) }
	214	}
	215	};
94222f64	216	(op, self.lower_span(*op_sp))
17df50a5 XL	217	})
	218	.collect();
	219
	220	// Validate template modifiers against the register classes for the operands
	221	for p in &asm.template {
	222	if let InlineAsmTemplatePiece::Placeholder {
	223	operand_idx,
	224	modifier: Some(modifier),
	225	span: placeholder_span,
	226	} = *p
	227	{
	228	let op_sp = asm.operands[operand_idx].1;
	229	match &operands[operand_idx].0 {
	230	hir::InlineAsmOperand::In { reg, .. }
	231	\| hir::InlineAsmOperand::Out { reg, .. }
	232	\| hir::InlineAsmOperand::InOut { reg, .. }
	233	\| hir::InlineAsmOperand::SplitInOut { reg, .. } => {
	234	let class = reg.reg_class();
	235	if class == asm::InlineAsmRegClass::Err {
	236	continue;
	237	}
	238	let valid_modifiers = class.valid_modifiers(asm_arch.unwrap());
	239	if !valid_modifiers.contains(&modifier) {
	240	let mut err = sess.struct_span_err(
	241	placeholder_span,
	242	"invalid asm template modifier for this register class",
	243	);
	244	err.span_label(placeholder_span, "template modifier");
	245	err.span_label(op_sp, "argument");
	246	if !valid_modifiers.is_empty() {
	247	let mut mods = format!("`{}`", valid_modifiers[0]);
	248	for m in &valid_modifiers[1..] {
	249	let _ = write!(mods, ", `{}`", m);
	250	}
	251	err.note(&format!(
	252	"the `{}` register class supports \
	253	the following template modifiers: {}",
	254	class.name(),
	255	mods
	256	));
	257	} else {
	258	err.note(&format!(
	259	"the `{}` register class does not support template modifiers",
	260	class.name()
	261	));
	262	}
	263	err.emit();
	264	}
	265	}
	266	hir::InlineAsmOperand::Const { .. } => {
	267	let mut err = sess.struct_span_err(
	268	placeholder_span,
	269	"asm template modifiers are not allowed for `const` arguments",
	270	);
	271	err.span_label(placeholder_span, "template modifier");
	272	err.span_label(op_sp, "argument");
	273	err.emit();
	274	}
	275	hir::InlineAsmOperand::Sym { .. } => {
	276	let mut err = sess.struct_span_err(
	277	placeholder_span,
	278	"asm template modifiers are not allowed for `sym` arguments",
	279	);
	280	err.span_label(placeholder_span, "template modifier");
281	err.span_label(op_sp, "argument");
282	err.emit();
283	}
284	}
285	}
286	}
287
288	let mut used_input_regs = FxHashMap::default();
289	let mut used_output_regs = FxHashMap::default();
c295e0f8	290
17df50a5 XL	291	for (idx, &(ref op, op_sp)) in operands.iter().enumerate() {
17df50a5 XL	292	if let Some(reg) = op.reg() {
17df50a5 XL	293	let reg_class = reg.reg_class();
	294	if reg_class == asm::InlineAsmRegClass::Err {
	295	continue;
	296	}
	297
136023e0 XL	298	// Some register classes can only be used as clobbers. This
	299	// means that we disallow passing a value in/out of the asm and
	300	// require that the operand name an explicit register, not a
	301	// register class.
3c0e092e	302	if reg_class.is_clobber_only(asm_arch.unwrap()) && !op.is_clobber() {
136023e0 XL	303	let msg = format!(
	304	"register class `{}` can only be used as a clobber, \
	305	not as an input or output",
	306	reg_class.name()
	307	);
	308	sess.struct_span_err(op_sp, &msg).emit();
	309	continue;
	310	}
	311
17df50a5 XL	312	// Check for conflicts between explicit register operands.
	313	if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
	314	let (input, output) = match op {
	315	hir::InlineAsmOperand::In { .. } => (true, false),
	316
	317	// Late output do not conflict with inputs, but normal outputs do
	318	hir::InlineAsmOperand::Out { late, .. } => (!late, true),
	319
	320	hir::InlineAsmOperand::InOut { .. }
	321	\| hir::InlineAsmOperand::SplitInOut { .. } => (true, true),
	322
	323	hir::InlineAsmOperand::Const { .. } \| hir::InlineAsmOperand::Sym { .. } => {
	324	unreachable!()
	325	}
	326	};
	327
	328	// Flag to output the error only once per operand
	329	let mut skip = false;
	330	reg.overlapping_regs(\|r\| {
	331	let mut check = \|used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
	332	input\| {
	333	match used_regs.entry(r) {
	334	Entry::Occupied(o) => {
	335	if skip {
	336	return;
	337	}
	338	skip = true;
	339
	340	let idx2 = *o.get();
	341	let &(ref op2, op_sp2) = &operands[idx2];
	342	let reg2 = match op2.reg() {
	343	Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
	344	_ => unreachable!(),
	345	};
	346
	347	let msg = format!(
	348	"register `{}` conflicts with register `{}`",
	349	reg.name(),
	350	reg2.name()
	351	);
	352	let mut err = sess.struct_span_err(op_sp, &msg);
	353	err.span_label(op_sp, &format!("register `{}`", reg.name()));
	354	err.span_label(op_sp2, &format!("register `{}`", reg2.name()));
	355
	356	match (op, op2) {
	357	(
	358	hir::InlineAsmOperand::In { .. },
	359	hir::InlineAsmOperand::Out { late, .. },
	360	)
	361	\| (
	362	hir::InlineAsmOperand::Out { late, .. },
	363	hir::InlineAsmOperand::In { .. },
	364	) => {
	365	assert!(!*late);
	366	let out_op_sp = if input { op_sp2 } else { op_sp };
	367	let msg = "use `lateout` instead of \
	368	`out` to avoid conflict";
	369	err.span_help(out_op_sp, msg);
	370	}
	371	_ => {}
	372	}
	373
	374	err.emit();
	375	}
376	Entry::Vacant(v) => {
5099ac24 FG	377	if r == reg {
	378	v.insert(idx);
	379	}
17df50a5 XL	380	}
	381	}
	382	};
	383	if input {
	384	check(&mut used_input_regs, true);
	385	}
	386	if output {
	387	check(&mut used_output_regs, false);
	388	}
	389	});
	390	}
	391	}
	392	}
	393
94222f64 XL	394	// If a clobber_abi is specified, add the necessary clobbers to the
94222f64 XL	395	// operands list.
3c0e092e XL	396	let mut clobbered = FxHashSet::default();
3c0e092e XL	397	for (abi, (_, abi_span)) in clobber_abis {
94222f64	398	for &clobber in abi.clobbered_regs() {
3c0e092e XL	399	// Don't emit a clobber for a register already clobbered
	400	if clobbered.contains(&clobber) {
	401	continue;
	402	}
	403
94222f64 XL	404	let mut output_used = false;
	405	clobber.overlapping_regs(\|reg\| {
	406	if used_output_regs.contains_key(&reg) {
	407	output_used = true;
	408	}
	409	});
	410
	411	if !output_used {
	412	operands.push((
	413	hir::InlineAsmOperand::Out {
	414	reg: asm::InlineAsmRegOrRegClass::Reg(clobber),
	415	late: true,
	416	expr: None,
	417	},
	418	self.lower_span(abi_span),
	419	));
3c0e092e	420	clobbered.insert(clobber);
94222f64 XL	421	}
	422	}
	423	}
	424
17df50a5 XL	425	let operands = self.arena.alloc_from_iter(operands);
17df50a5 XL	426	let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
94222f64 XL	427	let template_strs = self.arena.alloc_from_iter(
	428	asm.template_strs
	429	.iter()
	430	.map(\|(sym, snippet, span)\| (sym, snippet, self.lower_span(*span))),
	431	);
	432	let line_spans =
	433	self.arena.alloc_from_iter(asm.line_spans.iter().map(\|span\| self.lower_span(*span)));
	434	let hir_asm =
	435	hir::InlineAsm { template, template_strs, operands, options: asm.options, line_spans };
17df50a5 XL	436	self.arena.alloc(hir_asm)
	437	}
	438	}