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0731742a XL |
1 | // Targets the Cortex-M33 processor (Armv8-M Mainline architecture profile), |
2 | // with the Floating Point extension. | |
3 | ||
29967ef6 | 4 | use crate::spec::{Target, TargetOptions}; |
0731742a | 5 | |
29967ef6 XL |
6 | pub fn target() -> Target { |
7 | Target { | |
0731742a | 8 | llvm_target: "thumbv8m.main-none-eabihf".to_string(), |
29967ef6 | 9 | pointer_width: 32, |
416331ca | 10 | data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".to_string(), |
0731742a | 11 | arch: "arm".to_string(), |
0731742a XL |
12 | |
13 | options: TargetOptions { | |
136023e0 | 14 | abi: "eabihf".to_string(), |
0731742a XL |
15 | // If the Floating Point extension is implemented in the Cortex-M33 |
16 | // processor, the Cortex-M33 Technical Reference Manual states that | |
17 | // the FPU uses the FPv5 architecture, single-precision instructions | |
18 | // and 16 D registers. | |
19 | // These parameters map to the following LLVM features. | |
416331ca | 20 | features: "+fp-armv8,-fp64,-d32".to_string(), |
0731742a | 21 | max_atomic_width: Some(32), |
dfeec247 | 22 | ..super::thumb_base::opts() |
0731742a | 23 | }, |
29967ef6 | 24 | } |
0731742a | 25 | } |