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1/*
2 * common defines for all CPUs
5fafdf24 3 *
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4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 */
19#ifndef CPU_DEFS_H
20#define CPU_DEFS_H
21
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22#ifndef NEED_CPU_H
23#error cpu.h included from common code
24#endif
25
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26#include "config.h"
27#include <setjmp.h>
ed1c0bcb 28#include <inttypes.h>
be214e6c 29#include <signal.h>
ed1c0bcb 30#include "osdep.h"
72cf2d4f 31#include "qemu-queue.h"
a8170e5e 32#include "hwaddr.h"
ab93bbe2 33
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34#ifndef TARGET_LONG_BITS
35#error TARGET_LONG_BITS must be defined before including this header
36#endif
37
38#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
39
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40typedef int16_t target_short __attribute__ ((aligned(TARGET_SHORT_ALIGNMENT)));
41typedef uint16_t target_ushort __attribute__((aligned(TARGET_SHORT_ALIGNMENT)));
42typedef int32_t target_int __attribute__((aligned(TARGET_INT_ALIGNMENT)));
43typedef uint32_t target_uint __attribute__((aligned(TARGET_INT_ALIGNMENT)));
44typedef int64_t target_llong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
45typedef uint64_t target_ullong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
ab6d960f 46/* target_ulong is the type of a virtual address */
35b66fc4 47#if TARGET_LONG_SIZE == 4
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48typedef int32_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
49typedef uint32_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
c27004ec 50#define TARGET_FMT_lx "%08x"
b62b461b 51#define TARGET_FMT_ld "%d"
71c8b8fd 52#define TARGET_FMT_lu "%u"
35b66fc4 53#elif TARGET_LONG_SIZE == 8
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54typedef int64_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
55typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
26a76461 56#define TARGET_FMT_lx "%016" PRIx64
b62b461b 57#define TARGET_FMT_ld "%" PRId64
71c8b8fd 58#define TARGET_FMT_lu "%" PRIu64
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59#else
60#error TARGET_LONG_SIZE undefined
61#endif
62
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63#define EXCP_INTERRUPT 0x10000 /* async interruption */
64#define EXCP_HLT 0x10001 /* hlt instruction reached */
65#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
5a1e3cfc 66#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
ab93bbe2 67
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68#define TB_JMP_CACHE_BITS 12
69#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
70
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71/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
72 addresses on the same page. The top bits are the same. This allows
73 TLB invalidation to quickly clear a subset of the hash table. */
74#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
75#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
76#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
77#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
78
20cb400d 79#if !defined(CONFIG_USER_ONLY)
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80#define CPU_TLB_BITS 8
81#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
ab93bbe2 82
355b1943 83#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
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84#define CPU_TLB_ENTRY_BITS 4
85#else
86#define CPU_TLB_ENTRY_BITS 5
87#endif
88
ab93bbe2 89typedef struct CPUTLBEntry {
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90 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
91 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
92 go directly to ram.
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93 bit 3 : indicates that the entry is invalid
94 bit 2..0 : zero
95 */
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96 target_ulong addr_read;
97 target_ulong addr_write;
98 target_ulong addr_code;
355b1943 99 /* Addend to virtual address to get host address. IO accesses
ee50add9 100 use the corresponding iotlb value. */
3b2992e4 101 uintptr_t addend;
d656469f 102 /* padding to get a power of two size */
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103 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
104 (sizeof(target_ulong) * 3 +
105 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
106 sizeof(uintptr_t))];
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107} CPUTLBEntry;
108
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109extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
110
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111#define CPU_COMMON_TLB \
112 /* The meaning of the MMU modes is defined in the target code. */ \
113 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
a8170e5e 114 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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115 target_ulong tlb_flush_addr; \
116 target_ulong tlb_flush_mask;
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117
118#else
119
120#define CPU_COMMON_TLB
121
122#endif
123
124
e2542fe2 125#ifdef HOST_WORDS_BIGENDIAN
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126typedef struct icount_decr_u16 {
127 uint16_t high;
128 uint16_t low;
129} icount_decr_u16;
130#else
131typedef struct icount_decr_u16 {
132 uint16_t low;
133 uint16_t high;
134} icount_decr_u16;
135#endif
136
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137struct kvm_run;
138struct KVMState;
e82bcec2 139struct qemu_work_item;
7ba1e619 140
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141typedef struct CPUBreakpoint {
142 target_ulong pc;
143 int flags; /* BP_* */
72cf2d4f 144 QTAILQ_ENTRY(CPUBreakpoint) entry;
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145} CPUBreakpoint;
146
147typedef struct CPUWatchpoint {
148 target_ulong vaddr;
149 target_ulong len_mask;
150 int flags; /* BP_* */
72cf2d4f 151 QTAILQ_ENTRY(CPUWatchpoint) entry;
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152} CPUWatchpoint;
153
a20e31dc 154#define CPU_TEMP_BUF_NLONGS 128
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155#define CPU_COMMON \
156 struct TranslationBlock *current_tb; /* currently executing TB */ \
157 /* soft mmu support */ \
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158 /* in order to avoid passing too many arguments to the MMIO \
159 helpers, we store some rarely used information in the CPU \
a316d335 160 context) */ \
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161 uintptr_t mem_io_pc; /* host pc at which the memory was \
162 accessed */ \
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163 target_ulong mem_io_vaddr; /* target virtual addr at which the \
164 memory was accessed */ \
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165 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
166 uint32_t interrupt_request; \
be214e6c 167 volatile sig_atomic_t exit_request; \
20cb400d 168 CPU_COMMON_TLB \
a316d335 169 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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170 /* buffer for temporaries in the code generator */ \
171 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
a316d335 172 \
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173 int64_t icount_extra; /* Instructions until next timer event. */ \
174 /* Number of cycles left, with interrupt flag in high bit. \
175 This allows a single read-compare-cbranch-write sequence to test \
176 for both decrementer underflow and exceptions. */ \
177 union { \
178 uint32_t u32; \
179 icount_decr_u16 u16; \
180 } icount_decr; \
181 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
182 \
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183 /* from this point: preserved by CPU reset */ \
184 /* ice debug support */ \
72cf2d4f 185 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
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186 int singlestep_enabled; \
187 \
72cf2d4f 188 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
a1d1bb31 189 CPUWatchpoint *watchpoint_hit; \
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190 \
191 struct GDBRegisterState *gdb_regs; \
6658ffb8 192 \
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193 /* Core interrupt code */ \
194 jmp_buf jmp_env; \
acb6685f 195 int exception_index; \
9133e39b 196 \
9349b4f9 197 CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
6a00d601 198 int cpu_index; /* CPU index (informative) */ \
1e9fa730 199 uint32_t host_tid; /* host thread ID */ \
268a362c 200 int numa_node; /* NUMA node this cpu is belonging to */ \
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201 int nr_cores; /* number of cores within this CPU package */ \
202 int nr_threads;/* number of threads within this CPU */ \
d5975363 203 int running; /* Nonzero if cpu is currently running(usermode). */ \
dc7a09cf 204 int thread_id; \
a316d335 205 /* user data */ \
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206 void *opaque; \
207 \
d6dc3d42 208 uint32_t created; \
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209 uint32_t stop; /* Stop request */ \
210 uint32_t stopped; /* Artificially stopped */ \
d6dc3d42 211 struct QemuCond *halt_cond; \
e82bcec2 212 struct qemu_work_item *queued_work_first, *queued_work_last; \
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213 const char *cpu_model_str; \
214 struct KVMState *kvm_state; \
215 struct kvm_run *kvm_run; \
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216 int kvm_fd; \
217 int kvm_vcpu_dirty;
a316d335 218
ab93bbe2 219#endif