[mirror_qemu.git] / cpu-exec.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#ifdef TARGET_I386
#include "exec-i386.h"
#endif
#ifdef TARGET_ARM
#include "exec-arm.h"
#endif

#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

#if defined(TARGET_ARM)
/* XXX: unify with i386 target */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}
#endif

/* main execution loop */

int cpu_exec(CPUState *env1)
{
    int saved_T0, saved_T1, saved_T2;
    CPUState *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
#ifdef __sparc__
    int saved_i7, tmp_T0;
#endif
    int code_gen_size, ret, interrupt_request;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;

    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_T2 = T2;
    saved_env = env;
    env = env1;
#ifdef __sparc__
    /* we also save i7 because longjmp may not restore it */
    asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
#endif

#if defined(TARGET_I386)
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
    {
        unsigned int psr;
        psr = env->cpsr;
        env->CF = (psr >> 29) & 1;
        env->NZF = (psr & 0xc0000000) ^ 0x40000000;
        env->VF = (psr << 3) & 0x80000000;
        env->cpsr = psr & ~0xf0000000;
    }
#else
#error unsupported target CPU
#endif
    env->exception_index = -1;

    /* prepare setjmp context for exception handling */
    for(;;) {
        if (setjmp(env->jmp_env) == 0) {
            /* if an exception is pending, we execute it here */
            if (env->exception_index >= 0) {
                if (env->exception_index >= EXCP_INTERRUPT) {
                    /* exit request from the cpu execution loop */
                    ret = env->exception_index;
                    break;
                } else if (env->user_mode_only) {
                    /* if user mode only, we simulate a fake exception
                       which will be hanlded outside the cpu execution
                       loop */
#if defined(TARGET_I386)
                    do_interrupt_user(env->exception_index, 
                                      env->exception_is_int, 
                                      env->error_code, 
                                      env->exception_next_eip);
#endif
                    ret = env->exception_index;
                    break;
                } else {
#if defined(TARGET_I386)
                    /* simulate a real cpu exception. On i386, it can
                       trigger new exceptions, but we do not handle
                       double or triple faults yet. */
                    do_interrupt(env->exception_index, 
                                 env->exception_is_int, 
                                 env->error_code, 
                                 env->exception_next_eip, 0);
#endif
                }
                env->exception_index = -1;
            }
            T0 = 0; /* force lookup of first TB */
            for(;;) {
#ifdef __sparc__
                /* g1 can be modified by some libc? functions */ 
                tmp_T0 = T0;
#endif	    
                interrupt_request = env->interrupt_request;
                if (__builtin_expect(interrupt_request, 0)) {
#if defined(TARGET_I386)
                    /* if hardware interrupt pending, we execute it */
                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&
                        (env->eflags & IF_MASK) && 
                        !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
                        int intno;
                        intno = cpu_x86_get_pic_interrupt(env);
                        if (loglevel) {
                            fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
                        }
                        do_interrupt(intno, 0, 0, 0, 1);
                        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
                        /* ensure that no TB jump will be modified as
                           the program flow was changed */
#ifdef __sparc__
                        tmp_T0 = 0;
#else
                        T0 = 0;
#endif
                    }
#endif
                    if (interrupt_request & CPU_INTERRUPT_EXIT) {
                        env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
                        env->exception_index = EXCP_INTERRUPT;
                        cpu_loop_exit();
                    }
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
#if defined(TARGET_I386)
                    /* restore flags in standard format */
                    env->regs[R_EAX] = EAX;
                    env->regs[R_EBX] = EBX;
                    env->regs[R_ECX] = ECX;
                    env->regs[R_EDX] = EDX;
                    env->regs[R_ESI] = ESI;
                    env->regs[R_EDI] = EDI;
                    env->regs[R_EBP] = EBP;
                    env->regs[R_ESP] = ESP;
                    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                    cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
                    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
                    env->cpsr = compute_cpsr();
                    cpu_arm_dump_state(env, logfile, 0);
                    env->cpsr &= ~0xf0000000;
#else
#error unsupported target CPU 
#endif
                }
#endif
                /* we record a subset of the CPU state. It will
                   always be the same before a given translated block
                   is executed. */
#if defined(TARGET_I386)
                flags = env->hflags;
                flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
                cs_base = env->segs[R_CS].base;
                pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
                flags = 0;
                cs_base = 0;
                pc = (uint8_t *)env->regs[15];
#else
#error unsupported CPU
#endif
                tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                             flags);
                if (!tb) {
                    spin_lock(&tb_lock);
                    /* if no translated code available, then translate it now */
                    tb = tb_alloc((unsigned long)pc);
                    if (!tb) {
                        /* flush must be done */
                        tb_flush();
                        /* cannot fail at this point */
                        tb = tb_alloc((unsigned long)pc);
                        /* don't forget to invalidate previous TB info */
                        ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                        T0 = 0;
                    }
                    tc_ptr = code_gen_ptr;
                    tb->tc_ptr = tc_ptr;
                    tb->cs_base = (unsigned long)cs_base;
                    tb->flags = flags;
                    cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
                    *ptb = tb;
                    tb->hash_next = NULL;
                    tb_link(tb);
                    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                    spin_unlock(&tb_lock);
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
                    fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
                            (long)tb->tc_ptr, (long)tb->pc,
                            lookup_symbol((void *)tb->pc));
                }
#endif
#ifdef __sparc__
                T0 = tmp_T0;
#endif	    
                /* see if we can patch the calling TB. */
                if (T0 != 0) {
                    spin_lock(&tb_lock);
                    tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                    spin_unlock(&tb_lock);
                }
                tc_ptr = tb->tc_ptr;
                env->current_tb = tb;
                /* execute the generated code */
                gen_func = (void *)tc_ptr;
#if defined(__sparc__)
                __asm__ __volatile__("call	%0\n\t"
                                     "mov	%%o7,%%i0"
                                     : /* no outputs */
                                     : "r" (gen_func) 
                                     : "i0", "i1", "i2", "i3", "i4", "i5");
#elif defined(__arm__)
                asm volatile ("mov pc, %0\n\t"
                              ".global exec_loop\n\t"
                              "exec_loop:\n\t"
                              : /* no outputs */
                              : "r" (gen_func)
                              : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
#else
                gen_func();
#endif
                env->current_tb = NULL;
                /* reset soft MMU for next block (it can currently
                   only be set by a memory fault) */
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
                if (env->hflags & HF_SOFTMMU_MASK) {
                    env->hflags &= ~HF_SOFTMMU_MASK;
                    /* do not allow linking to another block */
                    T0 = 0;
                }
#endif
            }
        } else {
        }
    } /* for(;;) */


#if defined(TARGET_I386)
    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
#elif defined(TARGET_ARM)
    env->cpsr = compute_cpsr();
#else
#error unsupported target CPU
#endif
#ifdef __sparc__
    asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    T2 = saved_T2;
    env = saved_env;
    return ret;
}

#if defined(TARGET_I386)

void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
        selector &= 0xffff;
        cpu_x86_load_seg_cache(env, seg_reg, selector, 
                               (uint8_t *)(selector << 4), 0xffff, 0);
    } else {
        load_seg(seg_reg, selector, 0);
    }
    env = saved_env;
}

void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_fsave(ptr, data32);

    env = saved_env;
}

void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_frstor(ptr, data32);

    env = saved_env;
}

#endif /* TARGET_I386 */

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

#if defined(TARGET_I386)

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    TranslationBlock *tb;
    int ret;

    if (cpu_single_env)
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    /* see if it is an MMU fault */
    ret = cpu_x86_handle_mmu_fault(env, address, is_write);
    if (ret < 0)
        return 0; /* not an MMU fault */
    if (ret == 0)
        return 1; /* the MMU fault was handled without causing real CPU fault */
    /* now we have a real cpu fault */
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        cpu_restore_state(tb, env, pc);
    }
    if (ret == 1) {
#if 0
        printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", 
               env->eip, env->cr[2], env->error_code);
#endif
        /* we restore the process signal mask as the sigreturn should
           do it (XXX: use sigsetjmp) */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        raise_exception_err(EXCP0E_PAGE, env->error_code);
    } else {
        /* activate soft MMU for this block */
        env->hflags |= HF_SOFTMMU_MASK;
        sigprocmask(SIG_SETMASK, old_set, NULL);
        cpu_loop_exit();
    }
    /* never comes here */
    return 1;
}

#elif defined(TARGET_ARM)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    /* XXX: do more */
    return 0;
}
#else
#error unsupported target CPU
#endif

#if defined(__i386__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: // stw
    case 0x0e: // stb
    case 0x0f: // stq_u
    case 0x24: // stf
    case 0x25: // stg
    case 0x26: // sts
    case 0x27: // stt
    case 0x2c: // stl
    case 0x2d: // stq
    case 0x2e: // stl_c
    case 0x2f: // stq_c
	is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    unsigned long pc;
    int is_write;
    uint32_t insn;
    
    /* XXX: is there a standard glibc define ? */
    pc = regs[1];
    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
      switch((insn >> 19) & 0x3f) {
      case 0x05: // stb
      case 0x06: // sth
      case 0x04: // st
      case 0x07: // std
      case 0x24: // stf
      case 0x27: // stdf
      case 0x25: // stfsr
	is_write = 1;
	break;
      }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, sigmask);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[R15];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#elif defined(__mc68000)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[16];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d	19	*/
e4533c7a FB	20	#include "config.h"
e4533c7a FB	21	#ifdef TARGET_I386
7d13299d	22	#include "exec-i386.h"
e4533c7a FB	23	#endif
	24	#ifdef TARGET_ARM
	25	#include "exec-arm.h"
	26	#endif
	27
956034d7	28	#include "disas.h"
7d13299d	29
dc99065b	30	//#define DEBUG_EXEC
9de5e440	31	//#define DEBUG_SIGNAL
7d13299d	32
e4533c7a FB	33	#if defined(TARGET_ARM)
	34	/* XXX: unify with i386 target */
	35	void cpu_loop_exit(void)
	36	{
	37	longjmp(env->jmp_env, 1);
	38	}
	39	#endif
	40
7d13299d FB	41	/* main execution loop */
7d13299d FB	42
e4533c7a	43	int cpu_exec(CPUState *env1)
7d13299d	44	{
e4533c7a FB	45	int saved_T0, saved_T1, saved_T2;
e4533c7a FB	46	CPUState *saved_env;
04369ff2 FB	47	#ifdef reg_EAX
	48	int saved_EAX;
	49	#endif
	50	#ifdef reg_ECX
	51	int saved_ECX;
	52	#endif
	53	#ifdef reg_EDX
	54	int saved_EDX;
	55	#endif
	56	#ifdef reg_EBX
	57	int saved_EBX;
	58	#endif
	59	#ifdef reg_ESP
	60	int saved_ESP;
	61	#endif
	62	#ifdef reg_EBP
	63	int saved_EBP;
	64	#endif
	65	#ifdef reg_ESI
	66	int saved_ESI;
	67	#endif
	68	#ifdef reg_EDI
	69	int saved_EDI;
8c6939c0 FB	70	#endif
	71	#ifdef __sparc__
	72	int saved_i7, tmp_T0;
04369ff2	73	#endif
68a79315	74	int code_gen_size, ret, interrupt_request;
7d13299d	75	void (*gen_func)(void);
9de5e440	76	TranslationBlock tb, *ptb;
dab2ed99	77	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	78	unsigned int flags;
8c6939c0	79
7d13299d FB	80	/* first we save global registers */
	81	saved_T0 = T0;
	82	saved_T1 = T1;
e4533c7a	83	saved_T2 = T2;
7d13299d FB	84	saved_env = env;
7d13299d FB	85	env = env1;
e4533c7a FB	86	#ifdef __sparc__
	87	/* we also save i7 because longjmp may not restore it */
	88	asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
	89	#endif
	90
	91	#if defined(TARGET_I386)
04369ff2 FB	92	#ifdef reg_EAX
	93	saved_EAX = EAX;
	94	EAX = env->regs[R_EAX];
	95	#endif
	96	#ifdef reg_ECX
	97	saved_ECX = ECX;
	98	ECX = env->regs[R_ECX];
	99	#endif
	100	#ifdef reg_EDX
	101	saved_EDX = EDX;
	102	EDX = env->regs[R_EDX];
	103	#endif
	104	#ifdef reg_EBX
	105	saved_EBX = EBX;
	106	EBX = env->regs[R_EBX];
	107	#endif
	108	#ifdef reg_ESP
	109	saved_ESP = ESP;
	110	ESP = env->regs[R_ESP];
	111	#endif
	112	#ifdef reg_EBP
	113	saved_EBP = EBP;
	114	EBP = env->regs[R_EBP];
	115	#endif
	116	#ifdef reg_ESI
	117	saved_ESI = ESI;
	118	ESI = env->regs[R_ESI];
	119	#endif
	120	#ifdef reg_EDI
	121	saved_EDI = EDI;
	122	EDI = env->regs[R_EDI];
	123	#endif
7d13299d	124
9de5e440	125	/* put eflags in CPU temporary format */
fc2b4c48 FB	126	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	127	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	128	CC_OP = CC_OP_EFLAGS;
fc2b4c48	129	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a FB	130	#elif defined(TARGET_ARM)
	131	{
	132	unsigned int psr;
	133	psr = env->cpsr;
	134	env->CF = (psr >> 29) & 1;
	135	env->NZF = (psr & 0xc0000000) ^ 0x40000000;
	136	env->VF = (psr << 3) & 0x80000000;
	137	env->cpsr = psr & ~0xf0000000;
	138	}
	139	#else
	140	#error unsupported target CPU
	141	#endif
3fb2ded1	142	env->exception_index = -1;
9d27abd9	143
7d13299d	144	/* prepare setjmp context for exception handling */
3fb2ded1 FB	145	for(;;) {
	146	if (setjmp(env->jmp_env) == 0) {
	147	/* if an exception is pending, we execute it here */
	148	if (env->exception_index >= 0) {
	149	if (env->exception_index >= EXCP_INTERRUPT) {
	150	/* exit request from the cpu execution loop */
	151	ret = env->exception_index;
	152	break;
	153	} else if (env->user_mode_only) {
	154	/* if user mode only, we simulate a fake exception
	155	which will be hanlded outside the cpu execution
	156	loop */
83479e77	157	#if defined(TARGET_I386)
3fb2ded1 FB	158	do_interrupt_user(env->exception_index,
	159	env->exception_is_int,
	160	env->error_code,
	161	env->exception_next_eip);
83479e77	162	#endif
3fb2ded1 FB	163	ret = env->exception_index;
	164	break;
	165	} else {
83479e77	166	#if defined(TARGET_I386)
3fb2ded1 FB	167	/* simulate a real cpu exception. On i386, it can
	168	trigger new exceptions, but we do not handle
	169	double or triple faults yet. */
	170	do_interrupt(env->exception_index,
	171	env->exception_is_int,
	172	env->error_code,
d05e66d2	173	env->exception_next_eip, 0);
83479e77	174	#endif
3fb2ded1 FB	175	}
	176	env->exception_index = -1;
	177	}
3fb2ded1 FB	178	T0 = 0; /* force lookup of first TB */
3fb2ded1 FB	179	for(;;) {
8c6939c0	180	#ifdef __sparc__
3fb2ded1 FB	181	/* g1 can be modified by some libc? functions */
3fb2ded1 FB	182	tmp_T0 = T0;
8c6939c0	183	#endif
68a79315	184	interrupt_request = env->interrupt_request;
2e255c6b	185	if (__builtin_expect(interrupt_request, 0)) {
68a79315 FB	186	#if defined(TARGET_I386)
	187	/* if hardware interrupt pending, we execute it */
	188	if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316 FB	189	(env->eflags & IF_MASK) &&
3f337316 FB	190	!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 FB	191	int intno;
	192	intno = cpu_x86_get_pic_interrupt(env);
	193	if (loglevel) {
	194	fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
	195	}
d05e66d2	196	do_interrupt(intno, 0, 0, 0, 1);
68a79315	197	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
907a5b26 FB	198	/* ensure that no TB jump will be modified as
	199	the program flow was changed */
	200	#ifdef __sparc__
	201	tmp_T0 = 0;
	202	#else
	203	T0 = 0;
	204	#endif
68a79315 FB	205	}
	206	#endif
	207	if (interrupt_request & CPU_INTERRUPT_EXIT) {
	208	env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
	209	env->exception_index = EXCP_INTERRUPT;
	210	cpu_loop_exit();
	211	}
3fb2ded1	212	}
7d13299d	213	#ifdef DEBUG_EXEC
3fb2ded1	214	if (loglevel) {
e4533c7a	215	#if defined(TARGET_I386)
3fb2ded1 FB	216	/* restore flags in standard format */
	217	env->regs[R_EAX] = EAX;
	218	env->regs[R_EBX] = EBX;
	219	env->regs[R_ECX] = ECX;
	220	env->regs[R_EDX] = EDX;
	221	env->regs[R_ESI] = ESI;
	222	env->regs[R_EDI] = EDI;
	223	env->regs[R_EBP] = EBP;
	224	env->regs[R_ESP] = ESP;
	225	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
68a79315	226	cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
3fb2ded1	227	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a	228	#elif defined(TARGET_ARM)
1b21b62a	229	env->cpsr = compute_cpsr();
3fb2ded1	230	cpu_arm_dump_state(env, logfile, 0);
1b21b62a	231	env->cpsr &= ~0xf0000000;
e4533c7a FB	232	#else
	233	#error unsupported target CPU
	234	#endif
3fb2ded1	235	}
7d13299d	236	#endif
3f337316 FB	237	/* we record a subset of the CPU state. It will
	238	always be the same before a given translated block
	239	is executed. */
e4533c7a	240	#if defined(TARGET_I386)
2e255c6b	241	flags = env->hflags;
3f337316	242	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
3fb2ded1 FB	243	cs_base = env->segs[R_CS].base;
3fb2ded1 FB	244	pc = cs_base + env->eip;
e4533c7a	245	#elif defined(TARGET_ARM)
3fb2ded1 FB	246	flags = 0;
	247	cs_base = 0;
	248	pc = (uint8_t *)env->regs[15];
e4533c7a FB	249	#else
	250	#error unsupported CPU
	251	#endif
3fb2ded1 FB	252	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
3fb2ded1 FB	253	flags);
d4e8164f	254	if (!tb) {
3fb2ded1 FB	255	spin_lock(&tb_lock);
3fb2ded1 FB	256	/* if no translated code available, then translate it now */
d4e8164f	257	tb = tb_alloc((unsigned long)pc);
3fb2ded1 FB	258	if (!tb) {
	259	/* flush must be done */
	260	tb_flush();
	261	/* cannot fail at this point */
	262	tb = tb_alloc((unsigned long)pc);
	263	/* don't forget to invalidate previous TB info */
	264	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	265	T0 = 0;
	266	}
	267	tc_ptr = code_gen_ptr;
	268	tb->tc_ptr = tc_ptr;
	269	tb->cs_base = (unsigned long)cs_base;
	270	tb->flags = flags;
facc68be	271	cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
3fb2ded1 FB	272	*ptb = tb;
	273	tb->hash_next = NULL;
	274	tb_link(tb);
	275	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
25eb4484	276	spin_unlock(&tb_lock);
9de5e440	277	}
9d27abd9	278	#ifdef DEBUG_EXEC
3fb2ded1 FB	279	if (loglevel) {
	280	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	281	(long)tb->tc_ptr, (long)tb->pc,
	282	lookup_symbol((void *)tb->pc));
	283	}
9d27abd9	284	#endif
8c6939c0	285	#ifdef __sparc__
3fb2ded1	286	T0 = tmp_T0;
8c6939c0	287	#endif
facc68be FB	288	/* see if we can patch the calling TB. */
facc68be FB	289	if (T0 != 0) {
3fb2ded1 FB	290	spin_lock(&tb_lock);
	291	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
	292	spin_unlock(&tb_lock);
	293	}
3fb2ded1	294	tc_ptr = tb->tc_ptr;
83479e77	295	env->current_tb = tb;
3fb2ded1 FB	296	/* execute the generated code */
3fb2ded1 FB	297	gen_func = (void *)tc_ptr;
8c6939c0	298	#if defined(__sparc__)
3fb2ded1 FB	299	__asm__ __volatile__("call %0\n\t"
	300	"mov %%o7,%%i0"
	301	: /* no outputs */
	302	: "r" (gen_func)
	303	: "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0	304	#elif defined(__arm__)
3fb2ded1 FB	305	asm volatile ("mov pc, %0\n\t"
	306	".global exec_loop\n\t"
	307	"exec_loop:\n\t"
	308	: /* no outputs */
	309	: "r" (gen_func)
	310	: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
ae228531	311	#else
3fb2ded1	312	gen_func();
ae228531	313	#endif
83479e77	314	env->current_tb = NULL;
4cbf74b6 FB	315	/* reset soft MMU for next block (it can currently
	316	only be set by a memory fault) */
	317	#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316 FB	318	if (env->hflags & HF_SOFTMMU_MASK) {
3f337316 FB	319	env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6 FB	320	/* do not allow linking to another block */
	321	T0 = 0;
	322	}
	323	#endif
3fb2ded1 FB	324	}
3fb2ded1 FB	325	} else {
7d13299d	326	}
3fb2ded1 FB	327	} /* for(;;) */
3fb2ded1 FB	328
7d13299d	329
e4533c7a	330	#if defined(TARGET_I386)
9de5e440	331	/* restore flags in standard format */
fc2b4c48	332	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	333
7d13299d	334	/* restore global registers */
04369ff2 FB	335	#ifdef reg_EAX
	336	EAX = saved_EAX;
	337	#endif
	338	#ifdef reg_ECX
	339	ECX = saved_ECX;
	340	#endif
	341	#ifdef reg_EDX
	342	EDX = saved_EDX;
	343	#endif
	344	#ifdef reg_EBX
	345	EBX = saved_EBX;
	346	#endif
	347	#ifdef reg_ESP
	348	ESP = saved_ESP;
	349	#endif
	350	#ifdef reg_EBP
	351	EBP = saved_EBP;
	352	#endif
	353	#ifdef reg_ESI
	354	ESI = saved_ESI;
	355	#endif
	356	#ifdef reg_EDI
	357	EDI = saved_EDI;
8c6939c0	358	#endif
e4533c7a	359	#elif defined(TARGET_ARM)
1b21b62a	360	env->cpsr = compute_cpsr();
e4533c7a FB	361	#else
	362	#error unsupported target CPU
	363	#endif
8c6939c0 FB	364	#ifdef __sparc__
8c6939c0 FB	365	asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2	366	#endif
7d13299d FB	367	T0 = saved_T0;
7d13299d FB	368	T1 = saved_T1;
e4533c7a	369	T2 = saved_T2;
7d13299d FB	370	env = saved_env;
	371	return ret;
	372	}
6dbad63e	373
e4533c7a FB	374	#if defined(TARGET_I386)
e4533c7a FB	375
6dbad63e FB	376	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	377	{
	378	CPUX86State *saved_env;
	379
	380	saved_env = env;
	381	env = s;
a412ac57	382	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
a513fe19	383	selector &= 0xffff;
2e255c6b FB	384	cpu_x86_load_seg_cache(env, seg_reg, selector,
2e255c6b FB	385	(uint8_t *)(selector << 4), 0xffff, 0);
a513fe19 FB	386	} else {
	387	load_seg(seg_reg, selector, 0);
	388	}
6dbad63e FB	389	env = saved_env;
6dbad63e FB	390	}
9de5e440	391
d0a1ffc9 FB	392	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32)
	393	{
	394	CPUX86State *saved_env;
	395
	396	saved_env = env;
	397	env = s;
	398
	399	helper_fsave(ptr, data32);
	400
	401	env = saved_env;
	402	}
	403
	404	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32)
	405	{
	406	CPUX86State *saved_env;
	407
	408	saved_env = env;
	409	env = s;
	410
	411	helper_frstor(ptr, data32);
	412
	413	env = saved_env;
	414	}
	415
e4533c7a FB	416	#endif /* TARGET_I386 */
e4533c7a FB	417
9de5e440 FB	418	#undef EAX
	419	#undef ECX
	420	#undef EDX
	421	#undef EBX
	422	#undef ESP
	423	#undef EBP
	424	#undef ESI
	425	#undef EDI
	426	#undef EIP
	427	#include <signal.h>
	428	#include <sys/ucontext.h>
	429
3fb2ded1 FB	430	#if defined(TARGET_I386)
3fb2ded1 FB	431
b56dad1c	432	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	433	the effective address of the memory exception. 'is_write' is 1 if a
	434	write caused the exception and otherwise 0'. 'old_set' is the
	435	signal set which should be restored */
2b413144 FB	436	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	437	int is_write, sigset_t *old_set)
9de5e440	438	{
a513fe19 FB	439	TranslationBlock *tb;
a513fe19 FB	440	int ret;
68a79315	441
83479e77 FB	442	if (cpu_single_env)
83479e77 FB	443	env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6	444	#if defined(DEBUG_SIGNAL)
3fb2ded1	445	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
fd6ce8f6	446	pc, address, is_write, (unsigned long )old_set);
9de5e440	447	#endif
25eb4484	448	/* XXX: locking issue */
fd6ce8f6	449	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	450	return 1;
fd6ce8f6 FB	451	}
3fb2ded1 FB	452	/* see if it is an MMU fault */
	453	ret = cpu_x86_handle_mmu_fault(env, address, is_write);
	454	if (ret < 0)
	455	return 0; /* not an MMU fault */
	456	if (ret == 0)
	457	return 1; /* the MMU fault was handled without causing real CPU fault */
	458	/* now we have a real cpu fault */
a513fe19 FB	459	tb = tb_find_pc(pc);
a513fe19 FB	460	if (tb) {
9de5e440 FB	461	/* the PC is inside the translated code. It means that we have
9de5e440 FB	462	a virtual CPU fault */
3fb2ded1 FB	463	cpu_restore_state(tb, env, pc);
3fb2ded1 FB	464	}
4cbf74b6	465	if (ret == 1) {
3fb2ded1	466	#if 0
4cbf74b6 FB	467	printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
4cbf74b6 FB	468	env->eip, env->cr[2], env->error_code);
3fb2ded1	469	#endif
4cbf74b6 FB	470	/* we restore the process signal mask as the sigreturn should
	471	do it (XXX: use sigsetjmp) */
	472	sigprocmask(SIG_SETMASK, old_set, NULL);
	473	raise_exception_err(EXCP0E_PAGE, env->error_code);
	474	} else {
	475	/* activate soft MMU for this block */
3f337316	476	env->hflags \|= HF_SOFTMMU_MASK;
4cbf74b6 FB	477	sigprocmask(SIG_SETMASK, old_set, NULL);
	478	cpu_loop_exit();
	479	}
3fb2ded1 FB	480	/* never comes here */
	481	return 1;
	482	}
	483
e4533c7a	484	#elif defined(TARGET_ARM)
3fb2ded1 FB	485	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
	486	int is_write, sigset_t *old_set)
	487	{
	488	/* XXX: do more */
	489	return 0;
	490	}
e4533c7a FB	491	#else
	492	#error unsupported target CPU
	493	#endif
9de5e440	494
2b413144 FB	495	#if defined(__i386__)
2b413144 FB	496
e4533c7a FB	497	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	498	void *puc)
9de5e440	499	{
9de5e440 FB	500	struct ucontext *uc = puc;
9de5e440 FB	501	unsigned long pc;
9de5e440	502
d691f669 FB	503	#ifndef REG_EIP
d691f669 FB	504	/* for glibc 2.1 */
fd6ce8f6 FB	505	#define REG_EIP EIP
	506	#define REG_ERR ERR
	507	#define REG_TRAPNO TRAPNO
d691f669	508	#endif
fc2b4c48	509	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	510	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	511	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	512	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	513	&uc->uc_sigmask);
	514	}
	515
25eb4484	516	#elif defined(__powerpc)
2b413144	517
e4533c7a FB	518	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	519	void *puc)
2b413144	520	{
25eb4484 FB	521	struct ucontext *uc = puc;
	522	struct pt_regs *regs = uc->uc_mcontext.regs;
	523	unsigned long pc;
25eb4484 FB	524	int is_write;
	525
	526	pc = regs->nip;
25eb4484 FB	527	is_write = 0;
	528	#if 0
	529	/* ppc 4xx case */
	530	if (regs->dsisr & 0x00800000)
	531	is_write = 1;
	532	#else
	533	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	534	is_write = 1;
	535	#endif
	536	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	537	is_write, &uc->uc_sigmask);
	538	}
	539
2f87c607 FB	540	#elif defined(__alpha__)
2f87c607 FB	541
e4533c7a	542	int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607 FB	543	void *puc)
	544	{
	545	struct ucontext *uc = puc;
	546	uint32_t *pc = uc->uc_mcontext.sc_pc;
	547	uint32_t insn = *pc;
	548	int is_write = 0;
	549
8c6939c0	550	/* XXX: need kernel patch to get write flag faster */
2f87c607 FB	551	switch (insn >> 26) {
	552	case 0x0d: // stw
	553	case 0x0e: // stb
	554	case 0x0f: // stq_u
	555	case 0x24: // stf
	556	case 0x25: // stg
	557	case 0x26: // sts
	558	case 0x27: // stt
	559	case 0x2c: // stl
	560	case 0x2d: // stq
	561	case 0x2e: // stl_c
	562	case 0x2f: // stq_c
	563	is_write = 1;
	564	}
	565
	566	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	567	is_write, &uc->uc_sigmask);
	568	}
8c6939c0 FB	569	#elif defined(__sparc__)
8c6939c0 FB	570
e4533c7a FB	571	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	572	void *puc)
8c6939c0 FB	573	{
	574	uint32_t regs = (uint32_t )(info + 1);
	575	void *sigmask = (regs + 20);
	576	unsigned long pc;
	577	int is_write;
	578	uint32_t insn;
	579
	580	/* XXX: is there a standard glibc define ? */
	581	pc = regs[1];
	582	/* XXX: need kernel patch to get write flag faster */
	583	is_write = 0;
	584	insn = (uint32_t )pc;
	585	if ((insn >> 30) == 3) {
	586	switch((insn >> 19) & 0x3f) {
	587	case 0x05: // stb
	588	case 0x06: // sth
	589	case 0x04: // st
	590	case 0x07: // std
	591	case 0x24: // stf
	592	case 0x27: // stdf
	593	case 0x25: // stfsr
	594	is_write = 1;
	595	break;
	596	}
	597	}
	598	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	599	is_write, sigmask);
	600	}
	601
	602	#elif defined(__arm__)
	603
e4533c7a FB	604	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	605	void *puc)
8c6939c0 FB	606	{
	607	struct ucontext *uc = puc;
	608	unsigned long pc;
	609	int is_write;
	610
	611	pc = uc->uc_mcontext.gregs[R15];
	612	/* XXX: compute is_write */
	613	is_write = 0;
	614	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	615	is_write,
	616	&uc->uc_sigmask);
	617	}
	618
38e584a0 FB	619	#elif defined(__mc68000)
	620
	621	int cpu_signal_handler(int host_signum, struct siginfo *info,
	622	void *puc)
	623	{
	624	struct ucontext *uc = puc;
	625	unsigned long pc;
	626	int is_write;
	627
	628	pc = uc->uc_mcontext.gregs[16];
	629	/* XXX: compute is_write */
	630	is_write = 0;
	631	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	632	is_write,
	633	&uc->uc_sigmask);
	634	}
	635
9de5e440	636	#else
2b413144	637
3fb2ded1	638	#error host CPU specific signal handler needed
2b413144	639
9de5e440	640	#endif