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Commit | Line | Data |
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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
5fafdf24 | 3 | * |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 | 16 | * You should have received a copy of the GNU Lesser General Public |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7d13299d | 18 | */ |
e4533c7a | 19 | #include "config.h" |
93ac68bc | 20 | #include "exec.h" |
956034d7 | 21 | #include "disas.h" |
7cb69cae | 22 | #include "tcg.h" |
7ba1e619 | 23 | #include "kvm.h" |
1d93f0f0 | 24 | #include "qemu-barrier.h" |
7d13299d | 25 | |
dfe5fff3 | 26 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
572a9d4a BS |
27 | // Work around ugly bugs in glibc that mangle global register contents |
28 | #undef env | |
29 | #define env cpu_single_env | |
30 | #endif | |
31 | ||
36bdbe54 FB |
32 | int tb_invalidated_flag; |
33 | ||
f0667e66 | 34 | //#define CONFIG_DEBUG_EXEC |
7d13299d | 35 | |
6a4955a8 AL |
36 | int qemu_cpu_has_work(CPUState *env) |
37 | { | |
38 | return cpu_has_work(env); | |
39 | } | |
40 | ||
e4533c7a FB |
41 | void cpu_loop_exit(void) |
42 | { | |
1c3569fe | 43 | env->current_tb = NULL; |
e4533c7a FB |
44 | longjmp(env->jmp_env, 1); |
45 | } | |
bfed01fc | 46 | |
fbf9eeb3 FB |
47 | /* exit the current TB from a signal handler. The host registers are |
48 | restored in a state compatible with the CPU emulator | |
49 | */ | |
9eff14f3 BS |
50 | #if defined(CONFIG_SOFTMMU) |
51 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
52 | { | |
53 | env = env1; | |
54 | ||
55 | /* XXX: restore cpu registers saved in host registers */ | |
56 | ||
57 | env->exception_index = -1; | |
58 | longjmp(env->jmp_env, 1); | |
59 | } | |
9eff14f3 | 60 | #endif |
fbf9eeb3 | 61 | |
2e70f6ef PB |
62 | /* Execute the code without caching the generated code. An interpreter |
63 | could be used if available. */ | |
64 | static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb) | |
65 | { | |
66 | unsigned long next_tb; | |
67 | TranslationBlock *tb; | |
68 | ||
69 | /* Should never happen. | |
70 | We only end up here when an existing TB is too long. */ | |
71 | if (max_cycles > CF_COUNT_MASK) | |
72 | max_cycles = CF_COUNT_MASK; | |
73 | ||
74 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, | |
75 | max_cycles); | |
76 | env->current_tb = tb; | |
77 | /* execute the generated code */ | |
78 | next_tb = tcg_qemu_tb_exec(tb->tc_ptr); | |
1c3569fe | 79 | env->current_tb = NULL; |
2e70f6ef PB |
80 | |
81 | if ((next_tb & 3) == 2) { | |
82 | /* Restore PC. This may happen if async event occurs before | |
83 | the TB starts executing. */ | |
622ed360 | 84 | cpu_pc_from_tb(env, tb); |
2e70f6ef PB |
85 | } |
86 | tb_phys_invalidate(tb, -1); | |
87 | tb_free(tb); | |
88 | } | |
89 | ||
8a40a180 FB |
90 | static TranslationBlock *tb_find_slow(target_ulong pc, |
91 | target_ulong cs_base, | |
c068688b | 92 | uint64_t flags) |
8a40a180 FB |
93 | { |
94 | TranslationBlock *tb, **ptb1; | |
8a40a180 | 95 | unsigned int h; |
41c1b1c9 PB |
96 | tb_page_addr_t phys_pc, phys_page1, phys_page2; |
97 | target_ulong virt_page2; | |
3b46e624 | 98 | |
8a40a180 | 99 | tb_invalidated_flag = 0; |
3b46e624 | 100 | |
8a40a180 | 101 | /* find translated block using physical mappings */ |
41c1b1c9 | 102 | phys_pc = get_page_addr_code(env, pc); |
8a40a180 FB |
103 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
104 | phys_page2 = -1; | |
105 | h = tb_phys_hash_func(phys_pc); | |
106 | ptb1 = &tb_phys_hash[h]; | |
107 | for(;;) { | |
108 | tb = *ptb1; | |
109 | if (!tb) | |
110 | goto not_found; | |
5fafdf24 | 111 | if (tb->pc == pc && |
8a40a180 | 112 | tb->page_addr[0] == phys_page1 && |
5fafdf24 | 113 | tb->cs_base == cs_base && |
8a40a180 FB |
114 | tb->flags == flags) { |
115 | /* check next page if needed */ | |
116 | if (tb->page_addr[1] != -1) { | |
5fafdf24 | 117 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
8a40a180 | 118 | TARGET_PAGE_SIZE; |
41c1b1c9 | 119 | phys_page2 = get_page_addr_code(env, virt_page2); |
8a40a180 FB |
120 | if (tb->page_addr[1] == phys_page2) |
121 | goto found; | |
122 | } else { | |
123 | goto found; | |
124 | } | |
125 | } | |
126 | ptb1 = &tb->phys_hash_next; | |
127 | } | |
128 | not_found: | |
2e70f6ef PB |
129 | /* if no translated code available, then translate it now */ |
130 | tb = tb_gen_code(env, pc, cs_base, flags, 0); | |
3b46e624 | 131 | |
8a40a180 | 132 | found: |
2c90fe2b KB |
133 | /* Move the last found TB to the head of the list */ |
134 | if (likely(*ptb1)) { | |
135 | *ptb1 = tb->phys_hash_next; | |
136 | tb->phys_hash_next = tb_phys_hash[h]; | |
137 | tb_phys_hash[h] = tb; | |
138 | } | |
8a40a180 FB |
139 | /* we add the TB in the virtual pc hash table */ |
140 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; | |
8a40a180 FB |
141 | return tb; |
142 | } | |
143 | ||
144 | static inline TranslationBlock *tb_find_fast(void) | |
145 | { | |
146 | TranslationBlock *tb; | |
147 | target_ulong cs_base, pc; | |
6b917547 | 148 | int flags; |
8a40a180 FB |
149 | |
150 | /* we record a subset of the CPU state. It will | |
151 | always be the same before a given translated block | |
152 | is executed. */ | |
6b917547 | 153 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bce61846 | 154 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
551bd27f TS |
155 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
156 | tb->flags != flags)) { | |
8a40a180 FB |
157 | tb = tb_find_slow(pc, cs_base, flags); |
158 | } | |
159 | return tb; | |
160 | } | |
161 | ||
1009d2ed JK |
162 | static CPUDebugExcpHandler *debug_excp_handler; |
163 | ||
164 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) | |
165 | { | |
166 | CPUDebugExcpHandler *old_handler = debug_excp_handler; | |
167 | ||
168 | debug_excp_handler = handler; | |
169 | return old_handler; | |
170 | } | |
171 | ||
172 | static void cpu_handle_debug_exception(CPUState *env) | |
173 | { | |
174 | CPUWatchpoint *wp; | |
175 | ||
176 | if (!env->watchpoint_hit) { | |
177 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
178 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
179 | } | |
180 | } | |
181 | if (debug_excp_handler) { | |
182 | debug_excp_handler(env); | |
183 | } | |
184 | } | |
185 | ||
7d13299d FB |
186 | /* main execution loop */ |
187 | ||
1a28cac3 MT |
188 | volatile sig_atomic_t exit_request; |
189 | ||
e4533c7a | 190 | int cpu_exec(CPUState *env1) |
7d13299d | 191 | { |
1d9000e8 | 192 | volatile host_reg_t saved_env_reg; |
8a40a180 | 193 | int ret, interrupt_request; |
8a40a180 | 194 | TranslationBlock *tb; |
c27004ec | 195 | uint8_t *tc_ptr; |
d5975363 | 196 | unsigned long next_tb; |
8c6939c0 | 197 | |
eda48c34 PB |
198 | if (env1->halted) { |
199 | if (!cpu_has_work(env1)) { | |
200 | return EXCP_HALTED; | |
201 | } | |
202 | ||
203 | env1->halted = 0; | |
204 | } | |
5a1e3cfc | 205 | |
5fafdf24 | 206 | cpu_single_env = env1; |
6a00d601 | 207 | |
24ebf5f3 PB |
208 | /* the access to env below is actually saving the global register's |
209 | value, so that files not including target-xyz/exec.h are free to | |
210 | use it. */ | |
211 | QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env)); | |
212 | saved_env_reg = (host_reg_t) env; | |
1d93f0f0 | 213 | barrier(); |
c27004ec | 214 | env = env1; |
e4533c7a | 215 | |
c629a4bc | 216 | if (unlikely(exit_request)) { |
1a28cac3 | 217 | env->exit_request = 1; |
1a28cac3 MT |
218 | } |
219 | ||
ecb644f4 | 220 | #if defined(TARGET_I386) |
6792a57b JK |
221 | /* put eflags in CPU temporary format */ |
222 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
223 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
224 | CC_OP = CC_OP_EFLAGS; | |
225 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
93ac68bc | 226 | #elif defined(TARGET_SPARC) |
e6e5906b PB |
227 | #elif defined(TARGET_M68K) |
228 | env->cc_op = CC_OP_FLAGS; | |
229 | env->cc_dest = env->sr & 0xf; | |
230 | env->cc_x = (env->sr >> 4) & 1; | |
ecb644f4 TS |
231 | #elif defined(TARGET_ALPHA) |
232 | #elif defined(TARGET_ARM) | |
d2fbca94 | 233 | #elif defined(TARGET_UNICORE32) |
ecb644f4 | 234 | #elif defined(TARGET_PPC) |
81ea0e13 | 235 | #elif defined(TARGET_LM32) |
b779e29e | 236 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 237 | #elif defined(TARGET_MIPS) |
fdf9b3e8 | 238 | #elif defined(TARGET_SH4) |
f1ccf904 | 239 | #elif defined(TARGET_CRIS) |
10ec5117 | 240 | #elif defined(TARGET_S390X) |
fdf9b3e8 | 241 | /* XXXXX */ |
e4533c7a FB |
242 | #else |
243 | #error unsupported target CPU | |
244 | #endif | |
3fb2ded1 | 245 | env->exception_index = -1; |
9d27abd9 | 246 | |
7d13299d | 247 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
248 | for(;;) { |
249 | if (setjmp(env->jmp_env) == 0) { | |
dfe5fff3 | 250 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
9ddff3d2 | 251 | #undef env |
6792a57b | 252 | env = cpu_single_env; |
9ddff3d2 BS |
253 | #define env cpu_single_env |
254 | #endif | |
3fb2ded1 FB |
255 | /* if an exception is pending, we execute it here */ |
256 | if (env->exception_index >= 0) { | |
257 | if (env->exception_index >= EXCP_INTERRUPT) { | |
258 | /* exit request from the cpu execution loop */ | |
259 | ret = env->exception_index; | |
1009d2ed JK |
260 | if (ret == EXCP_DEBUG) { |
261 | cpu_handle_debug_exception(env); | |
262 | } | |
3fb2ded1 | 263 | break; |
72d239ed AJ |
264 | } else { |
265 | #if defined(CONFIG_USER_ONLY) | |
3fb2ded1 | 266 | /* if user mode only, we simulate a fake exception |
9f083493 | 267 | which will be handled outside the cpu execution |
3fb2ded1 | 268 | loop */ |
83479e77 | 269 | #if defined(TARGET_I386) |
5fafdf24 TS |
270 | do_interrupt_user(env->exception_index, |
271 | env->exception_is_int, | |
272 | env->error_code, | |
3fb2ded1 | 273 | env->exception_next_eip); |
eba01623 FB |
274 | /* successfully delivered */ |
275 | env->old_exception = -1; | |
83479e77 | 276 | #endif |
3fb2ded1 FB |
277 | ret = env->exception_index; |
278 | break; | |
72d239ed | 279 | #else |
83479e77 | 280 | #if defined(TARGET_I386) |
3fb2ded1 FB |
281 | /* simulate a real cpu exception. On i386, it can |
282 | trigger new exceptions, but we do not handle | |
283 | double or triple faults yet. */ | |
5fafdf24 TS |
284 | do_interrupt(env->exception_index, |
285 | env->exception_is_int, | |
286 | env->error_code, | |
d05e66d2 | 287 | env->exception_next_eip, 0); |
678dde13 TS |
288 | /* successfully delivered */ |
289 | env->old_exception = -1; | |
ce09776b FB |
290 | #elif defined(TARGET_PPC) |
291 | do_interrupt(env); | |
81ea0e13 MW |
292 | #elif defined(TARGET_LM32) |
293 | do_interrupt(env); | |
b779e29e EI |
294 | #elif defined(TARGET_MICROBLAZE) |
295 | do_interrupt(env); | |
6af0bf9c FB |
296 | #elif defined(TARGET_MIPS) |
297 | do_interrupt(env); | |
e95c8d51 | 298 | #elif defined(TARGET_SPARC) |
f2bc7e7f | 299 | do_interrupt(env); |
b5ff1b31 FB |
300 | #elif defined(TARGET_ARM) |
301 | do_interrupt(env); | |
d2fbca94 GX |
302 | #elif defined(TARGET_UNICORE32) |
303 | do_interrupt(env); | |
fdf9b3e8 FB |
304 | #elif defined(TARGET_SH4) |
305 | do_interrupt(env); | |
eddf68a6 JM |
306 | #elif defined(TARGET_ALPHA) |
307 | do_interrupt(env); | |
f1ccf904 TS |
308 | #elif defined(TARGET_CRIS) |
309 | do_interrupt(env); | |
0633879f PB |
310 | #elif defined(TARGET_M68K) |
311 | do_interrupt(0); | |
3110e292 AG |
312 | #elif defined(TARGET_S390X) |
313 | do_interrupt(env); | |
72d239ed | 314 | #endif |
301d2908 | 315 | env->exception_index = -1; |
83479e77 | 316 | #endif |
3fb2ded1 | 317 | } |
5fafdf24 | 318 | } |
9df217a3 | 319 | |
b5fc09ae | 320 | next_tb = 0; /* force lookup of first TB */ |
3fb2ded1 | 321 | for(;;) { |
68a79315 | 322 | interrupt_request = env->interrupt_request; |
e1638bd8 | 323 | if (unlikely(interrupt_request)) { |
324 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { | |
325 | /* Mask out external interrupts for this step. */ | |
3125f763 | 326 | interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; |
e1638bd8 | 327 | } |
6658ffb8 PB |
328 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
329 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; | |
330 | env->exception_index = EXCP_DEBUG; | |
331 | cpu_loop_exit(); | |
332 | } | |
a90b7318 | 333 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
b779e29e | 334 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
d2fbca94 | 335 | defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32) |
a90b7318 AZ |
336 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
337 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; | |
338 | env->halted = 1; | |
339 | env->exception_index = EXCP_HLT; | |
340 | cpu_loop_exit(); | |
341 | } | |
342 | #endif | |
68a79315 | 343 | #if defined(TARGET_I386) |
b09ea7d5 GN |
344 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
345 | svm_check_intercept(SVM_EXIT_INIT); | |
346 | do_cpu_init(env); | |
347 | env->exception_index = EXCP_HALTED; | |
348 | cpu_loop_exit(); | |
349 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { | |
350 | do_cpu_sipi(env); | |
351 | } else if (env->hflags2 & HF2_GIF_MASK) { | |
db620f46 FB |
352 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
353 | !(env->hflags & HF_SMM_MASK)) { | |
354 | svm_check_intercept(SVM_EXIT_SMI); | |
355 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
356 | do_smm_enter(); | |
357 | next_tb = 0; | |
358 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && | |
359 | !(env->hflags2 & HF2_NMI_MASK)) { | |
360 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
361 | env->hflags2 |= HF2_NMI_MASK; | |
362 | do_interrupt(EXCP02_NMI, 0, 0, 0, 1); | |
363 | next_tb = 0; | |
79c4f6b0 HY |
364 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
365 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
366 | do_interrupt(EXCP12_MCHK, 0, 0, 0, 0); | |
367 | next_tb = 0; | |
db620f46 FB |
368 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
369 | (((env->hflags2 & HF2_VINTR_MASK) && | |
370 | (env->hflags2 & HF2_HIF_MASK)) || | |
371 | (!(env->hflags2 & HF2_VINTR_MASK) && | |
372 | (env->eflags & IF_MASK && | |
373 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { | |
374 | int intno; | |
375 | svm_check_intercept(SVM_EXIT_INTR); | |
376 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); | |
377 | intno = cpu_get_pic_interrupt(env); | |
93fcfe39 | 378 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
dfe5fff3 | 379 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
9ddff3d2 BS |
380 | #undef env |
381 | env = cpu_single_env; | |
382 | #define env cpu_single_env | |
383 | #endif | |
db620f46 FB |
384 | do_interrupt(intno, 0, 0, 0, 1); |
385 | /* ensure that no TB jump will be modified as | |
386 | the program flow was changed */ | |
387 | next_tb = 0; | |
0573fbfc | 388 | #if !defined(CONFIG_USER_ONLY) |
db620f46 FB |
389 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
390 | (env->eflags & IF_MASK) && | |
391 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
392 | int intno; | |
393 | /* FIXME: this should respect TPR */ | |
394 | svm_check_intercept(SVM_EXIT_VINTR); | |
db620f46 | 395 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
93fcfe39 | 396 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
db620f46 | 397 | do_interrupt(intno, 0, 0, 0, 1); |
d40c54d6 | 398 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
db620f46 | 399 | next_tb = 0; |
907a5b26 | 400 | #endif |
db620f46 | 401 | } |
68a79315 | 402 | } |
ce09776b | 403 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
404 | #if 0 |
405 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
d84bda46 | 406 | cpu_reset(env); |
9fddaa0c FB |
407 | } |
408 | #endif | |
47103572 | 409 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
e9df014c JM |
410 | ppc_hw_interrupt(env); |
411 | if (env->pending_interrupts == 0) | |
412 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
b5fc09ae | 413 | next_tb = 0; |
ce09776b | 414 | } |
81ea0e13 MW |
415 | #elif defined(TARGET_LM32) |
416 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
417 | && (env->ie & IE_IE)) { | |
418 | env->exception_index = EXCP_IRQ; | |
419 | do_interrupt(env); | |
420 | next_tb = 0; | |
421 | } | |
b779e29e EI |
422 | #elif defined(TARGET_MICROBLAZE) |
423 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
424 | && (env->sregs[SR_MSR] & MSR_IE) | |
425 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) | |
426 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { | |
427 | env->exception_index = EXCP_IRQ; | |
428 | do_interrupt(env); | |
429 | next_tb = 0; | |
430 | } | |
6af0bf9c FB |
431 | #elif defined(TARGET_MIPS) |
432 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
4cdc1cd1 | 433 | cpu_mips_hw_interrupts_pending(env)) { |
6af0bf9c FB |
434 | /* Raise it */ |
435 | env->exception_index = EXCP_EXT_INTERRUPT; | |
436 | env->error_code = 0; | |
437 | do_interrupt(env); | |
b5fc09ae | 438 | next_tb = 0; |
6af0bf9c | 439 | } |
e95c8d51 | 440 | #elif defined(TARGET_SPARC) |
d532b26c IK |
441 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
442 | if (cpu_interrupts_enabled(env) && | |
443 | env->interrupt_index > 0) { | |
444 | int pil = env->interrupt_index & 0xf; | |
445 | int type = env->interrupt_index & 0xf0; | |
446 | ||
447 | if (((type == TT_EXTINT) && | |
448 | cpu_pil_allowed(env, pil)) || | |
449 | type != TT_EXTINT) { | |
450 | env->exception_index = env->interrupt_index; | |
451 | do_interrupt(env); | |
452 | next_tb = 0; | |
453 | } | |
454 | } | |
a90b7318 | 455 | } |
b5ff1b31 FB |
456 | #elif defined(TARGET_ARM) |
457 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
458 | && !(env->uncached_cpsr & CPSR_F)) { | |
459 | env->exception_index = EXCP_FIQ; | |
460 | do_interrupt(env); | |
b5fc09ae | 461 | next_tb = 0; |
b5ff1b31 | 462 | } |
9ee6e8bb PB |
463 | /* ARMv7-M interrupt return works by loading a magic value |
464 | into the PC. On real hardware the load causes the | |
465 | return to occur. The qemu implementation performs the | |
466 | jump normally, then does the exception return when the | |
467 | CPU tries to execute code at the magic address. | |
468 | This will cause the magic PC value to be pushed to | |
a1c7273b | 469 | the stack if an interrupt occurred at the wrong time. |
9ee6e8bb PB |
470 | We avoid this by disabling interrupts when |
471 | pc contains a magic address. */ | |
b5ff1b31 | 472 | if (interrupt_request & CPU_INTERRUPT_HARD |
9ee6e8bb PB |
473 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
474 | || !(env->uncached_cpsr & CPSR_I))) { | |
b5ff1b31 FB |
475 | env->exception_index = EXCP_IRQ; |
476 | do_interrupt(env); | |
b5fc09ae | 477 | next_tb = 0; |
b5ff1b31 | 478 | } |
d2fbca94 GX |
479 | #elif defined(TARGET_UNICORE32) |
480 | if (interrupt_request & CPU_INTERRUPT_HARD | |
481 | && !(env->uncached_asr & ASR_I)) { | |
482 | do_interrupt(env); | |
483 | next_tb = 0; | |
484 | } | |
fdf9b3e8 | 485 | #elif defined(TARGET_SH4) |
e96e2044 TS |
486 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
487 | do_interrupt(env); | |
b5fc09ae | 488 | next_tb = 0; |
e96e2044 | 489 | } |
eddf68a6 JM |
490 | #elif defined(TARGET_ALPHA) |
491 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
492 | do_interrupt(env); | |
b5fc09ae | 493 | next_tb = 0; |
eddf68a6 | 494 | } |
f1ccf904 | 495 | #elif defined(TARGET_CRIS) |
1b1a38b0 | 496 | if (interrupt_request & CPU_INTERRUPT_HARD |
fb9fb692 EI |
497 | && (env->pregs[PR_CCS] & I_FLAG) |
498 | && !env->locked_irq) { | |
1b1a38b0 EI |
499 | env->exception_index = EXCP_IRQ; |
500 | do_interrupt(env); | |
501 | next_tb = 0; | |
502 | } | |
503 | if (interrupt_request & CPU_INTERRUPT_NMI | |
504 | && (env->pregs[PR_CCS] & M_FLAG)) { | |
505 | env->exception_index = EXCP_NMI; | |
f1ccf904 | 506 | do_interrupt(env); |
b5fc09ae | 507 | next_tb = 0; |
f1ccf904 | 508 | } |
0633879f PB |
509 | #elif defined(TARGET_M68K) |
510 | if (interrupt_request & CPU_INTERRUPT_HARD | |
511 | && ((env->sr & SR_I) >> SR_I_SHIFT) | |
512 | < env->pending_level) { | |
513 | /* Real hardware gets the interrupt vector via an | |
514 | IACK cycle at this point. Current emulated | |
515 | hardware doesn't rely on this, so we | |
516 | provide/save the vector when the interrupt is | |
517 | first signalled. */ | |
518 | env->exception_index = env->pending_vector; | |
519 | do_interrupt(1); | |
b5fc09ae | 520 | next_tb = 0; |
0633879f | 521 | } |
3110e292 AG |
522 | #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY) |
523 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
524 | (env->psw.mask & PSW_MASK_EXT)) { | |
525 | do_interrupt(env); | |
526 | next_tb = 0; | |
527 | } | |
68a79315 | 528 | #endif |
ff2712ba | 529 | /* Don't use the cached interrupt_request value, |
9d05095e | 530 | do_interrupt may have updated the EXITTB flag. */ |
b5ff1b31 | 531 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bf3e8bf1 FB |
532 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
533 | /* ensure that no TB jump will be modified as | |
534 | the program flow was changed */ | |
b5fc09ae | 535 | next_tb = 0; |
bf3e8bf1 | 536 | } |
be214e6c AJ |
537 | } |
538 | if (unlikely(env->exit_request)) { | |
539 | env->exit_request = 0; | |
540 | env->exception_index = EXCP_INTERRUPT; | |
541 | cpu_loop_exit(); | |
3fb2ded1 | 542 | } |
a73b1fd9 | 543 | #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC) |
8fec2b8c | 544 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
3fb2ded1 | 545 | /* restore flags in standard format */ |
ecb644f4 | 546 | #if defined(TARGET_I386) |
a7812ae4 | 547 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
93fcfe39 | 548 | log_cpu_state(env, X86_DUMP_CCOP); |
3fb2ded1 | 549 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e6e5906b PB |
550 | #elif defined(TARGET_M68K) |
551 | cpu_m68k_flush_flags(env, env->cc_op); | |
552 | env->cc_op = CC_OP_FLAGS; | |
553 | env->sr = (env->sr & 0xffe0) | |
554 | | env->cc_dest | (env->cc_x << 4); | |
93fcfe39 | 555 | log_cpu_state(env, 0); |
e4533c7a | 556 | #else |
a73b1fd9 | 557 | log_cpu_state(env, 0); |
e4533c7a | 558 | #endif |
3fb2ded1 | 559 | } |
a73b1fd9 | 560 | #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */ |
d5975363 | 561 | spin_lock(&tb_lock); |
8a40a180 | 562 | tb = tb_find_fast(); |
d5975363 PB |
563 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
564 | doing it in tb_find_slow */ | |
565 | if (tb_invalidated_flag) { | |
566 | /* as some TB could have been invalidated because | |
567 | of memory exceptions while generating the code, we | |
568 | must recompute the hash index here */ | |
569 | next_tb = 0; | |
2e70f6ef | 570 | tb_invalidated_flag = 0; |
d5975363 | 571 | } |
f0667e66 | 572 | #ifdef CONFIG_DEBUG_EXEC |
93fcfe39 AL |
573 | qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
574 | (long)tb->tc_ptr, tb->pc, | |
575 | lookup_symbol(tb->pc)); | |
9d27abd9 | 576 | #endif |
8a40a180 FB |
577 | /* see if we can patch the calling TB. When the TB |
578 | spans two pages, we cannot safely do a direct | |
579 | jump. */ | |
040f2fb2 | 580 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
b5fc09ae | 581 | tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb); |
3fb2ded1 | 582 | } |
d5975363 | 583 | spin_unlock(&tb_lock); |
55e8b85e | 584 | |
585 | /* cpu_interrupt might be called while translating the | |
586 | TB, but before it is linked into a potentially | |
587 | infinite loop and becomes env->current_tb. Avoid | |
588 | starting execution if there is a pending interrupt. */ | |
b0052d15 JK |
589 | env->current_tb = tb; |
590 | barrier(); | |
591 | if (likely(!env->exit_request)) { | |
2e70f6ef | 592 | tc_ptr = tb->tc_ptr; |
3fb2ded1 | 593 | /* execute the generated code */ |
dfe5fff3 | 594 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
572a9d4a | 595 | #undef env |
2e70f6ef | 596 | env = cpu_single_env; |
572a9d4a BS |
597 | #define env cpu_single_env |
598 | #endif | |
2e70f6ef | 599 | next_tb = tcg_qemu_tb_exec(tc_ptr); |
2e70f6ef | 600 | if ((next_tb & 3) == 2) { |
bf20dc07 | 601 | /* Instruction counter expired. */ |
2e70f6ef PB |
602 | int insns_left; |
603 | tb = (TranslationBlock *)(long)(next_tb & ~3); | |
604 | /* Restore PC. */ | |
622ed360 | 605 | cpu_pc_from_tb(env, tb); |
2e70f6ef PB |
606 | insns_left = env->icount_decr.u32; |
607 | if (env->icount_extra && insns_left >= 0) { | |
608 | /* Refill decrementer and continue execution. */ | |
609 | env->icount_extra += insns_left; | |
610 | if (env->icount_extra > 0xffff) { | |
611 | insns_left = 0xffff; | |
612 | } else { | |
613 | insns_left = env->icount_extra; | |
614 | } | |
615 | env->icount_extra -= insns_left; | |
616 | env->icount_decr.u16.low = insns_left; | |
617 | } else { | |
618 | if (insns_left > 0) { | |
619 | /* Execute remaining instructions. */ | |
620 | cpu_exec_nocache(insns_left, tb); | |
621 | } | |
622 | env->exception_index = EXCP_INTERRUPT; | |
623 | next_tb = 0; | |
624 | cpu_loop_exit(); | |
625 | } | |
626 | } | |
627 | } | |
b0052d15 | 628 | env->current_tb = NULL; |
4cbf74b6 FB |
629 | /* reset soft MMU for next block (it can currently |
630 | only be set by a memory fault) */ | |
50a518e3 | 631 | } /* for(;;) */ |
7d13299d | 632 | } |
3fb2ded1 FB |
633 | } /* for(;;) */ |
634 | ||
7d13299d | 635 | |
e4533c7a | 636 | #if defined(TARGET_I386) |
9de5e440 | 637 | /* restore flags in standard format */ |
a7812ae4 | 638 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
e4533c7a | 639 | #elif defined(TARGET_ARM) |
b7bcbe95 | 640 | /* XXX: Save/restore host fpu exception state?. */ |
d2fbca94 | 641 | #elif defined(TARGET_UNICORE32) |
93ac68bc | 642 | #elif defined(TARGET_SPARC) |
67867308 | 643 | #elif defined(TARGET_PPC) |
81ea0e13 | 644 | #elif defined(TARGET_LM32) |
e6e5906b PB |
645 | #elif defined(TARGET_M68K) |
646 | cpu_m68k_flush_flags(env, env->cc_op); | |
647 | env->cc_op = CC_OP_FLAGS; | |
648 | env->sr = (env->sr & 0xffe0) | |
649 | | env->cc_dest | (env->cc_x << 4); | |
b779e29e | 650 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 651 | #elif defined(TARGET_MIPS) |
fdf9b3e8 | 652 | #elif defined(TARGET_SH4) |
eddf68a6 | 653 | #elif defined(TARGET_ALPHA) |
f1ccf904 | 654 | #elif defined(TARGET_CRIS) |
10ec5117 | 655 | #elif defined(TARGET_S390X) |
fdf9b3e8 | 656 | /* XXXXX */ |
e4533c7a FB |
657 | #else |
658 | #error unsupported target CPU | |
659 | #endif | |
1057eaa7 PB |
660 | |
661 | /* restore global registers */ | |
1d93f0f0 | 662 | barrier(); |
24ebf5f3 | 663 | env = (void *) saved_env_reg; |
1057eaa7 | 664 | |
6a00d601 | 665 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
5fafdf24 | 666 | cpu_single_env = NULL; |
7d13299d FB |
667 | return ret; |
668 | } |