]> git.proxmox.com Git - mirror_qemu.git/blame - cpu-exec.c
target-tilegx: Handle conditional branch instructions
[mirror_qemu.git] / cpu-exec.c
CommitLineData
7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
6db8b538 21#include "trace.h"
76cad711 22#include "disas/disas.h"
7cb69cae 23#include "tcg.h"
1de7afc9 24#include "qemu/atomic.h"
9c17d615 25#include "sysemu/qtest.h"
c2aa5f81 26#include "qemu/timer.h"
9d82b5a7
PB
27#include "exec/address-spaces.h"
28#include "exec/memory-internal.h"
79e2b9ae 29#include "qemu/rcu.h"
e1b89321 30#include "exec/tb-hash.h"
c2aa5f81
ST
31
32/* -icount align implementation. */
33
34typedef struct SyncClocks {
35 int64_t diff_clk;
36 int64_t last_cpu_icount;
7f7bc144 37 int64_t realtime_clock;
c2aa5f81
ST
38} SyncClocks;
39
40#if !defined(CONFIG_USER_ONLY)
41/* Allow the guest to have a max 3ms advance.
42 * The difference between the 2 clocks could therefore
43 * oscillate around 0.
44 */
45#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
46#define THRESHOLD_REDUCE 1.5
47#define MAX_DELAY_PRINT_RATE 2000000000LL
48#define MAX_NB_PRINTS 100
c2aa5f81
ST
49
50static void align_clocks(SyncClocks *sc, const CPUState *cpu)
51{
52 int64_t cpu_icount;
53
54 if (!icount_align_option) {
55 return;
56 }
57
58 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
59 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
60 sc->last_cpu_icount = cpu_icount;
61
62 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
63#ifndef _WIN32
64 struct timespec sleep_delay, rem_delay;
65 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
66 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
67 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 68 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
69 } else {
70 sc->diff_clk = 0;
71 }
72#else
73 Sleep(sc->diff_clk / SCALE_MS);
74 sc->diff_clk = 0;
75#endif
76 }
77}
78
7f7bc144
ST
79static void print_delay(const SyncClocks *sc)
80{
81 static float threshold_delay;
82 static int64_t last_realtime_clock;
83 static int nb_prints;
84
85 if (icount_align_option &&
86 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
87 nb_prints < MAX_NB_PRINTS) {
88 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
89 (-sc->diff_clk / (float)1000000000LL <
90 (threshold_delay - THRESHOLD_REDUCE))) {
91 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
92 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
93 threshold_delay - 1,
94 threshold_delay);
95 nb_prints++;
96 last_realtime_clock = sc->realtime_clock;
97 }
98 }
99}
100
c2aa5f81
ST
101static void init_delay_params(SyncClocks *sc,
102 const CPUState *cpu)
103{
104 if (!icount_align_option) {
105 return;
106 }
2e91cc62
PB
107 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
108 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
c2aa5f81 109 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
27498bef
ST
110 if (sc->diff_clk < max_delay) {
111 max_delay = sc->diff_clk;
112 }
113 if (sc->diff_clk > max_advance) {
114 max_advance = sc->diff_clk;
115 }
7f7bc144
ST
116
117 /* Print every 2s max if the guest is late. We limit the number
118 of printed messages to NB_PRINT_MAX(currently 100) */
119 print_delay(sc);
c2aa5f81
ST
120}
121#else
122static void align_clocks(SyncClocks *sc, const CPUState *cpu)
123{
124}
125
126static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
127{
128}
129#endif /* CONFIG USER ONLY */
7d13299d 130
5638d180 131void cpu_loop_exit(CPUState *cpu)
e4533c7a 132{
d77953b9 133 cpu->current_tb = NULL;
6f03bef0 134 siglongjmp(cpu->jmp_env, 1);
e4533c7a 135}
bfed01fc 136
1c3c8af1
PD
137void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
138{
139 if (pc) {
140 cpu_restore_state(cpu, pc);
141 }
142 cpu->current_tb = NULL;
143 siglongjmp(cpu->jmp_env, 1);
144}
145
fbf9eeb3
FB
146/* exit the current TB from a signal handler. The host registers are
147 restored in a state compatible with the CPU emulator
148 */
9eff14f3 149#if defined(CONFIG_SOFTMMU)
0ea8cb88 150void cpu_resume_from_signal(CPUState *cpu, void *puc)
9eff14f3 151{
9eff14f3
BS
152 /* XXX: restore cpu registers saved in host registers */
153
27103424 154 cpu->exception_index = -1;
6f03bef0 155 siglongjmp(cpu->jmp_env, 1);
9eff14f3 156}
76e5c76f
PB
157
158void cpu_reload_memory_map(CPUState *cpu)
159{
79e2b9ae
PB
160 AddressSpaceDispatch *d;
161
162 if (qemu_in_vcpu_thread()) {
163 /* Do not let the guest prolong the critical section as much as it
164 * as it desires.
165 *
166 * Currently, this is prevented by the I/O thread's periodinc kicking
167 * of the VCPU thread (iothread_requesting_mutex, qemu_cpu_kick_thread)
168 * but this will go away once TCG's execution moves out of the global
169 * mutex.
170 *
171 * This pair matches cpu_exec's rcu_read_lock()/rcu_read_unlock(), which
172 * only protects cpu->as->dispatch. Since we reload it below, we can
173 * split the critical section.
174 */
175 rcu_read_unlock();
176 rcu_read_lock();
177 }
178
9d82b5a7 179 /* The CPU and TLB are protected by the iothread lock. */
79e2b9ae 180 d = atomic_rcu_read(&cpu->as->dispatch);
9d82b5a7 181 cpu->memory_dispatch = d;
76e5c76f
PB
182 tlb_flush(cpu, 1);
183}
9eff14f3 184#endif
fbf9eeb3 185
77211379
PM
186/* Execute a TB, and fix up the CPU state afterwards if necessary */
187static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
188{
189 CPUArchState *env = cpu->env_ptr;
03afa5f8
RH
190 uintptr_t next_tb;
191
192#if defined(DEBUG_DISAS)
193 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
194#if defined(TARGET_I386)
195 log_cpu_state(cpu, CPU_DUMP_CCOP);
196#elif defined(TARGET_M68K)
197 /* ??? Should not modify env state for dumping. */
198 cpu_m68k_flush_flags(env, env->cc_op);
199 env->cc_op = CC_OP_FLAGS;
200 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
201 log_cpu_state(cpu, 0);
202#else
203 log_cpu_state(cpu, 0);
204#endif
205 }
206#endif /* DEBUG_DISAS */
207
414b15c9 208 cpu->can_do_io = !use_icount;
03afa5f8 209 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 210 cpu->can_do_io = 1;
6db8b538
AB
211 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
212 next_tb & TB_EXIT_MASK);
213
77211379
PM
214 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
215 /* We didn't start executing this TB (eg because the instruction
216 * counter hit zero); we must restore the guest PC to the address
217 * of the start of the TB.
218 */
bdf7ae5b 219 CPUClass *cc = CPU_GET_CLASS(cpu);
77211379 220 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
bdf7ae5b
AF
221 if (cc->synchronize_from_tb) {
222 cc->synchronize_from_tb(cpu, tb);
223 } else {
224 assert(cc->set_pc);
225 cc->set_pc(cpu, tb->pc);
226 }
77211379 227 }
378df4b2
PM
228 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
229 /* We were asked to stop executing TBs (probably a pending
230 * interrupt. We've now stopped, so clear the flag.
231 */
232 cpu->tcg_exit_req = 0;
233 }
77211379
PM
234 return next_tb;
235}
236
2e70f6ef
PB
237/* Execute the code without caching the generated code. An interpreter
238 could be used if available. */
ea3e9847 239static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
cea5f9a2 240 TranslationBlock *orig_tb)
2e70f6ef 241{
2e70f6ef
PB
242 TranslationBlock *tb;
243
244 /* Should never happen.
245 We only end up here when an existing TB is too long. */
246 if (max_cycles > CF_COUNT_MASK)
247 max_cycles = CF_COUNT_MASK;
248
02d57ea1 249 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
d8a499f1 250 max_cycles | CF_NOCACHE);
02d57ea1 251 tb->orig_tb = tcg_ctx.tb_ctx.tb_invalidated_flag ? NULL : orig_tb;
d77953b9 252 cpu->current_tb = tb;
2e70f6ef 253 /* execute the generated code */
6db8b538 254 trace_exec_tb_nocache(tb, tb->pc);
77211379 255 cpu_tb_exec(cpu, tb->tc_ptr);
d77953b9 256 cpu->current_tb = NULL;
2e70f6ef
PB
257 tb_phys_invalidate(tb, -1);
258 tb_free(tb);
259}
260
9fd1a948
PB
261static TranslationBlock *tb_find_physical(CPUState *cpu,
262 target_ulong pc,
263 target_ulong cs_base,
264 uint64_t flags)
8a40a180 265{
ea3e9847 266 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
8a40a180 267 TranslationBlock *tb, **ptb1;
8a40a180 268 unsigned int h;
337fc758 269 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 270 target_ulong virt_page2;
3b46e624 271
5e5f07e0 272 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
3b46e624 273
8a40a180 274 /* find translated block using physical mappings */
41c1b1c9 275 phys_pc = get_page_addr_code(env, pc);
8a40a180 276 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180 277 h = tb_phys_hash_func(phys_pc);
5e5f07e0 278 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
8a40a180
FB
279 for(;;) {
280 tb = *ptb1;
9fd1a948
PB
281 if (!tb) {
282 return NULL;
283 }
5fafdf24 284 if (tb->pc == pc &&
8a40a180 285 tb->page_addr[0] == phys_page1 &&
5fafdf24 286 tb->cs_base == cs_base &&
8a40a180
FB
287 tb->flags == flags) {
288 /* check next page if needed */
289 if (tb->page_addr[1] != -1) {
337fc758
BS
290 tb_page_addr_t phys_page2;
291
5fafdf24 292 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 293 TARGET_PAGE_SIZE;
41c1b1c9 294 phys_page2 = get_page_addr_code(env, virt_page2);
9fd1a948
PB
295 if (tb->page_addr[1] == phys_page2) {
296 break;
297 }
8a40a180 298 } else {
9fd1a948 299 break;
8a40a180
FB
300 }
301 }
302 ptb1 = &tb->phys_hash_next;
303 }
3b46e624 304
9fd1a948
PB
305 /* Move the TB to the head of the list */
306 *ptb1 = tb->phys_hash_next;
307 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
308 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
309 return tb;
310}
311
312static TranslationBlock *tb_find_slow(CPUState *cpu,
313 target_ulong pc,
314 target_ulong cs_base,
315 uint64_t flags)
316{
317 TranslationBlock *tb;
318
319 tb = tb_find_physical(cpu, pc, cs_base, flags);
320 if (tb) {
321 goto found;
322 }
323
324#ifdef CONFIG_USER_ONLY
325 /* mmap_lock is needed by tb_gen_code, and mmap_lock must be
326 * taken outside tb_lock. Since we're momentarily dropping
327 * tb_lock, there's a chance that our desired tb has been
328 * translated.
329 */
330 tb_unlock();
331 mmap_lock();
332 tb_lock();
333 tb = tb_find_physical(cpu, pc, cs_base, flags);
334 if (tb) {
335 mmap_unlock();
336 goto found;
2c90fe2b 337 }
9fd1a948
PB
338#endif
339
340 /* if no translated code available, then translate it now */
341 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
342
343#ifdef CONFIG_USER_ONLY
344 mmap_unlock();
345#endif
346
347found:
8a40a180 348 /* we add the TB in the virtual pc hash table */
8cd70437 349 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB
350 return tb;
351}
352
ea3e9847 353static inline TranslationBlock *tb_find_fast(CPUState *cpu)
8a40a180 354{
ea3e9847 355 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
8a40a180
FB
356 TranslationBlock *tb;
357 target_ulong cs_base, pc;
6b917547 358 int flags;
8a40a180
FB
359
360 /* we record a subset of the CPU state. It will
361 always be the same before a given translated block
362 is executed. */
6b917547 363 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
8cd70437 364 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS
365 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
366 tb->flags != flags)) {
ea3e9847 367 tb = tb_find_slow(cpu, pc, cs_base, flags);
8a40a180
FB
368 }
369 return tb;
370}
371
ea3e9847 372static void cpu_handle_debug_exception(CPUState *cpu)
1009d2ed 373{
86025ee4 374 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
375 CPUWatchpoint *wp;
376
ff4700b0
AF
377 if (!cpu->watchpoint_hit) {
378 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
379 wp->flags &= ~BP_WATCHPOINT_HIT;
380 }
381 }
86025ee4
PM
382
383 cc->debug_excp_handler(cpu);
1009d2ed
JK
384}
385
7d13299d
FB
386/* main execution loop */
387
e0c38211 388bool exit_request;
9373e632 389CPUState *tcg_current_cpu;
1a28cac3 390
ea3e9847 391int cpu_exec(CPUState *cpu)
7d13299d 392{
97a8ea5a 393 CPUClass *cc = CPU_GET_CLASS(cpu);
693fa551
AF
394#ifdef TARGET_I386
395 X86CPU *x86_cpu = X86_CPU(cpu);
ea3e9847 396 CPUArchState *env = &x86_cpu->env;
97a8ea5a 397#endif
8a40a180 398 int ret, interrupt_request;
8a40a180 399 TranslationBlock *tb;
c27004ec 400 uint8_t *tc_ptr;
3e9bd63a 401 uintptr_t next_tb;
c2aa5f81
ST
402 SyncClocks sc;
403
259186a7 404 if (cpu->halted) {
3993c6bd 405 if (!cpu_has_work(cpu)) {
eda48c34
PB
406 return EXCP_HALTED;
407 }
408
259186a7 409 cpu->halted = 0;
eda48c34 410 }
5a1e3cfc 411
4917cf44 412 current_cpu = cpu;
9373e632 413 atomic_mb_set(&tcg_current_cpu, cpu);
79e2b9ae
PB
414 rcu_read_lock();
415
aed807c8 416 if (unlikely(atomic_mb_read(&exit_request))) {
fcd7d003 417 cpu->exit_request = 1;
1a28cac3
MT
418 }
419
cffe7b32 420 cc->cpu_exec_enter(cpu);
9d27abd9 421
c2aa5f81
ST
422 /* Calculate difference between guest clock and host clock.
423 * This delay includes the delay of the last cycle, so
424 * what we have to do is sleep until it is 0. As for the
425 * advance/delay we gain here, we try to fix it next time.
426 */
427 init_delay_params(&sc, cpu);
428
7d13299d 429 /* prepare setjmp context for exception handling */
3fb2ded1 430 for(;;) {
6f03bef0 431 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
3fb2ded1 432 /* if an exception is pending, we execute it here */
27103424
AF
433 if (cpu->exception_index >= 0) {
434 if (cpu->exception_index >= EXCP_INTERRUPT) {
3fb2ded1 435 /* exit request from the cpu execution loop */
27103424 436 ret = cpu->exception_index;
1009d2ed 437 if (ret == EXCP_DEBUG) {
ea3e9847 438 cpu_handle_debug_exception(cpu);
1009d2ed 439 }
e511b4d7 440 cpu->exception_index = -1;
3fb2ded1 441 break;
72d239ed
AJ
442 } else {
443#if defined(CONFIG_USER_ONLY)
3fb2ded1 444 /* if user mode only, we simulate a fake exception
9f083493 445 which will be handled outside the cpu execution
3fb2ded1 446 loop */
83479e77 447#if defined(TARGET_I386)
97a8ea5a 448 cc->do_interrupt(cpu);
83479e77 449#endif
27103424 450 ret = cpu->exception_index;
e511b4d7 451 cpu->exception_index = -1;
3fb2ded1 452 break;
72d239ed 453#else
97a8ea5a 454 cc->do_interrupt(cpu);
27103424 455 cpu->exception_index = -1;
83479e77 456#endif
3fb2ded1 457 }
5fafdf24 458 }
9df217a3 459
b5fc09ae 460 next_tb = 0; /* force lookup of first TB */
3fb2ded1 461 for(;;) {
259186a7 462 interrupt_request = cpu->interrupt_request;
e1638bd8 463 if (unlikely(interrupt_request)) {
ed2803da 464 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
e1638bd8 465 /* Mask out external interrupts for this step. */
3125f763 466 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 467 }
6658ffb8 468 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
259186a7 469 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
27103424 470 cpu->exception_index = EXCP_DEBUG;
5638d180 471 cpu_loop_exit(cpu);
6658ffb8 472 }
a90b7318 473 if (interrupt_request & CPU_INTERRUPT_HALT) {
259186a7
AF
474 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
475 cpu->halted = 1;
27103424 476 cpu->exception_index = EXCP_HLT;
5638d180 477 cpu_loop_exit(cpu);
a90b7318 478 }
4a92a558
PB
479#if defined(TARGET_I386)
480 if (interrupt_request & CPU_INTERRUPT_INIT) {
481 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
482 do_cpu_init(x86_cpu);
483 cpu->exception_index = EXCP_HALTED;
484 cpu_loop_exit(cpu);
485 }
486#else
487 if (interrupt_request & CPU_INTERRUPT_RESET) {
488 cpu_reset(cpu);
489 }
68a79315 490#endif
9585db68
RH
491 /* The target hook has 3 exit conditions:
492 False when the interrupt isn't processed,
493 True when it is, and we should restart on a new TB,
494 and via longjmp via cpu_loop_exit. */
495 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
496 next_tb = 0;
497 }
498 /* Don't use the cached interrupt_request value,
499 do_interrupt may have updated the EXITTB flag. */
259186a7
AF
500 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
501 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bf3e8bf1
FB
502 /* ensure that no TB jump will be modified as
503 the program flow was changed */
b5fc09ae 504 next_tb = 0;
bf3e8bf1 505 }
be214e6c 506 }
fcd7d003
AF
507 if (unlikely(cpu->exit_request)) {
508 cpu->exit_request = 0;
27103424 509 cpu->exception_index = EXCP_INTERRUPT;
5638d180 510 cpu_loop_exit(cpu);
3fb2ded1 511 }
677ef623 512 tb_lock();
ea3e9847 513 tb = tb_find_fast(cpu);
d5975363
PB
514 /* Note: we do it here to avoid a gcc bug on Mac OS X when
515 doing it in tb_find_slow */
5e5f07e0 516 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
d5975363
PB
517 /* as some TB could have been invalidated because
518 of memory exceptions while generating the code, we
519 must recompute the hash index here */
520 next_tb = 0;
5e5f07e0 521 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
d5975363 522 }
c30d1aea
PM
523 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
524 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
525 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
526 }
8a40a180
FB
527 /* see if we can patch the calling TB. When the TB
528 spans two pages, we cannot safely do a direct
529 jump. */
040f2fb2 530 if (next_tb != 0 && tb->page_addr[1] == -1) {
0980011b
PM
531 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
532 next_tb & TB_EXIT_MASK, tb);
3fb2ded1 533 }
677ef623 534 tb_unlock();
fcd7d003 535 if (likely(!cpu->exit_request)) {
6db8b538 536 trace_exec_tb(tb, tb->pc);
2e70f6ef 537 tc_ptr = tb->tc_ptr;
e965fc38 538 /* execute the generated code */
b0a46fa7 539 cpu->current_tb = tb;
77211379 540 next_tb = cpu_tb_exec(cpu, tc_ptr);
b0a46fa7 541 cpu->current_tb = NULL;
378df4b2
PM
542 switch (next_tb & TB_EXIT_MASK) {
543 case TB_EXIT_REQUESTED:
544 /* Something asked us to stop executing
545 * chained TBs; just continue round the main
546 * loop. Whatever requested the exit will also
547 * have set something else (eg exit_request or
548 * interrupt_request) which we will handle
ab096a75
PB
549 * next time around the loop. But we need to
550 * ensure the tcg_exit_req read in generated code
551 * comes before the next read of cpu->exit_request
552 * or cpu->interrupt_request.
378df4b2 553 */
ab096a75 554 smp_rmb();
378df4b2
PM
555 next_tb = 0;
556 break;
557 case TB_EXIT_ICOUNT_EXPIRED:
558 {
bf20dc07 559 /* Instruction counter expired. */
52851b7e 560 int insns_left = cpu->icount_decr.u32;
efee7340 561 if (cpu->icount_extra && insns_left >= 0) {
2e70f6ef 562 /* Refill decrementer and continue execution. */
efee7340 563 cpu->icount_extra += insns_left;
52851b7e 564 insns_left = MIN(0xffff, cpu->icount_extra);
efee7340 565 cpu->icount_extra -= insns_left;
28ecfd7a 566 cpu->icount_decr.u16.low = insns_left;
2e70f6ef
PB
567 } else {
568 if (insns_left > 0) {
569 /* Execute remaining instructions. */
52851b7e 570 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
ea3e9847 571 cpu_exec_nocache(cpu, insns_left, tb);
c2aa5f81 572 align_clocks(&sc, cpu);
2e70f6ef 573 }
27103424 574 cpu->exception_index = EXCP_INTERRUPT;
2e70f6ef 575 next_tb = 0;
5638d180 576 cpu_loop_exit(cpu);
2e70f6ef 577 }
378df4b2
PM
578 break;
579 }
580 default:
581 break;
2e70f6ef
PB
582 }
583 }
c2aa5f81
ST
584 /* Try to align the host and virtual clocks
585 if the guest is in advance */
586 align_clocks(&sc, cpu);
4cbf74b6
FB
587 /* reset soft MMU for next block (it can currently
588 only be set by a memory fault) */
50a518e3 589 } /* for(;;) */
0d101938
JK
590 } else {
591 /* Reload env after longjmp - the compiler may have smashed all
592 * local variables as longjmp is marked 'noreturn'. */
4917cf44 593 cpu = current_cpu;
6c78f29a 594 cc = CPU_GET_CLASS(cpu);
626cf8f4 595 cpu->can_do_io = 1;
693fa551
AF
596#ifdef TARGET_I386
597 x86_cpu = X86_CPU(cpu);
ea3e9847 598 env = &x86_cpu->env;
6c78f29a 599#endif
677ef623 600 tb_lock_reset();
7d13299d 601 }
3fb2ded1
FB
602 } /* for(;;) */
603
cffe7b32 604 cc->cpu_exec_exit(cpu);
79e2b9ae 605 rcu_read_unlock();
1057eaa7 606
4917cf44
AF
607 /* fail safe : never use current_cpu outside cpu_exec() */
608 current_cpu = NULL;
9373e632
PB
609
610 /* Does not need atomic_mb_set because a spurious wakeup is okay. */
611 atomic_set(&tcg_current_cpu, NULL);
7d13299d
FB
612 return ret;
613}