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7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
6db8b538 21#include "trace.h"
76cad711 22#include "disas/disas.h"
7cb69cae 23#include "tcg.h"
1de7afc9 24#include "qemu/atomic.h"
9c17d615 25#include "sysemu/qtest.h"
c2aa5f81
ST
26#include "qemu/timer.h"
27
28/* -icount align implementation. */
29
30typedef struct SyncClocks {
31 int64_t diff_clk;
32 int64_t last_cpu_icount;
7f7bc144 33 int64_t realtime_clock;
c2aa5f81
ST
34} SyncClocks;
35
36#if !defined(CONFIG_USER_ONLY)
37/* Allow the guest to have a max 3ms advance.
38 * The difference between the 2 clocks could therefore
39 * oscillate around 0.
40 */
41#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
42#define THRESHOLD_REDUCE 1.5
43#define MAX_DELAY_PRINT_RATE 2000000000LL
44#define MAX_NB_PRINTS 100
c2aa5f81
ST
45
46static void align_clocks(SyncClocks *sc, const CPUState *cpu)
47{
48 int64_t cpu_icount;
49
50 if (!icount_align_option) {
51 return;
52 }
53
54 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
55 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
56 sc->last_cpu_icount = cpu_icount;
57
58 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
59#ifndef _WIN32
60 struct timespec sleep_delay, rem_delay;
61 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
62 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
63 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 64 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
65 } else {
66 sc->diff_clk = 0;
67 }
68#else
69 Sleep(sc->diff_clk / SCALE_MS);
70 sc->diff_clk = 0;
71#endif
72 }
73}
74
7f7bc144
ST
75static void print_delay(const SyncClocks *sc)
76{
77 static float threshold_delay;
78 static int64_t last_realtime_clock;
79 static int nb_prints;
80
81 if (icount_align_option &&
82 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
83 nb_prints < MAX_NB_PRINTS) {
84 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
85 (-sc->diff_clk / (float)1000000000LL <
86 (threshold_delay - THRESHOLD_REDUCE))) {
87 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
88 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
89 threshold_delay - 1,
90 threshold_delay);
91 nb_prints++;
92 last_realtime_clock = sc->realtime_clock;
93 }
94 }
95}
96
c2aa5f81
ST
97static void init_delay_params(SyncClocks *sc,
98 const CPUState *cpu)
99{
100 if (!icount_align_option) {
101 return;
102 }
2e91cc62
PB
103 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
104 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
c2aa5f81 105 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
27498bef
ST
106 if (sc->diff_clk < max_delay) {
107 max_delay = sc->diff_clk;
108 }
109 if (sc->diff_clk > max_advance) {
110 max_advance = sc->diff_clk;
111 }
7f7bc144
ST
112
113 /* Print every 2s max if the guest is late. We limit the number
114 of printed messages to NB_PRINT_MAX(currently 100) */
115 print_delay(sc);
c2aa5f81
ST
116}
117#else
118static void align_clocks(SyncClocks *sc, const CPUState *cpu)
119{
120}
121
122static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
123{
124}
125#endif /* CONFIG USER ONLY */
7d13299d 126
5638d180 127void cpu_loop_exit(CPUState *cpu)
e4533c7a 128{
d77953b9 129 cpu->current_tb = NULL;
6f03bef0 130 siglongjmp(cpu->jmp_env, 1);
e4533c7a 131}
bfed01fc 132
fbf9eeb3
FB
133/* exit the current TB from a signal handler. The host registers are
134 restored in a state compatible with the CPU emulator
135 */
9eff14f3 136#if defined(CONFIG_SOFTMMU)
0ea8cb88 137void cpu_resume_from_signal(CPUState *cpu, void *puc)
9eff14f3 138{
9eff14f3
BS
139 /* XXX: restore cpu registers saved in host registers */
140
27103424 141 cpu->exception_index = -1;
6f03bef0 142 siglongjmp(cpu->jmp_env, 1);
9eff14f3 143}
9eff14f3 144#endif
fbf9eeb3 145
77211379
PM
146/* Execute a TB, and fix up the CPU state afterwards if necessary */
147static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
148{
149 CPUArchState *env = cpu->env_ptr;
03afa5f8
RH
150 uintptr_t next_tb;
151
152#if defined(DEBUG_DISAS)
153 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
154#if defined(TARGET_I386)
155 log_cpu_state(cpu, CPU_DUMP_CCOP);
156#elif defined(TARGET_M68K)
157 /* ??? Should not modify env state for dumping. */
158 cpu_m68k_flush_flags(env, env->cc_op);
159 env->cc_op = CC_OP_FLAGS;
160 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
161 log_cpu_state(cpu, 0);
162#else
163 log_cpu_state(cpu, 0);
164#endif
165 }
166#endif /* DEBUG_DISAS */
167
626cf8f4 168 cpu->can_do_io = 0;
03afa5f8 169 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 170 cpu->can_do_io = 1;
6db8b538
AB
171 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
172 next_tb & TB_EXIT_MASK);
173
77211379
PM
174 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
175 /* We didn't start executing this TB (eg because the instruction
176 * counter hit zero); we must restore the guest PC to the address
177 * of the start of the TB.
178 */
bdf7ae5b 179 CPUClass *cc = CPU_GET_CLASS(cpu);
77211379 180 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
bdf7ae5b
AF
181 if (cc->synchronize_from_tb) {
182 cc->synchronize_from_tb(cpu, tb);
183 } else {
184 assert(cc->set_pc);
185 cc->set_pc(cpu, tb->pc);
186 }
77211379 187 }
378df4b2
PM
188 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
189 /* We were asked to stop executing TBs (probably a pending
190 * interrupt. We've now stopped, so clear the flag.
191 */
192 cpu->tcg_exit_req = 0;
193 }
77211379
PM
194 return next_tb;
195}
196
2e70f6ef
PB
197/* Execute the code without caching the generated code. An interpreter
198 could be used if available. */
9349b4f9 199static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
cea5f9a2 200 TranslationBlock *orig_tb)
2e70f6ef 201{
d77953b9 202 CPUState *cpu = ENV_GET_CPU(env);
2e70f6ef 203 TranslationBlock *tb;
b4ac20b4
PD
204 target_ulong pc = orig_tb->pc;
205 target_ulong cs_base = orig_tb->cs_base;
206 uint64_t flags = orig_tb->flags;
2e70f6ef
PB
207
208 /* Should never happen.
209 We only end up here when an existing TB is too long. */
210 if (max_cycles > CF_COUNT_MASK)
211 max_cycles = CF_COUNT_MASK;
212
b4ac20b4
PD
213 /* tb_gen_code can flush our orig_tb, invalidate it now */
214 tb_phys_invalidate(orig_tb, -1);
215 tb = tb_gen_code(cpu, pc, cs_base, flags,
d8a499f1 216 max_cycles | CF_NOCACHE);
d77953b9 217 cpu->current_tb = tb;
2e70f6ef 218 /* execute the generated code */
6db8b538 219 trace_exec_tb_nocache(tb, tb->pc);
77211379 220 cpu_tb_exec(cpu, tb->tc_ptr);
d77953b9 221 cpu->current_tb = NULL;
2e70f6ef
PB
222 tb_phys_invalidate(tb, -1);
223 tb_free(tb);
224}
225
9349b4f9 226static TranslationBlock *tb_find_slow(CPUArchState *env,
cea5f9a2 227 target_ulong pc,
8a40a180 228 target_ulong cs_base,
c068688b 229 uint64_t flags)
8a40a180 230{
8cd70437 231 CPUState *cpu = ENV_GET_CPU(env);
8a40a180 232 TranslationBlock *tb, **ptb1;
8a40a180 233 unsigned int h;
337fc758 234 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 235 target_ulong virt_page2;
3b46e624 236
5e5f07e0 237 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
3b46e624 238
8a40a180 239 /* find translated block using physical mappings */
41c1b1c9 240 phys_pc = get_page_addr_code(env, pc);
8a40a180 241 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180 242 h = tb_phys_hash_func(phys_pc);
5e5f07e0 243 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
8a40a180
FB
244 for(;;) {
245 tb = *ptb1;
246 if (!tb)
247 goto not_found;
5fafdf24 248 if (tb->pc == pc &&
8a40a180 249 tb->page_addr[0] == phys_page1 &&
5fafdf24 250 tb->cs_base == cs_base &&
8a40a180
FB
251 tb->flags == flags) {
252 /* check next page if needed */
253 if (tb->page_addr[1] != -1) {
337fc758
BS
254 tb_page_addr_t phys_page2;
255
5fafdf24 256 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 257 TARGET_PAGE_SIZE;
41c1b1c9 258 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB
259 if (tb->page_addr[1] == phys_page2)
260 goto found;
261 } else {
262 goto found;
263 }
264 }
265 ptb1 = &tb->phys_hash_next;
266 }
267 not_found:
2e70f6ef 268 /* if no translated code available, then translate it now */
648f034c 269 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
3b46e624 270
8a40a180 271 found:
2c90fe2b
KB
272 /* Move the last found TB to the head of the list */
273 if (likely(*ptb1)) {
274 *ptb1 = tb->phys_hash_next;
5e5f07e0
EV
275 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
276 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
2c90fe2b 277 }
8a40a180 278 /* we add the TB in the virtual pc hash table */
8cd70437 279 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB
280 return tb;
281}
282
9349b4f9 283static inline TranslationBlock *tb_find_fast(CPUArchState *env)
8a40a180 284{
8cd70437 285 CPUState *cpu = ENV_GET_CPU(env);
8a40a180
FB
286 TranslationBlock *tb;
287 target_ulong cs_base, pc;
6b917547 288 int flags;
8a40a180
FB
289
290 /* we record a subset of the CPU state. It will
291 always be the same before a given translated block
292 is executed. */
6b917547 293 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
8cd70437 294 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS
295 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
296 tb->flags != flags)) {
cea5f9a2 297 tb = tb_find_slow(env, pc, cs_base, flags);
8a40a180
FB
298 }
299 return tb;
300}
301
9349b4f9 302static void cpu_handle_debug_exception(CPUArchState *env)
1009d2ed 303{
ff4700b0 304 CPUState *cpu = ENV_GET_CPU(env);
86025ee4 305 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
306 CPUWatchpoint *wp;
307
ff4700b0
AF
308 if (!cpu->watchpoint_hit) {
309 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
310 wp->flags &= ~BP_WATCHPOINT_HIT;
311 }
312 }
86025ee4
PM
313
314 cc->debug_excp_handler(cpu);
1009d2ed
JK
315}
316
7d13299d
FB
317/* main execution loop */
318
1a28cac3
MT
319volatile sig_atomic_t exit_request;
320
9349b4f9 321int cpu_exec(CPUArchState *env)
7d13299d 322{
c356a1bc 323 CPUState *cpu = ENV_GET_CPU(env);
97a8ea5a 324 CPUClass *cc = CPU_GET_CLASS(cpu);
693fa551
AF
325#ifdef TARGET_I386
326 X86CPU *x86_cpu = X86_CPU(cpu);
97a8ea5a 327#endif
8a40a180 328 int ret, interrupt_request;
8a40a180 329 TranslationBlock *tb;
c27004ec 330 uint8_t *tc_ptr;
3e9bd63a 331 uintptr_t next_tb;
c2aa5f81
ST
332 SyncClocks sc;
333
bae2c270
PM
334 /* This must be volatile so it is not trashed by longjmp() */
335 volatile bool have_tb_lock = false;
8c6939c0 336
259186a7 337 if (cpu->halted) {
3993c6bd 338 if (!cpu_has_work(cpu)) {
eda48c34
PB
339 return EXCP_HALTED;
340 }
341
259186a7 342 cpu->halted = 0;
eda48c34 343 }
5a1e3cfc 344
4917cf44 345 current_cpu = cpu;
e4533c7a 346
4917cf44 347 /* As long as current_cpu is null, up to the assignment just above,
ec9bd89f
OH
348 * requests by other threads to exit the execution loop are expected to
349 * be issued using the exit_request global. We must make sure that our
4917cf44 350 * evaluation of the global value is performed past the current_cpu
ec9bd89f
OH
351 * value transition point, which requires a memory barrier as well as
352 * an instruction scheduling constraint on modern architectures. */
353 smp_mb();
354
c629a4bc 355 if (unlikely(exit_request)) {
fcd7d003 356 cpu->exit_request = 1;
1a28cac3
MT
357 }
358
cffe7b32 359 cc->cpu_exec_enter(cpu);
9d27abd9 360
c2aa5f81
ST
361 /* Calculate difference between guest clock and host clock.
362 * This delay includes the delay of the last cycle, so
363 * what we have to do is sleep until it is 0. As for the
364 * advance/delay we gain here, we try to fix it next time.
365 */
366 init_delay_params(&sc, cpu);
367
7d13299d 368 /* prepare setjmp context for exception handling */
3fb2ded1 369 for(;;) {
6f03bef0 370 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
3fb2ded1 371 /* if an exception is pending, we execute it here */
27103424
AF
372 if (cpu->exception_index >= 0) {
373 if (cpu->exception_index >= EXCP_INTERRUPT) {
3fb2ded1 374 /* exit request from the cpu execution loop */
27103424 375 ret = cpu->exception_index;
1009d2ed
JK
376 if (ret == EXCP_DEBUG) {
377 cpu_handle_debug_exception(env);
378 }
e511b4d7 379 cpu->exception_index = -1;
3fb2ded1 380 break;
72d239ed
AJ
381 } else {
382#if defined(CONFIG_USER_ONLY)
3fb2ded1 383 /* if user mode only, we simulate a fake exception
9f083493 384 which will be handled outside the cpu execution
3fb2ded1 385 loop */
83479e77 386#if defined(TARGET_I386)
97a8ea5a 387 cc->do_interrupt(cpu);
83479e77 388#endif
27103424 389 ret = cpu->exception_index;
e511b4d7 390 cpu->exception_index = -1;
3fb2ded1 391 break;
72d239ed 392#else
97a8ea5a 393 cc->do_interrupt(cpu);
27103424 394 cpu->exception_index = -1;
83479e77 395#endif
3fb2ded1 396 }
5fafdf24 397 }
9df217a3 398
b5fc09ae 399 next_tb = 0; /* force lookup of first TB */
3fb2ded1 400 for(;;) {
259186a7 401 interrupt_request = cpu->interrupt_request;
e1638bd8 402 if (unlikely(interrupt_request)) {
ed2803da 403 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
e1638bd8 404 /* Mask out external interrupts for this step. */
3125f763 405 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 406 }
6658ffb8 407 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
259186a7 408 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
27103424 409 cpu->exception_index = EXCP_DEBUG;
5638d180 410 cpu_loop_exit(cpu);
6658ffb8 411 }
a90b7318 412 if (interrupt_request & CPU_INTERRUPT_HALT) {
259186a7
AF
413 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
414 cpu->halted = 1;
27103424 415 cpu->exception_index = EXCP_HLT;
5638d180 416 cpu_loop_exit(cpu);
a90b7318 417 }
4a92a558
PB
418#if defined(TARGET_I386)
419 if (interrupt_request & CPU_INTERRUPT_INIT) {
420 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
421 do_cpu_init(x86_cpu);
422 cpu->exception_index = EXCP_HALTED;
423 cpu_loop_exit(cpu);
424 }
425#else
426 if (interrupt_request & CPU_INTERRUPT_RESET) {
427 cpu_reset(cpu);
428 }
68a79315 429#endif
9585db68
RH
430 /* The target hook has 3 exit conditions:
431 False when the interrupt isn't processed,
432 True when it is, and we should restart on a new TB,
433 and via longjmp via cpu_loop_exit. */
434 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
435 next_tb = 0;
436 }
437 /* Don't use the cached interrupt_request value,
438 do_interrupt may have updated the EXITTB flag. */
259186a7
AF
439 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
440 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bf3e8bf1
FB
441 /* ensure that no TB jump will be modified as
442 the program flow was changed */
b5fc09ae 443 next_tb = 0;
bf3e8bf1 444 }
be214e6c 445 }
fcd7d003
AF
446 if (unlikely(cpu->exit_request)) {
447 cpu->exit_request = 0;
27103424 448 cpu->exception_index = EXCP_INTERRUPT;
5638d180 449 cpu_loop_exit(cpu);
3fb2ded1 450 }
5e5f07e0 451 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
bae2c270 452 have_tb_lock = true;
cea5f9a2 453 tb = tb_find_fast(env);
d5975363
PB
454 /* Note: we do it here to avoid a gcc bug on Mac OS X when
455 doing it in tb_find_slow */
5e5f07e0 456 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
d5975363
PB
457 /* as some TB could have been invalidated because
458 of memory exceptions while generating the code, we
459 must recompute the hash index here */
460 next_tb = 0;
5e5f07e0 461 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
d5975363 462 }
c30d1aea
PM
463 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
464 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
465 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
466 }
8a40a180
FB
467 /* see if we can patch the calling TB. When the TB
468 spans two pages, we cannot safely do a direct
469 jump. */
040f2fb2 470 if (next_tb != 0 && tb->page_addr[1] == -1) {
0980011b
PM
471 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
472 next_tb & TB_EXIT_MASK, tb);
3fb2ded1 473 }
bae2c270 474 have_tb_lock = false;
5e5f07e0 475 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
55e8b85e 476
477 /* cpu_interrupt might be called while translating the
478 TB, but before it is linked into a potentially
479 infinite loop and becomes env->current_tb. Avoid
480 starting execution if there is a pending interrupt. */
d77953b9 481 cpu->current_tb = tb;
b0052d15 482 barrier();
fcd7d003 483 if (likely(!cpu->exit_request)) {
6db8b538 484 trace_exec_tb(tb, tb->pc);
2e70f6ef 485 tc_ptr = tb->tc_ptr;
e965fc38 486 /* execute the generated code */
77211379 487 next_tb = cpu_tb_exec(cpu, tc_ptr);
378df4b2
PM
488 switch (next_tb & TB_EXIT_MASK) {
489 case TB_EXIT_REQUESTED:
490 /* Something asked us to stop executing
491 * chained TBs; just continue round the main
492 * loop. Whatever requested the exit will also
493 * have set something else (eg exit_request or
494 * interrupt_request) which we will handle
495 * next time around the loop.
496 */
497 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
498 next_tb = 0;
499 break;
500 case TB_EXIT_ICOUNT_EXPIRED:
501 {
bf20dc07 502 /* Instruction counter expired. */
2e70f6ef 503 int insns_left;
0980011b 504 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
28ecfd7a 505 insns_left = cpu->icount_decr.u32;
efee7340 506 if (cpu->icount_extra && insns_left >= 0) {
2e70f6ef 507 /* Refill decrementer and continue execution. */
efee7340
AF
508 cpu->icount_extra += insns_left;
509 if (cpu->icount_extra > 0xffff) {
2e70f6ef
PB
510 insns_left = 0xffff;
511 } else {
efee7340 512 insns_left = cpu->icount_extra;
2e70f6ef 513 }
efee7340 514 cpu->icount_extra -= insns_left;
28ecfd7a 515 cpu->icount_decr.u16.low = insns_left;
2e70f6ef
PB
516 } else {
517 if (insns_left > 0) {
518 /* Execute remaining instructions. */
cea5f9a2 519 cpu_exec_nocache(env, insns_left, tb);
c2aa5f81 520 align_clocks(&sc, cpu);
2e70f6ef 521 }
27103424 522 cpu->exception_index = EXCP_INTERRUPT;
2e70f6ef 523 next_tb = 0;
5638d180 524 cpu_loop_exit(cpu);
2e70f6ef 525 }
378df4b2
PM
526 break;
527 }
528 default:
529 break;
2e70f6ef
PB
530 }
531 }
d77953b9 532 cpu->current_tb = NULL;
c2aa5f81
ST
533 /* Try to align the host and virtual clocks
534 if the guest is in advance */
535 align_clocks(&sc, cpu);
4cbf74b6
FB
536 /* reset soft MMU for next block (it can currently
537 only be set by a memory fault) */
50a518e3 538 } /* for(;;) */
0d101938
JK
539 } else {
540 /* Reload env after longjmp - the compiler may have smashed all
541 * local variables as longjmp is marked 'noreturn'. */
4917cf44
AF
542 cpu = current_cpu;
543 env = cpu->env_ptr;
6c78f29a 544 cc = CPU_GET_CLASS(cpu);
626cf8f4 545 cpu->can_do_io = 1;
693fa551
AF
546#ifdef TARGET_I386
547 x86_cpu = X86_CPU(cpu);
6c78f29a 548#endif
bae2c270
PM
549 if (have_tb_lock) {
550 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
551 have_tb_lock = false;
552 }
7d13299d 553 }
3fb2ded1
FB
554 } /* for(;;) */
555
cffe7b32 556 cc->cpu_exec_exit(cpu);
1057eaa7 557
4917cf44
AF
558 /* fail safe : never use current_cpu outside cpu_exec() */
559 current_cpu = NULL;
7d13299d
FB
560 return ret;
561}