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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
93ac68bc | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
50 | ||
fbf9eeb3 FB |
51 | /* exit the current TB from a signal handler. The host registers are |
52 | restored in a state compatible with the CPU emulator | |
53 | */ | |
54 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
55 | { | |
56 | #if !defined(CONFIG_SOFTMMU) | |
57 | struct ucontext *uc = puc; | |
58 | #endif | |
59 | ||
60 | env = env1; | |
61 | ||
62 | /* XXX: restore cpu registers saved in host registers */ | |
63 | ||
64 | #if !defined(CONFIG_SOFTMMU) | |
65 | if (puc) { | |
66 | /* XXX: use siglongjmp ? */ | |
67 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
68 | } | |
69 | #endif | |
70 | longjmp(env->jmp_env, 1); | |
71 | } | |
72 | ||
7d13299d FB |
73 | /* main execution loop */ |
74 | ||
e4533c7a | 75 | int cpu_exec(CPUState *env1) |
7d13299d | 76 | { |
e4533c7a FB |
77 | int saved_T0, saved_T1, saved_T2; |
78 | CPUState *saved_env; | |
04369ff2 FB |
79 | #ifdef reg_EAX |
80 | int saved_EAX; | |
81 | #endif | |
82 | #ifdef reg_ECX | |
83 | int saved_ECX; | |
84 | #endif | |
85 | #ifdef reg_EDX | |
86 | int saved_EDX; | |
87 | #endif | |
88 | #ifdef reg_EBX | |
89 | int saved_EBX; | |
90 | #endif | |
91 | #ifdef reg_ESP | |
92 | int saved_ESP; | |
93 | #endif | |
94 | #ifdef reg_EBP | |
95 | int saved_EBP; | |
96 | #endif | |
97 | #ifdef reg_ESI | |
98 | int saved_ESI; | |
99 | #endif | |
100 | #ifdef reg_EDI | |
101 | int saved_EDI; | |
8c6939c0 FB |
102 | #endif |
103 | #ifdef __sparc__ | |
104 | int saved_i7, tmp_T0; | |
04369ff2 | 105 | #endif |
68a79315 | 106 | int code_gen_size, ret, interrupt_request; |
7d13299d | 107 | void (*gen_func)(void); |
9de5e440 | 108 | TranslationBlock *tb, **ptb; |
c27004ec FB |
109 | target_ulong cs_base, pc; |
110 | uint8_t *tc_ptr; | |
6dbad63e | 111 | unsigned int flags; |
8c6939c0 | 112 | |
7d13299d | 113 | /* first we save global registers */ |
c27004ec FB |
114 | saved_env = env; |
115 | env = env1; | |
7d13299d FB |
116 | saved_T0 = T0; |
117 | saved_T1 = T1; | |
e4533c7a | 118 | saved_T2 = T2; |
e4533c7a FB |
119 | #ifdef __sparc__ |
120 | /* we also save i7 because longjmp may not restore it */ | |
121 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
122 | #endif | |
123 | ||
124 | #if defined(TARGET_I386) | |
04369ff2 FB |
125 | #ifdef reg_EAX |
126 | saved_EAX = EAX; | |
04369ff2 FB |
127 | #endif |
128 | #ifdef reg_ECX | |
129 | saved_ECX = ECX; | |
04369ff2 FB |
130 | #endif |
131 | #ifdef reg_EDX | |
132 | saved_EDX = EDX; | |
04369ff2 FB |
133 | #endif |
134 | #ifdef reg_EBX | |
135 | saved_EBX = EBX; | |
04369ff2 FB |
136 | #endif |
137 | #ifdef reg_ESP | |
138 | saved_ESP = ESP; | |
04369ff2 FB |
139 | #endif |
140 | #ifdef reg_EBP | |
141 | saved_EBP = EBP; | |
04369ff2 FB |
142 | #endif |
143 | #ifdef reg_ESI | |
144 | saved_ESI = ESI; | |
04369ff2 FB |
145 | #endif |
146 | #ifdef reg_EDI | |
147 | saved_EDI = EDI; | |
04369ff2 | 148 | #endif |
0d1a29f9 FB |
149 | |
150 | env_to_regs(); | |
9de5e440 | 151 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
152 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
153 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 154 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 155 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a FB |
156 | #elif defined(TARGET_ARM) |
157 | { | |
158 | unsigned int psr; | |
159 | psr = env->cpsr; | |
160 | env->CF = (psr >> 29) & 1; | |
161 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; | |
162 | env->VF = (psr << 3) & 0x80000000; | |
99c475ab FB |
163 | env->QF = (psr >> 27) & 1; |
164 | env->cpsr = psr & ~CACHED_CPSR_BITS; | |
e4533c7a | 165 | } |
93ac68bc | 166 | #elif defined(TARGET_SPARC) |
67867308 | 167 | #elif defined(TARGET_PPC) |
e4533c7a FB |
168 | #else |
169 | #error unsupported target CPU | |
170 | #endif | |
3fb2ded1 | 171 | env->exception_index = -1; |
9d27abd9 | 172 | |
7d13299d | 173 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
174 | for(;;) { |
175 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 176 | env->current_tb = NULL; |
3fb2ded1 FB |
177 | /* if an exception is pending, we execute it here */ |
178 | if (env->exception_index >= 0) { | |
179 | if (env->exception_index >= EXCP_INTERRUPT) { | |
180 | /* exit request from the cpu execution loop */ | |
181 | ret = env->exception_index; | |
182 | break; | |
183 | } else if (env->user_mode_only) { | |
184 | /* if user mode only, we simulate a fake exception | |
185 | which will be hanlded outside the cpu execution | |
186 | loop */ | |
83479e77 | 187 | #if defined(TARGET_I386) |
3fb2ded1 FB |
188 | do_interrupt_user(env->exception_index, |
189 | env->exception_is_int, | |
190 | env->error_code, | |
191 | env->exception_next_eip); | |
83479e77 | 192 | #endif |
3fb2ded1 FB |
193 | ret = env->exception_index; |
194 | break; | |
195 | } else { | |
83479e77 | 196 | #if defined(TARGET_I386) |
3fb2ded1 FB |
197 | /* simulate a real cpu exception. On i386, it can |
198 | trigger new exceptions, but we do not handle | |
199 | double or triple faults yet. */ | |
200 | do_interrupt(env->exception_index, | |
201 | env->exception_is_int, | |
202 | env->error_code, | |
d05e66d2 | 203 | env->exception_next_eip, 0); |
ce09776b FB |
204 | #elif defined(TARGET_PPC) |
205 | do_interrupt(env); | |
e95c8d51 FB |
206 | #elif defined(TARGET_SPARC) |
207 | do_interrupt(env->exception_index, | |
68016c62 | 208 | env->error_code); |
83479e77 | 209 | #endif |
3fb2ded1 FB |
210 | } |
211 | env->exception_index = -1; | |
212 | } | |
3fb2ded1 FB |
213 | T0 = 0; /* force lookup of first TB */ |
214 | for(;;) { | |
8c6939c0 | 215 | #ifdef __sparc__ |
3fb2ded1 FB |
216 | /* g1 can be modified by some libc? functions */ |
217 | tmp_T0 = T0; | |
8c6939c0 | 218 | #endif |
68a79315 | 219 | interrupt_request = env->interrupt_request; |
2e255c6b | 220 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
221 | #if defined(TARGET_I386) |
222 | /* if hardware interrupt pending, we execute it */ | |
223 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
224 | (env->eflags & IF_MASK) && |
225 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 226 | int intno; |
fbf9eeb3 | 227 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 228 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 229 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
230 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
231 | } | |
d05e66d2 | 232 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
233 | /* ensure that no TB jump will be modified as |
234 | the program flow was changed */ | |
235 | #ifdef __sparc__ | |
236 | tmp_T0 = 0; | |
237 | #else | |
238 | T0 = 0; | |
239 | #endif | |
68a79315 | 240 | } |
ce09776b | 241 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
242 | #if 0 |
243 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
244 | cpu_ppc_reset(env); | |
245 | } | |
246 | #endif | |
247 | if (msr_ee != 0) { | |
ce09776b | 248 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
249 | /* Raise it */ |
250 | env->exception_index = EXCP_EXTERNAL; | |
251 | env->error_code = 0; | |
ce09776b FB |
252 | do_interrupt(env); |
253 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
9fddaa0c FB |
254 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
255 | /* Raise it */ | |
256 | env->exception_index = EXCP_DECR; | |
257 | env->error_code = 0; | |
258 | do_interrupt(env); | |
259 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
260 | } | |
ce09776b | 261 | } |
e95c8d51 FB |
262 | #elif defined(TARGET_SPARC) |
263 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
68016c62 | 264 | do_interrupt(env->interrupt_index, 0); |
e95c8d51 FB |
265 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
266 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { | |
267 | //do_interrupt(0, 0, 0, 0, 0); | |
268 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
269 | } | |
68a79315 | 270 | #endif |
bf3e8bf1 FB |
271 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
272 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; | |
273 | /* ensure that no TB jump will be modified as | |
274 | the program flow was changed */ | |
275 | #ifdef __sparc__ | |
276 | tmp_T0 = 0; | |
277 | #else | |
278 | T0 = 0; | |
279 | #endif | |
280 | } | |
68a79315 FB |
281 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
282 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
283 | env->exception_index = EXCP_INTERRUPT; | |
284 | cpu_loop_exit(); | |
285 | } | |
3fb2ded1 | 286 | } |
7d13299d | 287 | #ifdef DEBUG_EXEC |
c27004ec | 288 | if ((loglevel & CPU_LOG_EXEC)) { |
e4533c7a | 289 | #if defined(TARGET_I386) |
3fb2ded1 FB |
290 | /* restore flags in standard format */ |
291 | env->regs[R_EAX] = EAX; | |
292 | env->regs[R_EBX] = EBX; | |
293 | env->regs[R_ECX] = ECX; | |
294 | env->regs[R_EDX] = EDX; | |
295 | env->regs[R_ESI] = ESI; | |
296 | env->regs[R_EDI] = EDI; | |
297 | env->regs[R_EBP] = EBP; | |
298 | env->regs[R_ESP] = ESP; | |
299 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
7fe48483 | 300 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
3fb2ded1 | 301 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 302 | #elif defined(TARGET_ARM) |
1b21b62a | 303 | env->cpsr = compute_cpsr(); |
7fe48483 | 304 | cpu_dump_state(env, logfile, fprintf, 0); |
99c475ab | 305 | env->cpsr &= ~CACHED_CPSR_BITS; |
93ac68bc | 306 | #elif defined(TARGET_SPARC) |
7fe48483 | 307 | cpu_dump_state (env, logfile, fprintf, 0); |
67867308 | 308 | #elif defined(TARGET_PPC) |
7fe48483 | 309 | cpu_dump_state(env, logfile, fprintf, 0); |
e4533c7a FB |
310 | #else |
311 | #error unsupported target CPU | |
312 | #endif | |
3fb2ded1 | 313 | } |
7d13299d | 314 | #endif |
3f337316 FB |
315 | /* we record a subset of the CPU state. It will |
316 | always be the same before a given translated block | |
317 | is executed. */ | |
e4533c7a | 318 | #if defined(TARGET_I386) |
2e255c6b | 319 | flags = env->hflags; |
3f337316 | 320 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
3fb2ded1 FB |
321 | cs_base = env->segs[R_CS].base; |
322 | pc = cs_base + env->eip; | |
e4533c7a | 323 | #elif defined(TARGET_ARM) |
99c475ab | 324 | flags = env->thumb; |
3fb2ded1 | 325 | cs_base = 0; |
c27004ec | 326 | pc = env->regs[15]; |
93ac68bc | 327 | #elif defined(TARGET_SPARC) |
67867308 | 328 | flags = 0; |
c27004ec FB |
329 | cs_base = env->npc; |
330 | pc = env->pc; | |
67867308 FB |
331 | #elif defined(TARGET_PPC) |
332 | flags = 0; | |
333 | cs_base = 0; | |
c27004ec | 334 | pc = env->nip; |
e4533c7a FB |
335 | #else |
336 | #error unsupported CPU | |
337 | #endif | |
c27004ec | 338 | tb = tb_find(&ptb, pc, cs_base, |
3fb2ded1 | 339 | flags); |
d4e8164f | 340 | if (!tb) { |
1376847f FB |
341 | TranslationBlock **ptb1; |
342 | unsigned int h; | |
343 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
344 | ||
345 | ||
3fb2ded1 | 346 | spin_lock(&tb_lock); |
1376847f FB |
347 | |
348 | tb_invalidated_flag = 0; | |
0d1a29f9 FB |
349 | |
350 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
1376847f FB |
351 | |
352 | /* find translated block using physical mappings */ | |
c27004ec | 353 | phys_pc = get_phys_addr_code(env, pc); |
1376847f FB |
354 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
355 | phys_page2 = -1; | |
356 | h = tb_phys_hash_func(phys_pc); | |
357 | ptb1 = &tb_phys_hash[h]; | |
358 | for(;;) { | |
359 | tb = *ptb1; | |
360 | if (!tb) | |
361 | goto not_found; | |
c27004ec | 362 | if (tb->pc == pc && |
1376847f | 363 | tb->page_addr[0] == phys_page1 && |
c27004ec | 364 | tb->cs_base == cs_base && |
1376847f FB |
365 | tb->flags == flags) { |
366 | /* check next page if needed */ | |
b516f85c | 367 | if (tb->page_addr[1] != -1) { |
c27004ec | 368 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
b516f85c | 369 | TARGET_PAGE_SIZE; |
1376847f FB |
370 | phys_page2 = get_phys_addr_code(env, virt_page2); |
371 | if (tb->page_addr[1] == phys_page2) | |
372 | goto found; | |
373 | } else { | |
374 | goto found; | |
375 | } | |
376 | } | |
377 | ptb1 = &tb->phys_hash_next; | |
378 | } | |
379 | not_found: | |
3fb2ded1 | 380 | /* if no translated code available, then translate it now */ |
c27004ec | 381 | tb = tb_alloc(pc); |
3fb2ded1 FB |
382 | if (!tb) { |
383 | /* flush must be done */ | |
b453b70b | 384 | tb_flush(env); |
3fb2ded1 | 385 | /* cannot fail at this point */ |
c27004ec | 386 | tb = tb_alloc(pc); |
3fb2ded1 | 387 | /* don't forget to invalidate previous TB info */ |
c27004ec | 388 | ptb = &tb_hash[tb_hash_func(pc)]; |
3fb2ded1 FB |
389 | T0 = 0; |
390 | } | |
391 | tc_ptr = code_gen_ptr; | |
392 | tb->tc_ptr = tc_ptr; | |
c27004ec | 393 | tb->cs_base = cs_base; |
3fb2ded1 | 394 | tb->flags = flags; |
facc68be | 395 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
1376847f FB |
396 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
397 | ||
398 | /* check next page if needed */ | |
c27004ec | 399 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
1376847f | 400 | phys_page2 = -1; |
c27004ec | 401 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
1376847f FB |
402 | phys_page2 = get_phys_addr_code(env, virt_page2); |
403 | } | |
404 | tb_link_phys(tb, phys_pc, phys_page2); | |
405 | ||
406 | found: | |
36bdbe54 FB |
407 | if (tb_invalidated_flag) { |
408 | /* as some TB could have been invalidated because | |
409 | of memory exceptions while generating the code, we | |
410 | must recompute the hash index here */ | |
c27004ec | 411 | ptb = &tb_hash[tb_hash_func(pc)]; |
36bdbe54 FB |
412 | while (*ptb != NULL) |
413 | ptb = &(*ptb)->hash_next; | |
414 | T0 = 0; | |
415 | } | |
1376847f | 416 | /* we add the TB in the virtual pc hash table */ |
3fb2ded1 FB |
417 | *ptb = tb; |
418 | tb->hash_next = NULL; | |
419 | tb_link(tb); | |
25eb4484 | 420 | spin_unlock(&tb_lock); |
9de5e440 | 421 | } |
9d27abd9 | 422 | #ifdef DEBUG_EXEC |
c1135f61 | 423 | if ((loglevel & CPU_LOG_EXEC)) { |
c27004ec FB |
424 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
425 | (long)tb->tc_ptr, tb->pc, | |
426 | lookup_symbol(tb->pc)); | |
3fb2ded1 | 427 | } |
9d27abd9 | 428 | #endif |
8c6939c0 | 429 | #ifdef __sparc__ |
3fb2ded1 | 430 | T0 = tmp_T0; |
8c6939c0 | 431 | #endif |
facc68be | 432 | /* see if we can patch the calling TB. */ |
c27004ec FB |
433 | { |
434 | if (T0 != 0 | |
bf3e8bf1 FB |
435 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
436 | && (tb->cflags & CF_CODE_COPY) == | |
437 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
438 | #endif | |
439 | ) { | |
3fb2ded1 | 440 | spin_lock(&tb_lock); |
c27004ec | 441 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
97eb5b14 FB |
442 | #if defined(USE_CODE_COPY) |
443 | /* propagates the FP use info */ | |
444 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
445 | (tb->cflags & CF_FP_USED); | |
446 | #endif | |
3fb2ded1 FB |
447 | spin_unlock(&tb_lock); |
448 | } | |
c27004ec | 449 | } |
3fb2ded1 | 450 | tc_ptr = tb->tc_ptr; |
83479e77 | 451 | env->current_tb = tb; |
3fb2ded1 FB |
452 | /* execute the generated code */ |
453 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 454 | #if defined(__sparc__) |
3fb2ded1 FB |
455 | __asm__ __volatile__("call %0\n\t" |
456 | "mov %%o7,%%i0" | |
457 | : /* no outputs */ | |
458 | : "r" (gen_func) | |
459 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 460 | #elif defined(__arm__) |
3fb2ded1 FB |
461 | asm volatile ("mov pc, %0\n\t" |
462 | ".global exec_loop\n\t" | |
463 | "exec_loop:\n\t" | |
464 | : /* no outputs */ | |
465 | : "r" (gen_func) | |
466 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
467 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
468 | { | |
469 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
470 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
471 | save_native_fp_state(env); | |
472 | } | |
bf3e8bf1 FB |
473 | gen_func(); |
474 | } else { | |
97eb5b14 FB |
475 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
476 | restore_native_fp_state(env); | |
477 | } | |
bf3e8bf1 FB |
478 | /* we work with native eflags */ |
479 | CC_SRC = cc_table[CC_OP].compute_all(); | |
480 | CC_OP = CC_OP_EFLAGS; | |
481 | asm(".globl exec_loop\n" | |
482 | "\n" | |
483 | "debug1:\n" | |
484 | " pushl %%ebp\n" | |
485 | " fs movl %10, %9\n" | |
486 | " fs movl %11, %%eax\n" | |
487 | " andl $0x400, %%eax\n" | |
488 | " fs orl %8, %%eax\n" | |
489 | " pushl %%eax\n" | |
490 | " popf\n" | |
491 | " fs movl %%esp, %12\n" | |
492 | " fs movl %0, %%eax\n" | |
493 | " fs movl %1, %%ecx\n" | |
494 | " fs movl %2, %%edx\n" | |
495 | " fs movl %3, %%ebx\n" | |
496 | " fs movl %4, %%esp\n" | |
497 | " fs movl %5, %%ebp\n" | |
498 | " fs movl %6, %%esi\n" | |
499 | " fs movl %7, %%edi\n" | |
500 | " fs jmp *%9\n" | |
501 | "exec_loop:\n" | |
502 | " fs movl %%esp, %4\n" | |
503 | " fs movl %12, %%esp\n" | |
504 | " fs movl %%eax, %0\n" | |
505 | " fs movl %%ecx, %1\n" | |
506 | " fs movl %%edx, %2\n" | |
507 | " fs movl %%ebx, %3\n" | |
508 | " fs movl %%ebp, %5\n" | |
509 | " fs movl %%esi, %6\n" | |
510 | " fs movl %%edi, %7\n" | |
511 | " pushf\n" | |
512 | " popl %%eax\n" | |
513 | " movl %%eax, %%ecx\n" | |
514 | " andl $0x400, %%ecx\n" | |
515 | " shrl $9, %%ecx\n" | |
516 | " andl $0x8d5, %%eax\n" | |
517 | " fs movl %%eax, %8\n" | |
518 | " movl $1, %%eax\n" | |
519 | " subl %%ecx, %%eax\n" | |
520 | " fs movl %%eax, %11\n" | |
521 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
522 | " popl %%ebp\n" | |
523 | : | |
524 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
525 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
526 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
527 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
528 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
529 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
530 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
531 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
532 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
533 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
534 | "a" (gen_func), | |
535 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
536 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
537 | : "%ecx", "%edx" | |
538 | ); | |
539 | } | |
540 | } | |
ae228531 | 541 | #else |
3fb2ded1 | 542 | gen_func(); |
ae228531 | 543 | #endif |
83479e77 | 544 | env->current_tb = NULL; |
4cbf74b6 FB |
545 | /* reset soft MMU for next block (it can currently |
546 | only be set by a memory fault) */ | |
547 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
548 | if (env->hflags & HF_SOFTMMU_MASK) { |
549 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
550 | /* do not allow linking to another block */ |
551 | T0 = 0; | |
552 | } | |
553 | #endif | |
3fb2ded1 FB |
554 | } |
555 | } else { | |
0d1a29f9 | 556 | env_to_regs(); |
7d13299d | 557 | } |
3fb2ded1 FB |
558 | } /* for(;;) */ |
559 | ||
7d13299d | 560 | |
e4533c7a | 561 | #if defined(TARGET_I386) |
97eb5b14 FB |
562 | #if defined(USE_CODE_COPY) |
563 | if (env->native_fp_regs) { | |
564 | save_native_fp_state(env); | |
565 | } | |
566 | #endif | |
9de5e440 | 567 | /* restore flags in standard format */ |
fc2b4c48 | 568 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 569 | |
7d13299d | 570 | /* restore global registers */ |
04369ff2 FB |
571 | #ifdef reg_EAX |
572 | EAX = saved_EAX; | |
573 | #endif | |
574 | #ifdef reg_ECX | |
575 | ECX = saved_ECX; | |
576 | #endif | |
577 | #ifdef reg_EDX | |
578 | EDX = saved_EDX; | |
579 | #endif | |
580 | #ifdef reg_EBX | |
581 | EBX = saved_EBX; | |
582 | #endif | |
583 | #ifdef reg_ESP | |
584 | ESP = saved_ESP; | |
585 | #endif | |
586 | #ifdef reg_EBP | |
587 | EBP = saved_EBP; | |
588 | #endif | |
589 | #ifdef reg_ESI | |
590 | ESI = saved_ESI; | |
591 | #endif | |
592 | #ifdef reg_EDI | |
593 | EDI = saved_EDI; | |
8c6939c0 | 594 | #endif |
e4533c7a | 595 | #elif defined(TARGET_ARM) |
1b21b62a | 596 | env->cpsr = compute_cpsr(); |
93ac68bc | 597 | #elif defined(TARGET_SPARC) |
67867308 | 598 | #elif defined(TARGET_PPC) |
e4533c7a FB |
599 | #else |
600 | #error unsupported target CPU | |
601 | #endif | |
8c6939c0 FB |
602 | #ifdef __sparc__ |
603 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 604 | #endif |
7d13299d FB |
605 | T0 = saved_T0; |
606 | T1 = saved_T1; | |
e4533c7a | 607 | T2 = saved_T2; |
7d13299d FB |
608 | env = saved_env; |
609 | return ret; | |
610 | } | |
6dbad63e | 611 | |
fbf9eeb3 FB |
612 | /* must only be called from the generated code as an exception can be |
613 | generated */ | |
614 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
615 | { | |
dc5d0b3d FB |
616 | /* XXX: cannot enable it yet because it yields to MMU exception |
617 | where NIP != read address on PowerPC */ | |
618 | #if 0 | |
fbf9eeb3 FB |
619 | target_ulong phys_addr; |
620 | phys_addr = get_phys_addr_code(env, start); | |
621 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 622 | #endif |
fbf9eeb3 FB |
623 | } |
624 | ||
1a18c71b | 625 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 626 | |
6dbad63e FB |
627 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
628 | { | |
629 | CPUX86State *saved_env; | |
630 | ||
631 | saved_env = env; | |
632 | env = s; | |
a412ac57 | 633 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 634 | selector &= 0xffff; |
2e255c6b | 635 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 636 | (selector << 4), 0xffff, 0); |
a513fe19 | 637 | } else { |
b453b70b | 638 | load_seg(seg_reg, selector); |
a513fe19 | 639 | } |
6dbad63e FB |
640 | env = saved_env; |
641 | } | |
9de5e440 | 642 | |
d0a1ffc9 FB |
643 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
644 | { | |
645 | CPUX86State *saved_env; | |
646 | ||
647 | saved_env = env; | |
648 | env = s; | |
649 | ||
c27004ec | 650 | helper_fsave((target_ulong)ptr, data32); |
d0a1ffc9 FB |
651 | |
652 | env = saved_env; | |
653 | } | |
654 | ||
655 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
656 | { | |
657 | CPUX86State *saved_env; | |
658 | ||
659 | saved_env = env; | |
660 | env = s; | |
661 | ||
c27004ec | 662 | helper_frstor((target_ulong)ptr, data32); |
d0a1ffc9 FB |
663 | |
664 | env = saved_env; | |
665 | } | |
666 | ||
e4533c7a FB |
667 | #endif /* TARGET_I386 */ |
668 | ||
67b915a5 FB |
669 | #if !defined(CONFIG_SOFTMMU) |
670 | ||
3fb2ded1 FB |
671 | #if defined(TARGET_I386) |
672 | ||
b56dad1c | 673 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
674 | the effective address of the memory exception. 'is_write' is 1 if a |
675 | write caused the exception and otherwise 0'. 'old_set' is the | |
676 | signal set which should be restored */ | |
2b413144 | 677 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
678 | int is_write, sigset_t *old_set, |
679 | void *puc) | |
9de5e440 | 680 | { |
a513fe19 FB |
681 | TranslationBlock *tb; |
682 | int ret; | |
68a79315 | 683 | |
83479e77 FB |
684 | if (cpu_single_env) |
685 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 686 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
687 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
688 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 689 | #endif |
25eb4484 | 690 | /* XXX: locking issue */ |
fbf9eeb3 | 691 | if (is_write && page_unprotect(address, pc, puc)) { |
fd6ce8f6 FB |
692 | return 1; |
693 | } | |
fbf9eeb3 | 694 | |
3fb2ded1 | 695 | /* see if it is an MMU fault */ |
93a40ea9 FB |
696 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
697 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
698 | if (ret < 0) |
699 | return 0; /* not an MMU fault */ | |
700 | if (ret == 0) | |
701 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
702 | /* now we have a real cpu fault */ | |
a513fe19 FB |
703 | tb = tb_find_pc(pc); |
704 | if (tb) { | |
9de5e440 FB |
705 | /* the PC is inside the translated code. It means that we have |
706 | a virtual CPU fault */ | |
bf3e8bf1 | 707 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 708 | } |
4cbf74b6 | 709 | if (ret == 1) { |
3fb2ded1 | 710 | #if 0 |
4cbf74b6 FB |
711 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
712 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 713 | #endif |
4cbf74b6 FB |
714 | /* we restore the process signal mask as the sigreturn should |
715 | do it (XXX: use sigsetjmp) */ | |
716 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
717 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
718 | } else { | |
719 | /* activate soft MMU for this block */ | |
3f337316 | 720 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 721 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 722 | } |
3fb2ded1 FB |
723 | /* never comes here */ |
724 | return 1; | |
725 | } | |
726 | ||
e4533c7a | 727 | #elif defined(TARGET_ARM) |
3fb2ded1 | 728 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
729 | int is_write, sigset_t *old_set, |
730 | void *puc) | |
3fb2ded1 | 731 | { |
68016c62 FB |
732 | TranslationBlock *tb; |
733 | int ret; | |
734 | ||
735 | if (cpu_single_env) | |
736 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
737 | #if defined(DEBUG_SIGNAL) | |
738 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
739 | pc, address, is_write, *(unsigned long *)old_set); | |
740 | #endif | |
9f0777ed FB |
741 | /* XXX: locking issue */ |
742 | if (is_write && page_unprotect(address, pc, puc)) { | |
743 | return 1; | |
744 | } | |
68016c62 FB |
745 | /* see if it is an MMU fault */ |
746 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); | |
747 | if (ret < 0) | |
748 | return 0; /* not an MMU fault */ | |
749 | if (ret == 0) | |
750 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
751 | /* now we have a real cpu fault */ | |
752 | tb = tb_find_pc(pc); | |
753 | if (tb) { | |
754 | /* the PC is inside the translated code. It means that we have | |
755 | a virtual CPU fault */ | |
756 | cpu_restore_state(tb, env, pc, puc); | |
757 | } | |
758 | /* we restore the process signal mask as the sigreturn should | |
759 | do it (XXX: use sigsetjmp) */ | |
760 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
761 | cpu_loop_exit(); | |
3fb2ded1 | 762 | } |
93ac68bc FB |
763 | #elif defined(TARGET_SPARC) |
764 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
765 | int is_write, sigset_t *old_set, |
766 | void *puc) | |
93ac68bc | 767 | { |
68016c62 FB |
768 | TranslationBlock *tb; |
769 | int ret; | |
770 | ||
771 | if (cpu_single_env) | |
772 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
773 | #if defined(DEBUG_SIGNAL) | |
774 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
775 | pc, address, is_write, *(unsigned long *)old_set); | |
776 | #endif | |
b453b70b | 777 | /* XXX: locking issue */ |
fbf9eeb3 | 778 | if (is_write && page_unprotect(address, pc, puc)) { |
b453b70b FB |
779 | return 1; |
780 | } | |
68016c62 FB |
781 | /* see if it is an MMU fault */ |
782 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); | |
783 | if (ret < 0) | |
784 | return 0; /* not an MMU fault */ | |
785 | if (ret == 0) | |
786 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
787 | /* now we have a real cpu fault */ | |
788 | tb = tb_find_pc(pc); | |
789 | if (tb) { | |
790 | /* the PC is inside the translated code. It means that we have | |
791 | a virtual CPU fault */ | |
792 | cpu_restore_state(tb, env, pc, puc); | |
793 | } | |
794 | /* we restore the process signal mask as the sigreturn should | |
795 | do it (XXX: use sigsetjmp) */ | |
796 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
797 | cpu_loop_exit(); | |
93ac68bc | 798 | } |
67867308 FB |
799 | #elif defined (TARGET_PPC) |
800 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
801 | int is_write, sigset_t *old_set, |
802 | void *puc) | |
67867308 FB |
803 | { |
804 | TranslationBlock *tb; | |
ce09776b | 805 | int ret; |
67867308 | 806 | |
67867308 FB |
807 | if (cpu_single_env) |
808 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
67867308 FB |
809 | #if defined(DEBUG_SIGNAL) |
810 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
811 | pc, address, is_write, *(unsigned long *)old_set); | |
812 | #endif | |
813 | /* XXX: locking issue */ | |
fbf9eeb3 | 814 | if (is_write && page_unprotect(address, pc, puc)) { |
67867308 FB |
815 | return 1; |
816 | } | |
817 | ||
ce09776b | 818 | /* see if it is an MMU fault */ |
7f957d28 | 819 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
820 | if (ret < 0) |
821 | return 0; /* not an MMU fault */ | |
822 | if (ret == 0) | |
823 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
824 | ||
67867308 FB |
825 | /* now we have a real cpu fault */ |
826 | tb = tb_find_pc(pc); | |
827 | if (tb) { | |
828 | /* the PC is inside the translated code. It means that we have | |
829 | a virtual CPU fault */ | |
bf3e8bf1 | 830 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 831 | } |
ce09776b | 832 | if (ret == 1) { |
67867308 | 833 | #if 0 |
ce09776b FB |
834 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
835 | env->nip, env->error_code, tb); | |
67867308 FB |
836 | #endif |
837 | /* we restore the process signal mask as the sigreturn should | |
838 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 839 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 840 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
841 | } else { |
842 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 843 | cpu_resume_from_signal(env, puc); |
ce09776b | 844 | } |
67867308 FB |
845 | /* never comes here */ |
846 | return 1; | |
847 | } | |
e4533c7a FB |
848 | #else |
849 | #error unsupported target CPU | |
850 | #endif | |
9de5e440 | 851 | |
2b413144 FB |
852 | #if defined(__i386__) |
853 | ||
bf3e8bf1 FB |
854 | #if defined(USE_CODE_COPY) |
855 | static void cpu_send_trap(unsigned long pc, int trap, | |
856 | struct ucontext *uc) | |
857 | { | |
858 | TranslationBlock *tb; | |
859 | ||
860 | if (cpu_single_env) | |
861 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
862 | /* now we have a real cpu fault */ | |
863 | tb = tb_find_pc(pc); | |
864 | if (tb) { | |
865 | /* the PC is inside the translated code. It means that we have | |
866 | a virtual CPU fault */ | |
867 | cpu_restore_state(tb, env, pc, uc); | |
868 | } | |
869 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
870 | raise_exception_err(trap, env->error_code); | |
871 | } | |
872 | #endif | |
873 | ||
e4533c7a FB |
874 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
875 | void *puc) | |
9de5e440 | 876 | { |
9de5e440 FB |
877 | struct ucontext *uc = puc; |
878 | unsigned long pc; | |
bf3e8bf1 | 879 | int trapno; |
97eb5b14 | 880 | |
d691f669 FB |
881 | #ifndef REG_EIP |
882 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
883 | #define REG_EIP EIP |
884 | #define REG_ERR ERR | |
885 | #define REG_TRAPNO TRAPNO | |
d691f669 | 886 | #endif |
fc2b4c48 | 887 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bf3e8bf1 FB |
888 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
889 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
890 | if (trapno == 0x00 || trapno == 0x05) { | |
891 | /* send division by zero or bound exception */ | |
892 | cpu_send_trap(pc, trapno, uc); | |
893 | return 1; | |
894 | } else | |
895 | #endif | |
896 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
897 | trapno == 0xe ? | |
898 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
899 | &uc->uc_sigmask, puc); | |
2b413144 FB |
900 | } |
901 | ||
bc51c5c9 FB |
902 | #elif defined(__x86_64__) |
903 | ||
904 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
905 | void *puc) | |
906 | { | |
907 | struct ucontext *uc = puc; | |
908 | unsigned long pc; | |
909 | ||
910 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
911 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
912 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
913 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
914 | &uc->uc_sigmask, puc); | |
915 | } | |
916 | ||
83fb7adf | 917 | #elif defined(__powerpc__) |
2b413144 | 918 | |
83fb7adf FB |
919 | /*********************************************************************** |
920 | * signal context platform-specific definitions | |
921 | * From Wine | |
922 | */ | |
923 | #ifdef linux | |
924 | /* All Registers access - only for local access */ | |
925 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
926 | /* Gpr Registers access */ | |
927 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
928 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
929 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
930 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
931 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
932 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
933 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
934 | /* Float Registers access */ | |
935 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
936 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
937 | /* Exception Registers access */ | |
938 | # define DAR_sig(context) REG_sig(dar, context) | |
939 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
940 | # define TRAP_sig(context) REG_sig(trap, context) | |
941 | #endif /* linux */ | |
942 | ||
943 | #ifdef __APPLE__ | |
944 | # include <sys/ucontext.h> | |
945 | typedef struct ucontext SIGCONTEXT; | |
946 | /* All Registers access - only for local access */ | |
947 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
948 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
949 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
950 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
951 | /* Gpr Registers access */ | |
952 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
953 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
954 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
955 | # define CTR_sig(context) REG_sig(ctr, context) | |
956 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
957 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
958 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
959 | /* Float Registers access */ | |
960 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
961 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
962 | /* Exception Registers access */ | |
963 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
964 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
965 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
966 | #endif /* __APPLE__ */ | |
967 | ||
d1d9f421 | 968 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
e4533c7a | 969 | void *puc) |
2b413144 | 970 | { |
25eb4484 | 971 | struct ucontext *uc = puc; |
25eb4484 | 972 | unsigned long pc; |
25eb4484 FB |
973 | int is_write; |
974 | ||
83fb7adf | 975 | pc = IAR_sig(uc); |
25eb4484 FB |
976 | is_write = 0; |
977 | #if 0 | |
978 | /* ppc 4xx case */ | |
83fb7adf | 979 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
980 | is_write = 1; |
981 | #else | |
83fb7adf | 982 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
983 | is_write = 1; |
984 | #endif | |
985 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 986 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
987 | } |
988 | ||
2f87c607 FB |
989 | #elif defined(__alpha__) |
990 | ||
e4533c7a | 991 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
992 | void *puc) |
993 | { | |
994 | struct ucontext *uc = puc; | |
995 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
996 | uint32_t insn = *pc; | |
997 | int is_write = 0; | |
998 | ||
8c6939c0 | 999 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
1000 | switch (insn >> 26) { |
1001 | case 0x0d: // stw | |
1002 | case 0x0e: // stb | |
1003 | case 0x0f: // stq_u | |
1004 | case 0x24: // stf | |
1005 | case 0x25: // stg | |
1006 | case 0x26: // sts | |
1007 | case 0x27: // stt | |
1008 | case 0x2c: // stl | |
1009 | case 0x2d: // stq | |
1010 | case 0x2e: // stl_c | |
1011 | case 0x2f: // stq_c | |
1012 | is_write = 1; | |
1013 | } | |
1014 | ||
1015 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1016 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1017 | } |
8c6939c0 FB |
1018 | #elif defined(__sparc__) |
1019 | ||
e4533c7a FB |
1020 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1021 | void *puc) | |
8c6939c0 FB |
1022 | { |
1023 | uint32_t *regs = (uint32_t *)(info + 1); | |
1024 | void *sigmask = (regs + 20); | |
1025 | unsigned long pc; | |
1026 | int is_write; | |
1027 | uint32_t insn; | |
1028 | ||
1029 | /* XXX: is there a standard glibc define ? */ | |
1030 | pc = regs[1]; | |
1031 | /* XXX: need kernel patch to get write flag faster */ | |
1032 | is_write = 0; | |
1033 | insn = *(uint32_t *)pc; | |
1034 | if ((insn >> 30) == 3) { | |
1035 | switch((insn >> 19) & 0x3f) { | |
1036 | case 0x05: // stb | |
1037 | case 0x06: // sth | |
1038 | case 0x04: // st | |
1039 | case 0x07: // std | |
1040 | case 0x24: // stf | |
1041 | case 0x27: // stdf | |
1042 | case 0x25: // stfsr | |
1043 | is_write = 1; | |
1044 | break; | |
1045 | } | |
1046 | } | |
1047 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1048 | is_write, sigmask, NULL); |
8c6939c0 FB |
1049 | } |
1050 | ||
1051 | #elif defined(__arm__) | |
1052 | ||
e4533c7a FB |
1053 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1054 | void *puc) | |
8c6939c0 FB |
1055 | { |
1056 | struct ucontext *uc = puc; | |
1057 | unsigned long pc; | |
1058 | int is_write; | |
1059 | ||
1060 | pc = uc->uc_mcontext.gregs[R15]; | |
1061 | /* XXX: compute is_write */ | |
1062 | is_write = 0; | |
1063 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1064 | is_write, | |
1065 | &uc->uc_sigmask); | |
1066 | } | |
1067 | ||
38e584a0 FB |
1068 | #elif defined(__mc68000) |
1069 | ||
1070 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1071 | void *puc) | |
1072 | { | |
1073 | struct ucontext *uc = puc; | |
1074 | unsigned long pc; | |
1075 | int is_write; | |
1076 | ||
1077 | pc = uc->uc_mcontext.gregs[16]; | |
1078 | /* XXX: compute is_write */ | |
1079 | is_write = 0; | |
1080 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1081 | is_write, | |
bf3e8bf1 | 1082 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1083 | } |
1084 | ||
9de5e440 | 1085 | #else |
2b413144 | 1086 | |
3fb2ded1 | 1087 | #error host CPU specific signal handler needed |
2b413144 | 1088 | |
9de5e440 | 1089 | #endif |
67b915a5 FB |
1090 | |
1091 | #endif /* !defined(CONFIG_SOFTMMU) */ |