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Preliminary patch for Alpha Linux user mode emulation support.
[mirror_qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
e6e5906b 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
e6e5906b 50#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
8a40a180
FB		 76
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
15388002 129 tb_invalidated_flag = 1;
8a40a180
FB		 130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
8a40a180
FB		 147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151}
152
153static inline TranslationBlock *tb_find_fast(void)
154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162#if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167#elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
40f137e1
PB		 172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
8a40a180
FB		 174 cs_base = 0;
175 pc = env->regs[15];
176#elif defined(TARGET_SPARC)
177#ifdef TARGET_SPARC64
a80dde08
FB		 178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 181#else
a80dde08
FB		 182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
8a40a180
FB		 185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
56b19403 194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 195 cs_base = 0;
8a40a180 196 pc = env->PC;
e6e5906b
PB		 197#elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
fdf9b3e8
FB		 201#elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
8a40a180
FB		 205#else
206#error unsupported CPU
207#endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
8a40a180
FB		 220 }
221 return tb;
222}
223
224
7d13299d
FB		 225/* main execution loop */
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
1057eaa7
PB		 229#define DECLARE_HOST_REGS 1
230#include "hostregs_helper.h"
231#if defined(TARGET_SPARC)
3475187d
FB		 232#if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
234#endif
235#endif
fdbb4691 236#if defined(__sparc__) && !defined(HOST_SOLARIS)
b49d07ba
TS		 237 int saved_i7;
238 target_ulong tmp_T0;
04369ff2 239#endif
8a40a180 240 int ret, interrupt_request;
7d13299d 241 void (*gen_func)(void);
8a40a180 242 TranslationBlock *tb;
c27004ec 243 uint8_t *tc_ptr;
8c6939c0 244
5a1e3cfc
FB		 245#if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
252 } else {
253 return EXCP_HALTED;
e80e1cc4
FB		 254 }
255 }
256#elif defined(TARGET_PPC)
50443c98 257 if (env1->halted) {
e80e1cc4 258 if (env1->msr[MSR_EE] &&
47103572 259 (env1->interrupt_request & CPU_INTERRUPT_HARD)) {
50443c98 260 env1->halted = 0;
e80e1cc4
FB		 261 } else {
262 return EXCP_HALTED;
5a1e3cfc
FB		 263 }
264 }
ba3c64fb
FB		 265#elif defined(TARGET_SPARC)
266 if (env1->halted) {
267 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
268 (env1->psret != 0)) {
269 env1->halted = 0;
270 } else {
271 return EXCP_HALTED;
272 }
273 }
9332f9da
FB		 274#elif defined(TARGET_ARM)
275 if (env1->halted) {
276 /* An interrupt wakes the CPU even if the I and F CPSR bits are
277 set. */
278 if (env1->interrupt_request
279 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
280 env1->halted = 0;
281 } else {
282 return EXCP_HALTED;
283 }
284 }
6810e154
FB		 285#elif defined(TARGET_MIPS)
286 if (env1->halted) {
287 if (env1->interrupt_request &
288 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
289 env1->halted = 0;
290 } else {
291 return EXCP_HALTED;
292 }
293 }
5a1e3cfc
FB		 294#endif
295
6a00d601
FB		 296 cpu_single_env = env1;
297
7d13299d 298 /* first we save global registers */
1057eaa7
PB		 299#define SAVE_HOST_REGS 1
300#include "hostregs_helper.h"
c27004ec 301 env = env1;
fdbb4691 302#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 303 /* we also save i7 because longjmp may not restore it */
304 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
305#endif
306
307#if defined(TARGET_I386)
0d1a29f9 308 env_to_regs();
9de5e440 309 /* put eflags in CPU temporary format */
fc2b4c48
FB		 310 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
311 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 312 CC_OP = CC_OP_EFLAGS;
fc2b4c48 313 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 314#elif defined(TARGET_ARM)
93ac68bc 315#elif defined(TARGET_SPARC)
3475187d
FB		 316#if defined(reg_REGWPTR)
317 saved_regwptr = REGWPTR;
318#endif
67867308 319#elif defined(TARGET_PPC)
e6e5906b
PB		 320#elif defined(TARGET_M68K)
321 env->cc_op = CC_OP_FLAGS;
322 env->cc_dest = env->sr & 0xf;
323 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 324#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 325#elif defined(TARGET_SH4)
326 /* XXXXX */
e4533c7a
FB		 327#else
328#error unsupported target CPU
329#endif
3fb2ded1 330 env->exception_index = -1;
9d27abd9 331
7d13299d 332 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 333 for(;;) {
334 if (setjmp(env->jmp_env) == 0) {
ee8b7021 335 env->current_tb = NULL;
3fb2ded1
FB		 336 /* if an exception is pending, we execute it here */
337 if (env->exception_index >= 0) {
338 if (env->exception_index >= EXCP_INTERRUPT) {
339 /* exit request from the cpu execution loop */
340 ret = env->exception_index;
341 break;
342 } else if (env->user_mode_only) {
343 /* if user mode only, we simulate a fake exception
9f083493 344 which will be handled outside the cpu execution
3fb2ded1 345 loop */
83479e77 346#if defined(TARGET_I386)
3fb2ded1
FB		 347 do_interrupt_user(env->exception_index,
348 env->exception_is_int,
349 env->error_code,
350 env->exception_next_eip);
83479e77 351#endif
3fb2ded1
FB		 352 ret = env->exception_index;
353 break;
354 } else {
83479e77 355#if defined(TARGET_I386)
3fb2ded1
FB		 356 /* simulate a real cpu exception. On i386, it can
357 trigger new exceptions, but we do not handle
358 double or triple faults yet. */
359 do_interrupt(env->exception_index,
360 env->exception_is_int,
361 env->error_code,
d05e66d2 362 env->exception_next_eip, 0);
678dde13
TS		 363 /* successfully delivered */
364 env->old_exception = -1;
ce09776b
FB		 365#elif defined(TARGET_PPC)
366 do_interrupt(env);
6af0bf9c
FB		 367#elif defined(TARGET_MIPS)
368 do_interrupt(env);
e95c8d51 369#elif defined(TARGET_SPARC)
1a0c3292 370 do_interrupt(env->exception_index);
b5ff1b31
FB		 371#elif defined(TARGET_ARM)
372 do_interrupt(env);
fdf9b3e8
FB		 373#elif defined(TARGET_SH4)
374 do_interrupt(env);
83479e77 375#endif
3fb2ded1
FB		 376 }
377 env->exception_index = -1;
9df217a3
FB		 378 }
379#ifdef USE_KQEMU
380 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
381 int ret;
382 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
383 ret = kqemu_cpu_exec(env);
384 /* put eflags in CPU temporary format */
385 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
386 DF = 1 - (2 * ((env->eflags >> 10) & 1));
387 CC_OP = CC_OP_EFLAGS;
388 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
389 if (ret == 1) {
390 /* exception */
391 longjmp(env->jmp_env, 1);
392 } else if (ret == 2) {
393 /* softmmu execution needed */
394 } else {
395 if (env->interrupt_request != 0) {
396 /* hardware interrupt will be executed just after */
397 } else {
398 /* otherwise, we restart */
399 longjmp(env->jmp_env, 1);
400 }
401 }
3fb2ded1 402 }
9df217a3
FB		 403#endif
404
3fb2ded1
FB		 405 T0 = 0; /* force lookup of first TB */
406 for(;;) {
fdbb4691 407#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 408 /* g1 can be modified by some libc? functions */
409 tmp_T0 = T0;
8c6939c0 410#endif
68a79315 411 interrupt_request = env->interrupt_request;
2e255c6b 412 if (__builtin_expect(interrupt_request, 0)) {
6658ffb8
PB		 413 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
414 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
415 env->exception_index = EXCP_DEBUG;
416 cpu_loop_exit();
417 }
68a79315 418#if defined(TARGET_I386)
3b21e03e
FB		 419 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
420 !(env->hflags & HF_SMM_MASK)) {
421 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
422 do_smm_enter();
423#if defined(__sparc__) && !defined(HOST_SOLARIS)
424 tmp_T0 = 0;
425#else
426 T0 = 0;
427#endif
428 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 429 (env->eflags & IF_MASK) &&
430 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 431 int intno;
fbf9eeb3 432 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 433 intno = cpu_get_pic_interrupt(env);
f193c797 434 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 435 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
436 }
d05e66d2 437 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 438 /* ensure that no TB jump will be modified as
439 the program flow was changed */
fdbb4691 440#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 441 tmp_T0 = 0;
442#else
443 T0 = 0;
444#endif
68a79315 445 }
ce09776b 446#elif defined(TARGET_PPC)
9fddaa0c
FB		 447#if 0
448 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
449 cpu_ppc_reset(env);
450 }
451#endif
47103572
JM		 452 if (interrupt_request & CPU_INTERRUPT_HARD) {
453 if (ppc_hw_interrupt(env) == 1) {
454 /* Some exception was raised */
455 if (env->pending_interrupts == 0)
456 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 457#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 458 tmp_T0 = 0;
459#else
460 T0 = 0;
461#endif
462 }
ce09776b 463 }
6af0bf9c
FB		 464#elif defined(TARGET_MIPS)
465 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 466 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 467 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 468 !(env->CP0_Status & (1 << CP0St_EXL)) &&
469 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 470 !(env->hflags & MIPS_HFLAG_DM)) {
471 /* Raise it */
472 env->exception_index = EXCP_EXT_INTERRUPT;
473 env->error_code = 0;
474 do_interrupt(env);
fdbb4691 475#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 476 tmp_T0 = 0;
477#else
478 T0 = 0;
479#endif
6af0bf9c 480 }
e95c8d51 481#elif defined(TARGET_SPARC)
66321a11
FB		 482 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
483 (env->psret != 0)) {
484 int pil = env->interrupt_index & 15;
485 int type = env->interrupt_index & 0xf0;
486
487 if (((type == TT_EXTINT) &&
488 (pil == 15 || pil > env->psrpil)) ||
489 type != TT_EXTINT) {
490 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
491 do_interrupt(env->interrupt_index);
492 env->interrupt_index = 0;
fdbb4691 493#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 494 tmp_T0 = 0;
495#else
496 T0 = 0;
497#endif
66321a11 498 }
e95c8d51
FB		 499 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
500 //do_interrupt(0, 0, 0, 0, 0);
501 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb 502 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
df52b000
FB		 503 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
504 env->halted = 1;
505 env->exception_index = EXCP_HLT;
506 cpu_loop_exit();
ba3c64fb 507 }
b5ff1b31
FB		 508#elif defined(TARGET_ARM)
509 if (interrupt_request & CPU_INTERRUPT_FIQ
510 && !(env->uncached_cpsr & CPSR_F)) {
511 env->exception_index = EXCP_FIQ;
512 do_interrupt(env);
513 }
514 if (interrupt_request & CPU_INTERRUPT_HARD
515 && !(env->uncached_cpsr & CPSR_I)) {
516 env->exception_index = EXCP_IRQ;
517 do_interrupt(env);
518 }
fdf9b3e8
FB		 519#elif defined(TARGET_SH4)
520 /* XXXXX */
68a79315 521#endif
9d05095e
FB		 522 /* Don't use the cached interupt_request value,
523 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 524 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 525 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
526 /* ensure that no TB jump will be modified as
527 the program flow was changed */
fdbb4691 528#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 529 tmp_T0 = 0;
530#else
531 T0 = 0;
532#endif
533 }
68a79315
FB		 534 if (interrupt_request & CPU_INTERRUPT_EXIT) {
535 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
536 env->exception_index = EXCP_INTERRUPT;
537 cpu_loop_exit();
538 }
3fb2ded1 539 }
7d13299d 540#ifdef DEBUG_EXEC
b5ff1b31 541 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 542#if defined(TARGET_I386)
3fb2ded1 543 /* restore flags in standard format */
fc9f715d 544#ifdef reg_EAX
3fb2ded1 545 env->regs[R_EAX] = EAX;
fc9f715d
FB		 546#endif
547#ifdef reg_EBX
3fb2ded1 548 env->regs[R_EBX] = EBX;
fc9f715d
FB		 549#endif
550#ifdef reg_ECX
3fb2ded1 551 env->regs[R_ECX] = ECX;
fc9f715d
FB		 552#endif
553#ifdef reg_EDX
3fb2ded1 554 env->regs[R_EDX] = EDX;
fc9f715d
FB		 555#endif
556#ifdef reg_ESI
3fb2ded1 557 env->regs[R_ESI] = ESI;
fc9f715d
FB		 558#endif
559#ifdef reg_EDI
3fb2ded1 560 env->regs[R_EDI] = EDI;
fc9f715d
FB		 561#endif
562#ifdef reg_EBP
3fb2ded1 563 env->regs[R_EBP] = EBP;
fc9f715d
FB		 564#endif
565#ifdef reg_ESP
3fb2ded1 566 env->regs[R_ESP] = ESP;
fc9f715d 567#endif
3fb2ded1 568 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 569 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 570 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 571#elif defined(TARGET_ARM)
7fe48483 572 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 573#elif defined(TARGET_SPARC)
3475187d
FB		 574 REGWPTR = env->regbase + (env->cwp * 16);
575 env->regwptr = REGWPTR;
576 cpu_dump_state(env, logfile, fprintf, 0);
67867308 577#elif defined(TARGET_PPC)
7fe48483 578 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 579#elif defined(TARGET_M68K)
580 cpu_m68k_flush_flags(env, env->cc_op);
581 env->cc_op = CC_OP_FLAGS;
582 env->sr = (env->sr & 0xffe0)
583 | env->cc_dest | (env->cc_x << 4);
584 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 585#elif defined(TARGET_MIPS)
586 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 587#elif defined(TARGET_SH4)
588 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 589#else
590#error unsupported target CPU
591#endif
3fb2ded1 592 }
7d13299d 593#endif
8a40a180 594 tb = tb_find_fast();
9d27abd9 595#ifdef DEBUG_EXEC
c1135f61 596 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 597 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
598 (long)tb->tc_ptr, tb->pc,
599 lookup_symbol(tb->pc));
3fb2ded1 600 }
9d27abd9 601#endif
fdbb4691 602#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 603 T0 = tmp_T0;
8c6939c0 604#endif
8a40a180
FB		 605 /* see if we can patch the calling TB. When the TB
606 spans two pages, we cannot safely do a direct
607 jump. */
c27004ec 608 {
8a40a180 609 if (T0 != 0 &&
f32fc648
FB		 610#if USE_KQEMU
611 (env->kqemu_enabled != 2) &&
612#endif
8a40a180 613 tb->page_addr[1] == -1
bf3e8bf1
FB		 614#if defined(TARGET_I386) && defined(USE_CODE_COPY)
615 && (tb->cflags & CF_CODE_COPY) ==
616 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
617#endif
618 ) {
3fb2ded1 619 spin_lock(&tb_lock);
c27004ec 620 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 621#if defined(USE_CODE_COPY)
622 /* propagates the FP use info */
623 ((TranslationBlock *)(T0 & ~3))->cflags |=
624 (tb->cflags & CF_FP_USED);
625#endif
3fb2ded1
FB		 626 spin_unlock(&tb_lock);
627 }
c27004ec 628 }
3fb2ded1 629 tc_ptr = tb->tc_ptr;
83479e77 630 env->current_tb = tb;
3fb2ded1
FB		 631 /* execute the generated code */
632 gen_func = (void *)tc_ptr;
8c6939c0 633#if defined(__sparc__)
3fb2ded1
FB		 634 __asm__ __volatile__("call %0\n\t"
635 "mov %%o7,%%i0"
636 : /* no outputs */
637 : "r" (gen_func)
fdbb4691 638 : "i0", "i1", "i2", "i3", "i4", "i5",
faab7592 639 "o0", "o1", "o2", "o3", "o4", "o5",
fdbb4691
FB		 640 "l0", "l1", "l2", "l3", "l4", "l5",
641 "l6", "l7");
8c6939c0 642#elif defined(__arm__)
3fb2ded1
FB		 643 asm volatile ("mov pc, %0\n\t"
644 ".global exec_loop\n\t"
645 "exec_loop:\n\t"
646 : /* no outputs */
647 : "r" (gen_func)
648 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 649#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
650{
651 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 652 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
653 save_native_fp_state(env);
654 }
bf3e8bf1
FB		 655 gen_func();
656 } else {
97eb5b14
FB		 657 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
658 restore_native_fp_state(env);
659 }
bf3e8bf1
FB		 660 /* we work with native eflags */
661 CC_SRC = cc_table[CC_OP].compute_all();
662 CC_OP = CC_OP_EFLAGS;
663 asm(".globl exec_loop\n"
664 "\n"
665 "debug1:\n"
666 " pushl %%ebp\n"
667 " fs movl %10, %9\n"
668 " fs movl %11, %%eax\n"
669 " andl $0x400, %%eax\n"
670 " fs orl %8, %%eax\n"
671 " pushl %%eax\n"
672 " popf\n"
673 " fs movl %%esp, %12\n"
674 " fs movl %0, %%eax\n"
675 " fs movl %1, %%ecx\n"
676 " fs movl %2, %%edx\n"
677 " fs movl %3, %%ebx\n"
678 " fs movl %4, %%esp\n"
679 " fs movl %5, %%ebp\n"
680 " fs movl %6, %%esi\n"
681 " fs movl %7, %%edi\n"
682 " fs jmp *%9\n"
683 "exec_loop:\n"
684 " fs movl %%esp, %4\n"
685 " fs movl %12, %%esp\n"
686 " fs movl %%eax, %0\n"
687 " fs movl %%ecx, %1\n"
688 " fs movl %%edx, %2\n"
689 " fs movl %%ebx, %3\n"
690 " fs movl %%ebp, %5\n"
691 " fs movl %%esi, %6\n"
692 " fs movl %%edi, %7\n"
693 " pushf\n"
694 " popl %%eax\n"
695 " movl %%eax, %%ecx\n"
696 " andl $0x400, %%ecx\n"
697 " shrl $9, %%ecx\n"
698 " andl $0x8d5, %%eax\n"
699 " fs movl %%eax, %8\n"
700 " movl $1, %%eax\n"
701 " subl %%ecx, %%eax\n"
702 " fs movl %%eax, %11\n"
703 " fs movl %9, %%ebx\n" /* get T0 value */
704 " popl %%ebp\n"
705 :
706 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
707 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
708 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
709 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
710 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
711 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
712 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
713 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
714 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
715 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
716 "a" (gen_func),
717 "m" (*(uint8_t *)offsetof(CPUState, df)),
718 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
719 : "%ecx", "%edx"
720 );
721 }
722}
b8076a74
FB		 723#elif defined(__ia64)
724 struct fptr {
725 void *ip;
726 void *gp;
727 } fp;
728
729 fp.ip = tc_ptr;
730 fp.gp = code_gen_buffer + 2 * (1 << 20);
731 (*(void (*)(void)) &fp)();
ae228531 732#else
3fb2ded1 733 gen_func();
ae228531 734#endif
83479e77 735 env->current_tb = NULL;
4cbf74b6
FB		 736 /* reset soft MMU for next block (it can currently
737 only be set by a memory fault) */
738#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 739 if (env->hflags & HF_SOFTMMU_MASK) {
740 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 741 /* do not allow linking to another block */
742 T0 = 0;
743 }
f32fc648
FB		 744#endif
745#if defined(USE_KQEMU)
746#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
747 if (kqemu_is_ok(env) &&
748 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
749 cpu_loop_exit();
750 }
4cbf74b6 751#endif
3fb2ded1
FB		 752 }
753 } else {
0d1a29f9 754 env_to_regs();
7d13299d 755 }
3fb2ded1
FB		 756 } /* for(;;) */
757
7d13299d 758
e4533c7a 759#if defined(TARGET_I386)
97eb5b14
FB		 760#if defined(USE_CODE_COPY)
761 if (env->native_fp_regs) {
762 save_native_fp_state(env);
763 }
764#endif
9de5e440 765 /* restore flags in standard format */
fc2b4c48 766 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
e4533c7a 767#elif defined(TARGET_ARM)
b7bcbe95 768 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 769#elif defined(TARGET_SPARC)
3475187d
FB		 770#if defined(reg_REGWPTR)
771 REGWPTR = saved_regwptr;
772#endif
67867308 773#elif defined(TARGET_PPC)
e6e5906b
PB		 774#elif defined(TARGET_M68K)
775 cpu_m68k_flush_flags(env, env->cc_op);
776 env->cc_op = CC_OP_FLAGS;
777 env->sr = (env->sr & 0xffe0)
778 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 779#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 780#elif defined(TARGET_SH4)
781 /* XXXXX */
e4533c7a
FB		 782#else
783#error unsupported target CPU
784#endif
1057eaa7
PB		 785
786 /* restore global registers */
fdbb4691 787#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 788 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 789#endif
1057eaa7
PB		 790#include "hostregs_helper.h"
791
6a00d601
FB		 792 /* fail safe : never use cpu_single_env outside cpu_exec() */
793 cpu_single_env = NULL;
7d13299d
FB		 794 return ret;
795}
6dbad63e 796
fbf9eeb3
FB		 797/* must only be called from the generated code as an exception can be
798 generated */
799void tb_invalidate_page_range(target_ulong start, target_ulong end)
800{
dc5d0b3d
FB		 801 /* XXX: cannot enable it yet because it yields to MMU exception
802 where NIP != read address on PowerPC */
803#if 0
fbf9eeb3
FB		 804 target_ulong phys_addr;
805 phys_addr = get_phys_addr_code(env, start);
806 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 807#endif
fbf9eeb3
FB		 808}
809
1a18c71b 810#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 811
6dbad63e
FB		 812void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
813{
814 CPUX86State *saved_env;
815
816 saved_env = env;
817 env = s;
a412ac57 818 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 819 selector &= 0xffff;
2e255c6b 820 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 821 (selector << 4), 0xffff, 0);
a513fe19 822 } else {
b453b70b 823 load_seg(seg_reg, selector);
a513fe19 824 }
6dbad63e
FB		 825 env = saved_env;
826}
9de5e440 827
d0a1ffc9
FB		 828void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
829{
830 CPUX86State *saved_env;
831
832 saved_env = env;
833 env = s;
834
c27004ec 835 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 836
837 env = saved_env;
838}
839
840void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
841{
842 CPUX86State *saved_env;
843
844 saved_env = env;
845 env = s;
846
c27004ec 847 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 848
849 env = saved_env;
850}
851
e4533c7a
FB		 852#endif /* TARGET_I386 */
853
67b915a5
FB		 854#if !defined(CONFIG_SOFTMMU)
855
3fb2ded1
FB		 856#if defined(TARGET_I386)
857
b56dad1c 858/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 859 the effective address of the memory exception. 'is_write' is 1 if a
860 write caused the exception and otherwise 0'. 'old_set' is the
861 signal set which should be restored */
2b413144 862static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 863 int is_write, sigset_t *old_set,
864 void *puc)
9de5e440 865{
a513fe19
FB		 866 TranslationBlock *tb;
867 int ret;
68a79315 868
83479e77
FB		 869 if (cpu_single_env)
870 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 871#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 872 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
873 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 874#endif
25eb4484 875 /* XXX: locking issue */
53a5960a 876 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 877 return 1;
878 }
fbf9eeb3 879
3fb2ded1 880 /* see if it is an MMU fault */
93a40ea9
FB		 881 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
882 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 883 if (ret < 0)
884 return 0; /* not an MMU fault */
885 if (ret == 0)
886 return 1; /* the MMU fault was handled without causing real CPU fault */
887 /* now we have a real cpu fault */
a513fe19
FB		 888 tb = tb_find_pc(pc);
889 if (tb) {
9de5e440
FB		 890 /* the PC is inside the translated code. It means that we have
891 a virtual CPU fault */
bf3e8bf1 892 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 893 }
4cbf74b6 894 if (ret == 1) {
3fb2ded1 895#if 0
4cbf74b6
FB		 896 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
897 env->eip, env->cr[2], env->error_code);
3fb2ded1 898#endif
4cbf74b6
FB		 899 /* we restore the process signal mask as the sigreturn should
900 do it (XXX: use sigsetjmp) */
901 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 902 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 903 } else {
904 /* activate soft MMU for this block */
3f337316 905 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 906 cpu_resume_from_signal(env, puc);
4cbf74b6 907 }
3fb2ded1
FB		 908 /* never comes here */
909 return 1;
910}
911
e4533c7a 912#elif defined(TARGET_ARM)
3fb2ded1 913static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 914 int is_write, sigset_t *old_set,
915 void *puc)
3fb2ded1 916{
68016c62
FB		 917 TranslationBlock *tb;
918 int ret;
919
920 if (cpu_single_env)
921 env = cpu_single_env; /* XXX: find a correct solution for multithread */
922#if defined(DEBUG_SIGNAL)
923 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
924 pc, address, is_write, *(unsigned long *)old_set);
925#endif
9f0777ed 926 /* XXX: locking issue */
53a5960a 927 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 928 return 1;
929 }
68016c62
FB		 930 /* see if it is an MMU fault */
931 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
932 if (ret < 0)
933 return 0; /* not an MMU fault */
934 if (ret == 0)
935 return 1; /* the MMU fault was handled without causing real CPU fault */
936 /* now we have a real cpu fault */
937 tb = tb_find_pc(pc);
938 if (tb) {
939 /* the PC is inside the translated code. It means that we have
940 a virtual CPU fault */
941 cpu_restore_state(tb, env, pc, puc);
942 }
943 /* we restore the process signal mask as the sigreturn should
944 do it (XXX: use sigsetjmp) */
945 sigprocmask(SIG_SETMASK, old_set, NULL);
946 cpu_loop_exit();
3fb2ded1 947}
93ac68bc
FB		 948#elif defined(TARGET_SPARC)
949static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 950 int is_write, sigset_t *old_set,
951 void *puc)
93ac68bc 952{
68016c62
FB		 953 TranslationBlock *tb;
954 int ret;
955
956 if (cpu_single_env)
957 env = cpu_single_env; /* XXX: find a correct solution for multithread */
958#if defined(DEBUG_SIGNAL)
959 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
960 pc, address, is_write, *(unsigned long *)old_set);
961#endif
b453b70b 962 /* XXX: locking issue */
53a5960a 963 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 964 return 1;
965 }
68016c62
FB		 966 /* see if it is an MMU fault */
967 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
968 if (ret < 0)
969 return 0; /* not an MMU fault */
970 if (ret == 0)
971 return 1; /* the MMU fault was handled without causing real CPU fault */
972 /* now we have a real cpu fault */
973 tb = tb_find_pc(pc);
974 if (tb) {
975 /* the PC is inside the translated code. It means that we have
976 a virtual CPU fault */
977 cpu_restore_state(tb, env, pc, puc);
978 }
979 /* we restore the process signal mask as the sigreturn should
980 do it (XXX: use sigsetjmp) */
981 sigprocmask(SIG_SETMASK, old_set, NULL);
982 cpu_loop_exit();
93ac68bc 983}
67867308
FB		 984#elif defined (TARGET_PPC)
985static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 986 int is_write, sigset_t *old_set,
987 void *puc)
67867308
FB		 988{
989 TranslationBlock *tb;
ce09776b 990 int ret;
67867308 991
67867308
FB		 992 if (cpu_single_env)
993 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 994#if defined(DEBUG_SIGNAL)
995 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
996 pc, address, is_write, *(unsigned long *)old_set);
997#endif
998 /* XXX: locking issue */
53a5960a 999 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 1000 return 1;
1001 }
1002
ce09776b 1003 /* see if it is an MMU fault */
7f957d28 1004 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1005 if (ret < 0)
1006 return 0; /* not an MMU fault */
1007 if (ret == 0)
1008 return 1; /* the MMU fault was handled without causing real CPU fault */
1009
67867308
FB		 1010 /* now we have a real cpu fault */
1011 tb = tb_find_pc(pc);
1012 if (tb) {
1013 /* the PC is inside the translated code. It means that we have
1014 a virtual CPU fault */
bf3e8bf1 1015 cpu_restore_state(tb, env, pc, puc);
67867308 1016 }
ce09776b 1017 if (ret == 1) {
67867308 1018#if 0
ce09776b
FB		 1019 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1020 env->nip, env->error_code, tb);
67867308
FB		 1021#endif
1022 /* we restore the process signal mask as the sigreturn should
1023 do it (XXX: use sigsetjmp) */
bf3e8bf1 1024 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1025 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1026 } else {
1027 /* activate soft MMU for this block */
fbf9eeb3 1028 cpu_resume_from_signal(env, puc);
ce09776b 1029 }
67867308 1030 /* never comes here */
e6e5906b
PB		 1031 return 1;
1032}
1033
1034#elif defined(TARGET_M68K)
1035static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1036 int is_write, sigset_t *old_set,
1037 void *puc)
1038{
1039 TranslationBlock *tb;
1040 int ret;
1041
1042 if (cpu_single_env)
1043 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1044#if defined(DEBUG_SIGNAL)
1045 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1046 pc, address, is_write, *(unsigned long *)old_set);
1047#endif
1048 /* XXX: locking issue */
1049 if (is_write && page_unprotect(address, pc, puc)) {
1050 return 1;
1051 }
1052 /* see if it is an MMU fault */
1053 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1054 if (ret < 0)
1055 return 0; /* not an MMU fault */
1056 if (ret == 0)
1057 return 1; /* the MMU fault was handled without causing real CPU fault */
1058 /* now we have a real cpu fault */
1059 tb = tb_find_pc(pc);
1060 if (tb) {
1061 /* the PC is inside the translated code. It means that we have
1062 a virtual CPU fault */
1063 cpu_restore_state(tb, env, pc, puc);
1064 }
1065 /* we restore the process signal mask as the sigreturn should
1066 do it (XXX: use sigsetjmp) */
1067 sigprocmask(SIG_SETMASK, old_set, NULL);
1068 cpu_loop_exit();
1069 /* never comes here */
67867308
FB		 1070 return 1;
1071}
6af0bf9c
FB		 1072
1073#elif defined (TARGET_MIPS)
1074static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1075 int is_write, sigset_t *old_set,
1076 void *puc)
1077{
1078 TranslationBlock *tb;
1079 int ret;
1080
1081 if (cpu_single_env)
1082 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1083#if defined(DEBUG_SIGNAL)
1084 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1085 pc, address, is_write, *(unsigned long *)old_set);
1086#endif
1087 /* XXX: locking issue */
53a5960a 1088 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1089 return 1;
1090 }
1091
1092 /* see if it is an MMU fault */
cc9442b9 1093 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1094 if (ret < 0)
1095 return 0; /* not an MMU fault */
1096 if (ret == 0)
1097 return 1; /* the MMU fault was handled without causing real CPU fault */
1098
1099 /* now we have a real cpu fault */
1100 tb = tb_find_pc(pc);
1101 if (tb) {
1102 /* the PC is inside the translated code. It means that we have
1103 a virtual CPU fault */
1104 cpu_restore_state(tb, env, pc, puc);
1105 }
1106 if (ret == 1) {
1107#if 0
1108 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1109 env->nip, env->error_code, tb);
1110#endif
1111 /* we restore the process signal mask as the sigreturn should
1112 do it (XXX: use sigsetjmp) */
1113 sigprocmask(SIG_SETMASK, old_set, NULL);
1114 do_raise_exception_err(env->exception_index, env->error_code);
1115 } else {
1116 /* activate soft MMU for this block */
1117 cpu_resume_from_signal(env, puc);
1118 }
1119 /* never comes here */
1120 return 1;
1121}
1122
fdf9b3e8
FB		 1123#elif defined (TARGET_SH4)
1124static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1125 int is_write, sigset_t *old_set,
1126 void *puc)
1127{
1128 TranslationBlock *tb;
1129 int ret;
1130
1131 if (cpu_single_env)
1132 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1133#if defined(DEBUG_SIGNAL)
1134 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1135 pc, address, is_write, *(unsigned long *)old_set);
1136#endif
1137 /* XXX: locking issue */
1138 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1139 return 1;
1140 }
1141
1142 /* see if it is an MMU fault */
1143 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1144 if (ret < 0)
1145 return 0; /* not an MMU fault */
1146 if (ret == 0)
1147 return 1; /* the MMU fault was handled without causing real CPU fault */
1148
1149 /* now we have a real cpu fault */
1150 tb = tb_find_pc(pc);
1151 if (tb) {
1152 /* the PC is inside the translated code. It means that we have
1153 a virtual CPU fault */
1154 cpu_restore_state(tb, env, pc, puc);
1155 }
fdf9b3e8
FB		 1156#if 0
1157 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1158 env->nip, env->error_code, tb);
1159#endif
1160 /* we restore the process signal mask as the sigreturn should
1161 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1162 sigprocmask(SIG_SETMASK, old_set, NULL);
1163 cpu_loop_exit();
fdf9b3e8
FB		 1164 /* never comes here */
1165 return 1;
1166}
e4533c7a
FB		 1167#else
1168#error unsupported target CPU
1169#endif
9de5e440 1170
2b413144
FB		 1171#if defined(__i386__)
1172
d8ecc0b9
FB		 1173#if defined(__APPLE__)
1174# include <sys/ucontext.h>
1175
1176# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1177# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1178# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1179#else
1180# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1181# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1182# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1183#endif
1184
bf3e8bf1
FB		 1185#if defined(USE_CODE_COPY)
1186static void cpu_send_trap(unsigned long pc, int trap,
1187 struct ucontext *uc)
1188{
1189 TranslationBlock *tb;
1190
1191 if (cpu_single_env)
1192 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1193 /* now we have a real cpu fault */
1194 tb = tb_find_pc(pc);
1195 if (tb) {
1196 /* the PC is inside the translated code. It means that we have
1197 a virtual CPU fault */
1198 cpu_restore_state(tb, env, pc, uc);
1199 }
1200 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1201 raise_exception_err(trap, env->error_code);
1202}
1203#endif
1204
5a7b542b 1205int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1206 void *puc)
9de5e440 1207{
5a7b542b 1208 siginfo_t *info = pinfo;
9de5e440
FB		 1209 struct ucontext *uc = puc;
1210 unsigned long pc;
bf3e8bf1 1211 int trapno;
97eb5b14 1212
d691f669
FB		 1213#ifndef REG_EIP
1214/* for glibc 2.1 */
fd6ce8f6
FB		 1215#define REG_EIP EIP
1216#define REG_ERR ERR
1217#define REG_TRAPNO TRAPNO
d691f669 1218#endif
d8ecc0b9
FB		 1219 pc = EIP_sig(uc);
1220 trapno = TRAP_sig(uc);
bf3e8bf1
FB		 1221#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1222 if (trapno == 0x00 || trapno == 0x05) {
1223 /* send division by zero or bound exception */
1224 cpu_send_trap(pc, trapno, uc);
1225 return 1;
1226 } else
1227#endif
1228 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1229 trapno == 0xe ?
d8ecc0b9 1230 (ERROR_sig(uc) >> 1) & 1 : 0,
bf3e8bf1 1231 &uc->uc_sigmask, puc);
2b413144
FB		 1232}
1233
bc51c5c9
FB		 1234#elif defined(__x86_64__)
1235
5a7b542b 1236int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 1237 void *puc)
1238{
5a7b542b 1239 siginfo_t *info = pinfo;
bc51c5c9
FB		 1240 struct ucontext *uc = puc;
1241 unsigned long pc;
1242
1243 pc = uc->uc_mcontext.gregs[REG_RIP];
1244 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1245 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1246 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1247 &uc->uc_sigmask, puc);
1248}
1249
83fb7adf 1250#elif defined(__powerpc__)
2b413144 1251
83fb7adf
FB		 1252/***********************************************************************
1253 * signal context platform-specific definitions
1254 * From Wine
1255 */
1256#ifdef linux
1257/* All Registers access - only for local access */
1258# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1259/* Gpr Registers access */
1260# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1261# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1262# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1263# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1264# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1265# define LR_sig(context) REG_sig(link, context) /* Link register */
1266# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1267/* Float Registers access */
1268# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1269# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1270/* Exception Registers access */
1271# define DAR_sig(context) REG_sig(dar, context)
1272# define DSISR_sig(context) REG_sig(dsisr, context)
1273# define TRAP_sig(context) REG_sig(trap, context)
1274#endif /* linux */
1275
1276#ifdef __APPLE__
1277# include <sys/ucontext.h>
1278typedef struct ucontext SIGCONTEXT;
1279/* All Registers access - only for local access */
1280# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1281# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1282# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1283# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1284/* Gpr Registers access */
1285# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1286# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1287# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1288# define CTR_sig(context) REG_sig(ctr, context)
1289# define XER_sig(context) REG_sig(xer, context) /* Link register */
1290# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1291# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1292/* Float Registers access */
1293# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1294# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1295/* Exception Registers access */
1296# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1297# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1298# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1299#endif /* __APPLE__ */
1300
5a7b542b 1301int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1302 void *puc)
2b413144 1303{
5a7b542b 1304 siginfo_t *info = pinfo;
25eb4484 1305 struct ucontext *uc = puc;
25eb4484 1306 unsigned long pc;
25eb4484
FB		 1307 int is_write;
1308
83fb7adf 1309 pc = IAR_sig(uc);
25eb4484
FB		 1310 is_write = 0;
1311#if 0
1312 /* ppc 4xx case */
83fb7adf 1313 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1314 is_write = 1;
1315#else
83fb7adf 1316 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1317 is_write = 1;
1318#endif
1319 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1320 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1321}
1322
2f87c607
FB		 1323#elif defined(__alpha__)
1324
5a7b542b 1325int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1326 void *puc)
1327{
5a7b542b 1328 siginfo_t *info = pinfo;
2f87c607
FB		 1329 struct ucontext *uc = puc;
1330 uint32_t *pc = uc->uc_mcontext.sc_pc;
1331 uint32_t insn = *pc;
1332 int is_write = 0;
1333
8c6939c0 1334 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1335 switch (insn >> 26) {
1336 case 0x0d: // stw
1337 case 0x0e: // stb
1338 case 0x0f: // stq_u
1339 case 0x24: // stf
1340 case 0x25: // stg
1341 case 0x26: // sts
1342 case 0x27: // stt
1343 case 0x2c: // stl
1344 case 0x2d: // stq
1345 case 0x2e: // stl_c
1346 case 0x2f: // stq_c
1347 is_write = 1;
1348 }
1349
1350 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1351 is_write, &uc->uc_sigmask, puc);
2f87c607 1352}
8c6939c0
FB		 1353#elif defined(__sparc__)
1354
5a7b542b 1355int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1356 void *puc)
8c6939c0 1357{
5a7b542b 1358 siginfo_t *info = pinfo;
8c6939c0
FB		 1359 uint32_t *regs = (uint32_t *)(info + 1);
1360 void *sigmask = (regs + 20);
1361 unsigned long pc;
1362 int is_write;
1363 uint32_t insn;
1364
1365 /* XXX: is there a standard glibc define ? */
1366 pc = regs[1];
1367 /* XXX: need kernel patch to get write flag faster */
1368 is_write = 0;
1369 insn = *(uint32_t *)pc;
1370 if ((insn >> 30) == 3) {
1371 switch((insn >> 19) & 0x3f) {
1372 case 0x05: // stb
1373 case 0x06: // sth
1374 case 0x04: // st
1375 case 0x07: // std
1376 case 0x24: // stf
1377 case 0x27: // stdf
1378 case 0x25: // stfsr
1379 is_write = 1;
1380 break;
1381 }
1382 }
1383 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1384 is_write, sigmask, NULL);
8c6939c0
FB		 1385}
1386
1387#elif defined(__arm__)
1388
5a7b542b 1389int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1390 void *puc)
8c6939c0 1391{
5a7b542b 1392 siginfo_t *info = pinfo;
8c6939c0
FB		 1393 struct ucontext *uc = puc;
1394 unsigned long pc;
1395 int is_write;
1396
1397 pc = uc->uc_mcontext.gregs[R15];
1398 /* XXX: compute is_write */
1399 is_write = 0;
1400 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1401 is_write,
f3a9676a 1402 &uc->uc_sigmask, puc);
8c6939c0
FB		 1403}
1404
38e584a0
FB		 1405#elif defined(__mc68000)
1406
5a7b542b 1407int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1408 void *puc)
1409{
5a7b542b 1410 siginfo_t *info = pinfo;
38e584a0
FB		 1411 struct ucontext *uc = puc;
1412 unsigned long pc;
1413 int is_write;
1414
1415 pc = uc->uc_mcontext.gregs[16];
1416 /* XXX: compute is_write */
1417 is_write = 0;
1418 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1419 is_write,
bf3e8bf1 1420 &uc->uc_sigmask, puc);
38e584a0
FB		 1421}
1422
b8076a74
FB		 1423#elif defined(__ia64)
1424
1425#ifndef __ISR_VALID
1426 /* This ought to be in <bits/siginfo.h>... */
1427# define __ISR_VALID 1
b8076a74
FB		 1428#endif
1429
5a7b542b 1430int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1431{
5a7b542b 1432 siginfo_t *info = pinfo;
b8076a74
FB		 1433 struct ucontext *uc = puc;
1434 unsigned long ip;
1435 int is_write = 0;
1436
1437 ip = uc->uc_mcontext.sc_ip;
1438 switch (host_signum) {
1439 case SIGILL:
1440 case SIGFPE:
1441 case SIGSEGV:
1442 case SIGBUS:
1443 case SIGTRAP:
fd4a43e4 1444 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1445 /* ISR.W (write-access) is bit 33: */
1446 is_write = (info->si_isr >> 33) & 1;
1447 break;
1448
1449 default:
1450 break;
1451 }
1452 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1453 is_write,
1454 &uc->uc_sigmask, puc);
1455}
1456
90cb9493
FB		 1457#elif defined(__s390__)
1458
5a7b542b 1459int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1460 void *puc)
1461{
5a7b542b 1462 siginfo_t *info = pinfo;
90cb9493
FB		 1463 struct ucontext *uc = puc;
1464 unsigned long pc;
1465 int is_write;
1466
1467 pc = uc->uc_mcontext.psw.addr;
1468 /* XXX: compute is_write */
1469 is_write = 0;
1470 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1471 is_write,
1472 &uc->uc_sigmask, puc);
1473}
1474
9de5e440 1475#else
2b413144 1476
3fb2ded1 1477#error host CPU specific signal handler needed
2b413144 1478
9de5e440 1479#endif
67b915a5
FB		 1480
1481#endif /* !defined(CONFIG_SOFTMMU) */
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