[mirror_qemu.git] / cpu-exec.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#ifdef TARGET_I386
#include "exec-i386.h"
#endif
#ifdef TARGET_ARM
#include "exec-arm.h"
#endif

#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

#if defined(TARGET_ARM)
/* XXX: unify with i386 target */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}
#endif

/* main execution loop */

int cpu_exec(CPUState *env1)
{
    int saved_T0, saved_T1, saved_T2;
    CPUState *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
#ifdef __sparc__
    int saved_i7, tmp_T0;
#endif
    int code_gen_size, ret;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;

    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_T2 = T2;
    saved_env = env;
    env = env1;
#ifdef __sparc__
    /* we also save i7 because longjmp may not restore it */
    asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
#endif

#if defined(TARGET_I386)
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
    {
        unsigned int psr;
        psr = env->cpsr;
        env->CF = (psr >> 29) & 1;
        env->NZF = (psr & 0xc0000000) ^ 0x40000000;
        env->VF = (psr << 3) & 0x80000000;
        env->cpsr = psr & ~0xf0000000;
    }
#else
#error unsupported target CPU
#endif
    env->interrupt_request = 0;

    /* prepare setjmp context for exception handling */
    if (setjmp(env->jmp_env) == 0) {
        T0 = 0; /* force lookup of first TB */
        for(;;) {
#ifdef __sparc__
	  /* g1 can be modified by some libc? functions */ 
	    tmp_T0 = T0;
#endif	    
            if (env->interrupt_request) {
                env->exception_index = EXCP_INTERRUPT;
                cpu_loop_exit();
            }
#ifdef DEBUG_EXEC
            if (loglevel) {
#if defined(TARGET_I386)
                /* restore flags in standard format */
                env->regs[R_EAX] = EAX;
                env->regs[R_EBX] = EBX;
                env->regs[R_ECX] = ECX;
                env->regs[R_EDX] = EDX;
                env->regs[R_ESI] = ESI;
                env->regs[R_EDI] = EDI;
                env->regs[R_EBP] = EBP;
                env->regs[R_ESP] = ESP;
                env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                cpu_x86_dump_state(env, logfile, 0);
                env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
                cpu_arm_dump_state(env, logfile, 0);
#else
#error unsupported target CPU 
#endif
            }
#endif
            /* we compute the CPU state. We assume it will not
               change during the whole generated block. */
#if defined(TARGET_I386)
            flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
            flags |= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
            flags |= (((unsigned long)env->segs[R_DS].base | 
                       (unsigned long)env->segs[R_ES].base |
                       (unsigned long)env->segs[R_SS].base) != 0) << 
                GEN_FLAG_ADDSEG_SHIFT;
            if (!(env->eflags & VM_MASK)) {
                flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
            } else {
                /* NOTE: a dummy CPL is kept */
                flags |= (1 << GEN_FLAG_VM_SHIFT);
                flags |= (3 << GEN_FLAG_CPL_SHIFT);
            }
            flags |= (env->eflags & (IOPL_MASK | TF_MASK));
            cs_base = env->segs[R_CS].base;
            pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
            flags = 0;
            cs_base = 0;
            pc = (uint8_t *)env->regs[15];
#else
#error unsupported CPU
#endif
            tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                         flags);
            if (!tb) {
                spin_lock(&tb_lock);
                /* if no translated code available, then translate it now */
                tb = tb_alloc((unsigned long)pc);
                if (!tb) {
                    /* flush must be done */
                    tb_flush();
                    /* cannot fail at this point */
                    tb = tb_alloc((unsigned long)pc);
                    /* don't forget to invalidate previous TB info */
                    ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                    T0 = 0;
                }
                tc_ptr = code_gen_ptr;
                tb->tc_ptr = tc_ptr;
                tb->cs_base = (unsigned long)cs_base;
                tb->flags = flags;
                ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
#if defined(TARGET_I386)
                /* XXX: suppress that, this is incorrect */
                /* if invalid instruction, signal it */
                if (ret != 0) {
                    /* NOTE: the tb is allocated but not linked, so we
                       can leave it */
                    spin_unlock(&tb_lock);
                    raise_exception(EXCP06_ILLOP);
                }
#endif
                *ptb = tb;
                tb->hash_next = NULL;
                tb_link(tb);
                code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                spin_unlock(&tb_lock);
            }
#ifdef DEBUG_EXEC
	    if (loglevel) {
		fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
			(long)tb->tc_ptr, (long)tb->pc,
			lookup_symbol((void *)tb->pc));
	    }
#endif
#ifdef __sparc__
	    T0 = tmp_T0;
#endif	    
            /* see if we can patch the calling TB. XXX: remove TF test */
            if (T0 != 0 
#if defined(TARGET_I386)
                && !(env->eflags & TF_MASK)
#endif
                ) {
                spin_lock(&tb_lock);
                tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                spin_unlock(&tb_lock);
            }
            tc_ptr = tb->tc_ptr;

            /* execute the generated code */
            gen_func = (void *)tc_ptr;
#if defined(__sparc__)
	    __asm__ __volatile__("call	%0\n\t"
				 "mov	%%o7,%%i0"
				 : /* no outputs */
				 : "r" (gen_func) 
				 : "i0", "i1", "i2", "i3", "i4", "i5");
#elif defined(__arm__)
            asm volatile ("mov pc, %0\n\t"
                          ".global exec_loop\n\t"
                          "exec_loop:\n\t"
                          : /* no outputs */
                          : "r" (gen_func)
                          : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
#else
            gen_func();
#endif
        }
    }
    ret = env->exception_index;

#if defined(TARGET_I386)
    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
#elif defined(TARGET_ARM)
    {
        int ZF;
        ZF = (env->NZF == 0);
        env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) | 
            (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
    }
#else
#error unsupported target CPU
#endif
#ifdef __sparc__
    asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    T2 = saved_T2;
    env = saved_env;
    return ret;
}

void cpu_interrupt(CPUState *s)
{
    s->interrupt_request = 1;
}


#if defined(TARGET_I386)

void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    if (env->eflags & VM_MASK) {
        SegmentCache *sc;
        selector &= 0xffff;
        sc = &env->segs[seg_reg];
        /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
           so we must load them here */
        sc->base = (void *)(selector << 4);
        sc->limit = 0xffff;
        sc->seg_32bit = 0;
        sc->selector = selector;
    } else {
        load_seg(seg_reg, selector, 0);
    }
    env = saved_env;
}

void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_fsave(ptr, data32);

    env = saved_env;
}

void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_frstor(ptr, data32);

    env = saved_env;
}

#endif /* TARGET_I386 */

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    TranslationBlock *tb;
    int ret;
    uint32_t found_pc;
    
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        ret = cpu_search_pc(tb, &found_pc, pc);
        if (ret < 0)
            return 0;
#if defined(TARGET_I386)
        env->eip = found_pc - tb->cs_base;
        env->cr[2] = address;
        /* we restore the process signal mask as the sigreturn should
           do it (XXX: use sigsetjmp) */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
#elif defined(TARGET_ARM)
        env->regs[15] = found_pc;
        /* XXX: do more */
#else
#error unsupported target CPU
#endif
        /* never comes here */
        return 1;
    } else {
        return 0;
    }
}

#if defined(__i386__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: // stw
    case 0x0e: // stb
    case 0x0f: // stq_u
    case 0x24: // stf
    case 0x25: // stg
    case 0x26: // sts
    case 0x27: // stt
    case 0x2c: // stl
    case 0x2d: // stq
    case 0x2e: // stl_c
    case 0x2f: // stq_c
	is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    unsigned long pc;
    int is_write;
    uint32_t insn;
    
    /* XXX: is there a standard glibc define ? */
    pc = regs[1];
    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
      switch((insn >> 19) & 0x3f) {
      case 0x05: // stb
      case 0x06: // sth
      case 0x04: // st
      case 0x07: // std
      case 0x24: // stf
      case 0x27: // stdf
      case 0x25: // stfsr
	is_write = 1;
	break;
      }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, sigmask);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[R15];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#else

#error CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d	19	*/
e4533c7a FB	20	#include "config.h"
e4533c7a FB	21	#ifdef TARGET_I386
7d13299d	22	#include "exec-i386.h"
e4533c7a FB	23	#endif
	24	#ifdef TARGET_ARM
	25	#include "exec-arm.h"
	26	#endif
	27
956034d7	28	#include "disas.h"
7d13299d	29
dc99065b	30	//#define DEBUG_EXEC
9de5e440	31	//#define DEBUG_SIGNAL
7d13299d	32
e4533c7a FB	33	#if defined(TARGET_ARM)
	34	/* XXX: unify with i386 target */
	35	void cpu_loop_exit(void)
	36	{
	37	longjmp(env->jmp_env, 1);
	38	}
	39	#endif
	40
7d13299d FB	41	/* main execution loop */
7d13299d FB	42
e4533c7a	43	int cpu_exec(CPUState *env1)
7d13299d	44	{
e4533c7a FB	45	int saved_T0, saved_T1, saved_T2;
e4533c7a FB	46	CPUState *saved_env;
04369ff2 FB	47	#ifdef reg_EAX
	48	int saved_EAX;
	49	#endif
	50	#ifdef reg_ECX
	51	int saved_ECX;
	52	#endif
	53	#ifdef reg_EDX
	54	int saved_EDX;
	55	#endif
	56	#ifdef reg_EBX
	57	int saved_EBX;
	58	#endif
	59	#ifdef reg_ESP
	60	int saved_ESP;
	61	#endif
	62	#ifdef reg_EBP
	63	int saved_EBP;
	64	#endif
	65	#ifdef reg_ESI
	66	int saved_ESI;
	67	#endif
	68	#ifdef reg_EDI
	69	int saved_EDI;
8c6939c0 FB	70	#endif
	71	#ifdef __sparc__
	72	int saved_i7, tmp_T0;
04369ff2	73	#endif
a513fe19	74	int code_gen_size, ret;
7d13299d	75	void (*gen_func)(void);
9de5e440	76	TranslationBlock tb, *ptb;
dab2ed99	77	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	78	unsigned int flags;
8c6939c0	79
7d13299d FB	80	/* first we save global registers */
	81	saved_T0 = T0;
	82	saved_T1 = T1;
e4533c7a	83	saved_T2 = T2;
7d13299d FB	84	saved_env = env;
7d13299d FB	85	env = env1;
e4533c7a FB	86	#ifdef __sparc__
	87	/* we also save i7 because longjmp may not restore it */
	88	asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
	89	#endif
	90
	91	#if defined(TARGET_I386)
04369ff2 FB	92	#ifdef reg_EAX
	93	saved_EAX = EAX;
	94	EAX = env->regs[R_EAX];
	95	#endif
	96	#ifdef reg_ECX
	97	saved_ECX = ECX;
	98	ECX = env->regs[R_ECX];
	99	#endif
	100	#ifdef reg_EDX
	101	saved_EDX = EDX;
	102	EDX = env->regs[R_EDX];
	103	#endif
	104	#ifdef reg_EBX
	105	saved_EBX = EBX;
	106	EBX = env->regs[R_EBX];
	107	#endif
	108	#ifdef reg_ESP
	109	saved_ESP = ESP;
	110	ESP = env->regs[R_ESP];
	111	#endif
	112	#ifdef reg_EBP
	113	saved_EBP = EBP;
	114	EBP = env->regs[R_EBP];
	115	#endif
	116	#ifdef reg_ESI
	117	saved_ESI = ESI;
	118	ESI = env->regs[R_ESI];
	119	#endif
	120	#ifdef reg_EDI
	121	saved_EDI = EDI;
	122	EDI = env->regs[R_EDI];
	123	#endif
7d13299d	124
9de5e440	125	/* put eflags in CPU temporary format */
fc2b4c48 FB	126	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	127	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	128	CC_OP = CC_OP_EFLAGS;
fc2b4c48	129	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a FB	130	#elif defined(TARGET_ARM)
	131	{
	132	unsigned int psr;
	133	psr = env->cpsr;
	134	env->CF = (psr >> 29) & 1;
	135	env->NZF = (psr & 0xc0000000) ^ 0x40000000;
	136	env->VF = (psr << 3) & 0x80000000;
	137	env->cpsr = psr & ~0xf0000000;
	138	}
	139	#else
	140	#error unsupported target CPU
	141	#endif
9de5e440	142	env->interrupt_request = 0;
9d27abd9	143
7d13299d FB	144	/* prepare setjmp context for exception handling */
7d13299d FB	145	if (setjmp(env->jmp_env) == 0) {
d4e8164f	146	T0 = 0; /* force lookup of first TB */
7d13299d	147	for(;;) {
8c6939c0 FB	148	#ifdef __sparc__
	149	/* g1 can be modified by some libc? functions */
	150	tmp_T0 = T0;
	151	#endif
9de5e440	152	if (env->interrupt_request) {
a513fe19 FB	153	env->exception_index = EXCP_INTERRUPT;
a513fe19 FB	154	cpu_loop_exit();
9de5e440	155	}
7d13299d FB	156	#ifdef DEBUG_EXEC
7d13299d FB	157	if (loglevel) {
e4533c7a	158	#if defined(TARGET_I386)
9d27abd9 FB	159	/* restore flags in standard format */
	160	env->regs[R_EAX] = EAX;
	161	env->regs[R_EBX] = EBX;
	162	env->regs[R_ECX] = ECX;
	163	env->regs[R_EDX] = EDX;
	164	env->regs[R_ESI] = ESI;
	165	env->regs[R_EDI] = EDI;
	166	env->regs[R_EBP] = EBP;
	167	env->regs[R_ESP] = ESP;
	168	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	169	cpu_x86_dump_state(env, logfile, 0);
	170	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a FB	171	#elif defined(TARGET_ARM)
	172	cpu_arm_dump_state(env, logfile, 0);
	173	#else
	174	#error unsupported target CPU
	175	#endif
7d13299d FB	176	}
7d13299d FB	177	#endif
6dbad63e FB	178	/* we compute the CPU state. We assume it will not
6dbad63e FB	179	change during the whole generated block. */
e4533c7a	180	#if defined(TARGET_I386)
970a87a6 FB	181	flags = env->segs[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
	182	flags \|= env->segs[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
	183	flags \|= (((unsigned long)env->segs[R_DS].base \|
	184	(unsigned long)env->segs[R_ES].base \|
	185	(unsigned long)env->segs[R_SS].base) != 0) <<
6dbad63e	186	GEN_FLAG_ADDSEG_SHIFT;
9d27abd9	187	if (!(env->eflags & VM_MASK)) {
970a87a6	188	flags \|= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
9d27abd9 FB	189	} else {
	190	/* NOTE: a dummy CPL is kept */
	191	flags \|= (1 << GEN_FLAG_VM_SHIFT);
	192	flags \|= (3 << GEN_FLAG_CPL_SHIFT);
	193	}
cf25629d	194	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK));
970a87a6	195	cs_base = env->segs[R_CS].base;
dab2ed99	196	pc = cs_base + env->eip;
e4533c7a FB	197	#elif defined(TARGET_ARM)
	198	flags = 0;
	199	cs_base = 0;
	200	pc = (uint8_t *)env->regs[15];
	201	#else
	202	#error unsupported CPU
	203	#endif
9de5e440 FB	204	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
	205	flags);
	206	if (!tb) {
cf25629d	207	spin_lock(&tb_lock);
7d13299d	208	/* if no translated code available, then translate it now */
d4e8164f FB	209	tb = tb_alloc((unsigned long)pc);
	210	if (!tb) {
	211	/* flush must be done */
	212	tb_flush();
	213	/* cannot fail at this point */
	214	tb = tb_alloc((unsigned long)pc);
	215	/* don't forget to invalidate previous TB info */
	216	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	217	T0 = 0;
	218	}
7d13299d	219	tc_ptr = code_gen_ptr;
d4e8164f	220	tb->tc_ptr = tc_ptr;
a513fe19 FB	221	tb->cs_base = (unsigned long)cs_base;
a513fe19 FB	222	tb->flags = flags;
e4533c7a FB	223	ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
	224	#if defined(TARGET_I386)
	225	/* XXX: suppress that, this is incorrect */
9de5e440 FB	226	/* if invalid instruction, signal it */
9de5e440 FB	227	if (ret != 0) {
d4e8164f FB	228	/* NOTE: the tb is allocated but not linked, so we
d4e8164f FB	229	can leave it */
25eb4484	230	spin_unlock(&tb_lock);
9de5e440 FB	231	raise_exception(EXCP06_ILLOP);
9de5e440 FB	232	}
e4533c7a	233	#endif
9de5e440	234	*ptb = tb;
9de5e440	235	tb->hash_next = NULL;
d4e8164f	236	tb_link(tb);
7d13299d	237	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
cf25629d	238	spin_unlock(&tb_lock);
7d13299d	239	}
9d27abd9	240	#ifdef DEBUG_EXEC
956034d7 FB	241	if (loglevel) {
	242	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	243	(long)tb->tc_ptr, (long)tb->pc,
	244	lookup_symbol((void *)tb->pc));
956034d7	245	}
9d27abd9	246	#endif
8c6939c0 FB	247	#ifdef __sparc__
	248	T0 = tmp_T0;
	249	#endif
e4533c7a FB	250	/* see if we can patch the calling TB. XXX: remove TF test */
	251	if (T0 != 0
	252	#if defined(TARGET_I386)
	253	&& !(env->eflags & TF_MASK)
	254	#endif
	255	) {
cf25629d	256	spin_lock(&tb_lock);
d4e8164f	257	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
cf25629d	258	spin_unlock(&tb_lock);
d4e8164f	259	}
9de5e440	260	tc_ptr = tb->tc_ptr;
d4e8164f FB	261
d4e8164f FB	262	/* execute the generated code */
7d13299d	263	gen_func = (void *)tc_ptr;
8c6939c0	264	#if defined(__sparc__)
ae228531	265	__asm__ __volatile__("call %0\n\t"
8c6939c0	266	"mov %%o7,%%i0"
ae228531	267	: /* no outputs */
d4e8164f	268	: "r" (gen_func)
ae228531	269	: "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 FB	270	#elif defined(__arm__)
	271	asm volatile ("mov pc, %0\n\t"
	272	".global exec_loop\n\t"
	273	"exec_loop:\n\t"
	274	: /* no outputs */
	275	: "r" (gen_func)
	276	: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
ae228531	277	#else
7d13299d	278	gen_func();
ae228531	279	#endif
7d13299d FB	280	}
	281	}
	282	ret = env->exception_index;
	283
e4533c7a	284	#if defined(TARGET_I386)
9de5e440	285	/* restore flags in standard format */
fc2b4c48	286	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	287
7d13299d	288	/* restore global registers */
04369ff2 FB	289	#ifdef reg_EAX
	290	EAX = saved_EAX;
	291	#endif
	292	#ifdef reg_ECX
	293	ECX = saved_ECX;
	294	#endif
	295	#ifdef reg_EDX
	296	EDX = saved_EDX;
	297	#endif
	298	#ifdef reg_EBX
	299	EBX = saved_EBX;
	300	#endif
	301	#ifdef reg_ESP
	302	ESP = saved_ESP;
	303	#endif
	304	#ifdef reg_EBP
	305	EBP = saved_EBP;
	306	#endif
	307	#ifdef reg_ESI
	308	ESI = saved_ESI;
	309	#endif
	310	#ifdef reg_EDI
	311	EDI = saved_EDI;
8c6939c0	312	#endif
e4533c7a FB	313	#elif defined(TARGET_ARM)
	314	{
	315	int ZF;
	316	ZF = (env->NZF == 0);
	317	env->cpsr = env->cpsr \| (env->NZF & 0x80000000) \| (ZF << 30) \|
	318	(env->CF << 29) \| ((env->VF & 0x80000000) >> 3);
	319	}
	320	#else
	321	#error unsupported target CPU
	322	#endif
8c6939c0 FB	323	#ifdef __sparc__
8c6939c0 FB	324	asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2	325	#endif
7d13299d FB	326	T0 = saved_T0;
7d13299d FB	327	T1 = saved_T1;
e4533c7a	328	T2 = saved_T2;
7d13299d FB	329	env = saved_env;
	330	return ret;
	331	}
6dbad63e	332
e4533c7a	333	void cpu_interrupt(CPUState *s)
9de5e440 FB	334	{
	335	s->interrupt_request = 1;
	336	}
	337
	338
e4533c7a FB	339	#if defined(TARGET_I386)
e4533c7a FB	340
6dbad63e FB	341	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	342	{
	343	CPUX86State *saved_env;
	344
	345	saved_env = env;
	346	env = s;
a513fe19 FB	347	if (env->eflags & VM_MASK) {
	348	SegmentCache *sc;
	349	selector &= 0xffff;
970a87a6	350	sc = &env->segs[seg_reg];
a513fe19 FB	351	/* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
	352	so we must load them here */
	353	sc->base = (void *)(selector << 4);
	354	sc->limit = 0xffff;
	355	sc->seg_32bit = 0;
970a87a6	356	sc->selector = selector;
a513fe19 FB	357	} else {
	358	load_seg(seg_reg, selector, 0);
	359	}
6dbad63e FB	360	env = saved_env;
6dbad63e FB	361	}
9de5e440	362
d0a1ffc9 FB	363	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32)
	364	{
	365	CPUX86State *saved_env;
	366
	367	saved_env = env;
	368	env = s;
	369
	370	helper_fsave(ptr, data32);
	371
	372	env = saved_env;
	373	}
	374
	375	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32)
	376	{
	377	CPUX86State *saved_env;
	378
	379	saved_env = env;
	380	env = s;
	381
	382	helper_frstor(ptr, data32);
	383
	384	env = saved_env;
	385	}
	386
e4533c7a FB	387	#endif /* TARGET_I386 */
e4533c7a FB	388
9de5e440 FB	389	#undef EAX
	390	#undef ECX
	391	#undef EDX
	392	#undef EBX
	393	#undef ESP
	394	#undef EBP
	395	#undef ESI
	396	#undef EDI
	397	#undef EIP
	398	#include <signal.h>
	399	#include <sys/ucontext.h>
	400
b56dad1c	401	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	402	the effective address of the memory exception. 'is_write' is 1 if a
	403	write caused the exception and otherwise 0'. 'old_set' is the
	404	signal set which should be restored */
2b413144 FB	405	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	406	int is_write, sigset_t *old_set)
9de5e440	407	{
a513fe19 FB	408	TranslationBlock *tb;
	409	int ret;
	410	uint32_t found_pc;
	411
fd6ce8f6 FB	412	#if defined(DEBUG_SIGNAL)
	413	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
	414	pc, address, is_write, (unsigned long )old_set);
9de5e440	415	#endif
25eb4484	416	/* XXX: locking issue */
fd6ce8f6	417	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	418	return 1;
fd6ce8f6 FB	419	}
a513fe19 FB	420	tb = tb_find_pc(pc);
a513fe19 FB	421	if (tb) {
9de5e440 FB	422	/* the PC is inside the translated code. It means that we have
9de5e440 FB	423	a virtual CPU fault */
e4533c7a	424	ret = cpu_search_pc(tb, &found_pc, pc);
a513fe19 FB	425	if (ret < 0)
a513fe19 FB	426	return 0;
e4533c7a	427	#if defined(TARGET_I386)
a513fe19	428	env->eip = found_pc - tb->cs_base;
970a87a6	429	env->cr[2] = address;
9de5e440	430	/* we restore the process signal mask as the sigreturn should
a513fe19	431	do it (XXX: use sigsetjmp) */
9de5e440	432	sigprocmask(SIG_SETMASK, old_set, NULL);
fd6ce8f6	433	raise_exception_err(EXCP0E_PAGE, 4 \| (is_write << 1));
e4533c7a FB	434	#elif defined(TARGET_ARM)
	435	env->regs[15] = found_pc;
	436	/* XXX: do more */
	437	#else
	438	#error unsupported target CPU
	439	#endif
9de5e440 FB	440	/* never comes here */
	441	return 1;
	442	} else {
	443	return 0;
	444	}
	445	}
	446
2b413144 FB	447	#if defined(__i386__)
2b413144 FB	448
e4533c7a FB	449	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	450	void *puc)
9de5e440	451	{
9de5e440 FB	452	struct ucontext *uc = puc;
9de5e440 FB	453	unsigned long pc;
9de5e440	454
d691f669 FB	455	#ifndef REG_EIP
d691f669 FB	456	/* for glibc 2.1 */
fd6ce8f6 FB	457	#define REG_EIP EIP
	458	#define REG_ERR ERR
	459	#define REG_TRAPNO TRAPNO
d691f669	460	#endif
fc2b4c48	461	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	462	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	463	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	464	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	465	&uc->uc_sigmask);
	466	}
	467
25eb4484	468	#elif defined(__powerpc)
2b413144	469
e4533c7a FB	470	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	471	void *puc)
2b413144	472	{
25eb4484 FB	473	struct ucontext *uc = puc;
	474	struct pt_regs *regs = uc->uc_mcontext.regs;
	475	unsigned long pc;
25eb4484 FB	476	int is_write;
	477
	478	pc = regs->nip;
25eb4484 FB	479	is_write = 0;
	480	#if 0
	481	/* ppc 4xx case */
	482	if (regs->dsisr & 0x00800000)
	483	is_write = 1;
	484	#else
	485	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	486	is_write = 1;
	487	#endif
	488	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	489	is_write, &uc->uc_sigmask);
	490	}
	491
2f87c607 FB	492	#elif defined(__alpha__)
2f87c607 FB	493
e4533c7a	494	int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607 FB	495	void *puc)
	496	{
	497	struct ucontext *uc = puc;
	498	uint32_t *pc = uc->uc_mcontext.sc_pc;
	499	uint32_t insn = *pc;
	500	int is_write = 0;
	501
8c6939c0	502	/* XXX: need kernel patch to get write flag faster */
2f87c607 FB	503	switch (insn >> 26) {
	504	case 0x0d: // stw
	505	case 0x0e: // stb
	506	case 0x0f: // stq_u
	507	case 0x24: // stf
	508	case 0x25: // stg
	509	case 0x26: // sts
	510	case 0x27: // stt
	511	case 0x2c: // stl
	512	case 0x2d: // stq
	513	case 0x2e: // stl_c
	514	case 0x2f: // stq_c
	515	is_write = 1;
	516	}
	517
	518	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	519	is_write, &uc->uc_sigmask);
	520	}
8c6939c0 FB	521	#elif defined(__sparc__)
8c6939c0 FB	522
e4533c7a FB	523	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	524	void *puc)
8c6939c0 FB	525	{
	526	uint32_t regs = (uint32_t )(info + 1);
	527	void *sigmask = (regs + 20);
	528	unsigned long pc;
	529	int is_write;
	530	uint32_t insn;
	531
	532	/* XXX: is there a standard glibc define ? */
	533	pc = regs[1];
	534	/* XXX: need kernel patch to get write flag faster */
	535	is_write = 0;
	536	insn = (uint32_t )pc;
	537	if ((insn >> 30) == 3) {
	538	switch((insn >> 19) & 0x3f) {
	539	case 0x05: // stb
	540	case 0x06: // sth
	541	case 0x04: // st
	542	case 0x07: // std
	543	case 0x24: // stf
	544	case 0x27: // stdf
	545	case 0x25: // stfsr
	546	is_write = 1;
	547	break;
	548	}
	549	}
	550	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	551	is_write, sigmask);
	552	}
	553
	554	#elif defined(__arm__)
	555
e4533c7a FB	556	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	557	void *puc)
8c6939c0 FB	558	{
	559	struct ucontext *uc = puc;
	560	unsigned long pc;
	561	int is_write;
	562
	563	pc = uc->uc_mcontext.gregs[R15];
	564	/* XXX: compute is_write */
	565	is_write = 0;
	566	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	567	is_write,
	568	&uc->uc_sigmask);
	569	}
	570
9de5e440	571	#else
2b413144	572
25eb4484	573	#error CPU specific signal handler needed
2b413144	574
9de5e440	575	#endif