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Use Cocoa and CoreAudio backend by default on Darwin systems, by Pierre
[mirror_qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
e6e5906b 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
e6e5906b 50#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
8a40a180
FB		 76
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
15388002 129 tb_invalidated_flag = 1;
8a40a180
FB		 130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
8a40a180
FB		 147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151}
152
153static inline TranslationBlock *tb_find_fast(void)
154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162#if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167#elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
40f137e1
PB		 172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
8a40a180
FB		 174 cs_base = 0;
175 pc = env->regs[15];
176#elif defined(TARGET_SPARC)
177#ifdef TARGET_SPARC64
a80dde08
FB		 178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 181#else
a80dde08
FB		 182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
8a40a180
FB		 185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
56b19403 194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 195 cs_base = 0;
8a40a180 196 pc = env->PC;
e6e5906b
PB		 197#elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
fdf9b3e8
FB		 201#elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
8a40a180
FB		 205#else
206#error unsupported CPU
207#endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
8a40a180
FB		 220 }
221 return tb;
222}
223
224
7d13299d
FB		 225/* main execution loop */
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
3475187d
FB		 229 int saved_T0, saved_T1;
230#if defined(reg_T2)
231 int saved_T2;
232#endif
e4533c7a 233 CPUState *saved_env;
3475187d 234#if defined(TARGET_I386)
04369ff2
FB		 235#ifdef reg_EAX
236 int saved_EAX;
237#endif
238#ifdef reg_ECX
239 int saved_ECX;
240#endif
241#ifdef reg_EDX
242 int saved_EDX;
243#endif
244#ifdef reg_EBX
245 int saved_EBX;
246#endif
247#ifdef reg_ESP
248 int saved_ESP;
249#endif
250#ifdef reg_EBP
251 int saved_EBP;
252#endif
253#ifdef reg_ESI
254 int saved_ESI;
255#endif
256#ifdef reg_EDI
257 int saved_EDI;
8c6939c0 258#endif
3475187d
FB		 259#elif defined(TARGET_SPARC)
260#if defined(reg_REGWPTR)
261 uint32_t *saved_regwptr;
262#endif
263#endif
fdbb4691 264#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 265 int saved_i7, tmp_T0;
04369ff2 266#endif
8a40a180 267 int ret, interrupt_request;
7d13299d 268 void (*gen_func)(void);
8a40a180 269 TranslationBlock *tb;
c27004ec 270 uint8_t *tc_ptr;
8c6939c0 271
5a1e3cfc
FB		 272#if defined(TARGET_I386)
273 /* handle exit of HALTED state */
274 if (env1->hflags & HF_HALTED_MASK) {
275 /* disable halt condition */
276 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
277 (env1->eflags & IF_MASK)) {
278 env1->hflags &= ~HF_HALTED_MASK;
279 } else {
280 return EXCP_HALTED;
e80e1cc4
FB		 281 }
282 }
283#elif defined(TARGET_PPC)
50443c98 284 if (env1->halted) {
e80e1cc4
FB		 285 if (env1->msr[MSR_EE] &&
286 (env1->interrupt_request &
287 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
50443c98 288 env1->halted = 0;
e80e1cc4
FB		 289 } else {
290 return EXCP_HALTED;
5a1e3cfc
FB		 291 }
292 }
ba3c64fb
FB		 293#elif defined(TARGET_SPARC)
294 if (env1->halted) {
295 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
296 (env1->psret != 0)) {
297 env1->halted = 0;
298 } else {
299 return EXCP_HALTED;
300 }
301 }
9332f9da
FB		 302#elif defined(TARGET_ARM)
303 if (env1->halted) {
304 /* An interrupt wakes the CPU even if the I and F CPSR bits are
305 set. */
306 if (env1->interrupt_request
307 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
308 env1->halted = 0;
309 } else {
310 return EXCP_HALTED;
311 }
312 }
6810e154
FB		 313#elif defined(TARGET_MIPS)
314 if (env1->halted) {
315 if (env1->interrupt_request &
316 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
317 env1->halted = 0;
318 } else {
319 return EXCP_HALTED;
320 }
321 }
5a1e3cfc
FB		 322#endif
323
6a00d601
FB		 324 cpu_single_env = env1;
325
7d13299d 326 /* first we save global registers */
c27004ec
FB		 327 saved_env = env;
328 env = env1;
7d13299d
FB		 329 saved_T0 = T0;
330 saved_T1 = T1;
3475187d 331#if defined(reg_T2)
e4533c7a 332 saved_T2 = T2;
3475187d 333#endif
fdbb4691 334#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 335 /* we also save i7 because longjmp may not restore it */
336 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
337#endif
338
339#if defined(TARGET_I386)
04369ff2
FB		 340#ifdef reg_EAX
341 saved_EAX = EAX;
04369ff2
FB		 342#endif
343#ifdef reg_ECX
344 saved_ECX = ECX;
04369ff2
FB		 345#endif
346#ifdef reg_EDX
347 saved_EDX = EDX;
04369ff2
FB		 348#endif
349#ifdef reg_EBX
350 saved_EBX = EBX;
04369ff2
FB		 351#endif
352#ifdef reg_ESP
353 saved_ESP = ESP;
04369ff2
FB		 354#endif
355#ifdef reg_EBP
356 saved_EBP = EBP;
04369ff2
FB		 357#endif
358#ifdef reg_ESI
359 saved_ESI = ESI;
04369ff2
FB		 360#endif
361#ifdef reg_EDI
362 saved_EDI = EDI;
04369ff2 363#endif
0d1a29f9
FB		 364
365 env_to_regs();
9de5e440 366 /* put eflags in CPU temporary format */
fc2b4c48
FB		 367 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
368 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 369 CC_OP = CC_OP_EFLAGS;
fc2b4c48 370 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 371#elif defined(TARGET_ARM)
93ac68bc 372#elif defined(TARGET_SPARC)
3475187d
FB		 373#if defined(reg_REGWPTR)
374 saved_regwptr = REGWPTR;
375#endif
67867308 376#elif defined(TARGET_PPC)
e6e5906b
PB		 377#elif defined(TARGET_M68K)
378 env->cc_op = CC_OP_FLAGS;
379 env->cc_dest = env->sr & 0xf;
380 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 381#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 382#elif defined(TARGET_SH4)
383 /* XXXXX */
e4533c7a
FB		 384#else
385#error unsupported target CPU
386#endif
3fb2ded1 387 env->exception_index = -1;
9d27abd9 388
7d13299d 389 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 390 for(;;) {
391 if (setjmp(env->jmp_env) == 0) {
ee8b7021 392 env->current_tb = NULL;
3fb2ded1
FB		 393 /* if an exception is pending, we execute it here */
394 if (env->exception_index >= 0) {
395 if (env->exception_index >= EXCP_INTERRUPT) {
396 /* exit request from the cpu execution loop */
397 ret = env->exception_index;
398 break;
399 } else if (env->user_mode_only) {
400 /* if user mode only, we simulate a fake exception
9f083493 401 which will be handled outside the cpu execution
3fb2ded1 402 loop */
83479e77 403#if defined(TARGET_I386)
3fb2ded1
FB		 404 do_interrupt_user(env->exception_index,
405 env->exception_is_int,
406 env->error_code,
407 env->exception_next_eip);
83479e77 408#endif
3fb2ded1
FB		 409 ret = env->exception_index;
410 break;
411 } else {
83479e77 412#if defined(TARGET_I386)
3fb2ded1
FB		 413 /* simulate a real cpu exception. On i386, it can
414 trigger new exceptions, but we do not handle
415 double or triple faults yet. */
416 do_interrupt(env->exception_index,
417 env->exception_is_int,
418 env->error_code,
d05e66d2 419 env->exception_next_eip, 0);
ce09776b
FB		 420#elif defined(TARGET_PPC)
421 do_interrupt(env);
6af0bf9c
FB		 422#elif defined(TARGET_MIPS)
423 do_interrupt(env);
e95c8d51 424#elif defined(TARGET_SPARC)
1a0c3292 425 do_interrupt(env->exception_index);
b5ff1b31
FB		 426#elif defined(TARGET_ARM)
427 do_interrupt(env);
fdf9b3e8
FB		 428#elif defined(TARGET_SH4)
429 do_interrupt(env);
83479e77 430#endif
3fb2ded1
FB		 431 }
432 env->exception_index = -1;
9df217a3
FB		 433 }
434#ifdef USE_KQEMU
435 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
436 int ret;
437 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
438 ret = kqemu_cpu_exec(env);
439 /* put eflags in CPU temporary format */
440 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
441 DF = 1 - (2 * ((env->eflags >> 10) & 1));
442 CC_OP = CC_OP_EFLAGS;
443 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
444 if (ret == 1) {
445 /* exception */
446 longjmp(env->jmp_env, 1);
447 } else if (ret == 2) {
448 /* softmmu execution needed */
449 } else {
450 if (env->interrupt_request != 0) {
451 /* hardware interrupt will be executed just after */
452 } else {
453 /* otherwise, we restart */
454 longjmp(env->jmp_env, 1);
455 }
456 }
3fb2ded1 457 }
9df217a3
FB		 458#endif
459
3fb2ded1
FB		 460 T0 = 0; /* force lookup of first TB */
461 for(;;) {
fdbb4691 462#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 463 /* g1 can be modified by some libc? functions */
464 tmp_T0 = T0;
8c6939c0 465#endif
68a79315 466 interrupt_request = env->interrupt_request;
2e255c6b 467 if (__builtin_expect(interrupt_request, 0)) {
68a79315 468#if defined(TARGET_I386)
3b21e03e
FB		 469 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
470 !(env->hflags & HF_SMM_MASK)) {
471 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
472 do_smm_enter();
473#if defined(__sparc__) && !defined(HOST_SOLARIS)
474 tmp_T0 = 0;
475#else
476 T0 = 0;
477#endif
478 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 479 (env->eflags & IF_MASK) &&
480 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 481 int intno;
fbf9eeb3 482 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 483 intno = cpu_get_pic_interrupt(env);
f193c797 484 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 485 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
486 }
d05e66d2 487 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 488 /* ensure that no TB jump will be modified as
489 the program flow was changed */
fdbb4691 490#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 491 tmp_T0 = 0;
492#else
493 T0 = 0;
494#endif
68a79315 495 }
ce09776b 496#elif defined(TARGET_PPC)
9fddaa0c
FB		 497#if 0
498 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
499 cpu_ppc_reset(env);
500 }
501#endif
502 if (msr_ee != 0) {
8a40a180 503 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 504 /* Raise it */
505 env->exception_index = EXCP_EXTERNAL;
506 env->error_code = 0;
ce09776b 507 do_interrupt(env);
8a40a180 508 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 509#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 510 tmp_T0 = 0;
511#else
512 T0 = 0;
513#endif
514 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
515 /* Raise it */
516 env->exception_index = EXCP_DECR;
517 env->error_code = 0;
518 do_interrupt(env);
9fddaa0c 519 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
fdbb4691 520#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 521 tmp_T0 = 0;
522#else
523 T0 = 0;
524#endif
525 }
ce09776b 526 }
6af0bf9c
FB		 527#elif defined(TARGET_MIPS)
528 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
529 (env->CP0_Status & (1 << CP0St_IE)) &&
7ebab699 530 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
6af0bf9c
FB		 531 !(env->hflags & MIPS_HFLAG_EXL) &&
532 !(env->hflags & MIPS_HFLAG_ERL) &&
533 !(env->hflags & MIPS_HFLAG_DM)) {
534 /* Raise it */
535 env->exception_index = EXCP_EXT_INTERRUPT;
536 env->error_code = 0;
537 do_interrupt(env);
fdbb4691 538#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 539 tmp_T0 = 0;
540#else
541 T0 = 0;
542#endif
6af0bf9c 543 }
e95c8d51 544#elif defined(TARGET_SPARC)
66321a11
FB		 545 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
546 (env->psret != 0)) {
547 int pil = env->interrupt_index & 15;
548 int type = env->interrupt_index & 0xf0;
549
550 if (((type == TT_EXTINT) &&
551 (pil == 15 || pil > env->psrpil)) ||
552 type != TT_EXTINT) {
553 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
554 do_interrupt(env->interrupt_index);
555 env->interrupt_index = 0;
fdbb4691 556#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 557 tmp_T0 = 0;
558#else
559 T0 = 0;
560#endif
66321a11 561 }
e95c8d51
FB		 562 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
563 //do_interrupt(0, 0, 0, 0, 0);
564 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb 565 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
df52b000
FB		 566 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
567 env->halted = 1;
568 env->exception_index = EXCP_HLT;
569 cpu_loop_exit();
ba3c64fb 570 }
b5ff1b31
FB		 571#elif defined(TARGET_ARM)
572 if (interrupt_request & CPU_INTERRUPT_FIQ
573 && !(env->uncached_cpsr & CPSR_F)) {
574 env->exception_index = EXCP_FIQ;
575 do_interrupt(env);
576 }
577 if (interrupt_request & CPU_INTERRUPT_HARD
578 && !(env->uncached_cpsr & CPSR_I)) {
579 env->exception_index = EXCP_IRQ;
580 do_interrupt(env);
581 }
fdf9b3e8
FB		 582#elif defined(TARGET_SH4)
583 /* XXXXX */
68a79315 584#endif
9d05095e
FB		 585 /* Don't use the cached interupt_request value,
586 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 587 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 588 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
589 /* ensure that no TB jump will be modified as
590 the program flow was changed */
fdbb4691 591#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 592 tmp_T0 = 0;
593#else
594 T0 = 0;
595#endif
596 }
68a79315
FB		 597 if (interrupt_request & CPU_INTERRUPT_EXIT) {
598 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
599 env->exception_index = EXCP_INTERRUPT;
600 cpu_loop_exit();
601 }
3fb2ded1 602 }
7d13299d 603#ifdef DEBUG_EXEC
b5ff1b31 604 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 605#if defined(TARGET_I386)
3fb2ded1 606 /* restore flags in standard format */
fc9f715d 607#ifdef reg_EAX
3fb2ded1 608 env->regs[R_EAX] = EAX;
fc9f715d
FB		 609#endif
610#ifdef reg_EBX
3fb2ded1 611 env->regs[R_EBX] = EBX;
fc9f715d
FB		 612#endif
613#ifdef reg_ECX
3fb2ded1 614 env->regs[R_ECX] = ECX;
fc9f715d
FB		 615#endif
616#ifdef reg_EDX
3fb2ded1 617 env->regs[R_EDX] = EDX;
fc9f715d
FB		 618#endif
619#ifdef reg_ESI
3fb2ded1 620 env->regs[R_ESI] = ESI;
fc9f715d
FB		 621#endif
622#ifdef reg_EDI
3fb2ded1 623 env->regs[R_EDI] = EDI;
fc9f715d
FB		 624#endif
625#ifdef reg_EBP
3fb2ded1 626 env->regs[R_EBP] = EBP;
fc9f715d
FB		 627#endif
628#ifdef reg_ESP
3fb2ded1 629 env->regs[R_ESP] = ESP;
fc9f715d 630#endif
3fb2ded1 631 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 632 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 633 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 634#elif defined(TARGET_ARM)
7fe48483 635 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 636#elif defined(TARGET_SPARC)
3475187d
FB		 637 REGWPTR = env->regbase + (env->cwp * 16);
638 env->regwptr = REGWPTR;
639 cpu_dump_state(env, logfile, fprintf, 0);
67867308 640#elif defined(TARGET_PPC)
7fe48483 641 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 642#elif defined(TARGET_M68K)
643 cpu_m68k_flush_flags(env, env->cc_op);
644 env->cc_op = CC_OP_FLAGS;
645 env->sr = (env->sr & 0xffe0)
646 | env->cc_dest | (env->cc_x << 4);
647 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 648#elif defined(TARGET_MIPS)
649 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 650#elif defined(TARGET_SH4)
651 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 652#else
653#error unsupported target CPU
654#endif
3fb2ded1 655 }
7d13299d 656#endif
8a40a180 657 tb = tb_find_fast();
9d27abd9 658#ifdef DEBUG_EXEC
c1135f61 659 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 660 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
661 (long)tb->tc_ptr, tb->pc,
662 lookup_symbol(tb->pc));
3fb2ded1 663 }
9d27abd9 664#endif
fdbb4691 665#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 666 T0 = tmp_T0;
8c6939c0 667#endif
8a40a180
FB		 668 /* see if we can patch the calling TB. When the TB
669 spans two pages, we cannot safely do a direct
670 jump. */
c27004ec 671 {
8a40a180 672 if (T0 != 0 &&
f32fc648
FB		 673#if USE_KQEMU
674 (env->kqemu_enabled != 2) &&
675#endif
8a40a180 676 tb->page_addr[1] == -1
bf3e8bf1
FB		 677#if defined(TARGET_I386) && defined(USE_CODE_COPY)
678 && (tb->cflags & CF_CODE_COPY) ==
679 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
680#endif
681 ) {
3fb2ded1 682 spin_lock(&tb_lock);
c27004ec 683 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 684#if defined(USE_CODE_COPY)
685 /* propagates the FP use info */
686 ((TranslationBlock *)(T0 & ~3))->cflags |=
687 (tb->cflags & CF_FP_USED);
688#endif
3fb2ded1
FB		 689 spin_unlock(&tb_lock);
690 }
c27004ec 691 }
3fb2ded1 692 tc_ptr = tb->tc_ptr;
83479e77 693 env->current_tb = tb;
3fb2ded1
FB		 694 /* execute the generated code */
695 gen_func = (void *)tc_ptr;
8c6939c0 696#if defined(__sparc__)
3fb2ded1
FB		 697 __asm__ __volatile__("call %0\n\t"
698 "mov %%o7,%%i0"
699 : /* no outputs */
700 : "r" (gen_func)
fdbb4691
FB		 701 : "i0", "i1", "i2", "i3", "i4", "i5",
702 "l0", "l1", "l2", "l3", "l4", "l5",
703 "l6", "l7");
8c6939c0 704#elif defined(__arm__)
3fb2ded1
FB		 705 asm volatile ("mov pc, %0\n\t"
706 ".global exec_loop\n\t"
707 "exec_loop:\n\t"
708 : /* no outputs */
709 : "r" (gen_func)
710 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 711#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
712{
713 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 714 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
715 save_native_fp_state(env);
716 }
bf3e8bf1
FB		 717 gen_func();
718 } else {
97eb5b14
FB		 719 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
720 restore_native_fp_state(env);
721 }
bf3e8bf1
FB		 722 /* we work with native eflags */
723 CC_SRC = cc_table[CC_OP].compute_all();
724 CC_OP = CC_OP_EFLAGS;
725 asm(".globl exec_loop\n"
726 "\n"
727 "debug1:\n"
728 " pushl %%ebp\n"
729 " fs movl %10, %9\n"
730 " fs movl %11, %%eax\n"
731 " andl $0x400, %%eax\n"
732 " fs orl %8, %%eax\n"
733 " pushl %%eax\n"
734 " popf\n"
735 " fs movl %%esp, %12\n"
736 " fs movl %0, %%eax\n"
737 " fs movl %1, %%ecx\n"
738 " fs movl %2, %%edx\n"
739 " fs movl %3, %%ebx\n"
740 " fs movl %4, %%esp\n"
741 " fs movl %5, %%ebp\n"
742 " fs movl %6, %%esi\n"
743 " fs movl %7, %%edi\n"
744 " fs jmp *%9\n"
745 "exec_loop:\n"
746 " fs movl %%esp, %4\n"
747 " fs movl %12, %%esp\n"
748 " fs movl %%eax, %0\n"
749 " fs movl %%ecx, %1\n"
750 " fs movl %%edx, %2\n"
751 " fs movl %%ebx, %3\n"
752 " fs movl %%ebp, %5\n"
753 " fs movl %%esi, %6\n"
754 " fs movl %%edi, %7\n"
755 " pushf\n"
756 " popl %%eax\n"
757 " movl %%eax, %%ecx\n"
758 " andl $0x400, %%ecx\n"
759 " shrl $9, %%ecx\n"
760 " andl $0x8d5, %%eax\n"
761 " fs movl %%eax, %8\n"
762 " movl $1, %%eax\n"
763 " subl %%ecx, %%eax\n"
764 " fs movl %%eax, %11\n"
765 " fs movl %9, %%ebx\n" /* get T0 value */
766 " popl %%ebp\n"
767 :
768 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
769 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
770 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
771 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
772 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
773 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
774 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
775 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
776 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
777 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
778 "a" (gen_func),
779 "m" (*(uint8_t *)offsetof(CPUState, df)),
780 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
781 : "%ecx", "%edx"
782 );
783 }
784}
b8076a74
FB		 785#elif defined(__ia64)
786 struct fptr {
787 void *ip;
788 void *gp;
789 } fp;
790
791 fp.ip = tc_ptr;
792 fp.gp = code_gen_buffer + 2 * (1 << 20);
793 (*(void (*)(void)) &fp)();
ae228531 794#else
3fb2ded1 795 gen_func();
ae228531 796#endif
83479e77 797 env->current_tb = NULL;
4cbf74b6
FB		 798 /* reset soft MMU for next block (it can currently
799 only be set by a memory fault) */
800#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 801 if (env->hflags & HF_SOFTMMU_MASK) {
802 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 803 /* do not allow linking to another block */
804 T0 = 0;
805 }
f32fc648
FB		 806#endif
807#if defined(USE_KQEMU)
808#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
809 if (kqemu_is_ok(env) &&
810 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
811 cpu_loop_exit();
812 }
4cbf74b6 813#endif
3fb2ded1
FB		 814 }
815 } else {
0d1a29f9 816 env_to_regs();
7d13299d 817 }
3fb2ded1
FB		 818 } /* for(;;) */
819
7d13299d 820
e4533c7a 821#if defined(TARGET_I386)
97eb5b14
FB		 822#if defined(USE_CODE_COPY)
823 if (env->native_fp_regs) {
824 save_native_fp_state(env);
825 }
826#endif
9de5e440 827 /* restore flags in standard format */
fc2b4c48 828 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 829
7d13299d 830 /* restore global registers */
04369ff2
FB		 831#ifdef reg_EAX
832 EAX = saved_EAX;
833#endif
834#ifdef reg_ECX
835 ECX = saved_ECX;
836#endif
837#ifdef reg_EDX
838 EDX = saved_EDX;
839#endif
840#ifdef reg_EBX
841 EBX = saved_EBX;
842#endif
843#ifdef reg_ESP
844 ESP = saved_ESP;
845#endif
846#ifdef reg_EBP
847 EBP = saved_EBP;
848#endif
849#ifdef reg_ESI
850 ESI = saved_ESI;
851#endif
852#ifdef reg_EDI
853 EDI = saved_EDI;
8c6939c0 854#endif
e4533c7a 855#elif defined(TARGET_ARM)
b7bcbe95 856 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 857#elif defined(TARGET_SPARC)
3475187d
FB		 858#if defined(reg_REGWPTR)
859 REGWPTR = saved_regwptr;
860#endif
67867308 861#elif defined(TARGET_PPC)
e6e5906b
PB		 862#elif defined(TARGET_M68K)
863 cpu_m68k_flush_flags(env, env->cc_op);
864 env->cc_op = CC_OP_FLAGS;
865 env->sr = (env->sr & 0xffe0)
866 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 867#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 868#elif defined(TARGET_SH4)
869 /* XXXXX */
e4533c7a
FB		 870#else
871#error unsupported target CPU
872#endif
fdbb4691 873#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 874 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 875#endif
7d13299d
FB		 876 T0 = saved_T0;
877 T1 = saved_T1;
3475187d 878#if defined(reg_T2)
e4533c7a 879 T2 = saved_T2;
3475187d 880#endif
7d13299d 881 env = saved_env;
6a00d601
FB		 882 /* fail safe : never use cpu_single_env outside cpu_exec() */
883 cpu_single_env = NULL;
7d13299d
FB		 884 return ret;
885}
6dbad63e 886
fbf9eeb3
FB		 887/* must only be called from the generated code as an exception can be
888 generated */
889void tb_invalidate_page_range(target_ulong start, target_ulong end)
890{
dc5d0b3d
FB		 891 /* XXX: cannot enable it yet because it yields to MMU exception
892 where NIP != read address on PowerPC */
893#if 0
fbf9eeb3
FB		 894 target_ulong phys_addr;
895 phys_addr = get_phys_addr_code(env, start);
896 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 897#endif
fbf9eeb3
FB		 898}
899
1a18c71b 900#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 901
6dbad63e
FB		 902void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
903{
904 CPUX86State *saved_env;
905
906 saved_env = env;
907 env = s;
a412ac57 908 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 909 selector &= 0xffff;
2e255c6b 910 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 911 (selector << 4), 0xffff, 0);
a513fe19 912 } else {
b453b70b 913 load_seg(seg_reg, selector);
a513fe19 914 }
6dbad63e
FB		 915 env = saved_env;
916}
9de5e440 917
d0a1ffc9
FB		 918void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
919{
920 CPUX86State *saved_env;
921
922 saved_env = env;
923 env = s;
924
c27004ec 925 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 926
927 env = saved_env;
928}
929
930void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
931{
932 CPUX86State *saved_env;
933
934 saved_env = env;
935 env = s;
936
c27004ec 937 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 938
939 env = saved_env;
940}
941
e4533c7a
FB		 942#endif /* TARGET_I386 */
943
67b915a5
FB		 944#if !defined(CONFIG_SOFTMMU)
945
3fb2ded1
FB		 946#if defined(TARGET_I386)
947
b56dad1c 948/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 949 the effective address of the memory exception. 'is_write' is 1 if a
950 write caused the exception and otherwise 0'. 'old_set' is the
951 signal set which should be restored */
2b413144 952static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 953 int is_write, sigset_t *old_set,
954 void *puc)
9de5e440 955{
a513fe19
FB		 956 TranslationBlock *tb;
957 int ret;
68a79315 958
83479e77
FB		 959 if (cpu_single_env)
960 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 961#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 962 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
963 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 964#endif
25eb4484 965 /* XXX: locking issue */
53a5960a 966 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 967 return 1;
968 }
fbf9eeb3 969
3fb2ded1 970 /* see if it is an MMU fault */
93a40ea9
FB		 971 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
972 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 973 if (ret < 0)
974 return 0; /* not an MMU fault */
975 if (ret == 0)
976 return 1; /* the MMU fault was handled without causing real CPU fault */
977 /* now we have a real cpu fault */
a513fe19
FB		 978 tb = tb_find_pc(pc);
979 if (tb) {
9de5e440
FB		 980 /* the PC is inside the translated code. It means that we have
981 a virtual CPU fault */
bf3e8bf1 982 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 983 }
4cbf74b6 984 if (ret == 1) {
3fb2ded1 985#if 0
4cbf74b6
FB		 986 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
987 env->eip, env->cr[2], env->error_code);
3fb2ded1 988#endif
4cbf74b6
FB		 989 /* we restore the process signal mask as the sigreturn should
990 do it (XXX: use sigsetjmp) */
991 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 992 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 993 } else {
994 /* activate soft MMU for this block */
3f337316 995 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 996 cpu_resume_from_signal(env, puc);
4cbf74b6 997 }
3fb2ded1
FB		 998 /* never comes here */
999 return 1;
1000}
1001
e4533c7a 1002#elif defined(TARGET_ARM)
3fb2ded1 1003static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1004 int is_write, sigset_t *old_set,
1005 void *puc)
3fb2ded1 1006{
68016c62
FB		 1007 TranslationBlock *tb;
1008 int ret;
1009
1010 if (cpu_single_env)
1011 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1012#if defined(DEBUG_SIGNAL)
1013 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1014 pc, address, is_write, *(unsigned long *)old_set);
1015#endif
9f0777ed 1016 /* XXX: locking issue */
53a5960a 1017 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 1018 return 1;
1019 }
68016c62
FB		 1020 /* see if it is an MMU fault */
1021 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
1022 if (ret < 0)
1023 return 0; /* not an MMU fault */
1024 if (ret == 0)
1025 return 1; /* the MMU fault was handled without causing real CPU fault */
1026 /* now we have a real cpu fault */
1027 tb = tb_find_pc(pc);
1028 if (tb) {
1029 /* the PC is inside the translated code. It means that we have
1030 a virtual CPU fault */
1031 cpu_restore_state(tb, env, pc, puc);
1032 }
1033 /* we restore the process signal mask as the sigreturn should
1034 do it (XXX: use sigsetjmp) */
1035 sigprocmask(SIG_SETMASK, old_set, NULL);
1036 cpu_loop_exit();
3fb2ded1 1037}
93ac68bc
FB		 1038#elif defined(TARGET_SPARC)
1039static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1040 int is_write, sigset_t *old_set,
1041 void *puc)
93ac68bc 1042{
68016c62
FB		 1043 TranslationBlock *tb;
1044 int ret;
1045
1046 if (cpu_single_env)
1047 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1048#if defined(DEBUG_SIGNAL)
1049 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1050 pc, address, is_write, *(unsigned long *)old_set);
1051#endif
b453b70b 1052 /* XXX: locking issue */
53a5960a 1053 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 1054 return 1;
1055 }
68016c62
FB		 1056 /* see if it is an MMU fault */
1057 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1058 if (ret < 0)
1059 return 0; /* not an MMU fault */
1060 if (ret == 0)
1061 return 1; /* the MMU fault was handled without causing real CPU fault */
1062 /* now we have a real cpu fault */
1063 tb = tb_find_pc(pc);
1064 if (tb) {
1065 /* the PC is inside the translated code. It means that we have
1066 a virtual CPU fault */
1067 cpu_restore_state(tb, env, pc, puc);
1068 }
1069 /* we restore the process signal mask as the sigreturn should
1070 do it (XXX: use sigsetjmp) */
1071 sigprocmask(SIG_SETMASK, old_set, NULL);
1072 cpu_loop_exit();
93ac68bc 1073}
67867308
FB		 1074#elif defined (TARGET_PPC)
1075static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1076 int is_write, sigset_t *old_set,
1077 void *puc)
67867308
FB		 1078{
1079 TranslationBlock *tb;
ce09776b 1080 int ret;
67867308 1081
67867308
FB		 1082 if (cpu_single_env)
1083 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 1084#if defined(DEBUG_SIGNAL)
1085 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1086 pc, address, is_write, *(unsigned long *)old_set);
1087#endif
1088 /* XXX: locking issue */
53a5960a 1089 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 1090 return 1;
1091 }
1092
ce09776b 1093 /* see if it is an MMU fault */
7f957d28 1094 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1095 if (ret < 0)
1096 return 0; /* not an MMU fault */
1097 if (ret == 0)
1098 return 1; /* the MMU fault was handled without causing real CPU fault */
1099
67867308
FB		 1100 /* now we have a real cpu fault */
1101 tb = tb_find_pc(pc);
1102 if (tb) {
1103 /* the PC is inside the translated code. It means that we have
1104 a virtual CPU fault */
bf3e8bf1 1105 cpu_restore_state(tb, env, pc, puc);
67867308 1106 }
ce09776b 1107 if (ret == 1) {
67867308 1108#if 0
ce09776b
FB		 1109 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1110 env->nip, env->error_code, tb);
67867308
FB		 1111#endif
1112 /* we restore the process signal mask as the sigreturn should
1113 do it (XXX: use sigsetjmp) */
bf3e8bf1 1114 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1115 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1116 } else {
1117 /* activate soft MMU for this block */
fbf9eeb3 1118 cpu_resume_from_signal(env, puc);
ce09776b 1119 }
67867308 1120 /* never comes here */
e6e5906b
PB		 1121 return 1;
1122}
1123
1124#elif defined(TARGET_M68K)
1125static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1126 int is_write, sigset_t *old_set,
1127 void *puc)
1128{
1129 TranslationBlock *tb;
1130 int ret;
1131
1132 if (cpu_single_env)
1133 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1134#if defined(DEBUG_SIGNAL)
1135 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1136 pc, address, is_write, *(unsigned long *)old_set);
1137#endif
1138 /* XXX: locking issue */
1139 if (is_write && page_unprotect(address, pc, puc)) {
1140 return 1;
1141 }
1142 /* see if it is an MMU fault */
1143 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1144 if (ret < 0)
1145 return 0; /* not an MMU fault */
1146 if (ret == 0)
1147 return 1; /* the MMU fault was handled without causing real CPU fault */
1148 /* now we have a real cpu fault */
1149 tb = tb_find_pc(pc);
1150 if (tb) {
1151 /* the PC is inside the translated code. It means that we have
1152 a virtual CPU fault */
1153 cpu_restore_state(tb, env, pc, puc);
1154 }
1155 /* we restore the process signal mask as the sigreturn should
1156 do it (XXX: use sigsetjmp) */
1157 sigprocmask(SIG_SETMASK, old_set, NULL);
1158 cpu_loop_exit();
1159 /* never comes here */
67867308
FB		 1160 return 1;
1161}
6af0bf9c
FB		 1162
1163#elif defined (TARGET_MIPS)
1164static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1165 int is_write, sigset_t *old_set,
1166 void *puc)
1167{
1168 TranslationBlock *tb;
1169 int ret;
1170
1171 if (cpu_single_env)
1172 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1173#if defined(DEBUG_SIGNAL)
1174 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1175 pc, address, is_write, *(unsigned long *)old_set);
1176#endif
1177 /* XXX: locking issue */
53a5960a 1178 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1179 return 1;
1180 }
1181
1182 /* see if it is an MMU fault */
cc9442b9 1183 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1184 if (ret < 0)
1185 return 0; /* not an MMU fault */
1186 if (ret == 0)
1187 return 1; /* the MMU fault was handled without causing real CPU fault */
1188
1189 /* now we have a real cpu fault */
1190 tb = tb_find_pc(pc);
1191 if (tb) {
1192 /* the PC is inside the translated code. It means that we have
1193 a virtual CPU fault */
1194 cpu_restore_state(tb, env, pc, puc);
1195 }
1196 if (ret == 1) {
1197#if 0
1198 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1199 env->nip, env->error_code, tb);
1200#endif
1201 /* we restore the process signal mask as the sigreturn should
1202 do it (XXX: use sigsetjmp) */
1203 sigprocmask(SIG_SETMASK, old_set, NULL);
1204 do_raise_exception_err(env->exception_index, env->error_code);
1205 } else {
1206 /* activate soft MMU for this block */
1207 cpu_resume_from_signal(env, puc);
1208 }
1209 /* never comes here */
1210 return 1;
1211}
1212
fdf9b3e8
FB		 1213#elif defined (TARGET_SH4)
1214static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1215 int is_write, sigset_t *old_set,
1216 void *puc)
1217{
1218 TranslationBlock *tb;
1219 int ret;
1220
1221 if (cpu_single_env)
1222 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1223#if defined(DEBUG_SIGNAL)
1224 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1225 pc, address, is_write, *(unsigned long *)old_set);
1226#endif
1227 /* XXX: locking issue */
1228 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1229 return 1;
1230 }
1231
1232 /* see if it is an MMU fault */
1233 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1234 if (ret < 0)
1235 return 0; /* not an MMU fault */
1236 if (ret == 0)
1237 return 1; /* the MMU fault was handled without causing real CPU fault */
1238
1239 /* now we have a real cpu fault */
1240 tb = tb_find_pc(pc);
1241 if (tb) {
1242 /* the PC is inside the translated code. It means that we have
1243 a virtual CPU fault */
1244 cpu_restore_state(tb, env, pc, puc);
1245 }
fdf9b3e8
FB		 1246#if 0
1247 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1248 env->nip, env->error_code, tb);
1249#endif
1250 /* we restore the process signal mask as the sigreturn should
1251 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1252 sigprocmask(SIG_SETMASK, old_set, NULL);
1253 cpu_loop_exit();
fdf9b3e8
FB		 1254 /* never comes here */
1255 return 1;
1256}
e4533c7a
FB		 1257#else
1258#error unsupported target CPU
1259#endif
9de5e440 1260
2b413144
FB		 1261#if defined(__i386__)
1262
bf3e8bf1
FB		 1263#if defined(USE_CODE_COPY)
1264static void cpu_send_trap(unsigned long pc, int trap,
1265 struct ucontext *uc)
1266{
1267 TranslationBlock *tb;
1268
1269 if (cpu_single_env)
1270 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1271 /* now we have a real cpu fault */
1272 tb = tb_find_pc(pc);
1273 if (tb) {
1274 /* the PC is inside the translated code. It means that we have
1275 a virtual CPU fault */
1276 cpu_restore_state(tb, env, pc, uc);
1277 }
1278 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1279 raise_exception_err(trap, env->error_code);
1280}
1281#endif
1282
e4533c7a
FB		 1283int cpu_signal_handler(int host_signum, struct siginfo *info,
1284 void *puc)
9de5e440 1285{
9de5e440
FB		 1286 struct ucontext *uc = puc;
1287 unsigned long pc;
bf3e8bf1 1288 int trapno;
97eb5b14 1289
d691f669
FB		 1290#ifndef REG_EIP
1291/* for glibc 2.1 */
fd6ce8f6
FB		 1292#define REG_EIP EIP
1293#define REG_ERR ERR
1294#define REG_TRAPNO TRAPNO
d691f669 1295#endif
fc2b4c48 1296 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 1297 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1298#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1299 if (trapno == 0x00 || trapno == 0x05) {
1300 /* send division by zero or bound exception */
1301 cpu_send_trap(pc, trapno, uc);
1302 return 1;
1303 } else
1304#endif
1305 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1306 trapno == 0xe ?
1307 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1308 &uc->uc_sigmask, puc);
2b413144
FB		 1309}
1310
bc51c5c9
FB		 1311#elif defined(__x86_64__)
1312
1313int cpu_signal_handler(int host_signum, struct siginfo *info,
1314 void *puc)
1315{
1316 struct ucontext *uc = puc;
1317 unsigned long pc;
1318
1319 pc = uc->uc_mcontext.gregs[REG_RIP];
1320 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1321 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1322 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1323 &uc->uc_sigmask, puc);
1324}
1325
83fb7adf 1326#elif defined(__powerpc__)
2b413144 1327
83fb7adf
FB		 1328/***********************************************************************
1329 * signal context platform-specific definitions
1330 * From Wine
1331 */
1332#ifdef linux
1333/* All Registers access - only for local access */
1334# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1335/* Gpr Registers access */
1336# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1337# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1338# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1339# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1340# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1341# define LR_sig(context) REG_sig(link, context) /* Link register */
1342# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1343/* Float Registers access */
1344# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1345# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1346/* Exception Registers access */
1347# define DAR_sig(context) REG_sig(dar, context)
1348# define DSISR_sig(context) REG_sig(dsisr, context)
1349# define TRAP_sig(context) REG_sig(trap, context)
1350#endif /* linux */
1351
1352#ifdef __APPLE__
1353# include <sys/ucontext.h>
1354typedef struct ucontext SIGCONTEXT;
1355/* All Registers access - only for local access */
1356# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1357# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1358# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1359# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1360/* Gpr Registers access */
1361# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1362# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1363# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1364# define CTR_sig(context) REG_sig(ctr, context)
1365# define XER_sig(context) REG_sig(xer, context) /* Link register */
1366# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1367# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1368/* Float Registers access */
1369# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1370# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1371/* Exception Registers access */
1372# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1373# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1374# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1375#endif /* __APPLE__ */
1376
d1d9f421 1377int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 1378 void *puc)
2b413144 1379{
25eb4484 1380 struct ucontext *uc = puc;
25eb4484 1381 unsigned long pc;
25eb4484
FB		 1382 int is_write;
1383
83fb7adf 1384 pc = IAR_sig(uc);
25eb4484
FB		 1385 is_write = 0;
1386#if 0
1387 /* ppc 4xx case */
83fb7adf 1388 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1389 is_write = 1;
1390#else
83fb7adf 1391 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1392 is_write = 1;
1393#endif
1394 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1395 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1396}
1397
2f87c607
FB		 1398#elif defined(__alpha__)
1399
e4533c7a 1400int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 1401 void *puc)
1402{
1403 struct ucontext *uc = puc;
1404 uint32_t *pc = uc->uc_mcontext.sc_pc;
1405 uint32_t insn = *pc;
1406 int is_write = 0;
1407
8c6939c0 1408 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1409 switch (insn >> 26) {
1410 case 0x0d: // stw
1411 case 0x0e: // stb
1412 case 0x0f: // stq_u
1413 case 0x24: // stf
1414 case 0x25: // stg
1415 case 0x26: // sts
1416 case 0x27: // stt
1417 case 0x2c: // stl
1418 case 0x2d: // stq
1419 case 0x2e: // stl_c
1420 case 0x2f: // stq_c
1421 is_write = 1;
1422 }
1423
1424 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1425 is_write, &uc->uc_sigmask, puc);
2f87c607 1426}
8c6939c0
FB		 1427#elif defined(__sparc__)
1428
e4533c7a
FB		 1429int cpu_signal_handler(int host_signum, struct siginfo *info,
1430 void *puc)
8c6939c0
FB		 1431{
1432 uint32_t *regs = (uint32_t *)(info + 1);
1433 void *sigmask = (regs + 20);
1434 unsigned long pc;
1435 int is_write;
1436 uint32_t insn;
1437
1438 /* XXX: is there a standard glibc define ? */
1439 pc = regs[1];
1440 /* XXX: need kernel patch to get write flag faster */
1441 is_write = 0;
1442 insn = *(uint32_t *)pc;
1443 if ((insn >> 30) == 3) {
1444 switch((insn >> 19) & 0x3f) {
1445 case 0x05: // stb
1446 case 0x06: // sth
1447 case 0x04: // st
1448 case 0x07: // std
1449 case 0x24: // stf
1450 case 0x27: // stdf
1451 case 0x25: // stfsr
1452 is_write = 1;
1453 break;
1454 }
1455 }
1456 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1457 is_write, sigmask, NULL);
8c6939c0
FB		 1458}
1459
1460#elif defined(__arm__)
1461
e4533c7a
FB		 1462int cpu_signal_handler(int host_signum, struct siginfo *info,
1463 void *puc)
8c6939c0
FB		 1464{
1465 struct ucontext *uc = puc;
1466 unsigned long pc;
1467 int is_write;
1468
1469 pc = uc->uc_mcontext.gregs[R15];
1470 /* XXX: compute is_write */
1471 is_write = 0;
1472 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1473 is_write,
f3a9676a 1474 &uc->uc_sigmask, puc);
8c6939c0
FB		 1475}
1476
38e584a0
FB		 1477#elif defined(__mc68000)
1478
1479int cpu_signal_handler(int host_signum, struct siginfo *info,
1480 void *puc)
1481{
1482 struct ucontext *uc = puc;
1483 unsigned long pc;
1484 int is_write;
1485
1486 pc = uc->uc_mcontext.gregs[16];
1487 /* XXX: compute is_write */
1488 is_write = 0;
1489 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1490 is_write,
bf3e8bf1 1491 &uc->uc_sigmask, puc);
38e584a0
FB		 1492}
1493
b8076a74
FB		 1494#elif defined(__ia64)
1495
1496#ifndef __ISR_VALID
1497 /* This ought to be in <bits/siginfo.h>... */
1498# define __ISR_VALID 1
b8076a74
FB		 1499#endif
1500
1501int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1502{
1503 struct ucontext *uc = puc;
1504 unsigned long ip;
1505 int is_write = 0;
1506
1507 ip = uc->uc_mcontext.sc_ip;
1508 switch (host_signum) {
1509 case SIGILL:
1510 case SIGFPE:
1511 case SIGSEGV:
1512 case SIGBUS:
1513 case SIGTRAP:
fd4a43e4 1514 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1515 /* ISR.W (write-access) is bit 33: */
1516 is_write = (info->si_isr >> 33) & 1;
1517 break;
1518
1519 default:
1520 break;
1521 }
1522 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1523 is_write,
1524 &uc->uc_sigmask, puc);
1525}
1526
90cb9493
FB		 1527#elif defined(__s390__)
1528
1529int cpu_signal_handler(int host_signum, struct siginfo *info,
1530 void *puc)
1531{
1532 struct ucontext *uc = puc;
1533 unsigned long pc;
1534 int is_write;
1535
1536 pc = uc->uc_mcontext.psw.addr;
1537 /* XXX: compute is_write */
1538 is_write = 0;
1539 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1540 is_write,
1541 &uc->uc_sigmask, puc);
1542}
1543
9de5e440 1544#else
2b413144 1545
3fb2ded1 1546#error host CPU specific signal handler needed
2b413144 1547
9de5e440 1548#endif
67b915a5
FB		 1549
1550#endif /* !defined(CONFIG_SOFTMMU) */
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