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Merge tag 'seabios-hppa-v13-pull-request' of https://github.com/hdeller/qemu-hppa...
[mirror_qemu.git] / cpu-target.c
CommitLineData
d9f24bf5
PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
d9f24bf5
PB
21#include "qapi/error.h"
22
23#include "exec/target_page.h"
24#include "hw/qdev-core.h"
25#include "hw/qdev-properties.h"
26#include "qemu/error-report.h"
27#include "migration/vmstate.h"
28#ifdef CONFIG_USER_ONLY
29#include "qemu.h"
30#else
8b80bd28 31#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5
PB
32#include "exec/address-spaces.h"
33#endif
412ae126 34#include "sysemu/cpus.h"
d9f24bf5 35#include "sysemu/tcg.h"
5b5968c4 36#include "exec/replay-core.h"
377bf6f3 37#include "exec/cpu-common.h"
3b04508c 38#include "exec/exec-all.h"
548c9609 39#include "exec/tb-flush.h"
3b9bd3f4 40#include "exec/translate-all.h"
d9f24bf5 41#include "exec/log.h"
30565f10 42#include "hw/core/accel-cpu.h"
ad1a706f 43#include "trace/trace-root.h"
3b04508c 44#include "qemu/accel.h"
d9f24bf5
PB
45
46uintptr_t qemu_host_page_size;
47intptr_t qemu_host_page_mask;
48
49#ifndef CONFIG_USER_ONLY
50static int cpu_common_post_load(void *opaque, int version_id)
51{
52 CPUState *cpu = opaque;
53
54 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
55 version_id is increased. */
56 cpu->interrupt_request &= ~0x01;
57 tlb_flush(cpu);
58
59 /* loadvm has just updated the content of RAM, bypassing the
60 * usual mechanisms that ensure we flush TBs for writes to
61 * memory we've translated code from. So we must flush all TBs,
62 * which will now be stale.
63 */
64 tb_flush(cpu);
65
66 return 0;
67}
68
69static int cpu_common_pre_load(void *opaque)
70{
71 CPUState *cpu = opaque;
72
73 cpu->exception_index = -1;
74
75 return 0;
76}
77
78static bool cpu_common_exception_index_needed(void *opaque)
79{
80 CPUState *cpu = opaque;
81
82 return tcg_enabled() && cpu->exception_index != -1;
83}
84
85static const VMStateDescription vmstate_cpu_common_exception_index = {
86 .name = "cpu_common/exception_index",
87 .version_id = 1,
88 .minimum_version_id = 1,
89 .needed = cpu_common_exception_index_needed,
90 .fields = (VMStateField[]) {
91 VMSTATE_INT32(exception_index, CPUState),
92 VMSTATE_END_OF_LIST()
93 }
94};
95
96static bool cpu_common_crash_occurred_needed(void *opaque)
97{
98 CPUState *cpu = opaque;
99
100 return cpu->crash_occurred;
101}
102
103static const VMStateDescription vmstate_cpu_common_crash_occurred = {
104 .name = "cpu_common/crash_occurred",
105 .version_id = 1,
106 .minimum_version_id = 1,
107 .needed = cpu_common_crash_occurred_needed,
108 .fields = (VMStateField[]) {
109 VMSTATE_BOOL(crash_occurred, CPUState),
110 VMSTATE_END_OF_LIST()
111 }
112};
113
114const VMStateDescription vmstate_cpu_common = {
115 .name = "cpu_common",
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .pre_load = cpu_common_pre_load,
119 .post_load = cpu_common_post_load,
120 .fields = (VMStateField[]) {
121 VMSTATE_UINT32(halted, CPUState),
122 VMSTATE_UINT32(interrupt_request, CPUState),
123 VMSTATE_END_OF_LIST()
124 },
125 .subsections = (const VMStateDescription*[]) {
126 &vmstate_cpu_common_exception_index,
127 &vmstate_cpu_common_crash_occurred,
128 NULL
129 }
130};
131#endif
132
79a99091 133bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 134{
6fbdff87
AB
135 /* cache the cpu class for the hotpath */
136 cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5 137
bd684b2f 138 if (!accel_cpu_common_realize(cpu, errp)) {
79a99091 139 return false;
9ea057dc 140 }
4e4fa6c1 141
4e4fa6c1
RH
142 /* Wait until cpu initialization complete before exposing cpu. */
143 cpu_list_add(cpu);
144
7df5e3d6 145#ifdef CONFIG_USER_ONLY
4336073b
PMD
146 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
147 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6
CF
148#else
149 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
150 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
151 }
6fbdff87
AB
152 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
153 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6
CF
154 }
155#endif /* CONFIG_USER_ONLY */
79a99091
PMD
156
157 return true;
7df5e3d6
CF
158}
159
160void cpu_exec_unrealizefn(CPUState *cpu)
161{
feece4d0 162#ifndef CONFIG_USER_ONLY
7df5e3d6 163 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 164
feece4d0
PMD
165 if (cc->sysemu_ops->legacy_vmsd != NULL) {
166 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5
PB
167 }
168 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
169 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
170 }
d9f24bf5 171#endif
4731f89b 172
7df5e3d6 173 cpu_list_remove(cpu);
4731f89b
EC
174 /*
175 * Now that the vCPU has been removed from the RCU list, we can call
1aa1d830 176 * accel_cpu_common_unrealize, which may free fields using call_rcu.
4731f89b 177 */
1aa1d830 178 accel_cpu_common_unrealize(cpu);
d9f24bf5
PB
179}
180
6e8dcacd
RH
181/*
182 * This can't go in hw/core/cpu.c because that file is compiled only
183 * once for both user-mode and system builds.
184 */
995b87de 185static Property cpu_common_props[] = {
6e8dcacd
RH
186#ifdef CONFIG_USER_ONLY
187 /*
188 * Create a property for the user-only object, so users can
189 * adjust prctl(PR_SET_UNALIGN) from the command-line.
190 * Has no effect if the target does not support the feature.
191 */
192 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
193 prctl_unalign_sigbus, false),
194#else
995b87de 195 /*
54b99122 196 * Create a memory property for system CPU object, so users can
6e8dcacd 197 * wire up its memory. The default if no link is set up is to use
995b87de
RH
198 * the system address space.
199 */
200 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
201 MemoryRegion *),
202#endif
995b87de
RH
203 DEFINE_PROP_END_OF_LIST(),
204};
205
0c3c25fc
PM
206static bool cpu_get_start_powered_off(Object *obj, Error **errp)
207{
208 CPUState *cpu = CPU(obj);
209 return cpu->start_powered_off;
210}
211
212static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
213{
214 CPUState *cpu = CPU(obj);
215 cpu->start_powered_off = value;
216}
217
995b87de
RH
218void cpu_class_init_props(DeviceClass *dc)
219{
0c3c25fc
PM
220 ObjectClass *oc = OBJECT_CLASS(dc);
221
995b87de 222 device_class_set_props(dc, cpu_common_props);
0c3c25fc
PM
223 /*
224 * We can't use DEFINE_PROP_BOOL in the Property array for this
225 * property, because we want this to be settable after realize.
226 */
227 object_class_property_add_bool(oc, "start-powered-off",
228 cpu_get_start_powered_off,
229 cpu_set_start_powered_off);
995b87de
RH
230}
231
d9f24bf5
PB
232void cpu_exec_initfn(CPUState *cpu)
233{
234 cpu->as = NULL;
235 cpu->num_ases = 0;
236
237#ifndef CONFIG_USER_ONLY
238 cpu->thread_id = qemu_get_thread_id();
239 cpu->memory = get_system_memory();
240 object_ref(OBJECT(cpu->memory));
241#endif
242}
243
d9f24bf5
PB
244const char *parse_cpu_option(const char *cpu_option)
245{
246 ObjectClass *oc;
247 CPUClass *cc;
248 gchar **model_pieces;
249 const char *cpu_type;
250
251 model_pieces = g_strsplit(cpu_option, ",", 2);
252 if (!model_pieces[0]) {
253 error_report("-cpu option cannot be empty");
254 exit(1);
255 }
256
257 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
258 if (oc == NULL) {
259 error_report("unable to find CPU model '%s'", model_pieces[0]);
260 g_strfreev(model_pieces);
261 exit(EXIT_FAILURE);
262 }
263
264 cpu_type = object_class_get_name(oc);
265 cc = CPU_CLASS(oc);
266 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
267 g_strfreev(model_pieces);
268 return cpu_type;
269}
270
c138c3b8 271void list_cpus(void)
377bf6f3
PMD
272{
273 /* XXX: implement xxx_cpu_list for targets that still miss it */
274#if defined(cpu_list)
275 cpu_list();
276#endif
277}
278
d9f24bf5 279#if defined(CONFIG_USER_ONLY)
c814c892 280void tb_invalidate_phys_addr(hwaddr addr)
d9f24bf5
PB
281{
282 mmap_lock();
d6d1fd29 283 tb_invalidate_phys_page(addr);
d9f24bf5
PB
284 mmap_unlock();
285}
d9f24bf5
PB
286#else
287void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
288{
289 ram_addr_t ram_addr;
290 MemoryRegion *mr;
291 hwaddr l = 1;
292
293 if (!tcg_enabled()) {
294 return;
295 }
296
297 RCU_READ_LOCK_GUARD();
298 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
299 if (!(memory_region_is_ram(mr)
300 || memory_region_is_romd(mr))) {
301 return;
302 }
303 ram_addr = memory_region_get_ram_addr(mr) + addr;
d6d1fd29 304 tb_invalidate_phys_page(ram_addr);
d9f24bf5 305}
d9f24bf5
PB
306#endif
307
d9f24bf5
PB
308/* enable or disable single step mode. EXCP_DEBUG is returned by the
309 CPU loop after each instruction */
310void cpu_single_step(CPUState *cpu, int enabled)
311{
312 if (cpu->singlestep_enabled != enabled) {
313 cpu->singlestep_enabled = enabled;
412ae126
MY
314
315#if !defined(CONFIG_USER_ONLY)
316 const AccelOpsClass *ops = cpus_get_accel();
317 if (ops->update_guest_debug) {
318 ops->update_guest_debug(cpu);
d9f24bf5 319 }
412ae126
MY
320#endif
321
ad1a706f 322 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5
PB
323 }
324}
325
326void cpu_abort(CPUState *cpu, const char *fmt, ...)
327{
328 va_list ap;
329 va_list ap2;
330
331 va_start(ap, fmt);
332 va_copy(ap2, ap);
333 fprintf(stderr, "qemu: fatal: ");
334 vfprintf(stderr, fmt, ap);
335 fprintf(stderr, "\n");
336 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
337 if (qemu_log_separate()) {
c60f599b 338 FILE *logfile = qemu_log_trylock();
78b54858
RH
339 if (logfile) {
340 fprintf(logfile, "qemu: fatal: ");
341 vfprintf(logfile, fmt, ap2);
342 fprintf(logfile, "\n");
343 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
78b54858
RH
344 qemu_log_unlock(logfile);
345 }
d9f24bf5
PB
346 }
347 va_end(ap2);
348 va_end(ap);
349 replay_finish();
350#if defined(CONFIG_USER_ONLY)
351 {
352 struct sigaction act;
353 sigfillset(&act.sa_mask);
354 act.sa_handler = SIG_DFL;
355 act.sa_flags = 0;
356 sigaction(SIGABRT, &act, NULL);
357 }
358#endif
359 abort();
360}
361
362/* physical memory access (slow version, mainly for debug) */
363#if defined(CONFIG_USER_ONLY)
73842ef0
PMD
364int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
365 void *ptr, size_t len, bool is_write)
d9f24bf5
PB
366{
367 int flags;
73842ef0 368 vaddr l, page;
d9f24bf5
PB
369 void * p;
370 uint8_t *buf = ptr;
371
372 while (len > 0) {
373 page = addr & TARGET_PAGE_MASK;
374 l = (page + TARGET_PAGE_SIZE) - addr;
375 if (l > len)
376 l = len;
377 flags = page_get_flags(page);
378 if (!(flags & PAGE_VALID))
379 return -1;
380 if (is_write) {
381 if (!(flags & PAGE_WRITE))
382 return -1;
383 /* XXX: this code should not depend on lock_user */
384 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
385 return -1;
386 memcpy(p, buf, l);
387 unlock_user(p, addr, l);
388 } else {
389 if (!(flags & PAGE_READ))
390 return -1;
391 /* XXX: this code should not depend on lock_user */
392 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
393 return -1;
394 memcpy(buf, p, l);
395 unlock_user(p, addr, 0);
396 }
397 len -= l;
398 buf += l;
399 addr += l;
400 }
401 return 0;
402}
403#endif
404
405bool target_words_bigendian(void)
406{
ded625e7 407 return TARGET_BIG_ENDIAN;
d9f24bf5
PB
408}
409
1077f50b
TH
410const char *target_name(void)
411{
412 return TARGET_NAME;
413}
414
d9f24bf5
PB
415void page_size_init(void)
416{
417 /* NOTE: we can always suppose that qemu_host_page_size >=
418 TARGET_PAGE_SIZE */
419 if (qemu_host_page_size == 0) {
8e3b0cbb 420 qemu_host_page_size = qemu_real_host_page_size();
d9f24bf5
PB
421 }
422 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
423 qemu_host_page_size = TARGET_PAGE_SIZE;
424 }
425 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
426}