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CommitLineData
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PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
d9f24bf5
PB
21#include "qapi/error.h"
22
23#include "exec/target_page.h"
24#include "hw/qdev-core.h"
25#include "hw/qdev-properties.h"
26#include "qemu/error-report.h"
27#include "migration/vmstate.h"
28#ifdef CONFIG_USER_ONLY
29#include "qemu.h"
30#else
8b80bd28 31#include "hw/core/sysemu-cpu-ops.h"
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PB
32#include "exec/address-spaces.h"
33#endif
412ae126 34#include "sysemu/cpus.h"
d9f24bf5 35#include "sysemu/tcg.h"
5b5968c4 36#include "exec/replay-core.h"
377bf6f3 37#include "exec/cpu-common.h"
3b04508c 38#include "exec/exec-all.h"
548c9609 39#include "exec/tb-flush.h"
3b9bd3f4 40#include "exec/translate-all.h"
d9f24bf5 41#include "exec/log.h"
30565f10 42#include "hw/core/accel-cpu.h"
ad1a706f 43#include "trace/trace-root.h"
3b04508c 44#include "qemu/accel.h"
720ace24 45#include "qemu/plugin.h"
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PB
46
47uintptr_t qemu_host_page_size;
48intptr_t qemu_host_page_mask;
49
50#ifndef CONFIG_USER_ONLY
51static int cpu_common_post_load(void *opaque, int version_id)
52{
53 CPUState *cpu = opaque;
54
55 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
56 version_id is increased. */
57 cpu->interrupt_request &= ~0x01;
58 tlb_flush(cpu);
59
60 /* loadvm has just updated the content of RAM, bypassing the
61 * usual mechanisms that ensure we flush TBs for writes to
62 * memory we've translated code from. So we must flush all TBs,
63 * which will now be stale.
64 */
65 tb_flush(cpu);
66
67 return 0;
68}
69
70static int cpu_common_pre_load(void *opaque)
71{
72 CPUState *cpu = opaque;
73
74 cpu->exception_index = -1;
75
76 return 0;
77}
78
79static bool cpu_common_exception_index_needed(void *opaque)
80{
81 CPUState *cpu = opaque;
82
83 return tcg_enabled() && cpu->exception_index != -1;
84}
85
86static const VMStateDescription vmstate_cpu_common_exception_index = {
87 .name = "cpu_common/exception_index",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .needed = cpu_common_exception_index_needed,
91 .fields = (VMStateField[]) {
92 VMSTATE_INT32(exception_index, CPUState),
93 VMSTATE_END_OF_LIST()
94 }
95};
96
97static bool cpu_common_crash_occurred_needed(void *opaque)
98{
99 CPUState *cpu = opaque;
100
101 return cpu->crash_occurred;
102}
103
104static const VMStateDescription vmstate_cpu_common_crash_occurred = {
105 .name = "cpu_common/crash_occurred",
106 .version_id = 1,
107 .minimum_version_id = 1,
108 .needed = cpu_common_crash_occurred_needed,
109 .fields = (VMStateField[]) {
110 VMSTATE_BOOL(crash_occurred, CPUState),
111 VMSTATE_END_OF_LIST()
112 }
113};
114
115const VMStateDescription vmstate_cpu_common = {
116 .name = "cpu_common",
117 .version_id = 1,
118 .minimum_version_id = 1,
119 .pre_load = cpu_common_pre_load,
120 .post_load = cpu_common_post_load,
121 .fields = (VMStateField[]) {
122 VMSTATE_UINT32(halted, CPUState),
123 VMSTATE_UINT32(interrupt_request, CPUState),
124 VMSTATE_END_OF_LIST()
125 },
126 .subsections = (const VMStateDescription*[]) {
127 &vmstate_cpu_common_exception_index,
128 &vmstate_cpu_common_crash_occurred,
129 NULL
130 }
131};
132#endif
133
7df5e3d6 134void cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 135{
6fbdff87
AB
136 /* cache the cpu class for the hotpath */
137 cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5 138
bd684b2f 139 if (!accel_cpu_common_realize(cpu, errp)) {
9ea057dc
CF
140 return;
141 }
4e4fa6c1 142
4e4fa6c1
RH
143 /* Wait until cpu initialization complete before exposing cpu. */
144 cpu_list_add(cpu);
145
146 /* Plugin initialization must wait until cpu_index assigned. */
147 if (tcg_enabled()) {
148 qemu_plugin_vcpu_init_hook(cpu);
149 }
150
7df5e3d6 151#ifdef CONFIG_USER_ONLY
4336073b
PMD
152 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
153 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6
CF
154#else
155 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
156 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
157 }
6fbdff87
AB
158 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
159 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6
CF
160 }
161#endif /* CONFIG_USER_ONLY */
162}
163
164void cpu_exec_unrealizefn(CPUState *cpu)
165{
feece4d0 166#ifndef CONFIG_USER_ONLY
7df5e3d6 167 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 168
feece4d0
PMD
169 if (cc->sysemu_ops->legacy_vmsd != NULL) {
170 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
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PB
171 }
172 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
173 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
174 }
d9f24bf5 175#endif
4731f89b
EC
176
177 /* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
7df5e3d6 178 if (tcg_enabled()) {
4731f89b 179 qemu_plugin_vcpu_exit_hook(cpu);
7df5e3d6 180 }
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CF
181
182 cpu_list_remove(cpu);
4731f89b
EC
183 /*
184 * Now that the vCPU has been removed from the RCU list, we can call
1aa1d830 185 * accel_cpu_common_unrealize, which may free fields using call_rcu.
4731f89b 186 */
1aa1d830 187 accel_cpu_common_unrealize(cpu);
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PB
188}
189
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190/*
191 * This can't go in hw/core/cpu.c because that file is compiled only
192 * once for both user-mode and system builds.
193 */
995b87de 194static Property cpu_common_props[] = {
6e8dcacd
RH
195#ifdef CONFIG_USER_ONLY
196 /*
197 * Create a property for the user-only object, so users can
198 * adjust prctl(PR_SET_UNALIGN) from the command-line.
199 * Has no effect if the target does not support the feature.
200 */
201 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
202 prctl_unalign_sigbus, false),
203#else
995b87de 204 /*
54b99122 205 * Create a memory property for system CPU object, so users can
6e8dcacd 206 * wire up its memory. The default if no link is set up is to use
995b87de
RH
207 * the system address space.
208 */
209 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
210 MemoryRegion *),
211#endif
995b87de
RH
212 DEFINE_PROP_END_OF_LIST(),
213};
214
0c3c25fc
PM
215static bool cpu_get_start_powered_off(Object *obj, Error **errp)
216{
217 CPUState *cpu = CPU(obj);
218 return cpu->start_powered_off;
219}
220
221static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
222{
223 CPUState *cpu = CPU(obj);
224 cpu->start_powered_off = value;
225}
226
995b87de
RH
227void cpu_class_init_props(DeviceClass *dc)
228{
0c3c25fc
PM
229 ObjectClass *oc = OBJECT_CLASS(dc);
230
995b87de 231 device_class_set_props(dc, cpu_common_props);
0c3c25fc
PM
232 /*
233 * We can't use DEFINE_PROP_BOOL in the Property array for this
234 * property, because we want this to be settable after realize.
235 */
236 object_class_property_add_bool(oc, "start-powered-off",
237 cpu_get_start_powered_off,
238 cpu_set_start_powered_off);
995b87de
RH
239}
240
d9f24bf5
PB
241void cpu_exec_initfn(CPUState *cpu)
242{
243 cpu->as = NULL;
244 cpu->num_ases = 0;
245
246#ifndef CONFIG_USER_ONLY
247 cpu->thread_id = qemu_get_thread_id();
248 cpu->memory = get_system_memory();
249 object_ref(OBJECT(cpu->memory));
250#endif
251}
252
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PB
253const char *parse_cpu_option(const char *cpu_option)
254{
255 ObjectClass *oc;
256 CPUClass *cc;
257 gchar **model_pieces;
258 const char *cpu_type;
259
260 model_pieces = g_strsplit(cpu_option, ",", 2);
261 if (!model_pieces[0]) {
262 error_report("-cpu option cannot be empty");
263 exit(1);
264 }
265
266 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
267 if (oc == NULL) {
268 error_report("unable to find CPU model '%s'", model_pieces[0]);
269 g_strfreev(model_pieces);
270 exit(EXIT_FAILURE);
271 }
272
273 cpu_type = object_class_get_name(oc);
274 cc = CPU_CLASS(oc);
275 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
276 g_strfreev(model_pieces);
277 return cpu_type;
278}
279
c138c3b8 280void list_cpus(void)
377bf6f3
PMD
281{
282 /* XXX: implement xxx_cpu_list for targets that still miss it */
283#if defined(cpu_list)
284 cpu_list();
285#endif
286}
287
d9f24bf5 288#if defined(CONFIG_USER_ONLY)
c814c892 289void tb_invalidate_phys_addr(hwaddr addr)
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PB
290{
291 mmap_lock();
d6d1fd29 292 tb_invalidate_phys_page(addr);
d9f24bf5
PB
293 mmap_unlock();
294}
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PB
295#else
296void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
297{
298 ram_addr_t ram_addr;
299 MemoryRegion *mr;
300 hwaddr l = 1;
301
302 if (!tcg_enabled()) {
303 return;
304 }
305
306 RCU_READ_LOCK_GUARD();
307 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
308 if (!(memory_region_is_ram(mr)
309 || memory_region_is_romd(mr))) {
310 return;
311 }
312 ram_addr = memory_region_get_ram_addr(mr) + addr;
d6d1fd29 313 tb_invalidate_phys_page(ram_addr);
d9f24bf5 314}
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PB
315#endif
316
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317/* enable or disable single step mode. EXCP_DEBUG is returned by the
318 CPU loop after each instruction */
319void cpu_single_step(CPUState *cpu, int enabled)
320{
321 if (cpu->singlestep_enabled != enabled) {
322 cpu->singlestep_enabled = enabled;
412ae126
MY
323
324#if !defined(CONFIG_USER_ONLY)
325 const AccelOpsClass *ops = cpus_get_accel();
326 if (ops->update_guest_debug) {
327 ops->update_guest_debug(cpu);
d9f24bf5 328 }
412ae126
MY
329#endif
330
ad1a706f 331 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
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PB
332 }
333}
334
335void cpu_abort(CPUState *cpu, const char *fmt, ...)
336{
337 va_list ap;
338 va_list ap2;
339
340 va_start(ap, fmt);
341 va_copy(ap2, ap);
342 fprintf(stderr, "qemu: fatal: ");
343 vfprintf(stderr, fmt, ap);
344 fprintf(stderr, "\n");
345 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
346 if (qemu_log_separate()) {
c60f599b 347 FILE *logfile = qemu_log_trylock();
78b54858
RH
348 if (logfile) {
349 fprintf(logfile, "qemu: fatal: ");
350 vfprintf(logfile, fmt, ap2);
351 fprintf(logfile, "\n");
352 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
78b54858
RH
353 qemu_log_unlock(logfile);
354 }
d9f24bf5
PB
355 }
356 va_end(ap2);
357 va_end(ap);
358 replay_finish();
359#if defined(CONFIG_USER_ONLY)
360 {
361 struct sigaction act;
362 sigfillset(&act.sa_mask);
363 act.sa_handler = SIG_DFL;
364 act.sa_flags = 0;
365 sigaction(SIGABRT, &act, NULL);
366 }
367#endif
368 abort();
369}
370
371/* physical memory access (slow version, mainly for debug) */
372#if defined(CONFIG_USER_ONLY)
73842ef0
PMD
373int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
374 void *ptr, size_t len, bool is_write)
d9f24bf5
PB
375{
376 int flags;
73842ef0 377 vaddr l, page;
d9f24bf5
PB
378 void * p;
379 uint8_t *buf = ptr;
380
381 while (len > 0) {
382 page = addr & TARGET_PAGE_MASK;
383 l = (page + TARGET_PAGE_SIZE) - addr;
384 if (l > len)
385 l = len;
386 flags = page_get_flags(page);
387 if (!(flags & PAGE_VALID))
388 return -1;
389 if (is_write) {
390 if (!(flags & PAGE_WRITE))
391 return -1;
392 /* XXX: this code should not depend on lock_user */
393 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
394 return -1;
395 memcpy(p, buf, l);
396 unlock_user(p, addr, l);
397 } else {
398 if (!(flags & PAGE_READ))
399 return -1;
400 /* XXX: this code should not depend on lock_user */
401 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
402 return -1;
403 memcpy(buf, p, l);
404 unlock_user(p, addr, 0);
405 }
406 len -= l;
407 buf += l;
408 addr += l;
409 }
410 return 0;
411}
412#endif
413
414bool target_words_bigendian(void)
415{
ded625e7 416 return TARGET_BIG_ENDIAN;
d9f24bf5
PB
417}
418
1077f50b
TH
419const char *target_name(void)
420{
421 return TARGET_NAME;
422}
423
d9f24bf5
PB
424void page_size_init(void)
425{
426 /* NOTE: we can always suppose that qemu_host_page_size >=
427 TARGET_PAGE_SIZE */
428 if (qemu_host_page_size == 0) {
8e3b0cbb 429 qemu_host_page_size = qemu_real_host_page_size();
d9f24bf5
PB
430 }
431 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
432 qemu_host_page_size = TARGET_PAGE_SIZE;
433 }
434 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
435}