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CommitLineData
d9f24bf5
PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
d9f24bf5
PB
21#include "qapi/error.h"
22
23#include "exec/target_page.h"
24#include "hw/qdev-core.h"
25#include "hw/qdev-properties.h"
26#include "qemu/error-report.h"
dfa47531 27#include "qemu/qemu-print.h"
d9f24bf5
PB
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
8b80bd28 32#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5 33#include "exec/address-spaces.h"
5f8d88bd 34#include "exec/memory.h"
d9f24bf5 35#endif
412ae126 36#include "sysemu/cpus.h"
d9f24bf5 37#include "sysemu/tcg.h"
42508261 38#include "exec/tswap.h"
5b5968c4 39#include "exec/replay-core.h"
377bf6f3 40#include "exec/cpu-common.h"
3b04508c 41#include "exec/exec-all.h"
548c9609 42#include "exec/tb-flush.h"
3b9bd3f4 43#include "exec/translate-all.h"
d9f24bf5 44#include "exec/log.h"
30565f10 45#include "hw/core/accel-cpu.h"
ad1a706f 46#include "trace/trace-root.h"
3b04508c 47#include "qemu/accel.h"
d9f24bf5 48
d9f24bf5
PB
49#ifndef CONFIG_USER_ONLY
50static int cpu_common_post_load(void *opaque, int version_id)
51{
52 CPUState *cpu = opaque;
53
54 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
55 version_id is increased. */
56 cpu->interrupt_request &= ~0x01;
57 tlb_flush(cpu);
58
59 /* loadvm has just updated the content of RAM, bypassing the
60 * usual mechanisms that ensure we flush TBs for writes to
61 * memory we've translated code from. So we must flush all TBs,
62 * which will now be stale.
63 */
64 tb_flush(cpu);
65
66 return 0;
67}
68
69static int cpu_common_pre_load(void *opaque)
70{
71 CPUState *cpu = opaque;
72
73 cpu->exception_index = -1;
74
75 return 0;
76}
77
78static bool cpu_common_exception_index_needed(void *opaque)
79{
80 CPUState *cpu = opaque;
81
82 return tcg_enabled() && cpu->exception_index != -1;
83}
84
85static const VMStateDescription vmstate_cpu_common_exception_index = {
86 .name = "cpu_common/exception_index",
87 .version_id = 1,
88 .minimum_version_id = 1,
89 .needed = cpu_common_exception_index_needed,
ee1381ce 90 .fields = (const VMStateField[]) {
d9f24bf5
PB
91 VMSTATE_INT32(exception_index, CPUState),
92 VMSTATE_END_OF_LIST()
93 }
94};
95
96static bool cpu_common_crash_occurred_needed(void *opaque)
97{
98 CPUState *cpu = opaque;
99
100 return cpu->crash_occurred;
101}
102
103static const VMStateDescription vmstate_cpu_common_crash_occurred = {
104 .name = "cpu_common/crash_occurred",
105 .version_id = 1,
106 .minimum_version_id = 1,
107 .needed = cpu_common_crash_occurred_needed,
ee1381ce 108 .fields = (const VMStateField[]) {
d9f24bf5
PB
109 VMSTATE_BOOL(crash_occurred, CPUState),
110 VMSTATE_END_OF_LIST()
111 }
112};
113
114const VMStateDescription vmstate_cpu_common = {
115 .name = "cpu_common",
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .pre_load = cpu_common_pre_load,
119 .post_load = cpu_common_post_load,
ee1381ce 120 .fields = (const VMStateField[]) {
d9f24bf5
PB
121 VMSTATE_UINT32(halted, CPUState),
122 VMSTATE_UINT32(interrupt_request, CPUState),
123 VMSTATE_END_OF_LIST()
124 },
ee1381ce 125 .subsections = (const VMStateDescription * const []) {
d9f24bf5
PB
126 &vmstate_cpu_common_exception_index,
127 &vmstate_cpu_common_crash_occurred,
128 NULL
129 }
130};
131#endif
132
79a99091 133bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 134{
6fbdff87
AB
135 /* cache the cpu class for the hotpath */
136 cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5 137
bd684b2f 138 if (!accel_cpu_common_realize(cpu, errp)) {
79a99091 139 return false;
9ea057dc 140 }
4e4fa6c1 141
4e4fa6c1
RH
142 /* Wait until cpu initialization complete before exposing cpu. */
143 cpu_list_add(cpu);
144
7df5e3d6 145#ifdef CONFIG_USER_ONLY
4336073b
PMD
146 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
147 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6
CF
148#else
149 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
150 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
151 }
6fbdff87
AB
152 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
153 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6
CF
154 }
155#endif /* CONFIG_USER_ONLY */
79a99091
PMD
156
157 return true;
7df5e3d6
CF
158}
159
160void cpu_exec_unrealizefn(CPUState *cpu)
161{
feece4d0 162#ifndef CONFIG_USER_ONLY
7df5e3d6 163 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 164
feece4d0
PMD
165 if (cc->sysemu_ops->legacy_vmsd != NULL) {
166 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5
PB
167 }
168 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
169 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
170 }
d9f24bf5 171#endif
4731f89b 172
7df5e3d6 173 cpu_list_remove(cpu);
4731f89b
EC
174 /*
175 * Now that the vCPU has been removed from the RCU list, we can call
1aa1d830 176 * accel_cpu_common_unrealize, which may free fields using call_rcu.
4731f89b 177 */
1aa1d830 178 accel_cpu_common_unrealize(cpu);
d9f24bf5
PB
179}
180
6e8dcacd
RH
181/*
182 * This can't go in hw/core/cpu.c because that file is compiled only
183 * once for both user-mode and system builds.
184 */
995b87de 185static Property cpu_common_props[] = {
6e8dcacd
RH
186#ifdef CONFIG_USER_ONLY
187 /*
188 * Create a property for the user-only object, so users can
189 * adjust prctl(PR_SET_UNALIGN) from the command-line.
190 * Has no effect if the target does not support the feature.
191 */
192 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
193 prctl_unalign_sigbus, false),
194#else
995b87de 195 /*
54b99122 196 * Create a memory property for system CPU object, so users can
6e8dcacd 197 * wire up its memory. The default if no link is set up is to use
995b87de
RH
198 * the system address space.
199 */
200 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
201 MemoryRegion *),
202#endif
995b87de
RH
203 DEFINE_PROP_END_OF_LIST(),
204};
205
0f9237f4 206#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
207static bool cpu_get_start_powered_off(Object *obj, Error **errp)
208{
209 CPUState *cpu = CPU(obj);
210 return cpu->start_powered_off;
211}
212
213static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
214{
215 CPUState *cpu = CPU(obj);
216 cpu->start_powered_off = value;
217}
0f9237f4 218#endif
0c3c25fc 219
995b87de
RH
220void cpu_class_init_props(DeviceClass *dc)
221{
0f9237f4 222#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
223 ObjectClass *oc = OBJECT_CLASS(dc);
224
0c3c25fc
PM
225 /*
226 * We can't use DEFINE_PROP_BOOL in the Property array for this
227 * property, because we want this to be settable after realize.
228 */
229 object_class_property_add_bool(oc, "start-powered-off",
230 cpu_get_start_powered_off,
231 cpu_set_start_powered_off);
0f9237f4
PMD
232#endif
233
234 device_class_set_props(dc, cpu_common_props);
995b87de
RH
235}
236
d9f24bf5
PB
237void cpu_exec_initfn(CPUState *cpu)
238{
239 cpu->as = NULL;
240 cpu->num_ases = 0;
241
242#ifndef CONFIG_USER_ONLY
243 cpu->thread_id = qemu_get_thread_id();
244 cpu->memory = get_system_memory();
245 object_ref(OBJECT(cpu->memory));
246#endif
247}
248
445946f4
GS
249char *cpu_model_from_type(const char *typename)
250{
251 const char *suffix = "-" CPU_RESOLVING_TYPE;
252
253 if (!object_class_by_name(typename)) {
254 return NULL;
255 }
256
257 if (g_str_has_suffix(typename, suffix)) {
258 return g_strndup(typename, strlen(typename) - strlen(suffix));
259 }
260
261 return g_strdup(typename);
262}
263
d9f24bf5
PB
264const char *parse_cpu_option(const char *cpu_option)
265{
266 ObjectClass *oc;
267 CPUClass *cc;
268 gchar **model_pieces;
269 const char *cpu_type;
270
271 model_pieces = g_strsplit(cpu_option, ",", 2);
272 if (!model_pieces[0]) {
273 error_report("-cpu option cannot be empty");
274 exit(1);
275 }
276
277 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
278 if (oc == NULL) {
279 error_report("unable to find CPU model '%s'", model_pieces[0]);
280 g_strfreev(model_pieces);
281 exit(EXIT_FAILURE);
282 }
283
284 cpu_type = object_class_get_name(oc);
285 cc = CPU_CLASS(oc);
286 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
287 g_strfreev(model_pieces);
288 return cpu_type;
289}
290
dfa47531
GS
291#ifndef cpu_list
292static void cpu_list_entry(gpointer data, gpointer user_data)
293{
294 CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data));
295 const char *typename = object_class_get_name(OBJECT_CLASS(data));
296 g_autofree char *model = cpu_model_from_type(typename);
297
298 if (cc->deprecation_note) {
299 qemu_printf(" %s (deprecated)\n", model);
300 } else {
301 qemu_printf(" %s\n", model);
302 }
303}
304
305static void cpu_list(void)
306{
307 GSList *list;
308
309 list = object_class_get_list_sorted(TYPE_CPU, false);
310 qemu_printf("Available CPUs:\n");
311 g_slist_foreach(list, cpu_list_entry, NULL);
312 g_slist_free(list);
313}
314#endif
315
c138c3b8 316void list_cpus(void)
377bf6f3 317{
377bf6f3 318 cpu_list();
377bf6f3
PMD
319}
320
d9f24bf5
PB
321/* enable or disable single step mode. EXCP_DEBUG is returned by the
322 CPU loop after each instruction */
323void cpu_single_step(CPUState *cpu, int enabled)
324{
325 if (cpu->singlestep_enabled != enabled) {
326 cpu->singlestep_enabled = enabled;
412ae126
MY
327
328#if !defined(CONFIG_USER_ONLY)
329 const AccelOpsClass *ops = cpus_get_accel();
330 if (ops->update_guest_debug) {
331 ops->update_guest_debug(cpu);
d9f24bf5 332 }
412ae126
MY
333#endif
334
ad1a706f 335 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5
PB
336 }
337}
338
339void cpu_abort(CPUState *cpu, const char *fmt, ...)
340{
341 va_list ap;
342 va_list ap2;
343
344 va_start(ap, fmt);
345 va_copy(ap2, ap);
346 fprintf(stderr, "qemu: fatal: ");
347 vfprintf(stderr, fmt, ap);
348 fprintf(stderr, "\n");
349 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
350 if (qemu_log_separate()) {
c60f599b 351 FILE *logfile = qemu_log_trylock();
78b54858
RH
352 if (logfile) {
353 fprintf(logfile, "qemu: fatal: ");
354 vfprintf(logfile, fmt, ap2);
355 fprintf(logfile, "\n");
356 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
78b54858
RH
357 qemu_log_unlock(logfile);
358 }
d9f24bf5
PB
359 }
360 va_end(ap2);
361 va_end(ap);
362 replay_finish();
363#if defined(CONFIG_USER_ONLY)
364 {
365 struct sigaction act;
366 sigfillset(&act.sa_mask);
367 act.sa_handler = SIG_DFL;
368 act.sa_flags = 0;
369 sigaction(SIGABRT, &act, NULL);
370 }
371#endif
372 abort();
373}
374
375/* physical memory access (slow version, mainly for debug) */
376#if defined(CONFIG_USER_ONLY)
73842ef0
PMD
377int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
378 void *ptr, size_t len, bool is_write)
d9f24bf5
PB
379{
380 int flags;
73842ef0 381 vaddr l, page;
d9f24bf5
PB
382 void * p;
383 uint8_t *buf = ptr;
87ab2704
IL
384 ssize_t written;
385 int ret = -1;
386 int fd = -1;
d9f24bf5
PB
387
388 while (len > 0) {
389 page = addr & TARGET_PAGE_MASK;
390 l = (page + TARGET_PAGE_SIZE) - addr;
391 if (l > len)
392 l = len;
393 flags = page_get_flags(page);
87ab2704
IL
394 if (!(flags & PAGE_VALID)) {
395 goto out_close;
396 }
d9f24bf5 397 if (is_write) {
87ab2704
IL
398 if (flags & PAGE_WRITE) {
399 /* XXX: this code should not depend on lock_user */
400 p = lock_user(VERIFY_WRITE, addr, l, 0);
401 if (!p) {
402 goto out_close;
403 }
404 memcpy(p, buf, l);
405 unlock_user(p, addr, l);
406 } else {
407 /* Bypass the host page protection using ptrace. */
408 if (fd == -1) {
409 fd = open("/proc/self/mem", O_WRONLY);
410 if (fd == -1) {
411 goto out;
412 }
413 }
414 /*
415 * If there is a TranslationBlock and we weren't bypassing the
416 * host page protection, the memcpy() above would SEGV,
417 * ultimately leading to page_unprotect(). So invalidate the
418 * translations manually. Both invalidation and pwrite() must
419 * be under mmap_lock() in order to prevent the creation of
420 * another TranslationBlock in between.
421 */
422 mmap_lock();
423 tb_invalidate_phys_range(addr, addr + l - 1);
424 written = pwrite(fd, buf, l,
425 (off_t)(uintptr_t)g2h_untagged(addr));
426 mmap_unlock();
427 if (written != l) {
428 goto out_close;
429 }
430 }
431 } else if (flags & PAGE_READ) {
d9f24bf5 432 /* XXX: this code should not depend on lock_user */
87ab2704
IL
433 p = lock_user(VERIFY_READ, addr, l, 1);
434 if (!p) {
435 goto out_close;
436 }
d9f24bf5
PB
437 memcpy(buf, p, l);
438 unlock_user(p, addr, 0);
87ab2704
IL
439 } else {
440 /* Bypass the host page protection using ptrace. */
441 if (fd == -1) {
442 fd = open("/proc/self/mem", O_RDONLY);
443 if (fd == -1) {
444 goto out;
445 }
446 }
447 if (pread(fd, buf, l,
448 (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
449 goto out_close;
450 }
d9f24bf5
PB
451 }
452 len -= l;
453 buf += l;
454 addr += l;
455 }
87ab2704
IL
456 ret = 0;
457out_close:
458 if (fd != -1) {
459 close(fd);
460 }
461out:
462 return ret;
d9f24bf5
PB
463}
464#endif
465
466bool target_words_bigendian(void)
467{
ded625e7 468 return TARGET_BIG_ENDIAN;
d9f24bf5
PB
469}
470
1077f50b
TH
471const char *target_name(void)
472{
473 return TARGET_NAME;
474}