]> git.proxmox.com Git - mirror_qemu.git/blame - cpu.c
target/riscv: remove CONFIG_TCG, as it is always TCG
[mirror_qemu.git] / cpu.c
CommitLineData
d9f24bf5
PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qapi/error.h"
23
24#include "exec/target_page.h"
25#include "hw/qdev-core.h"
26#include "hw/qdev-properties.h"
27#include "qemu/error-report.h"
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
32#include "exec/address-spaces.h"
33#endif
34#include "sysemu/tcg.h"
35#include "sysemu/kvm.h"
36#include "sysemu/replay.h"
3b9bd3f4 37#include "exec/translate-all.h"
d9f24bf5
PB
38#include "exec/log.h"
39
40uintptr_t qemu_host_page_size;
41intptr_t qemu_host_page_mask;
42
43#ifndef CONFIG_USER_ONLY
44static int cpu_common_post_load(void *opaque, int version_id)
45{
46 CPUState *cpu = opaque;
47
48 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
49 version_id is increased. */
50 cpu->interrupt_request &= ~0x01;
51 tlb_flush(cpu);
52
53 /* loadvm has just updated the content of RAM, bypassing the
54 * usual mechanisms that ensure we flush TBs for writes to
55 * memory we've translated code from. So we must flush all TBs,
56 * which will now be stale.
57 */
58 tb_flush(cpu);
59
60 return 0;
61}
62
63static int cpu_common_pre_load(void *opaque)
64{
65 CPUState *cpu = opaque;
66
67 cpu->exception_index = -1;
68
69 return 0;
70}
71
72static bool cpu_common_exception_index_needed(void *opaque)
73{
74 CPUState *cpu = opaque;
75
76 return tcg_enabled() && cpu->exception_index != -1;
77}
78
79static const VMStateDescription vmstate_cpu_common_exception_index = {
80 .name = "cpu_common/exception_index",
81 .version_id = 1,
82 .minimum_version_id = 1,
83 .needed = cpu_common_exception_index_needed,
84 .fields = (VMStateField[]) {
85 VMSTATE_INT32(exception_index, CPUState),
86 VMSTATE_END_OF_LIST()
87 }
88};
89
90static bool cpu_common_crash_occurred_needed(void *opaque)
91{
92 CPUState *cpu = opaque;
93
94 return cpu->crash_occurred;
95}
96
97static const VMStateDescription vmstate_cpu_common_crash_occurred = {
98 .name = "cpu_common/crash_occurred",
99 .version_id = 1,
100 .minimum_version_id = 1,
101 .needed = cpu_common_crash_occurred_needed,
102 .fields = (VMStateField[]) {
103 VMSTATE_BOOL(crash_occurred, CPUState),
104 VMSTATE_END_OF_LIST()
105 }
106};
107
108const VMStateDescription vmstate_cpu_common = {
109 .name = "cpu_common",
110 .version_id = 1,
111 .minimum_version_id = 1,
112 .pre_load = cpu_common_pre_load,
113 .post_load = cpu_common_post_load,
114 .fields = (VMStateField[]) {
115 VMSTATE_UINT32(halted, CPUState),
116 VMSTATE_UINT32(interrupt_request, CPUState),
117 VMSTATE_END_OF_LIST()
118 },
119 .subsections = (const VMStateDescription*[]) {
120 &vmstate_cpu_common_exception_index,
121 &vmstate_cpu_common_crash_occurred,
122 NULL
123 }
124};
125#endif
126
127void cpu_exec_unrealizefn(CPUState *cpu)
128{
129 CPUClass *cc = CPU_GET_CLASS(cpu);
130
131 tlb_destroy(cpu);
132 cpu_list_remove(cpu);
133
134#ifdef CONFIG_USER_ONLY
135 assert(cc->vmsd == NULL);
136#else
137 if (cc->vmsd != NULL) {
138 vmstate_unregister(NULL, cc->vmsd, cpu);
139 }
140 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
141 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
142 }
143 tcg_iommu_free_notifier_list(cpu);
144#endif
145}
146
d9f24bf5
PB
147void cpu_exec_initfn(CPUState *cpu)
148{
149 cpu->as = NULL;
150 cpu->num_ases = 0;
151
152#ifndef CONFIG_USER_ONLY
153 cpu->thread_id = qemu_get_thread_id();
154 cpu->memory = get_system_memory();
155 object_ref(OBJECT(cpu->memory));
156#endif
157}
158
159void cpu_exec_realizefn(CPUState *cpu, Error **errp)
160{
161 CPUClass *cc = CPU_GET_CLASS(cpu);
e9e51b71 162#ifdef CONFIG_TCG
d9f24bf5 163 static bool tcg_target_initialized;
e9e51b71 164#endif /* CONFIG_TCG */
d9f24bf5
PB
165
166 cpu_list_add(cpu);
167
e9e51b71 168#ifdef CONFIG_TCG
d9f24bf5
PB
169 if (tcg_enabled() && !tcg_target_initialized) {
170 tcg_target_initialized = true;
e9e51b71 171 cc->tcg_ops.initialize();
d9f24bf5 172 }
e9e51b71 173#endif /* CONFIG_TCG */
d9f24bf5
PB
174 tlb_init(cpu);
175
176 qemu_plugin_vcpu_init_hook(cpu);
177
178#ifdef CONFIG_USER_ONLY
179 assert(cc->vmsd == NULL);
180#else /* !CONFIG_USER_ONLY */
181 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
182 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
183 }
184 if (cc->vmsd != NULL) {
185 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
186 }
187
188 tcg_iommu_init_notifier_list(cpu);
189#endif
190}
191
192const char *parse_cpu_option(const char *cpu_option)
193{
194 ObjectClass *oc;
195 CPUClass *cc;
196 gchar **model_pieces;
197 const char *cpu_type;
198
199 model_pieces = g_strsplit(cpu_option, ",", 2);
200 if (!model_pieces[0]) {
201 error_report("-cpu option cannot be empty");
202 exit(1);
203 }
204
205 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
206 if (oc == NULL) {
207 error_report("unable to find CPU model '%s'", model_pieces[0]);
208 g_strfreev(model_pieces);
209 exit(EXIT_FAILURE);
210 }
211
212 cpu_type = object_class_get_name(oc);
213 cc = CPU_CLASS(oc);
214 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
215 g_strfreev(model_pieces);
216 return cpu_type;
217}
218
219#if defined(CONFIG_USER_ONLY)
220void tb_invalidate_phys_addr(target_ulong addr)
221{
222 mmap_lock();
223 tb_invalidate_phys_page_range(addr, addr + 1);
224 mmap_unlock();
225}
226
227static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
228{
229 tb_invalidate_phys_addr(pc);
230}
231#else
232void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
233{
234 ram_addr_t ram_addr;
235 MemoryRegion *mr;
236 hwaddr l = 1;
237
238 if (!tcg_enabled()) {
239 return;
240 }
241
242 RCU_READ_LOCK_GUARD();
243 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
244 if (!(memory_region_is_ram(mr)
245 || memory_region_is_romd(mr))) {
246 return;
247 }
248 ram_addr = memory_region_get_ram_addr(mr) + addr;
249 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
250}
251
252static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
253{
254 /*
255 * There may not be a virtual to physical translation for the pc
256 * right now, but there may exist cached TB for this pc.
257 * Flush the whole TB cache to force re-translation of such TBs.
258 * This is heavyweight, but we're debugging anyway.
259 */
260 tb_flush(cpu);
261}
262#endif
263
264/* Add a breakpoint. */
265int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
266 CPUBreakpoint **breakpoint)
267{
268 CPUBreakpoint *bp;
269
270 bp = g_malloc(sizeof(*bp));
271
272 bp->pc = pc;
273 bp->flags = flags;
274
275 /* keep all GDB-injected breakpoints in front */
276 if (flags & BP_GDB) {
277 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
278 } else {
279 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
280 }
281
282 breakpoint_invalidate(cpu, pc);
283
284 if (breakpoint) {
285 *breakpoint = bp;
286 }
287 return 0;
288}
289
290/* Remove a specific breakpoint. */
291int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
292{
293 CPUBreakpoint *bp;
294
295 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
296 if (bp->pc == pc && bp->flags == flags) {
297 cpu_breakpoint_remove_by_ref(cpu, bp);
298 return 0;
299 }
300 }
301 return -ENOENT;
302}
303
304/* Remove a specific breakpoint by reference. */
305void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
306{
307 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
308
309 breakpoint_invalidate(cpu, breakpoint->pc);
310
311 g_free(breakpoint);
312}
313
314/* Remove all matching breakpoints. */
315void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
316{
317 CPUBreakpoint *bp, *next;
318
319 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
320 if (bp->flags & mask) {
321 cpu_breakpoint_remove_by_ref(cpu, bp);
322 }
323 }
324}
325
326/* enable or disable single step mode. EXCP_DEBUG is returned by the
327 CPU loop after each instruction */
328void cpu_single_step(CPUState *cpu, int enabled)
329{
330 if (cpu->singlestep_enabled != enabled) {
331 cpu->singlestep_enabled = enabled;
332 if (kvm_enabled()) {
333 kvm_update_guest_debug(cpu, 0);
334 } else {
335 /* must flush all the translated code to avoid inconsistencies */
336 /* XXX: only flush what is necessary */
337 tb_flush(cpu);
338 }
339 }
340}
341
342void cpu_abort(CPUState *cpu, const char *fmt, ...)
343{
344 va_list ap;
345 va_list ap2;
346
347 va_start(ap, fmt);
348 va_copy(ap2, ap);
349 fprintf(stderr, "qemu: fatal: ");
350 vfprintf(stderr, fmt, ap);
351 fprintf(stderr, "\n");
352 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
353 if (qemu_log_separate()) {
354 FILE *logfile = qemu_log_lock();
355 qemu_log("qemu: fatal: ");
356 qemu_log_vprintf(fmt, ap2);
357 qemu_log("\n");
358 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
359 qemu_log_flush();
360 qemu_log_unlock(logfile);
361 qemu_log_close();
362 }
363 va_end(ap2);
364 va_end(ap);
365 replay_finish();
366#if defined(CONFIG_USER_ONLY)
367 {
368 struct sigaction act;
369 sigfillset(&act.sa_mask);
370 act.sa_handler = SIG_DFL;
371 act.sa_flags = 0;
372 sigaction(SIGABRT, &act, NULL);
373 }
374#endif
375 abort();
376}
377
378/* physical memory access (slow version, mainly for debug) */
379#if defined(CONFIG_USER_ONLY)
380int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
381 void *ptr, target_ulong len, bool is_write)
382{
383 int flags;
384 target_ulong l, page;
385 void * p;
386 uint8_t *buf = ptr;
387
388 while (len > 0) {
389 page = addr & TARGET_PAGE_MASK;
390 l = (page + TARGET_PAGE_SIZE) - addr;
391 if (l > len)
392 l = len;
393 flags = page_get_flags(page);
394 if (!(flags & PAGE_VALID))
395 return -1;
396 if (is_write) {
397 if (!(flags & PAGE_WRITE))
398 return -1;
399 /* XXX: this code should not depend on lock_user */
400 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
401 return -1;
402 memcpy(p, buf, l);
403 unlock_user(p, addr, l);
404 } else {
405 if (!(flags & PAGE_READ))
406 return -1;
407 /* XXX: this code should not depend on lock_user */
408 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
409 return -1;
410 memcpy(buf, p, l);
411 unlock_user(p, addr, 0);
412 }
413 len -= l;
414 buf += l;
415 addr += l;
416 }
417 return 0;
418}
419#endif
420
421bool target_words_bigendian(void)
422{
423#if defined(TARGET_WORDS_BIGENDIAN)
424 return true;
425#else
426 return false;
427#endif
428}
429
430void page_size_init(void)
431{
432 /* NOTE: we can always suppose that qemu_host_page_size >=
433 TARGET_PAGE_SIZE */
434 if (qemu_host_page_size == 0) {
435 qemu_host_page_size = qemu_real_host_page_size;
436 }
437 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
438 qemu_host_page_size = TARGET_PAGE_SIZE;
439 }
440 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
441}