[mirror_qemu.git] / cpu.c

/*
 * Target-specific parts of the CPU object
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qapi/error.h"

#include "exec/target_page.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "migration/vmstate.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/translate-all.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"

uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;

#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
    CPUState *cpu = opaque;

    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
       version_id is increased. */
    cpu->interrupt_request &= ~0x01;
    tlb_flush(cpu);

    /* loadvm has just updated the content of RAM, bypassing the
     * usual mechanisms that ensure we flush TBs for writes to
     * memory we've translated code from. So we must flush all TBs,
     * which will now be stale.
     */
    tb_flush(cpu);

    return 0;
}

static int cpu_common_pre_load(void *opaque)
{
    CPUState *cpu = opaque;

    cpu->exception_index = -1;

    return 0;
}

static bool cpu_common_exception_index_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return tcg_enabled() && cpu->exception_index != -1;
}

static const VMStateDescription vmstate_cpu_common_exception_index = {
    .name = "cpu_common/exception_index",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_exception_index_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(exception_index, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

static bool cpu_common_crash_occurred_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return cpu->crash_occurred;
}

static const VMStateDescription vmstate_cpu_common_crash_occurred = {
    .name = "cpu_common/crash_occurred",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_crash_occurred_needed,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(crash_occurred, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_cpu_common = {
    .name = "cpu_common",
    .version_id = 1,
    .minimum_version_id = 1,
    .pre_load = cpu_common_pre_load,
    .post_load = cpu_common_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(halted, CPUState),
        VMSTATE_UINT32(interrupt_request, CPUState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_cpu_common_exception_index,
        &vmstate_cpu_common_crash_occurred,
        NULL
    }
};
#endif

void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
#ifndef CONFIG_USER_ONLY
    CPUClass *cc = CPU_GET_CLASS(cpu);
#endif

    cpu_list_add(cpu);
    if (!accel_cpu_realizefn(cpu, errp)) {
        return;
    }
    /* NB: errp parameter is unused currently */
    if (tcg_enabled()) {
        tcg_exec_realizefn(cpu, errp);
    }

#ifdef CONFIG_USER_ONLY
    assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
           qdev_get_vmsd(DEVICE(cpu))->unmigratable);
#else
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
    }
    if (cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
    }
#endif /* CONFIG_USER_ONLY */
}

void cpu_exec_unrealizefn(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
    CPUClass *cc = CPU_GET_CLASS(cpu);

    if (cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
    }
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
    }
#endif
    if (tcg_enabled()) {
        tcg_exec_unrealizefn(cpu);
    }

    cpu_list_remove(cpu);
}

/*
 * This can't go in hw/core/cpu.c because that file is compiled only
 * once for both user-mode and system builds.
 */
static Property cpu_common_props[] = {
#ifdef CONFIG_USER_ONLY
    /*
     * Create a property for the user-only object, so users can
     * adjust prctl(PR_SET_UNALIGN) from the command-line.
     * Has no effect if the target does not support the feature.
     */
    DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
                     prctl_unalign_sigbus, false),
#else
    /*
     * Create a memory property for softmmu CPU object, so users can
     * wire up its memory.  The default if no link is set up is to use
     * the system address space.
     */
    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
#endif
    DEFINE_PROP_END_OF_LIST(),
};

static bool cpu_get_start_powered_off(Object *obj, Error **errp)
{
    CPUState *cpu = CPU(obj);
    return cpu->start_powered_off;
}

static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
{
    CPUState *cpu = CPU(obj);
    cpu->start_powered_off = value;
}

void cpu_class_init_props(DeviceClass *dc)
{
    ObjectClass *oc = OBJECT_CLASS(dc);

    device_class_set_props(dc, cpu_common_props);
    /*
     * We can't use DEFINE_PROP_BOOL in the Property array for this
     * property, because we want this to be settable after realize.
     */
    object_class_property_add_bool(oc, "start-powered-off",
                                   cpu_get_start_powered_off,
                                   cpu_set_start_powered_off);
}

void cpu_exec_initfn(CPUState *cpu)
{
    cpu->as = NULL;
    cpu->num_ases = 0;

#ifndef CONFIG_USER_ONLY
    cpu->thread_id = qemu_get_thread_id();
    cpu->memory = get_system_memory();
    object_ref(OBJECT(cpu->memory));
#endif
}

const char *parse_cpu_option(const char *cpu_option)
{
    ObjectClass *oc;
    CPUClass *cc;
    gchar **model_pieces;
    const char *cpu_type;

    model_pieces = g_strsplit(cpu_option, ",", 2);
    if (!model_pieces[0]) {
        error_report("-cpu option cannot be empty");
        exit(1);
    }

    oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
    if (oc == NULL) {
        error_report("unable to find CPU model '%s'", model_pieces[0]);
        g_strfreev(model_pieces);
        exit(EXIT_FAILURE);
    }

    cpu_type = object_class_get_name(oc);
    cc = CPU_CLASS(oc);
    cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
    g_strfreev(model_pieces);
    return cpu_type;
}

void list_cpus(const char *optarg)
{
    /* XXX: implement xxx_cpu_list for targets that still miss it */
#if defined(cpu_list)
    cpu_list();
#endif
}

#if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(target_ulong addr)
{
    mmap_lock();
    tb_invalidate_phys_page_range(addr, addr + 1);
    mmap_unlock();
}
#else
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
{
    ram_addr_t ram_addr;
    MemoryRegion *mr;
    hwaddr l = 1;

    if (!tcg_enabled()) {
        return;
    }

    RCU_READ_LOCK_GUARD();
    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
    if (!(memory_region_is_ram(mr)
          || memory_region_is_romd(mr))) {
        return;
    }
    ram_addr = memory_region_get_ram_addr(mr) + addr;
    tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
}
#endif

/* Add a breakpoint.  */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
                          CPUBreakpoint **breakpoint)
{
    CPUClass *cc = CPU_GET_CLASS(cpu);
    CPUBreakpoint *bp;

    if (cc->gdb_adjust_breakpoint) {
        pc = cc->gdb_adjust_breakpoint(cpu, pc);
    }

    bp = g_malloc(sizeof(*bp));

    bp->pc = pc;
    bp->flags = flags;

    /* keep all GDB-injected breakpoints in front */
    if (flags & BP_GDB) {
        QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
    } else {
        QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
    }

    if (breakpoint) {
        *breakpoint = bp;
    }

    trace_breakpoint_insert(cpu->cpu_index, pc, flags);
    return 0;
}

/* Remove a specific breakpoint.  */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
    CPUClass *cc = CPU_GET_CLASS(cpu);
    CPUBreakpoint *bp;

    if (cc->gdb_adjust_breakpoint) {
        pc = cc->gdb_adjust_breakpoint(cpu, pc);
    }

    QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
        if (bp->pc == pc && bp->flags == flags) {
            cpu_breakpoint_remove_by_ref(cpu, bp);
            return 0;
        }
    }
    return -ENOENT;
}

/* Remove a specific breakpoint by reference.  */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
    QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);

    trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
    g_free(bp);
}

/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
    CPUBreakpoint *bp, *next;

    QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
        if (bp->flags & mask) {
            cpu_breakpoint_remove_by_ref(cpu, bp);
        }
    }
}

/* enable or disable single step mode. EXCP_DEBUG is returned by the
   CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)
{
    if (cpu->singlestep_enabled != enabled) {
        cpu->singlestep_enabled = enabled;
        if (kvm_enabled()) {
            kvm_update_guest_debug(cpu, 0);
        }
        trace_breakpoint_singlestep(cpu->cpu_index, enabled);
    }
}

void cpu_abort(CPUState *cpu, const char *fmt, ...)
{
    va_list ap;
    va_list ap2;

    va_start(ap, fmt);
    va_copy(ap2, ap);
    fprintf(stderr, "qemu: fatal: ");
    vfprintf(stderr, fmt, ap);
    fprintf(stderr, "\n");
    cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
    if (qemu_log_separate()) {
        FILE *logfile = qemu_log_lock();
        qemu_log("qemu: fatal: ");
        qemu_log_vprintf(fmt, ap2);
        qemu_log("\n");
        log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
        qemu_log_flush();
        qemu_log_unlock(logfile);
        qemu_log_close();
    }
    va_end(ap2);
    va_end(ap);
    replay_finish();
#if defined(CONFIG_USER_ONLY)
    {
        struct sigaction act;
        sigfillset(&act.sa_mask);
        act.sa_handler = SIG_DFL;
        act.sa_flags = 0;
        sigaction(SIGABRT, &act, NULL);
    }
#endif
    abort();
}

/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
                        void *ptr, size_t len, bool is_write)
{
    int flags;
    vaddr l, page;
    void * p;
    uint8_t *buf = ptr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = page_get_flags(page);
        if (!(flags & PAGE_VALID))
            return -1;
        if (is_write) {
            if (!(flags & PAGE_WRITE))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
                return -1;
            memcpy(p, buf, l);
            unlock_user(p, addr, l);
        } else {
            if (!(flags & PAGE_READ))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
                return -1;
            memcpy(buf, p, l);
            unlock_user(p, addr, 0);
        }
        len -= l;
        buf += l;
        addr += l;
    }
    return 0;
}
#endif

bool target_words_bigendian(void)
{
#if defined(TARGET_WORDS_BIGENDIAN)
    return true;
#else
    return false;
#endif
}

void page_size_init(void)
{
    /* NOTE: we can always suppose that qemu_host_page_size >=
       TARGET_PAGE_SIZE */
    if (qemu_host_page_size == 0) {
        qemu_host_page_size = qemu_real_host_page_size;
    }
    if (qemu_host_page_size < TARGET_PAGE_SIZE) {
        qemu_host_page_size = TARGET_PAGE_SIZE;
    }
    qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
}
Commit	Line	Data
d9f24bf5 PB	1	/*
	2	* Target-specific parts of the CPU object
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu-common.h"
	22	#include "qapi/error.h"
	23
	24	#include "exec/target_page.h"
	25	#include "hw/qdev-core.h"
	26	#include "hw/qdev-properties.h"
	27	#include "qemu/error-report.h"
	28	#include "migration/vmstate.h"
	29	#ifdef CONFIG_USER_ONLY
	30	#include "qemu.h"
	31	#else
8b80bd28	32	#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5 PB	33	#include "exec/address-spaces.h"
	34	#endif
	35	#include "sysemu/tcg.h"
	36	#include "sysemu/kvm.h"
	37	#include "sysemu/replay.h"
377bf6f3	38	#include "exec/cpu-common.h"
3b04508c	39	#include "exec/exec-all.h"
3b9bd3f4	40	#include "exec/translate-all.h"
d9f24bf5	41	#include "exec/log.h"
30565f10	42	#include "hw/core/accel-cpu.h"
ad1a706f	43	#include "trace/trace-root.h"
3b04508c	44	#include "qemu/accel.h"
d9f24bf5 PB	45
	46	uintptr_t qemu_host_page_size;
	47	intptr_t qemu_host_page_mask;
	48
	49	#ifndef CONFIG_USER_ONLY
	50	static int cpu_common_post_load(void *opaque, int version_id)
	51	{
	52	CPUState *cpu = opaque;
	53
	54	/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
	55	version_id is increased. */
	56	cpu->interrupt_request &= ~0x01;
	57	tlb_flush(cpu);
	58
	59	/* loadvm has just updated the content of RAM, bypassing the
	60	* usual mechanisms that ensure we flush TBs for writes to
	61	* memory we've translated code from. So we must flush all TBs,
	62	* which will now be stale.
	63	*/
	64	tb_flush(cpu);
	65
	66	return 0;
	67	}
	68
	69	static int cpu_common_pre_load(void *opaque)
	70	{
	71	CPUState *cpu = opaque;
	72
	73	cpu->exception_index = -1;
	74
	75	return 0;
	76	}
	77
	78	static bool cpu_common_exception_index_needed(void *opaque)
	79	{
	80	CPUState *cpu = opaque;
	81
	82	return tcg_enabled() && cpu->exception_index != -1;
	83	}
	84
	85	static const VMStateDescription vmstate_cpu_common_exception_index = {
	86	.name = "cpu_common/exception_index",
	87	.version_id = 1,
	88	.minimum_version_id = 1,
	89	.needed = cpu_common_exception_index_needed,
	90	.fields = (VMStateField[]) {
	91	VMSTATE_INT32(exception_index, CPUState),
	92	VMSTATE_END_OF_LIST()
	93	}
	94	};
	95
	96	static bool cpu_common_crash_occurred_needed(void *opaque)
	97	{
	98	CPUState *cpu = opaque;
	99
	100	return cpu->crash_occurred;
	101	}
	102
	103	static const VMStateDescription vmstate_cpu_common_crash_occurred = {
	104	.name = "cpu_common/crash_occurred",
	105	.version_id = 1,
	106	.minimum_version_id = 1,
	107	.needed = cpu_common_crash_occurred_needed,
	108	.fields = (VMStateField[]) {
109	VMSTATE_BOOL(crash_occurred, CPUState),
110	VMSTATE_END_OF_LIST()
111	}
112	};
113
114	const VMStateDescription vmstate_cpu_common = {
115	.name = "cpu_common",
116	.version_id = 1,
117	.minimum_version_id = 1,
118	.pre_load = cpu_common_pre_load,
119	.post_load = cpu_common_post_load,
120	.fields = (VMStateField[]) {
121	VMSTATE_UINT32(halted, CPUState),
122	VMSTATE_UINT32(interrupt_request, CPUState),
123	VMSTATE_END_OF_LIST()
124	},
125	.subsections = (const VMStateDescription*[]) {
126	&vmstate_cpu_common_exception_index,
127	&vmstate_cpu_common_crash_occurred,
128	NULL
129	}
130	};
131	#endif
132
7df5e3d6	133	void cpu_exec_realizefn(CPUState cpu, Error *errp)
d9f24bf5	134	{
feece4d0	135	#ifndef CONFIG_USER_ONLY
d9f24bf5	136	CPUClass *cc = CPU_GET_CLASS(cpu);
feece4d0	137	#endif
d9f24bf5	138
7df5e3d6	139	cpu_list_add(cpu);
9ea057dc CF	140	if (!accel_cpu_realizefn(cpu, errp)) {
	141	return;
	142	}
7df5e3d6 CF	143	/* NB: errp parameter is unused currently */
	144	if (tcg_enabled()) {
	145	tcg_exec_realizefn(cpu, errp);
	146	}
7df5e3d6 CF	147
7df5e3d6 CF	148	#ifdef CONFIG_USER_ONLY
4336073b PMD	149	assert(qdev_get_vmsd(DEVICE(cpu)) == NULL \|\|
4336073b PMD	150	qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6 CF	151	#else
	152	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	153	vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
	154	}
feece4d0 PMD	155	if (cc->sysemu_ops->legacy_vmsd != NULL) {
feece4d0 PMD	156	vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6 CF	157	}
	158	#endif /* CONFIG_USER_ONLY */
	159	}
	160
	161	void cpu_exec_unrealizefn(CPUState *cpu)
	162	{
feece4d0	163	#ifndef CONFIG_USER_ONLY
7df5e3d6	164	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5	165
feece4d0 PMD	166	if (cc->sysemu_ops->legacy_vmsd != NULL) {
feece4d0 PMD	167	vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5 PB	168	}
	169	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	170	vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
	171	}
d9f24bf5	172	#endif
7df5e3d6 CF	173	if (tcg_enabled()) {
	174	tcg_exec_unrealizefn(cpu);
	175	}
7df5e3d6 CF	176
7df5e3d6 CF	177	cpu_list_remove(cpu);
d9f24bf5 PB	178	}
d9f24bf5 PB	179
6e8dcacd RH	180	/*
	181	* This can't go in hw/core/cpu.c because that file is compiled only
	182	* once for both user-mode and system builds.
	183	*/
995b87de	184	static Property cpu_common_props[] = {
6e8dcacd RH	185	#ifdef CONFIG_USER_ONLY
	186	/*
	187	* Create a property for the user-only object, so users can
	188	* adjust prctl(PR_SET_UNALIGN) from the command-line.
	189	* Has no effect if the target does not support the feature.
	190	*/
	191	DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
	192	prctl_unalign_sigbus, false),
	193	#else
995b87de	194	/*
6e8dcacd RH	195	* Create a memory property for softmmu CPU object, so users can
6e8dcacd RH	196	* wire up its memory. The default if no link is set up is to use
995b87de RH	197	* the system address space.
	198	*/
	199	DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
	200	MemoryRegion *),
	201	#endif
995b87de RH	202	DEFINE_PROP_END_OF_LIST(),
	203	};
	204
0c3c25fc PM	205	static bool cpu_get_start_powered_off(Object obj, Error *errp)
	206	{
	207	CPUState *cpu = CPU(obj);
	208	return cpu->start_powered_off;
	209	}
	210
	211	static void cpu_set_start_powered_off(Object obj, bool value, Error *errp)
	212	{
	213	CPUState *cpu = CPU(obj);
	214	cpu->start_powered_off = value;
	215	}
	216
995b87de RH	217	void cpu_class_init_props(DeviceClass *dc)
995b87de RH	218	{
0c3c25fc PM	219	ObjectClass *oc = OBJECT_CLASS(dc);
0c3c25fc PM	220
995b87de	221	device_class_set_props(dc, cpu_common_props);
0c3c25fc PM	222	/*
	223	* We can't use DEFINE_PROP_BOOL in the Property array for this
	224	* property, because we want this to be settable after realize.
	225	*/
	226	object_class_property_add_bool(oc, "start-powered-off",
	227	cpu_get_start_powered_off,
	228	cpu_set_start_powered_off);
995b87de RH	229	}
995b87de RH	230
d9f24bf5 PB	231	void cpu_exec_initfn(CPUState *cpu)
	232	{
	233	cpu->as = NULL;
	234	cpu->num_ases = 0;
	235
	236	#ifndef CONFIG_USER_ONLY
	237	cpu->thread_id = qemu_get_thread_id();
	238	cpu->memory = get_system_memory();
	239	object_ref(OBJECT(cpu->memory));
	240	#endif
	241	}
	242
d9f24bf5 PB	243	const char parse_cpu_option(const char cpu_option)
	244	{
	245	ObjectClass *oc;
	246	CPUClass *cc;
	247	gchar **model_pieces;
	248	const char *cpu_type;
	249
	250	model_pieces = g_strsplit(cpu_option, ",", 2);
	251	if (!model_pieces[0]) {
	252	error_report("-cpu option cannot be empty");
	253	exit(1);
	254	}
	255
	256	oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
	257	if (oc == NULL) {
	258	error_report("unable to find CPU model '%s'", model_pieces[0]);
	259	g_strfreev(model_pieces);
	260	exit(EXIT_FAILURE);
	261	}
	262
	263	cpu_type = object_class_get_name(oc);
	264	cc = CPU_CLASS(oc);
	265	cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
	266	g_strfreev(model_pieces);
	267	return cpu_type;
	268	}
	269
377bf6f3 PMD	270	void list_cpus(const char *optarg)
	271	{
	272	/* XXX: implement xxx_cpu_list for targets that still miss it */
	273	#if defined(cpu_list)
	274	cpu_list();
	275	#endif
	276	}
	277
d9f24bf5 PB	278	#if defined(CONFIG_USER_ONLY)
	279	void tb_invalidate_phys_addr(target_ulong addr)
	280	{
	281	mmap_lock();
	282	tb_invalidate_phys_page_range(addr, addr + 1);
	283	mmap_unlock();
	284	}
d9f24bf5 PB	285	#else
	286	void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
	287	{
	288	ram_addr_t ram_addr;
	289	MemoryRegion *mr;
	290	hwaddr l = 1;
	291
	292	if (!tcg_enabled()) {
	293	return;
	294	}
	295
	296	RCU_READ_LOCK_GUARD();
	297	mr = address_space_translate(as, addr, &addr, &l, false, attrs);
	298	if (!(memory_region_is_ram(mr)
	299	\|\| memory_region_is_romd(mr))) {
	300	return;
	301	}
	302	ram_addr = memory_region_get_ram_addr(mr) + addr;
	303	tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
	304	}
d9f24bf5 PB	305	#endif
	306
	307	/* Add a breakpoint. */
	308	int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
	309	CPUBreakpoint **breakpoint)
	310	{
5bc31e94	311	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 PB	312	CPUBreakpoint *bp;
d9f24bf5 PB	313
5bc31e94 RH	314	if (cc->gdb_adjust_breakpoint) {
	315	pc = cc->gdb_adjust_breakpoint(cpu, pc);
	316	}
	317
d9f24bf5 PB	318	bp = g_malloc(sizeof(*bp));
	319
	320	bp->pc = pc;
	321	bp->flags = flags;
	322
	323	/* keep all GDB-injected breakpoints in front */
	324	if (flags & BP_GDB) {
	325	QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
	326	} else {
	327	QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
	328	}
	329
d9f24bf5 PB	330	if (breakpoint) {
	331	*breakpoint = bp;
	332	}
ad1a706f RH	333
ad1a706f RH	334	trace_breakpoint_insert(cpu->cpu_index, pc, flags);
d9f24bf5 PB	335	return 0;
	336	}
	337
	338	/* Remove a specific breakpoint. */
	339	int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
	340	{
5bc31e94	341	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 PB	342	CPUBreakpoint *bp;
d9f24bf5 PB	343
5bc31e94 RH	344	if (cc->gdb_adjust_breakpoint) {
	345	pc = cc->gdb_adjust_breakpoint(cpu, pc);
	346	}
	347
d9f24bf5 PB	348	QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
	349	if (bp->pc == pc && bp->flags == flags) {
	350	cpu_breakpoint_remove_by_ref(cpu, bp);
	351	return 0;
	352	}
	353	}
	354	return -ENOENT;
	355	}
	356
	357	/* Remove a specific breakpoint by reference. */
ad1a706f	358	void cpu_breakpoint_remove_by_ref(CPUState cpu, CPUBreakpoint bp)
d9f24bf5	359	{
ad1a706f	360	QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
d9f24bf5	361
ad1a706f RH	362	trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
ad1a706f RH	363	g_free(bp);
d9f24bf5 PB	364	}
	365
	366	/* Remove all matching breakpoints. */
	367	void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
	368	{
	369	CPUBreakpoint bp, next;
	370
	371	QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
	372	if (bp->flags & mask) {
	373	cpu_breakpoint_remove_by_ref(cpu, bp);
	374	}
	375	}
	376	}
	377
	378	/* enable or disable single step mode. EXCP_DEBUG is returned by the
	379	CPU loop after each instruction */
	380	void cpu_single_step(CPUState *cpu, int enabled)
	381	{
	382	if (cpu->singlestep_enabled != enabled) {
	383	cpu->singlestep_enabled = enabled;
	384	if (kvm_enabled()) {
	385	kvm_update_guest_debug(cpu, 0);
d9f24bf5	386	}
ad1a706f	387	trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5 PB	388	}
	389	}
	390
	391	void cpu_abort(CPUState cpu, const char fmt, ...)
	392	{
	393	va_list ap;
	394	va_list ap2;
	395
	396	va_start(ap, fmt);
	397	va_copy(ap2, ap);
	398	fprintf(stderr, "qemu: fatal: ");
	399	vfprintf(stderr, fmt, ap);
	400	fprintf(stderr, "\n");
	401	cpu_dump_state(cpu, stderr, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
	402	if (qemu_log_separate()) {
	403	FILE *logfile = qemu_log_lock();
	404	qemu_log("qemu: fatal: ");
	405	qemu_log_vprintf(fmt, ap2);
	406	qemu_log("\n");
	407	log_cpu_state(cpu, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
	408	qemu_log_flush();
	409	qemu_log_unlock(logfile);
	410	qemu_log_close();
	411	}
	412	va_end(ap2);
	413	va_end(ap);
	414	replay_finish();
	415	#if defined(CONFIG_USER_ONLY)
	416	{
	417	struct sigaction act;
	418	sigfillset(&act.sa_mask);
	419	act.sa_handler = SIG_DFL;
	420	act.sa_flags = 0;
	421	sigaction(SIGABRT, &act, NULL);
	422	}
	423	#endif
	424	abort();
	425	}
	426
	427	/* physical memory access (slow version, mainly for debug) */
	428	#if defined(CONFIG_USER_ONLY)
73842ef0 PMD	429	int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
73842ef0 PMD	430	void *ptr, size_t len, bool is_write)
d9f24bf5 PB	431	{
d9f24bf5 PB	432	int flags;
73842ef0	433	vaddr l, page;
d9f24bf5 PB	434	void * p;
	435	uint8_t *buf = ptr;
	436
	437	while (len > 0) {
	438	page = addr & TARGET_PAGE_MASK;
	439	l = (page + TARGET_PAGE_SIZE) - addr;
	440	if (l > len)
	441	l = len;
	442	flags = page_get_flags(page);
	443	if (!(flags & PAGE_VALID))
	444	return -1;
	445	if (is_write) {
	446	if (!(flags & PAGE_WRITE))
	447	return -1;
	448	/* XXX: this code should not depend on lock_user */
	449	if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
	450	return -1;
	451	memcpy(p, buf, l);
	452	unlock_user(p, addr, l);
	453	} else {
	454	if (!(flags & PAGE_READ))
	455	return -1;
	456	/* XXX: this code should not depend on lock_user */
	457	if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
	458	return -1;
	459	memcpy(buf, p, l);
	460	unlock_user(p, addr, 0);
	461	}
	462	len -= l;
	463	buf += l;
	464	addr += l;
	465	}
	466	return 0;
	467	}
	468	#endif
	469
	470	bool target_words_bigendian(void)
	471	{
	472	#if defined(TARGET_WORDS_BIGENDIAN)
	473	return true;
	474	#else
	475	return false;
	476	#endif
	477	}
	478
	479	void page_size_init(void)
	480	{
	481	/* NOTE: we can always suppose that qemu_host_page_size >=
	482	TARGET_PAGE_SIZE */
	483	if (qemu_host_page_size == 0) {
	484	qemu_host_page_size = qemu_real_host_page_size;
	485	}
	486	if (qemu_host_page_size < TARGET_PAGE_SIZE) {
	487	qemu_host_page_size = TARGET_PAGE_SIZE;
	488	}
	489	qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
	490	}