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1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qapi/error.h"
23
24#include "exec/target_page.h"
25#include "hw/qdev-core.h"
26#include "hw/qdev-properties.h"
27#include "qemu/error-report.h"
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
8b80bd28 32#include "hw/core/sysemu-cpu-ops.h"
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33#include "exec/address-spaces.h"
34#endif
35#include "sysemu/tcg.h"
36#include "sysemu/kvm.h"
37#include "sysemu/replay.h"
3b9bd3f4 38#include "exec/translate-all.h"
d9f24bf5 39#include "exec/log.h"
30565f10 40#include "hw/core/accel-cpu.h"
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41
42uintptr_t qemu_host_page_size;
43intptr_t qemu_host_page_mask;
44
45#ifndef CONFIG_USER_ONLY
46static int cpu_common_post_load(void *opaque, int version_id)
47{
48 CPUState *cpu = opaque;
49
50 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
51 version_id is increased. */
52 cpu->interrupt_request &= ~0x01;
53 tlb_flush(cpu);
54
55 /* loadvm has just updated the content of RAM, bypassing the
56 * usual mechanisms that ensure we flush TBs for writes to
57 * memory we've translated code from. So we must flush all TBs,
58 * which will now be stale.
59 */
60 tb_flush(cpu);
61
62 return 0;
63}
64
65static int cpu_common_pre_load(void *opaque)
66{
67 CPUState *cpu = opaque;
68
69 cpu->exception_index = -1;
70
71 return 0;
72}
73
74static bool cpu_common_exception_index_needed(void *opaque)
75{
76 CPUState *cpu = opaque;
77
78 return tcg_enabled() && cpu->exception_index != -1;
79}
80
81static const VMStateDescription vmstate_cpu_common_exception_index = {
82 .name = "cpu_common/exception_index",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .needed = cpu_common_exception_index_needed,
86 .fields = (VMStateField[]) {
87 VMSTATE_INT32(exception_index, CPUState),
88 VMSTATE_END_OF_LIST()
89 }
90};
91
92static bool cpu_common_crash_occurred_needed(void *opaque)
93{
94 CPUState *cpu = opaque;
95
96 return cpu->crash_occurred;
97}
98
99static const VMStateDescription vmstate_cpu_common_crash_occurred = {
100 .name = "cpu_common/crash_occurred",
101 .version_id = 1,
102 .minimum_version_id = 1,
103 .needed = cpu_common_crash_occurred_needed,
104 .fields = (VMStateField[]) {
105 VMSTATE_BOOL(crash_occurred, CPUState),
106 VMSTATE_END_OF_LIST()
107 }
108};
109
110const VMStateDescription vmstate_cpu_common = {
111 .name = "cpu_common",
112 .version_id = 1,
113 .minimum_version_id = 1,
114 .pre_load = cpu_common_pre_load,
115 .post_load = cpu_common_post_load,
116 .fields = (VMStateField[]) {
117 VMSTATE_UINT32(halted, CPUState),
118 VMSTATE_UINT32(interrupt_request, CPUState),
119 VMSTATE_END_OF_LIST()
120 },
121 .subsections = (const VMStateDescription*[]) {
122 &vmstate_cpu_common_exception_index,
123 &vmstate_cpu_common_crash_occurred,
124 NULL
125 }
126};
127#endif
128
7df5e3d6 129void cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 130{
feece4d0 131#ifndef CONFIG_USER_ONLY
d9f24bf5 132 CPUClass *cc = CPU_GET_CLASS(cpu);
feece4d0 133#endif
d9f24bf5 134
7df5e3d6 135 cpu_list_add(cpu);
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136 if (!accel_cpu_realizefn(cpu, errp)) {
137 return;
138 }
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139#ifdef CONFIG_TCG
140 /* NB: errp parameter is unused currently */
141 if (tcg_enabled()) {
142 tcg_exec_realizefn(cpu, errp);
143 }
144#endif /* CONFIG_TCG */
145
146#ifdef CONFIG_USER_ONLY
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147 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
148 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
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149#else
150 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
151 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
152 }
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153 if (cc->sysemu_ops->legacy_vmsd != NULL) {
154 vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
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155 }
156#endif /* CONFIG_USER_ONLY */
157}
158
159void cpu_exec_unrealizefn(CPUState *cpu)
160{
feece4d0 161#ifndef CONFIG_USER_ONLY
7df5e3d6 162 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 163
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164 if (cc->sysemu_ops->legacy_vmsd != NULL) {
165 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
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166 }
167 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
168 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
169 }
d9f24bf5 170#endif
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171#ifdef CONFIG_TCG
172 /* NB: errp parameter is unused currently */
173 if (tcg_enabled()) {
174 tcg_exec_unrealizefn(cpu);
175 }
176#endif /* CONFIG_TCG */
177
178 cpu_list_remove(cpu);
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179}
180
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181void cpu_exec_initfn(CPUState *cpu)
182{
183 cpu->as = NULL;
184 cpu->num_ases = 0;
185
186#ifndef CONFIG_USER_ONLY
187 cpu->thread_id = qemu_get_thread_id();
188 cpu->memory = get_system_memory();
189 object_ref(OBJECT(cpu->memory));
190#endif
191}
192
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193const char *parse_cpu_option(const char *cpu_option)
194{
195 ObjectClass *oc;
196 CPUClass *cc;
197 gchar **model_pieces;
198 const char *cpu_type;
199
200 model_pieces = g_strsplit(cpu_option, ",", 2);
201 if (!model_pieces[0]) {
202 error_report("-cpu option cannot be empty");
203 exit(1);
204 }
205
206 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
207 if (oc == NULL) {
208 error_report("unable to find CPU model '%s'", model_pieces[0]);
209 g_strfreev(model_pieces);
210 exit(EXIT_FAILURE);
211 }
212
213 cpu_type = object_class_get_name(oc);
214 cc = CPU_CLASS(oc);
215 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
216 g_strfreev(model_pieces);
217 return cpu_type;
218}
219
220#if defined(CONFIG_USER_ONLY)
221void tb_invalidate_phys_addr(target_ulong addr)
222{
223 mmap_lock();
224 tb_invalidate_phys_page_range(addr, addr + 1);
225 mmap_unlock();
226}
227
228static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
229{
230 tb_invalidate_phys_addr(pc);
231}
232#else
233void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
234{
235 ram_addr_t ram_addr;
236 MemoryRegion *mr;
237 hwaddr l = 1;
238
239 if (!tcg_enabled()) {
240 return;
241 }
242
243 RCU_READ_LOCK_GUARD();
244 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
245 if (!(memory_region_is_ram(mr)
246 || memory_region_is_romd(mr))) {
247 return;
248 }
249 ram_addr = memory_region_get_ram_addr(mr) + addr;
250 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
251}
252
253static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
254{
255 /*
256 * There may not be a virtual to physical translation for the pc
257 * right now, but there may exist cached TB for this pc.
258 * Flush the whole TB cache to force re-translation of such TBs.
259 * This is heavyweight, but we're debugging anyway.
260 */
261 tb_flush(cpu);
262}
263#endif
264
265/* Add a breakpoint. */
266int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
267 CPUBreakpoint **breakpoint)
268{
269 CPUBreakpoint *bp;
270
271 bp = g_malloc(sizeof(*bp));
272
273 bp->pc = pc;
274 bp->flags = flags;
275
276 /* keep all GDB-injected breakpoints in front */
277 if (flags & BP_GDB) {
278 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
279 } else {
280 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
281 }
282
283 breakpoint_invalidate(cpu, pc);
284
285 if (breakpoint) {
286 *breakpoint = bp;
287 }
288 return 0;
289}
290
291/* Remove a specific breakpoint. */
292int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
293{
294 CPUBreakpoint *bp;
295
296 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
297 if (bp->pc == pc && bp->flags == flags) {
298 cpu_breakpoint_remove_by_ref(cpu, bp);
299 return 0;
300 }
301 }
302 return -ENOENT;
303}
304
305/* Remove a specific breakpoint by reference. */
306void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
307{
308 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
309
310 breakpoint_invalidate(cpu, breakpoint->pc);
311
312 g_free(breakpoint);
313}
314
315/* Remove all matching breakpoints. */
316void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
317{
318 CPUBreakpoint *bp, *next;
319
320 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
321 if (bp->flags & mask) {
322 cpu_breakpoint_remove_by_ref(cpu, bp);
323 }
324 }
325}
326
327/* enable or disable single step mode. EXCP_DEBUG is returned by the
328 CPU loop after each instruction */
329void cpu_single_step(CPUState *cpu, int enabled)
330{
331 if (cpu->singlestep_enabled != enabled) {
332 cpu->singlestep_enabled = enabled;
333 if (kvm_enabled()) {
334 kvm_update_guest_debug(cpu, 0);
335 } else {
336 /* must flush all the translated code to avoid inconsistencies */
337 /* XXX: only flush what is necessary */
338 tb_flush(cpu);
339 }
340 }
341}
342
343void cpu_abort(CPUState *cpu, const char *fmt, ...)
344{
345 va_list ap;
346 va_list ap2;
347
348 va_start(ap, fmt);
349 va_copy(ap2, ap);
350 fprintf(stderr, "qemu: fatal: ");
351 vfprintf(stderr, fmt, ap);
352 fprintf(stderr, "\n");
353 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
354 if (qemu_log_separate()) {
355 FILE *logfile = qemu_log_lock();
356 qemu_log("qemu: fatal: ");
357 qemu_log_vprintf(fmt, ap2);
358 qemu_log("\n");
359 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
360 qemu_log_flush();
361 qemu_log_unlock(logfile);
362 qemu_log_close();
363 }
364 va_end(ap2);
365 va_end(ap);
366 replay_finish();
367#if defined(CONFIG_USER_ONLY)
368 {
369 struct sigaction act;
370 sigfillset(&act.sa_mask);
371 act.sa_handler = SIG_DFL;
372 act.sa_flags = 0;
373 sigaction(SIGABRT, &act, NULL);
374 }
375#endif
376 abort();
377}
378
379/* physical memory access (slow version, mainly for debug) */
380#if defined(CONFIG_USER_ONLY)
381int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
382 void *ptr, target_ulong len, bool is_write)
383{
384 int flags;
385 target_ulong l, page;
386 void * p;
387 uint8_t *buf = ptr;
388
389 while (len > 0) {
390 page = addr & TARGET_PAGE_MASK;
391 l = (page + TARGET_PAGE_SIZE) - addr;
392 if (l > len)
393 l = len;
394 flags = page_get_flags(page);
395 if (!(flags & PAGE_VALID))
396 return -1;
397 if (is_write) {
398 if (!(flags & PAGE_WRITE))
399 return -1;
400 /* XXX: this code should not depend on lock_user */
401 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
402 return -1;
403 memcpy(p, buf, l);
404 unlock_user(p, addr, l);
405 } else {
406 if (!(flags & PAGE_READ))
407 return -1;
408 /* XXX: this code should not depend on lock_user */
409 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
410 return -1;
411 memcpy(buf, p, l);
412 unlock_user(p, addr, 0);
413 }
414 len -= l;
415 buf += l;
416 addr += l;
417 }
418 return 0;
419}
420#endif
421
422bool target_words_bigendian(void)
423{
424#if defined(TARGET_WORDS_BIGENDIAN)
425 return true;
426#else
427 return false;
428#endif
429}
430
431void page_size_init(void)
432{
433 /* NOTE: we can always suppose that qemu_host_page_size >=
434 TARGET_PAGE_SIZE */
435 if (qemu_host_page_size == 0) {
436 qemu_host_page_size = qemu_real_host_page_size;
437 }
438 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
439 qemu_host_page_size = TARGET_PAGE_SIZE;
440 }
441 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
442}