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a61127c2 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9bc89cd8 DW |
2 | /* |
3 | * xor offload engine api | |
4 | * | |
5 | * Copyright © 2006, Intel Corporation. | |
6 | * | |
7 | * Dan Williams <dan.j.williams@intel.com> | |
8 | * | |
9 | * with architecture considerations by: | |
10 | * Neil Brown <neilb@suse.de> | |
11 | * Jeff Garzik <jeff@garzik.org> | |
9bc89cd8 DW |
12 | */ |
13 | #include <linux/kernel.h> | |
14 | #include <linux/interrupt.h> | |
4bb33cc8 | 15 | #include <linux/module.h> |
9bc89cd8 DW |
16 | #include <linux/mm.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/raid/xor.h> | |
19 | #include <linux/async_tx.h> | |
20 | ||
06164f31 DW |
21 | /* do_async_xor - dma map the pages and perform the xor with an engine */ |
22 | static __async_inline struct dma_async_tx_descriptor * | |
fb36ab14 | 23 | do_async_xor(struct dma_chan *chan, struct dmaengine_unmap_data *unmap, |
a08abd8c | 24 | struct async_submit_ctl *submit) |
9bc89cd8 | 25 | { |
1e55db2d | 26 | struct dma_device *dma = chan->device; |
1e55db2d | 27 | struct dma_async_tx_descriptor *tx = NULL; |
a08abd8c DW |
28 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
29 | void *cb_param_orig = submit->cb_param; | |
30 | enum async_tx_flags flags_orig = submit->flags; | |
0776ae7b | 31 | enum dma_ctrl_flags dma_flags = 0; |
fb36ab14 DW |
32 | int src_cnt = unmap->to_cnt; |
33 | int xor_src_cnt; | |
34 | dma_addr_t dma_dest = unmap->addr[unmap->to_cnt]; | |
35 | dma_addr_t *src_list = unmap->addr; | |
0036731c | 36 | |
1e55db2d | 37 | while (src_cnt) { |
fb36ab14 DW |
38 | dma_addr_t tmp; |
39 | ||
a08abd8c | 40 | submit->flags = flags_orig; |
b2f46fd8 | 41 | xor_src_cnt = min(src_cnt, (int)dma->max_xor); |
fb36ab14 DW |
42 | /* if we are submitting additional xors, leave the chain open |
43 | * and clear the callback parameters | |
1e55db2d DW |
44 | */ |
45 | if (src_cnt > xor_src_cnt) { | |
a08abd8c | 46 | submit->flags &= ~ASYNC_TX_ACK; |
0403e382 | 47 | submit->flags |= ASYNC_TX_FENCE; |
a08abd8c DW |
48 | submit->cb_fn = NULL; |
49 | submit->cb_param = NULL; | |
1e55db2d | 50 | } else { |
a08abd8c DW |
51 | submit->cb_fn = cb_fn_orig; |
52 | submit->cb_param = cb_param_orig; | |
1e55db2d | 53 | } |
a08abd8c | 54 | if (submit->cb_fn) |
1e55db2d | 55 | dma_flags |= DMA_PREP_INTERRUPT; |
0403e382 DW |
56 | if (submit->flags & ASYNC_TX_FENCE) |
57 | dma_flags |= DMA_PREP_FENCE; | |
fb36ab14 DW |
58 | |
59 | /* Drivers force forward progress in case they can not provide a | |
60 | * descriptor | |
1e55db2d | 61 | */ |
fb36ab14 DW |
62 | tmp = src_list[0]; |
63 | if (src_list > unmap->addr) | |
64 | src_list[0] = dma_dest; | |
65 | tx = dma->device_prep_dma_xor(chan, dma_dest, src_list, | |
66 | xor_src_cnt, unmap->len, | |
67 | dma_flags); | |
1e55db2d | 68 | |
669ab0b2 | 69 | if (unlikely(!tx)) |
a08abd8c | 70 | async_tx_quiesce(&submit->depend_tx); |
0036731c | 71 | |
25985edc | 72 | /* spin wait for the preceding transactions to complete */ |
669ab0b2 DW |
73 | while (unlikely(!tx)) { |
74 | dma_async_issue_pending(chan); | |
1e55db2d | 75 | tx = dma->device_prep_dma_xor(chan, dma_dest, |
fb36ab14 DW |
76 | src_list, |
77 | xor_src_cnt, unmap->len, | |
1e55db2d | 78 | dma_flags); |
669ab0b2 | 79 | } |
87cea763 | 80 | src_list[0] = tmp; |
9bc89cd8 | 81 | |
fb36ab14 | 82 | dma_set_unmap(tx, unmap); |
a08abd8c DW |
83 | async_tx_submit(chan, tx, submit); |
84 | submit->depend_tx = tx; | |
1e55db2d DW |
85 | |
86 | if (src_cnt > xor_src_cnt) { | |
87 | /* drop completed sources */ | |
88 | src_cnt -= xor_src_cnt; | |
1e55db2d | 89 | /* use the intermediate result a source */ |
1e55db2d | 90 | src_cnt++; |
fb36ab14 | 91 | src_list += xor_src_cnt - 1; |
1e55db2d DW |
92 | } else |
93 | break; | |
94 | } | |
0036731c DW |
95 | |
96 | return tx; | |
9bc89cd8 DW |
97 | } |
98 | ||
99 | static void | |
100 | do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, | |
a08abd8c | 101 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
9bc89cd8 | 102 | { |
9bc89cd8 | 103 | int i; |
b2141e69 | 104 | int xor_src_cnt = 0; |
1e55db2d DW |
105 | int src_off = 0; |
106 | void *dest_buf; | |
04ce9ab3 | 107 | void **srcs; |
9bc89cd8 | 108 | |
04ce9ab3 DW |
109 | if (submit->scribble) |
110 | srcs = submit->scribble; | |
111 | else | |
112 | srcs = (void **) src_list; | |
113 | ||
114 | /* convert to buffer pointers */ | |
9bc89cd8 | 115 | for (i = 0; i < src_cnt; i++) |
b2141e69 N |
116 | if (src_list[i]) |
117 | srcs[xor_src_cnt++] = page_address(src_list[i]) + offset; | |
118 | src_cnt = xor_src_cnt; | |
9bc89cd8 | 119 | /* set destination address */ |
1e55db2d | 120 | dest_buf = page_address(dest) + offset; |
9bc89cd8 | 121 | |
a08abd8c | 122 | if (submit->flags & ASYNC_TX_XOR_ZERO_DST) |
1e55db2d | 123 | memset(dest_buf, 0, len); |
9bc89cd8 | 124 | |
1e55db2d DW |
125 | while (src_cnt > 0) { |
126 | /* process up to 'MAX_XOR_BLOCKS' sources */ | |
127 | xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS); | |
128 | xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]); | |
129 | ||
130 | /* drop completed sources */ | |
131 | src_cnt -= xor_src_cnt; | |
132 | src_off += xor_src_cnt; | |
133 | } | |
9bc89cd8 | 134 | |
a08abd8c | 135 | async_tx_sync_epilog(submit); |
9bc89cd8 DW |
136 | } |
137 | ||
138 | /** | |
139 | * async_xor - attempt to xor a set of blocks with a dma engine. | |
9bc89cd8 | 140 | * @dest: destination page |
a08abd8c DW |
141 | * @src_list: array of source pages |
142 | * @offset: common src/dst offset to start transaction | |
9bc89cd8 DW |
143 | * @src_cnt: number of source pages |
144 | * @len: length in bytes | |
a08abd8c DW |
145 | * @submit: submission / completion modifiers |
146 | * | |
147 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST | |
148 | * | |
149 | * xor_blocks always uses the dest as a source so the | |
150 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in | |
151 | * the calculation. The assumption with dma eninges is that they only | |
152 | * use the destination buffer as a source when it is explicity specified | |
153 | * in the source list. | |
154 | * | |
155 | * src_list note: if the dest is also a source it must be at index zero. | |
156 | * The contents of this array will be overwritten if a scribble region | |
157 | * is not specified. | |
9bc89cd8 DW |
158 | */ |
159 | struct dma_async_tx_descriptor * | |
160 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, | |
a08abd8c | 161 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
9bc89cd8 | 162 | { |
a08abd8c | 163 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, |
47437b2c DW |
164 | &dest, 1, src_list, |
165 | src_cnt, len); | |
fb36ab14 DW |
166 | struct dma_device *device = chan ? chan->device : NULL; |
167 | struct dmaengine_unmap_data *unmap = NULL; | |
04ce9ab3 | 168 | |
9bc89cd8 DW |
169 | BUG_ON(src_cnt <= 1); |
170 | ||
fb36ab14 | 171 | if (device) |
b02bab6b | 172 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt+1, GFP_NOWAIT); |
fb36ab14 DW |
173 | |
174 | if (unmap && is_dma_xor_aligned(device, offset, 0, len)) { | |
175 | struct dma_async_tx_descriptor *tx; | |
176 | int i, j; | |
04ce9ab3 | 177 | |
1e55db2d DW |
178 | /* run the xor asynchronously */ |
179 | pr_debug("%s (async): len: %zu\n", __func__, len); | |
9bc89cd8 | 180 | |
fb36ab14 DW |
181 | unmap->len = len; |
182 | for (i = 0, j = 0; i < src_cnt; i++) { | |
183 | if (!src_list[i]) | |
184 | continue; | |
185 | unmap->to_cnt++; | |
186 | unmap->addr[j++] = dma_map_page(device->dev, src_list[i], | |
187 | offset, len, DMA_TO_DEVICE); | |
188 | } | |
189 | ||
190 | /* map it bidirectional as it may be re-used as a source */ | |
191 | unmap->addr[j] = dma_map_page(device->dev, dest, offset, len, | |
192 | DMA_BIDIRECTIONAL); | |
193 | unmap->bidi_cnt = 1; | |
194 | ||
195 | tx = do_async_xor(chan, unmap, submit); | |
196 | dmaengine_unmap_put(unmap); | |
197 | return tx; | |
1e55db2d | 198 | } else { |
fb36ab14 | 199 | dmaengine_unmap_put(unmap); |
1e55db2d DW |
200 | /* run the xor synchronously */ |
201 | pr_debug("%s (sync): len: %zu\n", __func__, len); | |
04ce9ab3 DW |
202 | WARN_ONCE(chan, "%s: no space for dma address conversion\n", |
203 | __func__); | |
9bc89cd8 | 204 | |
1e55db2d DW |
205 | /* in the sync case the dest is an implied source |
206 | * (assumes the dest is the first source) | |
9bc89cd8 | 207 | */ |
a08abd8c | 208 | if (submit->flags & ASYNC_TX_XOR_DROP_DST) { |
1e55db2d DW |
209 | src_cnt--; |
210 | src_list++; | |
211 | } | |
9bc89cd8 | 212 | |
1e55db2d | 213 | /* wait for any prerequisite operations */ |
a08abd8c | 214 | async_tx_quiesce(&submit->depend_tx); |
9bc89cd8 | 215 | |
a08abd8c | 216 | do_sync_xor(dest, src_list, offset, src_cnt, len, submit); |
9bc89cd8 | 217 | |
1e55db2d | 218 | return NULL; |
9bc89cd8 | 219 | } |
9bc89cd8 DW |
220 | } |
221 | EXPORT_SYMBOL_GPL(async_xor); | |
222 | ||
223 | static int page_is_zero(struct page *p, unsigned int offset, size_t len) | |
224 | { | |
2c88ae90 | 225 | return !memchr_inv(page_address(p) + offset, 0, len); |
9bc89cd8 DW |
226 | } |
227 | ||
7b3cc2b1 DW |
228 | static inline struct dma_chan * |
229 | xor_val_chan(struct async_submit_ctl *submit, struct page *dest, | |
230 | struct page **src_list, int src_cnt, size_t len) | |
231 | { | |
232 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
233 | return NULL; | |
234 | #endif | |
235 | return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list, | |
236 | src_cnt, len); | |
237 | } | |
238 | ||
9bc89cd8 | 239 | /** |
099f53cb | 240 | * async_xor_val - attempt a xor parity check with a dma engine. |
9bc89cd8 | 241 | * @dest: destination page used if the xor is performed synchronously |
a08abd8c | 242 | * @src_list: array of source pages |
9bc89cd8 DW |
243 | * @offset: offset in pages to start transaction |
244 | * @src_cnt: number of source pages | |
245 | * @len: length in bytes | |
246 | * @result: 0 if sum == 0 else non-zero | |
a08abd8c DW |
247 | * @submit: submission / completion modifiers |
248 | * | |
249 | * honored flags: ASYNC_TX_ACK | |
250 | * | |
251 | * src_list note: if the dest is also a source it must be at index zero. | |
252 | * The contents of this array will be overwritten if a scribble region | |
253 | * is not specified. | |
9bc89cd8 DW |
254 | */ |
255 | struct dma_async_tx_descriptor * | |
a08abd8c | 256 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
ad283ea4 | 257 | int src_cnt, size_t len, enum sum_check_flags *result, |
a08abd8c | 258 | struct async_submit_ctl *submit) |
9bc89cd8 | 259 | { |
7b3cc2b1 | 260 | struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len); |
9bc89cd8 | 261 | struct dma_device *device = chan ? chan->device : NULL; |
0036731c | 262 | struct dma_async_tx_descriptor *tx = NULL; |
173e86b2 | 263 | struct dmaengine_unmap_data *unmap = NULL; |
9bc89cd8 DW |
264 | |
265 | BUG_ON(src_cnt <= 1); | |
266 | ||
173e86b2 | 267 | if (device) |
b02bab6b | 268 | unmap = dmaengine_get_unmap_data(device->dev, src_cnt, GFP_NOWAIT); |
04ce9ab3 | 269 | |
173e86b2 | 270 | if (unmap && src_cnt <= device->max_xor && |
83544ae9 | 271 | is_dma_xor_aligned(device, offset, 0, len)) { |
0776ae7b | 272 | unsigned long dma_prep_flags = 0; |
0036731c | 273 | int i; |
9bc89cd8 | 274 | |
3280ab3e | 275 | pr_debug("%s: (async) len: %zu\n", __func__, len); |
9bc89cd8 | 276 | |
0403e382 DW |
277 | if (submit->cb_fn) |
278 | dma_prep_flags |= DMA_PREP_INTERRUPT; | |
279 | if (submit->flags & ASYNC_TX_FENCE) | |
280 | dma_prep_flags |= DMA_PREP_FENCE; | |
0036731c | 281 | |
173e86b2 DW |
282 | for (i = 0; i < src_cnt; i++) { |
283 | unmap->addr[i] = dma_map_page(device->dev, src_list[i], | |
284 | offset, len, DMA_TO_DEVICE); | |
285 | unmap->to_cnt++; | |
286 | } | |
287 | unmap->len = len; | |
288 | ||
289 | tx = device->device_prep_dma_xor_val(chan, unmap->addr, src_cnt, | |
099f53cb DW |
290 | len, result, |
291 | dma_prep_flags); | |
669ab0b2 | 292 | if (unlikely(!tx)) { |
a08abd8c | 293 | async_tx_quiesce(&submit->depend_tx); |
0036731c | 294 | |
e34a8ae7 | 295 | while (!tx) { |
669ab0b2 | 296 | dma_async_issue_pending(chan); |
099f53cb | 297 | tx = device->device_prep_dma_xor_val(chan, |
173e86b2 | 298 | unmap->addr, src_cnt, len, result, |
d4c56f97 | 299 | dma_prep_flags); |
e34a8ae7 | 300 | } |
9bc89cd8 | 301 | } |
173e86b2 | 302 | dma_set_unmap(tx, unmap); |
a08abd8c | 303 | async_tx_submit(chan, tx, submit); |
9bc89cd8 | 304 | } else { |
a08abd8c | 305 | enum async_tx_flags flags_orig = submit->flags; |
9bc89cd8 | 306 | |
3280ab3e | 307 | pr_debug("%s: (sync) len: %zu\n", __func__, len); |
04ce9ab3 DW |
308 | WARN_ONCE(device && src_cnt <= device->max_xor, |
309 | "%s: no space for dma address conversion\n", | |
310 | __func__); | |
9bc89cd8 | 311 | |
a08abd8c DW |
312 | submit->flags |= ASYNC_TX_XOR_DROP_DST; |
313 | submit->flags &= ~ASYNC_TX_ACK; | |
9bc89cd8 | 314 | |
a08abd8c | 315 | tx = async_xor(dest, src_list, offset, src_cnt, len, submit); |
9bc89cd8 | 316 | |
d2c52b79 | 317 | async_tx_quiesce(&tx); |
9bc89cd8 | 318 | |
ad283ea4 | 319 | *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; |
9bc89cd8 | 320 | |
a08abd8c DW |
321 | async_tx_sync_epilog(submit); |
322 | submit->flags = flags_orig; | |
9bc89cd8 | 323 | } |
173e86b2 | 324 | dmaengine_unmap_put(unmap); |
9bc89cd8 DW |
325 | |
326 | return tx; | |
327 | } | |
099f53cb | 328 | EXPORT_SYMBOL_GPL(async_xor_val); |
9bc89cd8 | 329 | |
9bc89cd8 DW |
330 | MODULE_AUTHOR("Intel Corporation"); |
331 | MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); | |
332 | MODULE_LICENSE("GPL"); |