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Commit | Line | Data |
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82ad8941 WB |
1 | From 3f89d6f1f3ba9b316e3f17c78c8c6f06a8f9c974 Mon Sep 17 00:00:00 2001 |
2 | From: Wolfgang Bumiller <w.bumiller@proxmox.com> | |
3 | Date: Mon, 4 Jul 2016 15:02:26 +0200 | |
4 | Subject: [PATCH] Revert "target-i386: disable LINT0 after reset" | |
5 | ||
6 | This reverts commit b8eb5512fd8a115f164edbbe897cdf8884920ccb. | |
7 | --- | |
8 | see https://bugs.launchpad.net/qemu/+bug/1488363?comments=all | |
9 | hw/intc/apic_common.c | 9 +++++++++ | |
10 | 1 file changed, 9 insertions(+) | |
11 | ||
12 | diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c | |
13 | index ad959c4..0264a88 100644 | |
14 | --- a/hw/intc/apic_common.c | |
15 | +++ b/hw/intc/apic_common.c | |
16 | @@ -242,6 +242,15 @@ static void apic_reset_common(DeviceState *dev) | |
17 | info->vapic_base_update(s); | |
18 | ||
19 | apic_init_reset(dev); | |
20 | + | |
21 | + if (bsp) { | |
22 | + /* | |
23 | + * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
24 | + * time typically by BIOS, so PIC interrupt can be delivered to the | |
25 | + * processor when local APIC is enabled. | |
26 | + */ | |
27 | + s->lvt[APIC_LVT_LINT0] = 0x700; | |
28 | + } | |
29 | } | |
30 | ||
31 | /* This function is only used for old state version 1 and 2 */ | |
32 | -- | |
33 | 2.1.4 | |
34 |