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Commit | Line | Data |
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d37e80a3 WB |
1 | From 9d315a91caeb359045b2c730294bba3889911127 Mon Sep 17 00:00:00 2001 |
2 | From: Prasad J Pandit <pjp@fedoraproject.org> | |
3 | Date: Fri, 30 Sep 2016 00:27:33 +0530 | |
4 | Subject: [PATCH 5/5] net: pcnet: check rx/tx descriptor ring length | |
5 | ||
6 | The AMD PC-Net II emulator has set of control and status(CSR) | |
7 | registers. Of these, CSR76 and CSR78 hold receive and transmit | |
8 | descriptor ring length respectively. This ring length could range | |
9 | from 1 to 65535. Setting ring length to zero leads to an infinite | |
10 | loop in pcnet_rdra_addr. Add check to avoid it. | |
11 | ||
12 | Reported-by: Li Qiang <liqiang6-s@360.cn> | |
13 | Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> | |
14 | --- | |
15 | hw/net/pcnet.c | 3 +++ | |
16 | 1 file changed, 3 insertions(+) | |
17 | ||
18 | diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c | |
19 | index 198a01f..3078de8 100644 | |
20 | --- a/hw/net/pcnet.c | |
21 | +++ b/hw/net/pcnet.c | |
22 | @@ -1429,8 +1429,11 @@ static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value) | |
23 | case 47: /* POLLINT */ | |
24 | case 72: | |
25 | case 74: | |
26 | + break; | |
27 | case 76: /* RCVRL */ | |
28 | case 78: /* XMTRL */ | |
29 | + val = (val > 0) ? val : 512; | |
30 | + break; | |
31 | case 112: | |
32 | if (CSR_STOP(s) || CSR_SPND(s)) | |
33 | break; | |
34 | -- | |
35 | 2.1.4 | |
36 |