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6643d27e
FB		 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
8167ee88 20along with this program; if not, see <http://www.gnu.org/licenses/>. */
6643d27e 21
c684822a 22#include "qemu/osdep.h"
a6d89b45 23#include "qemu/bitops.h"
3979fca4 24#include "disas/dis-asm.h"
6643d27e
FB		 25
26/* mips.h. Mips opcode list for GDB, the GNU debugger.
27 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
28 Free Software Foundation, Inc.
29 Contributed by Ralph Campbell and OSF
30 Commented and modified by Ian Lance Taylor, Cygnus Support
31
32This file is part of GDB, GAS, and the GNU binutils.
33
34GDB, GAS, and the GNU binutils are free software; you can redistribute
35them and/or modify them under the terms of the GNU General Public
36License as published by the Free Software Foundation; either version
371, or (at your option) any later version.
38
39GDB, GAS, and the GNU binutils are distributed in the hope that they
40will be useful, but WITHOUT ANY WARRANTY; without even the implied
41warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
42the GNU General Public License for more details.
43
44You should have received a copy of the GNU General Public License
8167ee88
BS		 45along with this file; see the file COPYING. If not,
46see <http://www.gnu.org/licenses/>. */
6643d27e
FB		 47
48/* These are bit masks and shift counts to use to access the various
49 fields of an instruction. To retrieve the X field of an
50 instruction, use the expression
51 (i >> OP_SH_X) & OP_MASK_X
52 To set the same field (to j), use
53 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
54
55 Make sure you use fields that are appropriate for the instruction,
56 of course.
57
58 The 'i' format uses OP, RS, RT and IMMEDIATE.
59
60 The 'j' format uses OP and TARGET.
61
62 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
63
64 The 'b' format uses OP, RS, RT and DELTA.
65
66 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
67
68 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
69
70 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
71 breakpoint instruction are not defined; Kane says the breakpoint
72 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
73 only use ten bits). An optional two-operand form of break/sdbbp
74 allows the lower ten bits to be set too, and MIPS32 and later
75 architectures allow 20 bits to be set with a signal operand
76 (using CODE20).
77
78 The syscall instruction uses CODE20.
79
80 The general coprocessor instructions use COPZ. */
81
82#define OP_MASK_OP 0x3f
83#define OP_SH_OP 26
84#define OP_MASK_RS 0x1f
85#define OP_SH_RS 21
86#define OP_MASK_FR 0x1f
87#define OP_SH_FR 21
88#define OP_MASK_FMT 0x1f
89#define OP_SH_FMT 21
90#define OP_MASK_BCC 0x7
91#define OP_SH_BCC 18
92#define OP_MASK_CODE 0x3ff
93#define OP_SH_CODE 16
94#define OP_MASK_CODE2 0x3ff
95#define OP_SH_CODE2 6
96#define OP_MASK_RT 0x1f
97#define OP_SH_RT 16
98#define OP_MASK_FT 0x1f
99#define OP_SH_FT 16
100#define OP_MASK_CACHE 0x1f
101#define OP_SH_CACHE 16
102#define OP_MASK_RD 0x1f
103#define OP_SH_RD 11
104#define OP_MASK_FS 0x1f
105#define OP_SH_FS 11
106#define OP_MASK_PREFX 0x1f
107#define OP_SH_PREFX 11
108#define OP_MASK_CCC 0x7
109#define OP_SH_CCC 8
110#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
111#define OP_SH_CODE20 6
112#define OP_MASK_SHAMT 0x1f
113#define OP_SH_SHAMT 6
114#define OP_MASK_FD 0x1f
115#define OP_SH_FD 6
116#define OP_MASK_TARGET 0x3ffffff
117#define OP_SH_TARGET 0
118#define OP_MASK_COPZ 0x1ffffff
119#define OP_SH_COPZ 0
120#define OP_MASK_IMMEDIATE 0xffff
121#define OP_SH_IMMEDIATE 0
122#define OP_MASK_DELTA 0xffff
123#define OP_SH_DELTA 0
4368b29a
LA		 124#define OP_MASK_DELTA_R6 0x1ff
125#define OP_SH_DELTA_R6 7
6643d27e
FB		 126#define OP_MASK_FUNCT 0x3f
127#define OP_SH_FUNCT 0
128#define OP_MASK_SPEC 0x3f
129#define OP_SH_SPEC 0
130#define OP_SH_LOCC 8 /* FP condition code. */
131#define OP_SH_HICC 18 /* FP condition code. */
132#define OP_MASK_CC 0x7
133#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
134#define OP_MASK_COP1NORM 0x1 /* a single bit. */
135#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
136#define OP_MASK_COP1SPEC 0xf
137#define OP_MASK_COP1SCLR 0x4
138#define OP_MASK_COP1CMP 0x3
139#define OP_SH_COP1CMP 4
140#define OP_SH_FORMAT 21 /* FP short format field. */
141#define OP_MASK_FORMAT 0x7
142#define OP_SH_TRUE 16
143#define OP_MASK_TRUE 0x1
144#define OP_SH_GE 17
145#define OP_MASK_GE 0x01
146#define OP_SH_UNSIGNED 16
147#define OP_MASK_UNSIGNED 0x1
148#define OP_SH_HINT 16
149#define OP_MASK_HINT 0x1f
150#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
151#define OP_MASK_MMI 0x3f
152#define OP_SH_MMISUB 6
153#define OP_MASK_MMISUB 0x1f
154#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
155#define OP_SH_PERFREG 1
156#define OP_SH_SEL 0 /* Coprocessor select field. */
157#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
158#define OP_SH_CODE19 6 /* 19 bit wait code. */
159#define OP_MASK_CODE19 0x7ffff
160#define OP_SH_ALN 21
161#define OP_MASK_ALN 0x7
162#define OP_SH_VSEL 21
163#define OP_MASK_VSEL 0x1f
164#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
165 but 0x8-0xf don't select bytes. */
166#define OP_SH_VECBYTE 22
167#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
168#define OP_SH_VECALIGN 21
169#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
170#define OP_SH_INSMSB 11
171#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
172#define OP_SH_EXTMSBD 11
173
174#define OP_OP_COP0 0x10
175#define OP_OP_COP1 0x11
176#define OP_OP_COP2 0x12
177#define OP_OP_COP3 0x13
178#define OP_OP_LWC1 0x31
179#define OP_OP_LWC2 0x32
180#define OP_OP_LWC3 0x33 /* a.k.a. pref */
181#define OP_OP_LDC1 0x35
182#define OP_OP_LDC2 0x36
183#define OP_OP_LDC3 0x37 /* a.k.a. ld */
184#define OP_OP_SWC1 0x39
185#define OP_OP_SWC2 0x3a
186#define OP_OP_SWC3 0x3b
187#define OP_OP_SDC1 0x3d
188#define OP_OP_SDC2 0x3e
189#define OP_OP_SDC3 0x3f /* a.k.a. sd */
190
29490584
TS		 191/* MIPS DSP ASE */
192#define OP_SH_DSPACC 11
193#define OP_MASK_DSPACC 0x3
194#define OP_SH_DSPACC_S 21
195#define OP_MASK_DSPACC_S 0x3
196#define OP_SH_DSPSFT 20
197#define OP_MASK_DSPSFT 0x3f
198#define OP_SH_DSPSFT_7 19
199#define OP_MASK_DSPSFT_7 0x7f
200#define OP_SH_SA3 21
201#define OP_MASK_SA3 0x7
202#define OP_SH_SA4 21
203#define OP_MASK_SA4 0xf
204#define OP_SH_IMM8 16
205#define OP_MASK_IMM8 0xff
206#define OP_SH_IMM10 16
207#define OP_MASK_IMM10 0x3ff
208#define OP_SH_WRDSP 11
209#define OP_MASK_WRDSP 0x3f
210#define OP_SH_RDDSP 16
211#define OP_MASK_RDDSP 0x3f
212#define OP_SH_BP 11
213#define OP_MASK_BP 0x3
214
215/* MIPS MT ASE */
216#define OP_SH_MT_U 5
217#define OP_MASK_MT_U 0x1
218#define OP_SH_MT_H 4
219#define OP_MASK_MT_H 0x1
220#define OP_SH_MTACC_T 18
221#define OP_MASK_MTACC_T 0x3
222#define OP_SH_MTACC_D 13
223#define OP_MASK_MTACC_D 0x3
224
ed8a933f
YK		 225/* MSA */
226#define OP_MASK_1BIT 0x1
227#define OP_SH_1BIT 16
228#define OP_MASK_2BIT 0x3
229#define OP_SH_2BIT 16
230#define OP_MASK_3BIT 0x7
231#define OP_SH_3BIT 16
232#define OP_MASK_4BIT 0xf
233#define OP_SH_4BIT 16
234#define OP_MASK_5BIT 0x1f
235#define OP_SH_5BIT 16
236#define OP_MASK_10BIT 0x3ff
237#define OP_SH_10BIT 11
238#define OP_MASK_MSACR11 0x1f
239#define OP_SH_MSACR11 11
240#define OP_MASK_MSACR6 0x1f
241#define OP_SH_MSACR6 6
242#define OP_MASK_GPR 0x1f
243#define OP_SH_GPR 6
244#define OP_MASK_1_TO_4 0x3
245#define OP_SH_1_TO_4 6
246
29490584
TS		 247#define OP_OP_COP0 0x10
248#define OP_OP_COP1 0x11
249#define OP_OP_COP2 0x12
250#define OP_OP_COP3 0x13
251#define OP_OP_LWC1 0x31
252#define OP_OP_LWC2 0x32
253#define OP_OP_LWC3 0x33 /* a.k.a. pref */
254#define OP_OP_LDC1 0x35
255#define OP_OP_LDC2 0x36
256#define OP_OP_LDC3 0x37 /* a.k.a. ld */
257#define OP_OP_SWC1 0x39
258#define OP_OP_SWC2 0x3a
259#define OP_OP_SWC3 0x3b
260#define OP_OP_SDC1 0x3d
261#define OP_OP_SDC2 0x3e
262#define OP_OP_SDC3 0x3f /* a.k.a. sd */
263
6643d27e
FB		 264/* Values in the 'VSEL' field. */
265#define MDMX_FMTSEL_IMM_QH 0x1d
266#define MDMX_FMTSEL_IMM_OB 0x1e
267#define MDMX_FMTSEL_VEC_QH 0x15
268#define MDMX_FMTSEL_VEC_OB 0x16
269
29490584
TS		 270/* UDI */
271#define OP_SH_UDI1 6
272#define OP_MASK_UDI1 0x1f
273#define OP_SH_UDI2 6
274#define OP_MASK_UDI2 0x3ff
275#define OP_SH_UDI3 6
276#define OP_MASK_UDI3 0x7fff
277#define OP_SH_UDI4 6
278#define OP_MASK_UDI4 0xfffff
6643d27e
FB		 279/* This structure holds information for a particular instruction. */
280
281struct mips_opcode
282{
283 /* The name of the instruction. */
284 const char *name;
285 /* A string describing the arguments for this instruction. */
286 const char *args;
287 /* The basic opcode for the instruction. When assembling, this
288 opcode is modified by the arguments to produce the actual opcode
289 that is used. If pinfo is INSN_MACRO, then this is 0. */
290 unsigned long match;
291 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
292 relevant portions of the opcode when disassembling. If the
293 actual opcode anded with the match field equals the opcode field,
294 then we have found the correct instruction. If pinfo is
295 INSN_MACRO, then this field is the macro identifier. */
296 unsigned long mask;
297 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
298 of bits describing the instruction, notably any relevant hazard
299 information. */
300 unsigned long pinfo;
29490584
TS		 301 /* A collection of additional bits describing the instruction. */
302 unsigned long pinfo2;
6643d27e
FB		 303 /* A collection of bits describing the instruction sets of which this
304 instruction or macro is a member. */
305 unsigned long membership;
306};
307
308/* These are the characters which may appear in the args field of an
309 instruction. They appear in the order in which the fields appear
310 when the instruction is used. Commas and parentheses in the args
311 string are ignored when assembling, and written into the output
312 when disassembling.
313
314 Each of these characters corresponds to a mask field defined above.
315
316 "<" 5 bit shift amount (OP_*_SHAMT)
317 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
318 "a" 26 bit target address (OP_*_TARGET)
319 "b" 5 bit base register (OP_*_RS)
320 "c" 10 bit breakpoint code (OP_*_CODE)
321 "d" 5 bit destination register specifier (OP_*_RD)
322 "h" 5 bit prefx hint (OP_*_PREFX)
323 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
324 "j" 16 bit signed immediate (OP_*_DELTA)
325 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
326 Also used for immediate operands in vr5400 vector insns.
327 "o" 16 bit signed offset (OP_*_DELTA)
328 "p" 16 bit PC relative branch target address (OP_*_DELTA)
329 "q" 10 bit extra breakpoint code (OP_*_CODE2)
330 "r" 5 bit same register used as both source and target (OP_*_RS)
331 "s" 5 bit source register specifier (OP_*_RS)
332 "t" 5 bit target register (OP_*_RT)
333 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
334 "v" 5 bit same register used as both source and destination (OP_*_RS)
335 "w" 5 bit same register used as both target and destination (OP_*_RT)
336 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
337 (used by clo and clz)
338 "C" 25 bit coprocessor function code (OP_*_COPZ)
339 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
340 "J" 19 bit wait function code (OP_*_CODE19)
341 "x" accept and ignore register name
342 "z" must be zero register
343 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
29490584
TS		 344 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
345 LSB (OP_*_SHAMT).
6643d27e 346 Enforces: 0 <= pos < 32.
29490584 347 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
6643d27e
FB		 348 Requires that "+A" or "+E" occur first to set position.
349 Enforces: 0 < (pos+size) <= 32.
29490584 350 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
6643d27e
FB		 351 Requires that "+A" or "+E" occur first to set position.
352 Enforces: 0 < (pos+size) <= 32.
353 (Also used by "dext" w/ different limits, but limits for
354 that are checked by the M_DEXT macro.)
29490584 355 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
6643d27e 356 Enforces: 32 <= pos < 64.
29490584 357 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
6643d27e
FB		 358 Requires that "+A" or "+E" occur first to set position.
359 Enforces: 32 < (pos+size) <= 64.
360 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
361 Requires that "+A" or "+E" occur first to set position.
362 Enforces: 32 < (pos+size) <= 64.
363 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
364 Requires that "+A" or "+E" occur first to set position.
365 Enforces: 32 < (pos+size) <= 64.
366
367 Floating point instructions:
368 "D" 5 bit destination register (OP_*_FD)
369 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
370 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
371 "S" 5 bit fs source 1 register (OP_*_FS)
372 "T" 5 bit ft source 2 register (OP_*_FT)
373 "R" 5 bit fr source 3 register (OP_*_FR)
374 "V" 5 bit same register used as floating source and destination (OP_*_FS)
375 "W" 5 bit same register used as floating target and destination (OP_*_FT)
376
377 Coprocessor instructions:
378 "E" 5 bit target register (OP_*_RT)
379 "G" 5 bit destination register (OP_*_RD)
380 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
381 "P" 5 bit performance-monitor register (OP_*_PERFREG)
382 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
383 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
384 see also "k" above
385 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
386 for pretty-printing in disassembly only.
387
388 Macro instructions:
389 "A" General 32 bit expression
390 "I" 32 bit immediate (value placed in imm_expr).
391 "+I" 32 bit immediate (value placed in imm2_expr).
392 "F" 64 bit floating point constant in .rdata
393 "L" 64 bit floating point constant in .lit8
394 "f" 32 bit floating point constant
395 "l" 32 bit floating point constant in .lit4
396
397 MDMX instruction operands (note that while these use the FP register
3b46e624 398 fields, they accept both $fN and $vN names for the registers):
6643d27e
FB		 399 "O" MDMX alignment offset (OP_*_ALN)
400 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
5fafdf24 401 "X" MDMX destination register (OP_*_FD)
6643d27e
FB		 402 "Y" MDMX source register (OP_*_FS)
403 "Z" MDMX source register (OP_*_FT)
404
29490584
TS		 405 DSP ASE usage:
406 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
407 "3" 3 bit unsigned immediate (OP_*_SA3)
408 "4" 4 bit unsigned immediate (OP_*_SA4)
409 "5" 8 bit unsigned immediate (OP_*_IMM8)
410 "6" 5 bit unsigned immediate (OP_*_RS)
411 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
412 "8" 6 bit unsigned immediate (OP_*_WRDSP)
413 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
414 "0" 6 bit signed immediate (OP_*_DSPSFT)
415 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
416 "'" 6 bit unsigned immediate (OP_*_RDDSP)
417 "@" 10 bit signed immediate (OP_*_IMM10)
418
419 MT ASE usage:
420 "!" 1 bit usermode flag (OP_*_MT_U)
421 "$" 1 bit load high flag (OP_*_MT_H)
422 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
423 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
424 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
425 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
426 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
427
428 UDI immediates:
429 "+1" UDI immediate bits 6-10
430 "+2" UDI immediate bits 6-15
431 "+3" UDI immediate bits 6-20
432 "+4" UDI immediate bits 6-25
433
d4ea6acd
LA		 434 R6 immediates/displacements :
435 (adding suffix to 'o' to avoid adding new characters)
436 "+o" 9 bits immediate/displacement (shift = 7)
437 "+o1" 18 bits immediate/displacement (shift = 0)
438 "+o2" 19 bits immediate/displacement (shift = 0)
439
6643d27e
FB		 440 Other:
441 "()" parens surrounding optional value
442 "," separates operands
443 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
444 "+" Start of extension sequence.
445
446 Characters used so far, for quick reference when adding more:
29490584
TS		 447 "234567890"
448 "%[]<>(),+:'@!$*&"
6643d27e 449 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
29490584 450 "abcdefghijklopqrstuvwxz"
6643d27e
FB		 451
452 Extension character sequences used so far ("+" followed by the
453 following), for quick reference when adding more:
29490584
TS		 454 "1234"
455 "ABCDEFGHIT"
456 "t"
6643d27e
FB		 457*/
458
459/* These are the bits which may be set in the pinfo field of an
460 instructions, if it is not equal to INSN_MACRO. */
461
462/* Modifies the general purpose register in OP_*_RD. */
463#define INSN_WRITE_GPR_D 0x00000001
464/* Modifies the general purpose register in OP_*_RT. */
465#define INSN_WRITE_GPR_T 0x00000002
466/* Modifies general purpose register 31. */
467#define INSN_WRITE_GPR_31 0x00000004
468/* Modifies the floating point register in OP_*_FD. */
469#define INSN_WRITE_FPR_D 0x00000008
470/* Modifies the floating point register in OP_*_FS. */
471#define INSN_WRITE_FPR_S 0x00000010
472/* Modifies the floating point register in OP_*_FT. */
473#define INSN_WRITE_FPR_T 0x00000020
474/* Reads the general purpose register in OP_*_RS. */
475#define INSN_READ_GPR_S 0x00000040
476/* Reads the general purpose register in OP_*_RT. */
477#define INSN_READ_GPR_T 0x00000080
478/* Reads the floating point register in OP_*_FS. */
479#define INSN_READ_FPR_S 0x00000100
480/* Reads the floating point register in OP_*_FT. */
481#define INSN_READ_FPR_T 0x00000200
482/* Reads the floating point register in OP_*_FR. */
483#define INSN_READ_FPR_R 0x00000400
484/* Modifies coprocessor condition code. */
485#define INSN_WRITE_COND_CODE 0x00000800
486/* Reads coprocessor condition code. */
487#define INSN_READ_COND_CODE 0x00001000
488/* TLB operation. */
489#define INSN_TLB 0x00002000
490/* Reads coprocessor register other than floating point register. */
491#define INSN_COP 0x00004000
492/* Instruction loads value from memory, requiring delay. */
493#define INSN_LOAD_MEMORY_DELAY 0x00008000
494/* Instruction loads value from coprocessor, requiring delay. */
495#define INSN_LOAD_COPROC_DELAY 0x00010000
496/* Instruction has unconditional branch delay slot. */
497#define INSN_UNCOND_BRANCH_DELAY 0x00020000
498/* Instruction has conditional branch delay slot. */
499#define INSN_COND_BRANCH_DELAY 0x00040000
500/* Conditional branch likely: if branch not taken, insn nullified. */
501#define INSN_COND_BRANCH_LIKELY 0x00080000
502/* Moves to coprocessor register, requiring delay. */
503#define INSN_COPROC_MOVE_DELAY 0x00100000
504/* Loads coprocessor register from memory, requiring delay. */
505#define INSN_COPROC_MEMORY_DELAY 0x00200000
506/* Reads the HI register. */
507#define INSN_READ_HI 0x00400000
508/* Reads the LO register. */
509#define INSN_READ_LO 0x00800000
510/* Modifies the HI register. */
511#define INSN_WRITE_HI 0x01000000
512/* Modifies the LO register. */
513#define INSN_WRITE_LO 0x02000000
514/* Takes a trap (easier to keep out of delay slot). */
515#define INSN_TRAP 0x04000000
516/* Instruction stores value into memory. */
517#define INSN_STORE_MEMORY 0x08000000
518/* Instruction uses single precision floating point. */
519#define FP_S 0x10000000
520/* Instruction uses double precision floating point. */
521#define FP_D 0x20000000
522/* Instruction is part of the tx39's integer multiply family. */
523#define INSN_MULT 0x40000000
524/* Instruction synchronize shared memory. */
525#define INSN_SYNC 0x80000000
29490584
TS		 526
527/* These are the bits which may be set in the pinfo2 field of an
528 instruction. */
529
530/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
531#define INSN2_ALIAS 0x00000001
532/* Instruction reads MDMX accumulator. */
533#define INSN2_READ_MDMX_ACC 0x00000002
534/* Instruction writes MDMX accumulator. */
535#define INSN2_WRITE_MDMX_ACC 0x00000004
6643d27e 536
ed8a933f
YK		 537/* Reads the general purpose register in OP_*_RD. */
538#define INSN2_READ_GPR_D 0x00000200
539
6643d27e
FB		 540/* Instruction is actually a macro. It should be ignored by the
541 disassembler, and requires special treatment by the assembler. */
542#define INSN_MACRO 0xffffffff
543
544/* Masks used to mark instructions to indicate which MIPS ISA level
545 they were introduced in. ISAs, as defined below, are logical
546 ORs of these bits, indicating that they support the instructions
547 defined at the given level. */
548
549#define INSN_ISA_MASK 0x00000fff
550#define INSN_ISA1 0x00000001
551#define INSN_ISA2 0x00000002
552#define INSN_ISA3 0x00000004
553#define INSN_ISA4 0x00000008
554#define INSN_ISA5 0x00000010
555#define INSN_ISA32 0x00000020
556#define INSN_ISA64 0x00000040
557#define INSN_ISA32R2 0x00000080
558#define INSN_ISA64R2 0x00000100
b691d9d2
LA		 559#define INSN_ISA32R6 0x00000200
560#define INSN_ISA64R6 0x00000400
6643d27e
FB		 561
562/* Masks used for MIPS-defined ASEs. */
563#define INSN_ASE_MASK 0x0000f000
564
29490584
TS		 565/* DSP ASE */
566#define INSN_DSP 0x00001000
567#define INSN_DSP64 0x00002000
6643d27e 568/* MIPS 16 ASE */
29490584 569#define INSN_MIPS16 0x00004000
6643d27e 570/* MIPS-3D ASE */
29490584 571#define INSN_MIPS3D 0x00008000
6643d27e
FB		 572
573/* Chip specific instructions. These are bitmasks. */
574
575/* MIPS R4650 instruction. */
576#define INSN_4650 0x00010000
577/* LSI R4010 instruction. */
578#define INSN_4010 0x00020000
579/* NEC VR4100 instruction. */
580#define INSN_4100 0x00040000
581/* Toshiba R3900 instruction. */
582#define INSN_3900 0x00080000
583/* MIPS R10000 instruction. */
584#define INSN_10000 0x00100000
585/* Broadcom SB-1 instruction. */
586#define INSN_SB1 0x00200000
587/* NEC VR4111/VR4181 instruction. */
588#define INSN_4111 0x00400000
589/* NEC VR4120 instruction. */
590#define INSN_4120 0x00800000
591/* NEC VR5400 instruction. */
592#define INSN_5400 0x01000000
593/* NEC VR5500 instruction. */
594#define INSN_5500 0x02000000
595
29490584 596/* MDMX ASE */
ed8a933f
YK		 597#define INSN_MDMX 0x00000000 /* Deprecated */
598
599/* MIPS MSA Extension */
600#define INSN_MSA 0x04000000
601#define INSN_MSA64 0x04000000
602
29490584
TS		 603/* MT ASE */
604#define INSN_MT 0x08000000
605/* SmartMIPS ASE */
606#define INSN_SMARTMIPS 0x10000000
607/* DSP R2 ASE */
608#define INSN_DSPR2 0x20000000
609
15656e09
AJ		 610/* ST Microelectronics Loongson 2E. */
611#define INSN_LOONGSON_2E 0x40000000
612/* ST Microelectronics Loongson 2F. */
613#define INSN_LOONGSON_2F 0x80000000
614
6643d27e
FB		 615/* MIPS ISA defines, use instead of hardcoding ISA level. */
616
617#define ISA_UNKNOWN 0 /* Gas internal use. */
618#define ISA_MIPS1 (INSN_ISA1)
619#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
620#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
621#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
622#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
623
624#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
625#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
626
627#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
628#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
629
b691d9d2
LA		 630#define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6)
631#define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
6643d27e
FB		 632
633/* CPU defines, use instead of hardcoding processor number. Keep this
634 in sync with bfd/archures.c in order for machine selection to work. */
635#define CPU_UNKNOWN 0 /* Gas internal use. */
636#define CPU_R3000 3000
637#define CPU_R3900 3900
638#define CPU_R4000 4000
639#define CPU_R4010 4010
640#define CPU_VR4100 4100
641#define CPU_R4111 4111
642#define CPU_VR4120 4120
643#define CPU_R4300 4300
644#define CPU_R4400 4400
645#define CPU_R4600 4600
646#define CPU_R4650 4650
647#define CPU_R5000 5000
648#define CPU_VR5400 5400
649#define CPU_VR5500 5500
650#define CPU_R6000 6000
651#define CPU_RM7000 7000
652#define CPU_R8000 8000
653#define CPU_R10000 10000
654#define CPU_R12000 12000
655#define CPU_MIPS16 16
656#define CPU_MIPS32 32
657#define CPU_MIPS32R2 33
658#define CPU_MIPS5 5
659#define CPU_MIPS64 64
660#define CPU_MIPS64R2 65
661#define CPU_SB1 12310201 /* octal 'SB', 01. */
662
663/* Test for membership in an ISA including chip specific ISAs. INSN
664 is pointer to an element of the opcode table; ISA is the specified
665 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
666 test, or zero if no CPU specific ISA test is desired. */
667
42fe4044 668#if 0
6643d27e
FB		 669#define OPCODE_IS_MEMBER(insn, isa, cpu) \
670 (((insn)->membership & isa) != 0 \
671 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
672 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
29490584 673 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
6643d27e
FB		 674 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
675 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
676 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
677 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
678 && ((insn)->membership & INSN_10000) != 0) \
679 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
680 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
681 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
682 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
683 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
684 || 0) /* Please keep this term for easier source merging. */
42fe4044
FB		 685#else
686#define OPCODE_IS_MEMBER(insn, isa, cpu) \
687 (1 != 0)
688#endif
6643d27e
FB		 689
690/* This is a list of macro expanded instructions.
691
692 _I appended means immediate
693 _A appended means address
694 _AB appended means address with base register
695 _D appended means 64 bit floating point constant
696 _S appended means 32 bit floating point constant. */
697
698enum
699{
700 M_ABS,
701 M_ADD_I,
702 M_ADDU_I,
703 M_AND_I,
29490584 704 M_BALIGN,
6643d27e
FB		 705 M_BEQ,
706 M_BEQ_I,
707 M_BEQL_I,
708 M_BGE,
709 M_BGEL,
710 M_BGE_I,
711 M_BGEL_I,
712 M_BGEU,
713 M_BGEUL,
714 M_BGEU_I,
715 M_BGEUL_I,
716 M_BGT,
717 M_BGTL,
718 M_BGT_I,
719 M_BGTL_I,
720 M_BGTU,
721 M_BGTUL,
722 M_BGTU_I,
723 M_BGTUL_I,
724 M_BLE,
725 M_BLEL,
726 M_BLE_I,
727 M_BLEL_I,
728 M_BLEU,
729 M_BLEUL,
730 M_BLEU_I,
731 M_BLEUL_I,
732 M_BLT,
733 M_BLTL,
734 M_BLT_I,
735 M_BLTL_I,
736 M_BLTU,
737 M_BLTUL,
738 M_BLTU_I,
739 M_BLTUL_I,
740 M_BNE,
741 M_BNE_I,
742 M_BNEL_I,
29490584 743 M_CACHE_AB,
6643d27e
FB		 744 M_DABS,
745 M_DADD_I,
746 M_DADDU_I,
747 M_DDIV_3,
748 M_DDIV_3I,
749 M_DDIVU_3,
750 M_DDIVU_3I,
751 M_DEXT,
752 M_DINS,
753 M_DIV_3,
754 M_DIV_3I,
755 M_DIVU_3,
756 M_DIVU_3I,
757 M_DLA_AB,
758 M_DLCA_AB,
759 M_DLI,
760 M_DMUL,
761 M_DMUL_I,
762 M_DMULO,
763 M_DMULO_I,
764 M_DMULOU,
765 M_DMULOU_I,
766 M_DREM_3,
767 M_DREM_3I,
768 M_DREMU_3,
769 M_DREMU_3I,
770 M_DSUB_I,
771 M_DSUBU_I,
772 M_DSUBU_I_2,
773 M_J_A,
774 M_JAL_1,
775 M_JAL_2,
776 M_JAL_A,
777 M_L_DOB,
778 M_L_DAB,
779 M_LA_AB,
780 M_LB_A,
781 M_LB_AB,
782 M_LBU_A,
783 M_LBU_AB,
784 M_LCA_AB,
785 M_LD_A,
786 M_LD_OB,
787 M_LD_AB,
788 M_LDC1_AB,
789 M_LDC2_AB,
790 M_LDC3_AB,
791 M_LDL_AB,
792 M_LDR_AB,
793 M_LH_A,
794 M_LH_AB,
795 M_LHU_A,
796 M_LHU_AB,
797 M_LI,
798 M_LI_D,
799 M_LI_DD,
800 M_LI_S,
801 M_LI_SS,
802 M_LL_AB,
803 M_LLD_AB,
804 M_LS_A,
805 M_LW_A,
806 M_LW_AB,
807 M_LWC0_A,
808 M_LWC0_AB,
809 M_LWC1_A,
810 M_LWC1_AB,
811 M_LWC2_A,
812 M_LWC2_AB,
813 M_LWC3_A,
814 M_LWC3_AB,
815 M_LWL_A,
816 M_LWL_AB,
817 M_LWR_A,
818 M_LWR_AB,
819 M_LWU_AB,
820 M_MOVE,
821 M_MUL,
822 M_MUL_I,
823 M_MULO,
824 M_MULO_I,
825 M_MULOU,
826 M_MULOU_I,
827 M_NOR_I,
828 M_OR_I,
829 M_REM_3,
830 M_REM_3I,
831 M_REMU_3,
832 M_REMU_3I,
833 M_DROL,
834 M_ROL,
835 M_DROL_I,
836 M_ROL_I,
837 M_DROR,
838 M_ROR,
839 M_DROR_I,
840 M_ROR_I,
841 M_S_DA,
842 M_S_DOB,
843 M_S_DAB,
844 M_S_S,
845 M_SC_AB,
846 M_SCD_AB,
847 M_SD_A,
848 M_SD_OB,
849 M_SD_AB,
850 M_SDC1_AB,
851 M_SDC2_AB,
852 M_SDC3_AB,
853 M_SDL_AB,
854 M_SDR_AB,
855 M_SEQ,
856 M_SEQ_I,
857 M_SGE,
858 M_SGE_I,
859 M_SGEU,
860 M_SGEU_I,
861 M_SGT,
862 M_SGT_I,
863 M_SGTU,
864 M_SGTU_I,
865 M_SLE,
866 M_SLE_I,
867 M_SLEU,
868 M_SLEU_I,
869 M_SLT_I,
870 M_SLTU_I,
871 M_SNE,
872 M_SNE_I,
873 M_SB_A,
874 M_SB_AB,
875 M_SH_A,
876 M_SH_AB,
877 M_SW_A,
878 M_SW_AB,
879 M_SWC0_A,
880 M_SWC0_AB,
881 M_SWC1_A,
882 M_SWC1_AB,
883 M_SWC2_A,
884 M_SWC2_AB,
885 M_SWC3_A,
886 M_SWC3_AB,
887 M_SWL_A,
888 M_SWL_AB,
889 M_SWR_A,
890 M_SWR_AB,
891 M_SUB_I,
892 M_SUBU_I,
893 M_SUBU_I_2,
894 M_TEQ_I,
895 M_TGE_I,
896 M_TGEU_I,
897 M_TLT_I,
898 M_TLTU_I,
899 M_TNE_I,
900 M_TRUNCWD,
901 M_TRUNCWS,
902 M_ULD,
903 M_ULD_A,
904 M_ULH,
905 M_ULH_A,
906 M_ULHU,
907 M_ULHU_A,
908 M_ULW,
909 M_ULW_A,
910 M_USH,
911 M_USH_A,
912 M_USW,
913 M_USW_A,
914 M_USD,
915 M_USD_A,
916 M_XOR_I,
917 M_COP0,
918 M_COP1,
919 M_COP2,
920 M_COP3,
921 M_NUM_MACROS
922};
923
924
925/* The order of overloaded instructions matters. Label arguments and
926 register arguments look the same. Instructions that can have either
927 for arguments must apear in the correct order in this table for the
928 assembler to pick the right one. In other words, entries with
929 immediate operands must apear after the same instruction with
930 registers.
931
932 Many instructions are short hand for other instructions (i.e., The
933 jal <register> instruction is short for jalr <register>). */
934
935extern const struct mips_opcode mips_builtin_opcodes[];
936extern const int bfd_mips_num_builtin_opcodes;
937extern struct mips_opcode *mips_opcodes;
938extern int bfd_mips_num_opcodes;
939#define NUMOPCODES bfd_mips_num_opcodes
940
941\f
942/* The rest of this file adds definitions for the mips16 TinyRISC
943 processor. */
944
945/* These are the bitmasks and shift counts used for the different
946 fields in the instruction formats. Other than OP, no masks are
947 provided for the fixed portions of an instruction, since they are
948 not needed.
949
950 The I format uses IMM11.
951
952 The RI format uses RX and IMM8.
953
954 The RR format uses RX, and RY.
955
956 The RRI format uses RX, RY, and IMM5.
957
958 The RRR format uses RX, RY, and RZ.
959
960 The RRI_A format uses RX, RY, and IMM4.
961
962 The SHIFT format uses RX, RY, and SHAMT.
963
964 The I8 format uses IMM8.
965
966 The I8_MOVR32 format uses RY and REGR32.
967
968 The IR_MOV32R format uses REG32R and MOV32Z.
969
970 The I64 format uses IMM8.
971
972 The RI64 format uses RY and IMM5.
973 */
974
975#define MIPS16OP_MASK_OP 0x1f
976#define MIPS16OP_SH_OP 11
977#define MIPS16OP_MASK_IMM11 0x7ff
978#define MIPS16OP_SH_IMM11 0
979#define MIPS16OP_MASK_RX 0x7
980#define MIPS16OP_SH_RX 8
981#define MIPS16OP_MASK_IMM8 0xff
982#define MIPS16OP_SH_IMM8 0
983#define MIPS16OP_MASK_RY 0x7
984#define MIPS16OP_SH_RY 5
985#define MIPS16OP_MASK_IMM5 0x1f
986#define MIPS16OP_SH_IMM5 0
987#define MIPS16OP_MASK_RZ 0x7
988#define MIPS16OP_SH_RZ 2
989#define MIPS16OP_MASK_IMM4 0xf
990#define MIPS16OP_SH_IMM4 0
991#define MIPS16OP_MASK_REGR32 0x1f
992#define MIPS16OP_SH_REGR32 0
993#define MIPS16OP_MASK_REG32R 0x1f
994#define MIPS16OP_SH_REG32R 3
995#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
996#define MIPS16OP_MASK_MOVE32Z 0x7
997#define MIPS16OP_SH_MOVE32Z 0
998#define MIPS16OP_MASK_IMM6 0x3f
999#define MIPS16OP_SH_IMM6 5
1000
1001/* These are the characters which may appears in the args field of an
1002 instruction. They appear in the order in which the fields appear
1003 when the instruction is used. Commas and parentheses in the args
1004 string are ignored when assembling, and written into the output
1005 when disassembling.
1006
1007 "y" 3 bit register (MIPS16OP_*_RY)
1008 "x" 3 bit register (MIPS16OP_*_RX)
1009 "z" 3 bit register (MIPS16OP_*_RZ)
1010 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1011 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1012 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1013 "0" zero register ($0)
1014 "S" stack pointer ($sp or $29)
1015 "P" program counter
1016 "R" return address register ($ra or $31)
1017 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1018 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1019 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1020 "a" 26 bit jump address
1021 "e" 11 bit extension value
1022 "l" register list for entry instruction
1023 "L" register list for exit instruction
1024
1025 The remaining codes may be extended. Except as otherwise noted,
1026 the full extended operand is a 16 bit signed value.
1027 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1028 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1029 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1030 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1031 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1032 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1033 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1034 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1035 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1036 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1037 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1038 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1039 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1040 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1041 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1042 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1043 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1044 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1045 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1046 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1047 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1048 */
1049
29490584
TS		 1050/* Save/restore encoding for the args field when all 4 registers are
1051 either saved as arguments or saved/restored as statics. */
1052#define MIPS16_ALL_ARGS 0xe
1053#define MIPS16_ALL_STATICS 0xb
1054
6643d27e
FB		 1055/* For the mips16, we use the same opcode table format and a few of
1056 the same flags. However, most of the flags are different. */
1057
1058/* Modifies the register in MIPS16OP_*_RX. */
1059#define MIPS16_INSN_WRITE_X 0x00000001
1060/* Modifies the register in MIPS16OP_*_RY. */
1061#define MIPS16_INSN_WRITE_Y 0x00000002
1062/* Modifies the register in MIPS16OP_*_RZ. */
1063#define MIPS16_INSN_WRITE_Z 0x00000004
1064/* Modifies the T ($24) register. */
1065#define MIPS16_INSN_WRITE_T 0x00000008
1066/* Modifies the SP ($29) register. */
1067#define MIPS16_INSN_WRITE_SP 0x00000010
1068/* Modifies the RA ($31) register. */
1069#define MIPS16_INSN_WRITE_31 0x00000020
1070/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1071#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1072/* Reads the register in MIPS16OP_*_RX. */
1073#define MIPS16_INSN_READ_X 0x00000080
1074/* Reads the register in MIPS16OP_*_RY. */
1075#define MIPS16_INSN_READ_Y 0x00000100
1076/* Reads the register in MIPS16OP_*_MOVE32Z. */
1077#define MIPS16_INSN_READ_Z 0x00000200
1078/* Reads the T ($24) register. */
1079#define MIPS16_INSN_READ_T 0x00000400
1080/* Reads the SP ($29) register. */
1081#define MIPS16_INSN_READ_SP 0x00000800
1082/* Reads the RA ($31) register. */
1083#define MIPS16_INSN_READ_31 0x00001000
1084/* Reads the program counter. */
1085#define MIPS16_INSN_READ_PC 0x00002000
1086/* Reads the general purpose register in MIPS16OP_*_REGR32. */
1087#define MIPS16_INSN_READ_GPR_X 0x00004000
1088/* Is a branch insn. */
1089#define MIPS16_INSN_BRANCH 0x00010000
1090
1091/* The following flags have the same value for the mips16 opcode
1092 table:
1093 INSN_UNCOND_BRANCH_DELAY
1094 INSN_COND_BRANCH_DELAY
1095 INSN_COND_BRANCH_LIKELY (never used)
1096 INSN_READ_HI
1097 INSN_READ_LO
1098 INSN_WRITE_HI
1099 INSN_WRITE_LO
1100 INSN_TRAP
1101 INSN_ISA3
1102 */
1103
1104extern const struct mips_opcode mips16_opcodes[];
1105extern const int bfd_mips16_num_opcodes;
1106
1107/* Short hand so the lines aren't too long. */
1108
1109#define LDD INSN_LOAD_MEMORY_DELAY
1110#define LCD INSN_LOAD_COPROC_DELAY
1111#define UBD INSN_UNCOND_BRANCH_DELAY
1112#define CBD INSN_COND_BRANCH_DELAY
1113#define COD INSN_COPROC_MOVE_DELAY
1114#define CLD INSN_COPROC_MEMORY_DELAY
1115#define CBL INSN_COND_BRANCH_LIKELY
1116#define TRAP INSN_TRAP
1117#define SM INSN_STORE_MEMORY
1118
1119#define WR_d INSN_WRITE_GPR_D
1120#define WR_t INSN_WRITE_GPR_T
1121#define WR_31 INSN_WRITE_GPR_31
1122#define WR_D INSN_WRITE_FPR_D
1123#define WR_T INSN_WRITE_FPR_T
1124#define WR_S INSN_WRITE_FPR_S
1125#define RD_s INSN_READ_GPR_S
1126#define RD_b INSN_READ_GPR_S
1127#define RD_t INSN_READ_GPR_T
1128#define RD_S INSN_READ_FPR_S
1129#define RD_T INSN_READ_FPR_T
1130#define RD_R INSN_READ_FPR_R
1131#define WR_CC INSN_WRITE_COND_CODE
1132#define RD_CC INSN_READ_COND_CODE
1133#define RD_C0 INSN_COP
1134#define RD_C1 INSN_COP
1135#define RD_C2 INSN_COP
1136#define RD_C3 INSN_COP
1137#define WR_C0 INSN_COP
1138#define WR_C1 INSN_COP
1139#define WR_C2 INSN_COP
1140#define WR_C3 INSN_COP
1141
1142#define WR_HI INSN_WRITE_HI
1143#define RD_HI INSN_READ_HI
1144#define MOD_HI WR_HI|RD_HI
1145
1146#define WR_LO INSN_WRITE_LO
1147#define RD_LO INSN_READ_LO
1148#define MOD_LO WR_LO|RD_LO
1149
1150#define WR_HILO WR_HI|WR_LO
1151#define RD_HILO RD_HI|RD_LO
1152#define MOD_HILO WR_HILO|RD_HILO
1153
1154#define IS_M INSN_MULT
1155
29490584
TS		 1156#define WR_MACC INSN2_WRITE_MDMX_ACC
1157#define RD_MACC INSN2_READ_MDMX_ACC
6643d27e
FB		 1158
1159#define I1 INSN_ISA1
1160#define I2 INSN_ISA2
1161#define I3 INSN_ISA3
1162#define I4 INSN_ISA4
1163#define I5 INSN_ISA5
1164#define I32 INSN_ISA32
1165#define I64 INSN_ISA64
1166#define I33 INSN_ISA32R2
1167#define I65 INSN_ISA64R2
b691d9d2
LA		 1168#define I32R6 INSN_ISA32R6
1169#define I64R6 INSN_ISA64R6
6643d27e
FB		 1170
1171/* MIPS64 MIPS-3D ASE support. */
1172#define I16 INSN_MIPS16
1173
29490584
TS		 1174/* MIPS32 SmartMIPS ASE support. */
1175#define SMT INSN_SMARTMIPS
1176
6643d27e
FB		 1177/* MIPS64 MIPS-3D ASE support. */
1178#define M3D INSN_MIPS3D
1179
1180/* MIPS64 MDMX ASE support. */
1181#define MX INSN_MDMX
1182
15656e09
AJ		 1183#define IL2E (INSN_LOONGSON_2E)
1184#define IL2F (INSN_LOONGSON_2F)
1185
6643d27e
FB		 1186#define P3 INSN_4650
1187#define L1 INSN_4010
1188#define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1189#define T3 INSN_3900
1190#define M1 INSN_10000
1191#define SB1 INSN_SB1
1192#define N411 INSN_4111
1193#define N412 INSN_4120
1194#define N5 (INSN_5400 | INSN_5500)
1195#define N54 INSN_5400
1196#define N55 INSN_5500
1197
1198#define G1 (T3 \
1199 )
1200
1201#define G2 (T3 \
1202 )
1203
1204#define G3 (I4 \
1205 )
1206
29490584
TS		 1207/* MIPS DSP ASE support.
1208 NOTE:
1209 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
1210 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
1211 the same structure as $ac0 (HI + LO). For DSP instructions that write or
1212 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1213 (RD_HILO) attributes, such that HILO dependencies are maintained
1214 conservatively.
1215
1216 2. For some mul. instructions that use integer registers as destinations
1217 but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1218
1219 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1220 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
1221 certain fields of the DSP control register. For simplicity, we decide not
1222 to track dependencies of these fields.
1223 However, "bposge32" is a branch instruction that depends on the "pos"
1224 field. In order to make sure that GAS does not reorder DSP instructions
1225 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1226 attribute to those instructions that write the "pos" field. */
1227
1228#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
1229#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
1230#define MOD_a WR_a|RD_a
1231#define DSP_VOLA INSN_TRAP
1232#define D32 INSN_DSP
1233#define D33 INSN_DSPR2
1234#define D64 INSN_DSP64
1235
1236/* MIPS MT ASE support. */
1237#define MT32 INSN_MT
1238
ed8a933f
YK		 1239/* MSA */
1240#define MSA INSN_MSA
1241#define MSA64 INSN_MSA64
1242#define WR_VD INSN_WRITE_FPR_D /* Reuse INSN_WRITE_FPR_D */
1243#define RD_VD WR_VD /* Reuse WR_VD */
1244#define RD_VT INSN_READ_FPR_T /* Reuse INSN_READ_FPR_T */
1245#define RD_VS INSN_READ_FPR_S /* Reuse INSN_READ_FPR_S */
1246#define RD_d INSN2_READ_GPR_D /* Reuse INSN2_READ_GPR_D */
1247
1248#define RD_rd6 0
1249
6643d27e
FB		 1250/* The order of overloaded instructions matters. Label arguments and
1251 register arguments look the same. Instructions that can have either
1252 for arguments must apear in the correct order in this table for the
1253 assembler to pick the right one. In other words, entries with
1254 immediate operands must apear after the same instruction with
1255 registers.
1256
1257 Because of the lookup algorithm used, entries with the same opcode
1258 name must be contiguous.
5fafdf24 1259
6643d27e
FB		 1260 Many instructions are short hand for other instructions (i.e., The
1261 jal <register> instruction is short for jalr <register>). */
1262
1263const struct mips_opcode mips_builtin_opcodes[] =
1264{
1265/* These instructions appear first so that the disassembler will find
1266 them first. The assemblers uses a hash table based on the
1267 instruction name anyhow. */
1268/* name, args, match, mask, pinfo, membership */
d4ea6acd
LA		 1269{"lwpc", "s,+o2", 0xec080000, 0xfc180000, WR_d, 0, I32R6},
1270{"lwupc", "s,+o2", 0xec100000, 0xfc180000, WR_d, 0, I64R6},
1271{"ldpc", "s,+o1", 0xec180000, 0xfc1c0000, WR_d, 0, I64R6},
1272{"addiupc", "s,+o2", 0xec000000, 0xfc180000, WR_d, 0, I32R6},
1273{"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_d, 0, I32R6},
1274{"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_d, 0, I32R6},
1275{"daui", "s,t,u", 0x74000000, 0xfc000000, RD_s|WR_t, 0, I64R6},
1276{"dahi", "s,u", 0x04060000, 0xfc1f0000, RD_s, 0, I64R6},
1277{"dati", "s,u", 0x041e0000, 0xfc1f0000, RD_s, 0, I64R6},
1278{"lsa", "d,s,t", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
1279{"dlsa", "d,s,t", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, I64R6},
4267d3e6
LA		 1280{"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
1281{"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
1282{"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
1283{"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
1284{"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6},
b42ee5e1
LA		 1285{"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1286{"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1287{"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1288{"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1289{"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1290{"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1291{"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1292{"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1293{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1294{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1295{"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1296{"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1297{"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1298{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1299{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1300{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
6b9c26fb
YK		 1301{"ll", "t,+o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1302{"sc", "t,+o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1303{"lld", "t,+o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1304{"scd", "t,+o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1305{"pref", "h,+o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6},
1306{"cache", "k,+o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
b691d9d2
LA		 1307{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1308{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
e7f16abb
LA		 1309{"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1310{"maddf.d", "D,S,T", 0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1311{"msubf.s", "D,S,T", 0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1312{"msubf.d", "D,S,T", 0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1313{"max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1314{"max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1315{"maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1316{"maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1317{"rint.s", "D,S", 0x4600001a, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6},
1318{"rint.d", "D,S", 0x4620001a, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6},
1319{"class.s", "D,S", 0x4600001b, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6},
1320{"class.d", "D,S", 0x4620001b, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6},
1321{"min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1322{"min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1323{"mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1324{"mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1325{"sel.s", "D,S,T", 0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1326{"sel.d", "D,S,T", 0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1327{"seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1328{"seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
1329{"selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6},
1330{"selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6},
15eacb9b
YK		 1331{"align", "d,v,t", 0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
1332{"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6},
1333{"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6},
1334{"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6},
31837be3
YK		 1335{"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
1336{"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
1337{"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
a6d89b45 1338{"beqzc", "s,+q", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
31837be3 1339{"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
a6d89b45 1340{"bnezc", "s,+q", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
31837be3
YK		 1341{"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1342{"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1343{"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1344{"bnezalc", "s,t,p", 0x60000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1345{"bnvc", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1346{"bnec", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1347{"blezc", "s,t,p", 0x58000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1348{"bgezc", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1349{"bgec", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1350{"bgtzc", "s,t,p", 0x5c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1351{"bltzc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1352{"bltc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1353{"blezalc", "s,t,p", 0x18000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1354{"bgezalc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1355{"bgeuc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1356{"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
1357{"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
1358{"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
0aefa333
YK		 1359{"nal", "p", 0x04100000, 0xffff0000, WR_31, 0, I32R6},
1360{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0, I32R6},
31837be3
YK		 1361{"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
1362{"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
1363{"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6},
1364{"bc2nez", "E,p", 0x49a00000, 0xffe00000, CBD|RD_C2, 0, I32R6},
3f493883
YK		 1365{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1366{"cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1367{"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1368{"cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1369{"cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1370{"cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1371{"cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1372{"cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1373{"cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1374{"cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1375{"cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1376{"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1377{"cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1378{"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1379{"cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1380{"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1381{"cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1382{"cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1383{"cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1384{"cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1385{"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1386{"cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6},
1387{"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1388{"cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1389{"cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1390{"cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1391{"cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1392{"cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1393{"cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1394{"cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1395{"cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1396{"cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1397{"cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1398{"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1399{"cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1400{"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1401{"cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1402{"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1403{"cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1404{"cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1405{"cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1406{"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1407{"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
1408{"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6},
01bc435b
YK		 1409{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I32R6},
1410{"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I32R6},
1411{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I32R6},
1412{"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I32R6},
99029be1
YK		 1413{"ginvi", "v", 0x7c00003d, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6},
1414{"ginvt", "v", 0x7c0000bd, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6},
1415{"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1416{"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1417{"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1418{"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6},
1419{"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1420{"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1421{"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6},
1422{"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6},
ed8a933f
YK		 1423
1424/* MSA */
1425{"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426{"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427{"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428{"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1429{"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1430{"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1431{"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1432{"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1433{"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1434{"sra.h", "+d,+e,+f", 0x78a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1435{"sra.w", "+d,+e,+f", 0x78c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1436{"sra.d", "+d,+e,+f", 0x78e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1437{"srai.b", "+d,+e,+7", 0x78f00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1438{"srai.h", "+d,+e,+8", 0x78e00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1439{"srai.w", "+d,+e,+9", 0x78c00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1440{"srai.d", "+d,+e,'", 0x78800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1441{"srl.b", "+d,+e,+f", 0x7900000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1442{"srl.h", "+d,+e,+f", 0x7920000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1443{"srl.w", "+d,+e,+f", 0x7940000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1444{"srl.d", "+d,+e,+f", 0x7960000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1445{"srli.b", "+d,+e,+7", 0x79700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1446{"srli.h", "+d,+e,+8", 0x79600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1447{"srli.w", "+d,+e,+9", 0x79400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1448{"srli.d", "+d,+e,'", 0x79000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1449{"bclr.b", "+d,+e,+f", 0x7980000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1450{"bclr.h", "+d,+e,+f", 0x79a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1451{"bclr.w", "+d,+e,+f", 0x79c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1452{"bclr.d", "+d,+e,+f", 0x79e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1453{"bclri.b", "+d,+e,+7", 0x79f00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1454{"bclri.h", "+d,+e,+8", 0x79e00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1455{"bclri.w", "+d,+e,+9", 0x79c00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1456{"bclri.d", "+d,+e,'", 0x79800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1457{"bset.b", "+d,+e,+f", 0x7a00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1458{"bset.h", "+d,+e,+f", 0x7a20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1459{"bset.w", "+d,+e,+f", 0x7a40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1460{"bset.d", "+d,+e,+f", 0x7a60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1461{"bseti.b", "+d,+e,+7", 0x7a700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1462{"bseti.h", "+d,+e,+8", 0x7a600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1463{"bseti.w", "+d,+e,+9", 0x7a400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1464{"bseti.d", "+d,+e,'", 0x7a000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1465{"bneg.b", "+d,+e,+f", 0x7a80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1466{"bneg.h", "+d,+e,+f", 0x7aa0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1467{"bneg.w", "+d,+e,+f", 0x7ac0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1468{"bneg.d", "+d,+e,+f", 0x7ae0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1469{"bnegi.b", "+d,+e,+7", 0x7af00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1470{"bnegi.h", "+d,+e,+8", 0x7ae00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1471{"bnegi.w", "+d,+e,+9", 0x7ac00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1472{"bnegi.d", "+d,+e,'", 0x7a800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1473{"binsl.b", "+d,+e,+f", 0x7b00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1474{"binsl.h", "+d,+e,+f", 0x7b20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1475{"binsl.w", "+d,+e,+f", 0x7b40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1476{"binsl.d", "+d,+e,+f", 0x7b60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1477{"binsli.b", "+d,+e,+7", 0x7b700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1478{"binsli.h", "+d,+e,+8", 0x7b600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1479{"binsli.w", "+d,+e,+9", 0x7b400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1480{"binsli.d", "+d,+e,'", 0x7b000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1481{"binsr.b", "+d,+e,+f", 0x7b80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1482{"binsr.h", "+d,+e,+f", 0x7ba0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1483{"binsr.w", "+d,+e,+f", 0x7bc0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1484{"binsr.d", "+d,+e,+f", 0x7be0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1485{"binsri.b", "+d,+e,+7", 0x7bf00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1486{"binsri.h", "+d,+e,+8", 0x7be00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1487{"binsri.w", "+d,+e,+9", 0x7bc00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1488{"binsri.d", "+d,+e,'", 0x7b800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1489{"addv.b", "+d,+e,+f", 0x7800000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1490{"addv.h", "+d,+e,+f", 0x7820000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1491{"addv.w", "+d,+e,+f", 0x7840000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1492{"addv.d", "+d,+e,+f", 0x7860000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1493{"addvi.b", "+d,+e,k", 0x78000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1494{"addvi.h", "+d,+e,k", 0x78200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1495{"addvi.w", "+d,+e,k", 0x78400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1496{"addvi.d", "+d,+e,k", 0x78600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1497{"subv.b", "+d,+e,+f", 0x7880000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1498{"subv.h", "+d,+e,+f", 0x78a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1499{"subv.w", "+d,+e,+f", 0x78c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1500{"subv.d", "+d,+e,+f", 0x78e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1501{"subvi.b", "+d,+e,k", 0x78800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1502{"subvi.h", "+d,+e,k", 0x78a00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1503{"subvi.w", "+d,+e,k", 0x78c00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1504{"subvi.d", "+d,+e,k", 0x78e00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1505{"max_s.b", "+d,+e,+f", 0x7900000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1506{"max_s.h", "+d,+e,+f", 0x7920000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1507{"max_s.w", "+d,+e,+f", 0x7940000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1508{"max_s.d", "+d,+e,+f", 0x7960000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1509{"maxi_s.b", "+d,+e,+5", 0x79000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1510{"maxi_s.h", "+d,+e,+5", 0x79200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1511{"maxi_s.w", "+d,+e,+5", 0x79400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1512{"maxi_s.d", "+d,+e,+5", 0x79600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1513{"max_u.b", "+d,+e,+f", 0x7980000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1514{"max_u.h", "+d,+e,+f", 0x79a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1515{"max_u.w", "+d,+e,+f", 0x79c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1516{"max_u.d", "+d,+e,+f", 0x79e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1517{"maxi_u.b", "+d,+e,k", 0x79800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1518{"maxi_u.h", "+d,+e,k", 0x79a00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1519{"maxi_u.w", "+d,+e,k", 0x79c00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1520{"maxi_u.d", "+d,+e,k", 0x79e00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1521{"min_s.b", "+d,+e,+f", 0x7a00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1522{"min_s.h", "+d,+e,+f", 0x7a20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1523{"min_s.w", "+d,+e,+f", 0x7a40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1524{"min_s.d", "+d,+e,+f", 0x7a60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1525{"mini_s.b", "+d,+e,+5", 0x7a000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1526{"mini_s.h", "+d,+e,+5", 0x7a200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1527{"mini_s.w", "+d,+e,+5", 0x7a400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1528{"mini_s.d", "+d,+e,+5", 0x7a600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1529{"min_u.b", "+d,+e,+f", 0x7a80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1530{"min_u.h", "+d,+e,+f", 0x7aa0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1531{"min_u.w", "+d,+e,+f", 0x7ac0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1532{"min_u.d", "+d,+e,+f", 0x7ae0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1533{"mini_u.b", "+d,+e,k", 0x7a800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1534{"mini_u.h", "+d,+e,k", 0x7aa00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1535{"mini_u.w", "+d,+e,k", 0x7ac00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1536{"mini_u.d", "+d,+e,k", 0x7ae00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1537{"max_a.b", "+d,+e,+f", 0x7b00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1538{"max_a.h", "+d,+e,+f", 0x7b20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1539{"max_a.w", "+d,+e,+f", 0x7b40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1540{"max_a.d", "+d,+e,+f", 0x7b60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1541{"min_a.b", "+d,+e,+f", 0x7b80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1542{"min_a.h", "+d,+e,+f", 0x7ba0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1543{"min_a.w", "+d,+e,+f", 0x7bc0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1544{"min_a.d", "+d,+e,+f", 0x7be0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1545{"ceq.b", "+d,+e,+f", 0x7800000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1546{"ceq.h", "+d,+e,+f", 0x7820000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1547{"ceq.w", "+d,+e,+f", 0x7840000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1548{"ceq.d", "+d,+e,+f", 0x7860000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1549{"ceqi.b", "+d,+e,+5", 0x78000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1550{"ceqi.h", "+d,+e,+5", 0x78200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1551{"ceqi.w", "+d,+e,+5", 0x78400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1552{"ceqi.d", "+d,+e,+5", 0x78600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1553{"clt_s.b", "+d,+e,+f", 0x7900000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1554{"clt_s.h", "+d,+e,+f", 0x7920000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1555{"clt_s.w", "+d,+e,+f", 0x7940000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1556{"clt_s.d", "+d,+e,+f", 0x7960000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1557{"clti_s.b", "+d,+e,+5", 0x79000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1558{"clti_s.h", "+d,+e,+5", 0x79200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1559{"clti_s.w", "+d,+e,+5", 0x79400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1560{"clti_s.d", "+d,+e,+5", 0x79600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1561{"clt_u.b", "+d,+e,+f", 0x7980000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1562{"clt_u.h", "+d,+e,+f", 0x79a0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1563{"clt_u.w", "+d,+e,+f", 0x79c0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1564{"clt_u.d", "+d,+e,+f", 0x79e0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1565{"clti_u.b", "+d,+e,k", 0x79800007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1566{"clti_u.h", "+d,+e,k", 0x79a00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1567{"clti_u.w", "+d,+e,k", 0x79c00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1568{"clti_u.d", "+d,+e,k", 0x79e00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1569{"cle_s.b", "+d,+e,+f", 0x7a00000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1570{"cle_s.h", "+d,+e,+f", 0x7a20000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1571{"cle_s.w", "+d,+e,+f", 0x7a40000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1572{"cle_s.d", "+d,+e,+f", 0x7a60000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1573{"clei_s.b", "+d,+e,+5", 0x7a000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1574{"clei_s.h", "+d,+e,+5", 0x7a200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1575{"clei_s.w", "+d,+e,+5", 0x7a400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1576{"clei_s.d", "+d,+e,+5", 0x7a600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1577{"cle_u.b", "+d,+e,+f", 0x7a80000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1578{"cle_u.h", "+d,+e,+f", 0x7aa0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1579{"cle_u.w", "+d,+e,+f", 0x7ac0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1580{"cle_u.d", "+d,+e,+f", 0x7ae0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1581{"clei_u.b", "+d,+e,k", 0x7a800007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1582{"clei_u.h", "+d,+e,k", 0x7aa00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1583{"clei_u.w", "+d,+e,k", 0x7ac00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1584{"clei_u.d", "+d,+e,k", 0x7ae00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1585{"ld.b", "+d,+^(d)", 0x78000020, 0xfc00003f, WR_VD|LDD, RD_d, MSA},
1586{"ld.h", "+d,+#(d)", 0x78000021, 0xfc00003f, WR_VD|LDD, RD_d, MSA},
1587{"ld.w", "+d,+$(d)", 0x78000022, 0xfc00003f, WR_VD|LDD, RD_d, MSA},
1588{"ld.d", "+d,+%(d)", 0x78000023, 0xfc00003f, WR_VD|LDD, RD_d, MSA},
1589{"st.b", "+d,+^(d)", 0x78000024, 0xfc00003f, RD_VD|SM, RD_d, MSA},
1590{"st.h", "+d,+#(d)", 0x78000025, 0xfc00003f, RD_VD|SM, RD_d, MSA},
1591{"st.w", "+d,+$(d)", 0x78000026, 0xfc00003f, RD_VD|SM, RD_d, MSA},
1592{"st.d", "+d,+%(d)", 0x78000027, 0xfc00003f, RD_VD|SM, RD_d, MSA},
1593{"sat_s.b", "+d,+e,+7", 0x7870000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1594{"sat_s.h", "+d,+e,+8", 0x7860000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1595{"sat_s.w", "+d,+e,+9", 0x7840000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1596{"sat_s.d", "+d,+e,'", 0x7800000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1597{"sat_u.b", "+d,+e,+7", 0x78f0000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1598{"sat_u.h", "+d,+e,+8", 0x78e0000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1599{"sat_u.w", "+d,+e,+9", 0x78c0000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1600{"sat_u.d", "+d,+e,'", 0x7880000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1601{"add_a.b", "+d,+e,+f", 0x78000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1602{"add_a.h", "+d,+e,+f", 0x78200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1603{"add_a.w", "+d,+e,+f", 0x78400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1604{"add_a.d", "+d,+e,+f", 0x78600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1605{"adds_a.b", "+d,+e,+f", 0x78800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1606{"adds_a.h", "+d,+e,+f", 0x78a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1607{"adds_a.w", "+d,+e,+f", 0x78c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1608{"adds_a.d", "+d,+e,+f", 0x78e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1609{"adds_s.b", "+d,+e,+f", 0x79000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1610{"adds_s.h", "+d,+e,+f", 0x79200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1611{"adds_s.w", "+d,+e,+f", 0x79400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1612{"adds_s.d", "+d,+e,+f", 0x79600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1613{"adds_u.b", "+d,+e,+f", 0x79800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1614{"adds_u.h", "+d,+e,+f", 0x79a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1615{"adds_u.w", "+d,+e,+f", 0x79c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1616{"adds_u.d", "+d,+e,+f", 0x79e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1617{"ave_s.b", "+d,+e,+f", 0x7a000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1618{"ave_s.h", "+d,+e,+f", 0x7a200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1619{"ave_s.w", "+d,+e,+f", 0x7a400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1620{"ave_s.d", "+d,+e,+f", 0x7a600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1621{"ave_u.b", "+d,+e,+f", 0x7a800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1622{"ave_u.h", "+d,+e,+f", 0x7aa00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1623{"ave_u.w", "+d,+e,+f", 0x7ac00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1624{"ave_u.d", "+d,+e,+f", 0x7ae00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1625{"aver_s.b", "+d,+e,+f", 0x7b000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1626{"aver_s.h", "+d,+e,+f", 0x7b200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1627{"aver_s.w", "+d,+e,+f", 0x7b400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1628{"aver_s.d", "+d,+e,+f", 0x7b600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1629{"aver_u.b", "+d,+e,+f", 0x7b800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1630{"aver_u.h", "+d,+e,+f", 0x7ba00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1631{"aver_u.w", "+d,+e,+f", 0x7bc00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1632{"aver_u.d", "+d,+e,+f", 0x7be00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1633{"subs_s.b", "+d,+e,+f", 0x78000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1634{"subs_s.h", "+d,+e,+f", 0x78200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1635{"subs_s.w", "+d,+e,+f", 0x78400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1636{"subs_s.d", "+d,+e,+f", 0x78600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1637{"subs_u.b", "+d,+e,+f", 0x78800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1638{"subs_u.h", "+d,+e,+f", 0x78a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1639{"subs_u.w", "+d,+e,+f", 0x78c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1640{"subs_u.d", "+d,+e,+f", 0x78e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1641{"subsus_u.b", "+d,+e,+f", 0x79000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1642{"subsus_u.h", "+d,+e,+f", 0x79200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1643{"subsus_u.w", "+d,+e,+f", 0x79400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1644{"subsus_u.d", "+d,+e,+f", 0x79600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1645{"subsuu_s.b", "+d,+e,+f", 0x79800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1646{"subsuu_s.h", "+d,+e,+f", 0x79a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1647{"subsuu_s.w", "+d,+e,+f", 0x79c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1648{"subsuu_s.d", "+d,+e,+f", 0x79e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1649{"asub_s.b", "+d,+e,+f", 0x7a000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1650{"asub_s.h", "+d,+e,+f", 0x7a200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1651{"asub_s.w", "+d,+e,+f", 0x7a400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1652{"asub_s.d", "+d,+e,+f", 0x7a600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1653{"asub_u.b", "+d,+e,+f", 0x7a800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1654{"asub_u.h", "+d,+e,+f", 0x7aa00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1655{"asub_u.w", "+d,+e,+f", 0x7ac00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1656{"asub_u.d", "+d,+e,+f", 0x7ae00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1657{"mulv.b", "+d,+e,+f", 0x78000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1658{"mulv.h", "+d,+e,+f", 0x78200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1659{"mulv.w", "+d,+e,+f", 0x78400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1660{"mulv.d", "+d,+e,+f", 0x78600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1661{"maddv.b", "+d,+e,+f", 0x78800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1662{"maddv.h", "+d,+e,+f", 0x78a00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1663{"maddv.w", "+d,+e,+f", 0x78c00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1664{"maddv.d", "+d,+e,+f", 0x78e00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1665{"msubv.b", "+d,+e,+f", 0x79000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1666{"msubv.h", "+d,+e,+f", 0x79200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1667{"msubv.w", "+d,+e,+f", 0x79400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1668{"msubv.d", "+d,+e,+f", 0x79600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1669{"div_s.b", "+d,+e,+f", 0x7a000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1670{"div_s.h", "+d,+e,+f", 0x7a200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1671{"div_s.w", "+d,+e,+f", 0x7a400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1672{"div_s.d", "+d,+e,+f", 0x7a600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1673{"div_u.b", "+d,+e,+f", 0x7a800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1674{"div_u.h", "+d,+e,+f", 0x7aa00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1675{"div_u.w", "+d,+e,+f", 0x7ac00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1676{"div_u.d", "+d,+e,+f", 0x7ae00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1677{"mod_s.b", "+d,+e,+f", 0x7b000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1678{"mod_s.h", "+d,+e,+f", 0x7b200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1679{"mod_s.w", "+d,+e,+f", 0x7b400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1680{"mod_s.d", "+d,+e,+f", 0x7b600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1681{"mod_u.b", "+d,+e,+f", 0x7b800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1682{"mod_u.h", "+d,+e,+f", 0x7ba00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1683{"mod_u.w", "+d,+e,+f", 0x7bc00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1684{"mod_u.d", "+d,+e,+f", 0x7be00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1685{"dotp_s.h", "+d,+e,+f", 0x78200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1686{"dotp_s.w", "+d,+e,+f", 0x78400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1687{"dotp_s.d", "+d,+e,+f", 0x78600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1688{"dotp_u.h", "+d,+e,+f", 0x78a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1689{"dotp_u.w", "+d,+e,+f", 0x78c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1690{"dotp_u.d", "+d,+e,+f", 0x78e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1691{"dpadd_s.h", "+d,+e,+f", 0x79200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1692{"dpadd_s.w", "+d,+e,+f", 0x79400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1693{"dpadd_s.d", "+d,+e,+f", 0x79600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1694{"dpadd_u.h", "+d,+e,+f", 0x79a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1695{"dpadd_u.w", "+d,+e,+f", 0x79c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1696{"dpadd_u.d", "+d,+e,+f", 0x79e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1697{"dpsub_s.h", "+d,+e,+f", 0x7a200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1698{"dpsub_s.w", "+d,+e,+f", 0x7a400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1699{"dpsub_s.d", "+d,+e,+f", 0x7a600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1700{"dpsub_u.h", "+d,+e,+f", 0x7aa00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1701{"dpsub_u.w", "+d,+e,+f", 0x7ac00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1702{"dpsub_u.d", "+d,+e,+f", 0x7ae00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1703{"sld.b", "+d,+e[t]", 0x78000014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1704{"sld.h", "+d,+e[t]", 0x78200014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1705{"sld.w", "+d,+e[t]", 0x78400014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1706{"sld.d", "+d,+e[t]", 0x78600014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1707{"sldi.b", "+d,+e[+9]", 0x78000019, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1708{"sldi.h", "+d,+e[+8]", 0x78200019, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1709{"sldi.w", "+d,+e[+7]", 0x78300019, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1710{"sldi.d", "+d,+e[+6]", 0x78380019, 0xfffc003f, WR_VD|RD_VS, 0, MSA},
1711{"splat.b", "+d,+e[t]", 0x78800014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1712{"splat.h", "+d,+e[t]", 0x78a00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1713{"splat.w", "+d,+e[t]", 0x78c00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1714{"splat.d", "+d,+e[t]", 0x78e00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA},
1715{"splati.b", "+d,+e[+9]", 0x78400019, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1716{"splati.h", "+d,+e[+8]", 0x78600019, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1717{"splati.w", "+d,+e[+7]", 0x78700019, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1718{"splati.d", "+d,+e[+6]", 0x78780019, 0xfffc003f, WR_VD|RD_VS, 0, MSA},
1719{"pckev.b", "+d,+e,+f", 0x79000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1720{"pckev.h", "+d,+e,+f", 0x79200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1721{"pckev.w", "+d,+e,+f", 0x79400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1722{"pckev.d", "+d,+e,+f", 0x79600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1723{"pckod.b", "+d,+e,+f", 0x79800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1724{"pckod.h", "+d,+e,+f", 0x79a00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1725{"pckod.w", "+d,+e,+f", 0x79c00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1726{"pckod.d", "+d,+e,+f", 0x79e00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1727{"ilvl.b", "+d,+e,+f", 0x7a000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1728{"ilvl.h", "+d,+e,+f", 0x7a200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1729{"ilvl.w", "+d,+e,+f", 0x7a400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1730{"ilvl.d", "+d,+e,+f", 0x7a600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1731{"ilvr.b", "+d,+e,+f", 0x7a800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1732{"ilvr.h", "+d,+e,+f", 0x7aa00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1733{"ilvr.w", "+d,+e,+f", 0x7ac00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1734{"ilvr.d", "+d,+e,+f", 0x7ae00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1735{"ilvev.b", "+d,+e,+f", 0x7b000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1736{"ilvev.h", "+d,+e,+f", 0x7b200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1737{"ilvev.w", "+d,+e,+f", 0x7b400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1738{"ilvev.d", "+d,+e,+f", 0x7b600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1739{"ilvod.b", "+d,+e,+f", 0x7b800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1740{"ilvod.h", "+d,+e,+f", 0x7ba00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1741{"ilvod.w", "+d,+e,+f", 0x7bc00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1742{"ilvod.d", "+d,+e,+f", 0x7be00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1743{"vshf.b", "+d,+e,+f", 0x78000015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1744{"vshf.h", "+d,+e,+f", 0x78200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1745{"vshf.w", "+d,+e,+f", 0x78400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1746{"vshf.d", "+d,+e,+f", 0x78600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1747{"srar.b", "+d,+e,+f", 0x78800015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1748{"srar.h", "+d,+e,+f", 0x78a00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1749{"srar.w", "+d,+e,+f", 0x78c00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1750{"srar.d", "+d,+e,+f", 0x78e00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1751{"srari.b", "+d,+e,+7", 0x7970000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1752{"srari.h", "+d,+e,+8", 0x7960000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1753{"srari.w", "+d,+e,+9", 0x7940000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1754{"srari.d", "+d,+e,'", 0x7900000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1755{"srlr.b", "+d,+e,+f", 0x79000015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1756{"srlr.h", "+d,+e,+f", 0x79200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1757{"srlr.w", "+d,+e,+f", 0x79400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1758{"srlr.d", "+d,+e,+f", 0x79600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1759{"srlri.b", "+d,+e,+7", 0x79f0000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1760{"srlri.h", "+d,+e,+8", 0x79e0000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1761{"srlri.w", "+d,+e,+9", 0x79c0000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1762{"srlri.d", "+d,+e,'", 0x7980000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1763{"hadd_s.h", "+d,+e,+f", 0x7a200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1764{"hadd_s.w", "+d,+e,+f", 0x7a400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1765{"hadd_s.d", "+d,+e,+f", 0x7a600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1766{"hadd_u.h", "+d,+e,+f", 0x7aa00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1767{"hadd_u.w", "+d,+e,+f", 0x7ac00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1768{"hadd_u.d", "+d,+e,+f", 0x7ae00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1769{"hsub_s.h", "+d,+e,+f", 0x7b200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1770{"hsub_s.w", "+d,+e,+f", 0x7b400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1771{"hsub_s.d", "+d,+e,+f", 0x7b600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1772{"hsub_u.h", "+d,+e,+f", 0x7ba00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1773{"hsub_u.w", "+d,+e,+f", 0x7bc00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1774{"hsub_u.d", "+d,+e,+f", 0x7be00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1775{"and.v", "+d,+e,+f", 0x7800001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1776{"andi.b", "+d,+e,5", 0x78000000, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1777{"or.v", "+d,+e,+f", 0x7820001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1778{"ori.b", "+d,+e,5", 0x79000000, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1779{"nor.v", "+d,+e,+f", 0x7840001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1780{"nori.b", "+d,+e,5", 0x7a000000, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1781{"xor.v", "+d,+e,+f", 0x7860001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1782{"xori.b", "+d,+e,5", 0x7b000000, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1783{"bmnz.v", "+d,+e,+f", 0x7880001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1784{"bmnzi.b", "+d,+e,5", 0x78000001, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1785{"bmz.v", "+d,+e,+f", 0x78a0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1786{"bmzi.b", "+d,+e,5", 0x79000001, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1787{"bsel.v", "+d,+e,+f", 0x78c0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1788{"bseli.b", "+d,+e,5", 0x7a000001, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1789{"shf.b", "+d,+e,5", 0x78000002, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1790{"shf.h", "+d,+e,5", 0x79000002, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1791{"shf.w", "+d,+e,5", 0x7a000002, 0xff00003f, WR_VD|RD_VS, 0, MSA},
1792{"bnz.v", "+f,p", 0x45e00000, 0xffe00000, CBD|RD_VT, 0, MSA},
1793{"bz.v", "+f,p", 0x45600000, 0xffe00000, CBD|RD_VT, 0, MSA},
1794{"fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_VD, RD_d, MSA},
1795{"fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_VD, RD_d, MSA},
1796{"fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_VD, RD_d, MSA},
1797{"fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_VD, RD_d, MSA64},
1798{"pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1799{"pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1800{"pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1801{"pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1802{"nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1803{"nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1804{"nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1805{"nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1806{"nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1807{"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1808{"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1809{"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1810{"copy_s.b", "+i,+e[+9]", 0x78800019, 0xffe0003f, RD_VS, RD_rd6, MSA},
1811{"copy_s.h", "+i,+e[+8]", 0x78a00019, 0xfff0003f, RD_VS, RD_rd6, MSA},
1812{"copy_s.w", "+i,+e[+7]", 0x78b00019, 0xfff8003f, RD_VS, RD_rd6, MSA},
1813{"copy_s.d", "+i,+e[+6]", 0x78b80019, 0xfffc003f, RD_VS, RD_rd6, MSA64},
1814{"copy_u.b", "+i,+e[+9]", 0x78c00019, 0xffe0003f, RD_VS, RD_rd6, MSA},
1815{"copy_u.h", "+i,+e[+8]", 0x78e00019, 0xfff0003f, RD_VS, RD_rd6, MSA},
1816{"copy_u.w", "+i,+e[+7]", 0x78f00019, 0xfff8003f, RD_VS, RD_rd6, MSA},
1817{"copy_u.d", "+i,+e[+6]", 0x78f80019, 0xfffc003f, RD_VS, RD_rd6, MSA64},
1818{"insert.b", "+d[+9],d", 0x79000019, 0xffe0003f, WR_VD|RD_VD, RD_d, MSA},
1819{"insert.h", "+d[+8],d", 0x79200019, 0xfff0003f, WR_VD|RD_VD, RD_d, MSA},
1820{"insert.w", "+d[+7],d", 0x79300019, 0xfff8003f, WR_VD|RD_VD, RD_d, MSA},
1821{"insert.d", "+d[+6],d", 0x79380019, 0xfffc003f, WR_VD|RD_VD, RD_d, MSA64},
1822{"insve.b", "+d[+9],+e[+~]", 0x79400019, 0xffe0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1823{"insve.h", "+d[+8],+e[+~]", 0x79600019, 0xfff0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1824{"insve.w", "+d[+7],+e[+~]", 0x79700019, 0xfff8003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1825{"insve.d", "+d[+6],+e[+~]", 0x79780019, 0xfffc003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1826{"bnz.b", "+f,p", 0x47800000, 0xffe00000, CBD|RD_VT, 0, MSA},
1827{"bnz.h", "+f,p", 0x47a00000, 0xffe00000, CBD|RD_VT, 0, MSA},
1828{"bnz.w", "+f,p", 0x47c00000, 0xffe00000, CBD|RD_VT, 0, MSA},
1829{"bnz.d", "+f,p", 0x47e00000, 0xffe00000, CBD|RD_VT, 0, MSA},
1830{"bz.b", "+f,p", 0x47000000, 0xffe00000, CBD|RD_VT, 0, MSA},
1831{"bz.h", "+f,p", 0x47200000, 0xffe00000, CBD|RD_VT, 0, MSA},
1832{"bz.w", "+f,p", 0x47400000, 0xffe00000, CBD|RD_VT, 0, MSA},
1833{"bz.d", "+f,p", 0x47600000, 0xffe00000, CBD|RD_VT, 0, MSA},
1834{"ldi.b", "+d,+0", 0x7b000007, 0xffe0003f, WR_VD, 0, MSA},
1835{"ldi.h", "+d,+0", 0x7b200007, 0xffe0003f, WR_VD, 0, MSA},
1836{"ldi.w", "+d,+0", 0x7b400007, 0xffe0003f, WR_VD, 0, MSA},
1837{"ldi.d", "+d,+0", 0x7b600007, 0xffe0003f, WR_VD, 0, MSA},
1838{"fcaf.w", "+d,+e,+f", 0x7800001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1839{"fcaf.d", "+d,+e,+f", 0x7820001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1840{"fcun.w", "+d,+e,+f", 0x7840001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1841{"fcun.d", "+d,+e,+f", 0x7860001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1842{"fceq.w", "+d,+e,+f", 0x7880001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1843{"fceq.d", "+d,+e,+f", 0x78a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1844{"fcueq.w", "+d,+e,+f", 0x78c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1845{"fcueq.d", "+d,+e,+f", 0x78e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1846{"fclt.w", "+d,+e,+f", 0x7900001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1847{"fclt.d", "+d,+e,+f", 0x7920001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1848{"fcult.w", "+d,+e,+f", 0x7940001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1849{"fcult.d", "+d,+e,+f", 0x7960001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1850{"fcle.w", "+d,+e,+f", 0x7980001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1851{"fcle.d", "+d,+e,+f", 0x79a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1852{"fcule.w", "+d,+e,+f", 0x79c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1853{"fcule.d", "+d,+e,+f", 0x79e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1854{"fsaf.w", "+d,+e,+f", 0x7a00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1855{"fsaf.d", "+d,+e,+f", 0x7a20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1856{"fsun.w", "+d,+e,+f", 0x7a40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1857{"fsun.d", "+d,+e,+f", 0x7a60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1858{"fseq.w", "+d,+e,+f", 0x7a80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1859{"fseq.d", "+d,+e,+f", 0x7aa0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1860{"fsueq.w", "+d,+e,+f", 0x7ac0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1861{"fsueq.d", "+d,+e,+f", 0x7ae0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1862{"fslt.w", "+d,+e,+f", 0x7b00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1863{"fslt.d", "+d,+e,+f", 0x7b20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1864{"fsult.w", "+d,+e,+f", 0x7b40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1865{"fsult.d", "+d,+e,+f", 0x7b60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1866{"fsle.w", "+d,+e,+f", 0x7b80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1867{"fsle.d", "+d,+e,+f", 0x7ba0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1868{"fsule.w", "+d,+e,+f", 0x7bc0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1869{"fsule.d", "+d,+e,+f", 0x7be0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1870{"fadd.w", "+d,+e,+f", 0x7800001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1871{"fadd.d", "+d,+e,+f", 0x7820001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1872{"fsub.w", "+d,+e,+f", 0x7840001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1873{"fsub.d", "+d,+e,+f", 0x7860001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1874{"fmul.w", "+d,+e,+f", 0x7880001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1875{"fmul.d", "+d,+e,+f", 0x78a0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1876{"fdiv.w", "+d,+e,+f", 0x78c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1877{"fdiv.d", "+d,+e,+f", 0x78e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1878{"fmadd.w", "+d,+e,+f", 0x7900001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1879{"fmadd.d", "+d,+e,+f", 0x7920001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1880{"fmsub.w", "+d,+e,+f", 0x7940001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1881{"fmsub.d", "+d,+e,+f", 0x7960001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1882{"fexp2.w", "+d,+e,+f", 0x79c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1883{"fexp2.d", "+d,+e,+f", 0x79e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1884{"fexdo.h", "+d,+e,+f", 0x7a00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1885{"fexdo.w", "+d,+e,+f", 0x7a20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1886{"ftq.h", "+d,+e,+f", 0x7a80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1887{"ftq.w", "+d,+e,+f", 0x7aa0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1888{"fmin.w", "+d,+e,+f", 0x7b00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1889{"fmin.d", "+d,+e,+f", 0x7b20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1890{"fmin_a.w", "+d,+e,+f", 0x7b40001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1891{"fmin_a.d", "+d,+e,+f", 0x7b60001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1892{"fmax.w", "+d,+e,+f", 0x7b80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1893{"fmax.d", "+d,+e,+f", 0x7ba0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1894{"fmax_a.w", "+d,+e,+f", 0x7bc0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1895{"fmax_a.d", "+d,+e,+f", 0x7be0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1896{"fcor.w", "+d,+e,+f", 0x7840001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1897{"fcor.d", "+d,+e,+f", 0x7860001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1898{"fcune.w", "+d,+e,+f", 0x7880001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1899{"fcune.d", "+d,+e,+f", 0x78a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1900{"fcne.w", "+d,+e,+f", 0x78c0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1901{"fcne.d", "+d,+e,+f", 0x78e0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1902{"mul_q.h", "+d,+e,+f", 0x7900001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1903{"mul_q.w", "+d,+e,+f", 0x7920001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1904{"madd_q.h", "+d,+e,+f", 0x7940001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1905{"madd_q.w", "+d,+e,+f", 0x7960001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1906{"msub_q.h", "+d,+e,+f", 0x7980001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1907{"msub_q.w", "+d,+e,+f", 0x79a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1908{"fsor.w", "+d,+e,+f", 0x7a40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1909{"fsor.d", "+d,+e,+f", 0x7a60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1910{"fsune.w", "+d,+e,+f", 0x7a80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1911{"fsune.d", "+d,+e,+f", 0x7aa0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1912{"fsne.w", "+d,+e,+f", 0x7ac0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1913{"fsne.d", "+d,+e,+f", 0x7ae0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1914{"mulr_q.h", "+d,+e,+f", 0x7b00001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1915{"mulr_q.w", "+d,+e,+f", 0x7b20001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1916{"maddr_q.h", "+d,+e,+f", 0x7b40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1917{"maddr_q.w", "+d,+e,+f", 0x7b60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1918{"msubr_q.h", "+d,+e,+f", 0x7b80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1919{"msubr_q.w", "+d,+e,+f", 0x7ba0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1920{"fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1921{"fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1922{"fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1923{"fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1924{"frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1925{"frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1926{"frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1927{"frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1928{"frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1929{"frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1930{"flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1931{"flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1932{"fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1933{"fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1934{"fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1935{"fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1936{"ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1937{"ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1938{"ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1939{"ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1940{"ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1941{"ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1942{"ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1943{"ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1944{"ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1945{"ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1946{"ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1947{"ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1948{"ftrunc_s.w", "+d,+e", 0x7b40001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1949{"ftrunc_s.d", "+d,+e", 0x7b41001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1950{"ftrunc_u.w", "+d,+e", 0x7b42001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1951{"ftrunc_u.d", "+d,+e", 0x7b43001e, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1952{"ctcmsa", "+h,d", 0x783e0019, 0xffff003f, COD, RD_d, MSA},
1953{"cfcmsa", "+i,+g", 0x787e0019, 0xffff003f, COD, 0, MSA},
1954{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_VD|RD_VS, 0, MSA},
1955{"lsa", "d,v,t,+@", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, MSA},
1956{"dlsa", "d,v,t,+@", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, MSA64},
1957
29490584
TS		 1958{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
1959{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
1960{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
1961{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
1962{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
1963{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
1964{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
1965{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
1966{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
1967{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
1968{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
1969{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
1970{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
1971{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
1972{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
1973
1974{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
1975{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1976{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1977{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1978{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1979{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
1980{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1981{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1982{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1983{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1984{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1985{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1986{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1987{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1988{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1989{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1990{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1991{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1992{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1993{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1994{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1995{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1996{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
1997{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1998{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
1999{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2000{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2001{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
2002{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
2003{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2004{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
2005{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2006{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2007{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2008{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2009{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2010{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
6643d27e
FB		 2011/* b is at the top of the table. */
2012/* bal is at the top of the table. */
29490584
TS		 2013/* bc0[tf]l? are at the bottom of the table. */
2014{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
2015{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
2016{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
2017{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
2018{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
2019{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
2020{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
2021{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
2022{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
2023{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
2024{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
2025{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
6643d27e 2026/* bc2* are at the bottom of the table. */
29490584
TS		 2027/* bc3* are at the bottom of the table. */
2028{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2029{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2030{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
2031{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
2032{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
2033{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
2034{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
2035{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
2036{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
2037{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
2038{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
2039{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
2040{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
2041{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
2042{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2043{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2044{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
2045{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
2046{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
2047{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
2048{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
2049{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
2050{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
2051{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
2052{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
2053{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
2054{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2055{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2056{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
2057{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
2058{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
2059{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
2060{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
2061{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
2062{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
2063{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
2064{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2065{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2066{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
2067{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
2068{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
2069{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
2070{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
2071{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
2072{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
2073{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
2074{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2075{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2076{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
2077{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
2078{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
2079{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
2080{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
2081{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
2082{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
2083{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
2084{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
2085{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
2086{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
2087{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2088{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2089{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2090{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2091{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2092{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2093{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2094{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2095{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2096{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2097{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2098{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2099{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2100{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2101{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2102{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2103{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
2104{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2105{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2106{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2107{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2108{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2109{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
2110{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2111{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2112{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2113{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2114{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2115{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2116{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2117{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2118{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2119{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2120{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2121{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2122{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2123{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2124{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2125{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2126{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2127{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2128{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2129{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2130{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2131{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2132{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2133{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2134{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2135{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2136{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2137{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2138{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2139{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2140{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2141{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2142{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2143{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2144{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2145{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2146{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2147{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2148{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2149{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2150{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2151{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2152{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2153{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2154{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2155{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2156{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2157{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2158{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2159{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2160{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2161{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2162{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2163{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2164{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2165{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2166{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2167{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2168{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
2169{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2170{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2171{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2172{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2173{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2174{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
2175{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2176{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2177{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2178{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2179{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2180{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2181{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2182{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2183{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2184{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2185{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
2186{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2187{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2188{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2189{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2190{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2191{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
2192{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
2193{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
2194{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
2195{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
2196{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2197{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
2198{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2199{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2200{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2201{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2202{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2203{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2204{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2205{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2206{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2207{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2208{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2209{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2210{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2211{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2212{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2213{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2214{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2215{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2216{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2217{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2218{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2219{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2220{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2221{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2222{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2223{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2224{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2225{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2226{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2227{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2228{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2229{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2230{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2231{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2232{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2233{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2234{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2235{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2236{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2237{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2238{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2239{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2240{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2241{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2242{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2243{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2244{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
2245{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
2246/* CW4010 instructions which are aliases for the cache instruction. */
2247{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
2248{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
2249{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
2250{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
2251{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
2252{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
2253{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2254{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2255{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2256{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
5204ea79
LA		 2257{"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I33},
2258{"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I33},
29490584
TS		 2259{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
2260{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
2261{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
6643d27e 2262/* cfc2 is at the bottom of the table. */
29490584
TS		 2263/* cfc3 is at the bottom of the table. */
2264{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
2265{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
2266{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
2267{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
2268{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
2269{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2270{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
2271{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
6643d27e 2272/* ctc2 is at the bottom of the table. */
29490584
TS		 2273/* ctc3 is at the bottom of the table. */
2274{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
2275{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
2276{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
2277{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2278{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
2279{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
2280{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2281{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2282{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2283{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
2284{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2285{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
2286{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
2287{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
2288{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2289{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
2290{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
2291{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
2292{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
2293{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
2294{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
2295{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
2296{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
2297{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
2298{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
2299{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
2300{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
2301{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
6643d27e 2302/* dctr and dctw are used on the r5000. */
29490584
TS		 2303{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
2304{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
2305{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
2306{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
2307{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
2308{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
2309{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
6643d27e 2310/* For ddiv, see the comments about div. */
29490584
TS		 2311{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2312{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
2313{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
6643d27e 2314/* For ddivu, see the comments about div. */
29490584
TS		 2315{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2316{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
2317{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
2318{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
2319{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
2320{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
2321{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
2322{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
2323{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 },
6643d27e
FB		 2324/* The MIPS assembler treats the div opcode with two operands as
2325 though the first operand appeared twice (the first operand is both
2326 a source and a destination). To get the div machine instruction,
2327 you must use an explicit destination of $0. */
29490584
TS		 2328{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2329{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2330{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
2331{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
2332{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2333{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2334{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
6643d27e 2335/* For divu, see the comments about div. */
29490584
TS		 2336{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2337{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2338{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
2339{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
2340{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
2341{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
2342{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
2343{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */
2344{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
2345{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2346{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2347{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2348{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2349{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2350{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2351{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2352{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
2353{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
2354{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
2355{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
2356{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
2357{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
2358{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
2359{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
2360{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
2361{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
2362{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
2363{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
2364{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
2365{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
6643d27e
FB		 2366/* dmfc2 is at the bottom of the table. */
2367/* dmtc2 is at the bottom of the table. */
29490584
TS		 2368/* dmfc3 is at the bottom of the table. */
2369/* dmtc3 is at the bottom of the table. */
2370{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
2371{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
2372{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
2373{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
2374{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
2375{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
2376{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2377{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2378{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
2379{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
2380{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2381{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 },
2382{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
2383{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
2384{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
2385{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
2386{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
2387{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
2388{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
2389{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
2390{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
2391{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
2392{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 },
2393{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
2394{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
2395{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
2396{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
2397{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
2398{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 },
2399{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
2400{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
2401{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 },
2402{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
2403{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 },
2404{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
2405{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
2406{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
2407{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
2408{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
2409{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
2410{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
2411{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
2412{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
2413{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
2414{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
2415{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
2416{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
2417{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
2418{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
2419{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
2420{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
2421{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
2422{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
2423{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
2424{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
2425{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
2426{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
2427{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
ce9782f4 2428{"eretnc", "", 0x42000058, 0xffffffff, 0, 0, I33},
29490584
TS		 2429{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
2430{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
2431{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
2432{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2433{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2434{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2435{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2436{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
2437{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
2438{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
d76f3653 2439{"jr", "s", 0x00000009, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr */
29490584
TS		 2440/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
2441 the same hazard barrier effect. */
2442{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
d76f3653 2443{"jr.hb", "s", 0x00000409, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr.hb */
29490584 2444{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
6643d27e
FB		 2445/* SVR4 PIC code requires special handling for j, so it must be a
2446 macro. */
29490584 2447{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
6643d27e
FB		 2448/* This form of j is used by the disassembler and internally by the
2449 assembler, but will never match user input (because the line above
2450 will match first). */
29490584
TS		 2451{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
2452{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
2453{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
2454/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
2455 with the same hazard barrier effect. */
2456{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 },
2457{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 },
6643d27e
FB		 2458/* SVR4 PIC code requires special handling for jal, so it must be a
2459 macro. */
29490584
TS		 2460{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
2461{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
2462{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
6643d27e
FB		 2463/* This form of jal is used by the disassembler and internally by the
2464 assembler, but will never match user input (because the line above
2465 will match first). */
29490584
TS		 2466{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
2467{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
2468{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
2469{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2470{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
2471{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2472{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
2473{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
2474{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
2475{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
2476{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
2477{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
2478{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
2479{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
2480{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
2481{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
2482{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
2483{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
2484{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
2485{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
2486{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
2487{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
2488{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
2489{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
2490{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
2491{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
2492{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
2493{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2494{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
2495{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2496{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
6643d27e 2497/* li is at the start of the table. */
29490584
TS		 2498{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
2499{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
2500{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
2501{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
2502{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
2503{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
2504{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
2505{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
2506{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
d4ea6acd 2507{"aui", "s,t,u", 0x3c000000, 0xfc000000, RD_s|WR_t, 0, I32R6},
29490584
TS		 2508{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
2509{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2510{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
2511{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
2512{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
2513{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
2514{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
2515{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
2516{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
2517{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
2518{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
2519{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
2520{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
2521{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
2522{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
2523{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2524{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
2525{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
2526{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
2527{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
2528{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
2529{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
2530{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
2531{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
2532{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
2533{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
2534{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
2535{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
2536{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2537{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2538{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2539{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2540{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2541{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2542{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2543{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2544{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2545{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2546{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2547{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
2548{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
2549{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
2550{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2551{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2552{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2553{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2554{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2555{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
2556{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2557{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2558{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2559{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2560{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2561{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
2562{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2563{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2564{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
2565{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2566{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2567{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2568{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2569{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2570{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
2571{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
2572{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
2573{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
2574{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
2575{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
2576{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
2577{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
2578{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
2579{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
2580{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
2581{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
2582{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
2583{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
2584{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
2585{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
2586{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
2587{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
2588{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
2589{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
2590{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
2591{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
2592{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
2593{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
2594{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
2595{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
2596{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
6643d27e
FB		 2597/* mfc2 is at the bottom of the table. */
2598/* mfhc2 is at the bottom of the table. */
29490584
TS		 2599/* mfc3 is at the bottom of the table. */
2600{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
2601{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
2602{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
2603{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
2604{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
2605{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
2606{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2607{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2608{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2609{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2610{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2611{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2612{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2613{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2614{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
2615{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
2616{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2617{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2618{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
2619{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
2620{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
2621{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2622{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
2623{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2624{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2625{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
2626{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
2627{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
2628{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
2629{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2630{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
2631{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
2632{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
2633{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
2634{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
2635{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
2636{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2637{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
2638{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
2639{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
2640{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2641{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2642{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2643{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
6643d27e 2644/* move is at the top of the table. */
29490584
TS		 2645{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2646{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2647{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2648{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2649{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2650{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2651{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2652{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
2653{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
2654{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2655{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
2656{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
2657{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
2658{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
2659{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
2660{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
2661{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
2662{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
2663{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
6643d27e
FB		 2664/* mtc2 is at the bottom of the table. */
2665/* mthc2 is at the bottom of the table. */
29490584
TS		 2666/* mtc3 is at the bottom of the table. */
2667{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
2668{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
2669{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
2670{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
2671{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
2672{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
2673{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2674{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2675{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
2676{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
2677{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
2678{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
2679{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2680{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2681{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
2682{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
2683{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
2684{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
2685{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
2686{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2687{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2688{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
2689{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
2690{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
2691{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2692{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2693{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2694{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2695{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2696{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2697{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2698{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2699{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
2700{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
2701{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
2702{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
2703{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2704{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2705{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2706{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2707{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2708{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2709{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2710{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2711{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2712{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2713{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2714{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2715{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
2716{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
2717{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
2718{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
2719{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2720{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2721{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2722{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2723{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2724{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2725{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2726{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2727{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2728{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2729{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2730{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2731{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2732{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2733{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2734{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2735{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2736{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2737{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2738{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2739{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2740{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2741{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2742{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
2743{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
2744{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2745{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2746{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2747{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2748{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2749{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2750{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2751{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2752{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
6643d27e 2753/* nop is at the start of the table. */
29490584
TS		 2754{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2755{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
2756{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2757{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2758{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2759{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2760{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2761{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
2762{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2763{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2764{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2765{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2766{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2767{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2768{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2769{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2770{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2771{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
2772{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2773{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2774{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2775{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2776{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2777{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2778{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2779{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2780{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2781{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2782{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2783{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2784{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
6643d27e 2785 /* pref and prefx are at the start of the table. */
29490584
TS		 2786{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2787{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2788{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2789{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2790{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
2791{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2792{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2793{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 },
2794{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2795{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2796{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
2797{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2798{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2799{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2800{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2801{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2802{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2803{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2804{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2805{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2806{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2807{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2808{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
2809{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
2810{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2811{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
2812{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
2813{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
2814{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
2815{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
2816{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2817{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2818{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2819{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2820{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2821{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2822{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
2823{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
2824{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
2825{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
2826{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2827{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2828{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
2829{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
2830{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
2831{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
2832{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
2833{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2834{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2835{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2836{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2837{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2838{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2839{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2840{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2841{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2842{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2843{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2844{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2845{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2846{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2847{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2848{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
2849{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2850{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2851{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
2852{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
2853{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
2854{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
2855{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
2856{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2857{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
2858{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
2859{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
2860{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
2861{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
2862{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
2863{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
2864{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2865{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2866{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2867{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2868{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
2869{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
2870{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
2871{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
2872{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2873{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
2874{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
2875{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2876{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
2877{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2878{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
2879{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
2880{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
2881{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
2882{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2883{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2884{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
2885{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
2886{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
2887{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
2888{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
2889{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
2890{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
2891{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
2892{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
2893{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2894{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2895{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
2896{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2897{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2898{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2899{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2900{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2901{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2902{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2903{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2904{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2905{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2906{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2907{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2908{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2909{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2910{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
2911{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
2912{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
2913{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
2914{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2915{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
2916{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
2917{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2918{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2919{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2920{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2921{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2922{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
2923{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2924{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2925{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2926{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
2927{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
2928{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
2929{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
2930{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2931{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2932{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2933{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
2934{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
2935{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2936{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2937{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
2938{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
2939{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2940{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2941{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2942{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
6643d27e 2943/* ssnop is at the start of the table. */
29490584
TS		 2944{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
2945{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2946{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
2947{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2948{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2949{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2950{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2951{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2952{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2953{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2954{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2955{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2956{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2957{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2958{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2959{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2960{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
2961{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
2962{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
2963{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2964{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
2965{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
2966{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
2967{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2968{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2969{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2970{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2971{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
2972{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2973{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
2974{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
2975{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
2976{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
2977{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2978{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2979{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2980{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
2981{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2982{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
2983{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2984{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
2985{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
2986{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
2987{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
2988{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
2989{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
2990{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
2991{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
2992{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2993{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2994{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2995{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */
2996{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 },
2997{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2998{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2999{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
3000{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */
3001{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 },
3002{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
3003{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
3004{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
3005{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
3006{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
3007{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
3008{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
3009{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
9456c2fb
LA		 3010{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I32 },
3011{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I32 },
29490584
TS		 3012{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
3013{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
3014{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
3015{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
3016{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */
3017{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 },
3018{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
3019{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
3020{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
3021{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */
3022{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 },
3023{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
3024{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
3025{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
3026{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
3027{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 },
3028{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
3029{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
3030{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
3031{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
3032{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
3033{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
3034{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
3035{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
3036{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
3037{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
3038{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
3039{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
3040{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
3041{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
3042{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
3043{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
3044{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
3045{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
3046{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
3047{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
3048{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
3049{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
3050{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
3051{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
3052{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
3053{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
3054{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
3055{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
3056{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 },
3057{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
3058{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
3059{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
3060{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
3061{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
3062{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
3063{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
3064{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
3065{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
3066{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
3067{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
3068{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
3069{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
3070{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
3071
3072/* User Defined Instruction. */
3073{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3074{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3075{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3076{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3077{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3078{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3079{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3080{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3081{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3082{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3083{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3084{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3085{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3086{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3087{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3088{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3089{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3090{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3091{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3092{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3093{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3094{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3095{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3096{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3097{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3098{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3099{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3100{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3101{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3102{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3103{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3104{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3105{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3106{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3107{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3108{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3109{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3110{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3111{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3112{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3113{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3114{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3115{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3116{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3117{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3118{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3119{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3120{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3121{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3122{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3123{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3124{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3125{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3126{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3127{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3128{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3129{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3130{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3131{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3132{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3133{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3134{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3135{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
3136{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
6643d27e
FB		 3137
3138/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
3139 instructions so they are here for the latters to take precedence. */
29490584
TS		 3140{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
3141{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
3142{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
3143{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
3144{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
3145{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
3146{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
3147{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
3148{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
3149{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
3150{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
3151{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
3152{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
3153{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
3154{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
3155{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
3156{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
3157{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
3158{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
3159{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
3160{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
3161{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
3162{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
3163{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
3164
3165/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
3166 instructions, so they are here for the latters to take precedence. */
3167{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
3168{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
3169{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
3170{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
3171{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
3172{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
3173{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
3174{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
3175{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
3176{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
3177{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
3178{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
6643d27e
FB		 3179
3180/* No hazard protection on coprocessor instructions--they shouldn't
3181 change the state of the processor and if they do it's up to the
3182 user to put in nops as necessary. These are at the end so that the
3183 disassembler recognizes more specific versions first. */
29490584
TS		 3184{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
3185{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
3186{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
3187{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
3188{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
3189{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
3190{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
3191{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
6643d27e
FB		 3192 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
3193 4010 any more, so move this insn out of the way. If the object
3194 format gave us more info, we could do this right. */
29490584
TS		 3195{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 },
3196/* MIPS DSP ASE */
3197{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 },
3198{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 },
3199{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 },
3200{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 },
3201{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3202{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3203{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3204{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3205{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3206{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3207{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3208{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3209{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3210{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3211{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3212{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3213{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3214{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
3215{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
3216{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
3217{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3218{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3219{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3220{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3221{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3222{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3223{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3224{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3225{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3226{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3227{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3228{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3229{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3230{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3231{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3232{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3233{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3234{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3235{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3236{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 },
3237{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 },
3238{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 },
3239{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 },
3240{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3241{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3242{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3243{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3244{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3245{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3246{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3247{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3248{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3249{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3250{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3251{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3252{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3253{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3254{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
3255{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
3256{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 },
3257{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3258{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3259{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3260{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3261{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 },
3262{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3263{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3264{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3265{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3266{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3267{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3268{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3269{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3270{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3271{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3272{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3273{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3274{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3275{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3276{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3277{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3278{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 },
3279{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 },
3280{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 },
3281{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
3282{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
3283{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
3284{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
3285{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
3286{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
3287{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
3288{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
3289{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
3290{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
3291{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
3292{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
3293{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
3294{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
3295{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
3296{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
3297{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3298{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3299{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3300{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3301{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3302{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3303{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3304{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3305{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3306{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3307{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3308{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3309{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3310{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3311{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3312{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
3313{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
3314{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
3315{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
3316{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
3317{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
3318{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
3319{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
3320{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
3321{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
3322{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
3323{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3324{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
3325{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
3326{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3327{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3328{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3329{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3330{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3331{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3332{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3333{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 },
3334{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 },
3335{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3336{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 },
3337{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 },
3338{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 },
3339{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 },
3340{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 },
3341{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
3342{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 },
3343{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 },
3344{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 },
3345{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3346{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 },
3347{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 },
3348{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 },
3349{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 },
3350{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 },
3351{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
3352{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 },
3353{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 },
3354{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 },
3355{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3356{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 },
3357{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3358{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3359{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3360{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3361{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3362{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3363{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3364{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3365{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3366{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 },
3367{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 },
3368{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 },
3369{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 },
3370{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 },
3371{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 },
3372{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 },
3373{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 },
3374{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 },
3375{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3376{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
3377{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3378{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
3379{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
3380{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 },
3381{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 },
3382{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 },
3383{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 },
3384{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 },
3385{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 },
3386{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 },
3387{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 },
3388{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 },
3389{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 },
3390{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 },
3391{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3392{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3393{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3394{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3395{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3396{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3397{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3398{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3399{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3400{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 },
3401{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 },
3402{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 },
3403{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 },
3404{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 },
3405{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 },
3406{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 },
3407{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3408{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3409{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3410{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3411{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3412{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3413{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3414{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 },
3415{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 },
3416{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3417{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3418{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3419{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3420{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3421{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3422{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3423{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3424{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3425{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3426{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3427{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
3428{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
3429{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
3430{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
3431/* MIPS DSP ASE Rev2 */
3432{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
3433{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3434{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3435{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3436{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3437{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
3438{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
3439{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
3440{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3441{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3442{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3443{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3444{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3445{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
3446{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
3447{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
3448{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
3449{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
3450{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3451{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3452{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
3453{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
3454{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
3455{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
3456{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
3457{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3458{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3459{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
3460{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3461{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3462{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3463{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3464{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3465{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3466{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3467{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3468{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3469{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3470{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3471{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3472{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
3473{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3474{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3475{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3476{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3477{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3478{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
3479/* Move bc0* after mftr and mttr to avoid opcode collision. */
3480{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
3481{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
3482{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
3483{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
15656e09
AJ		 3484/* ST Microelectronics Loongson-2E and -2F. */
3485{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3486{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3487{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3488{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3489{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3490{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3491{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3492{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3493{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3494{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3495{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3496{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3497{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3498{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3499{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3500{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3501{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3502{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3503{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3504{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3505{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3506{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
3507{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
3508{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
6643d27e
FB		 3509};
3510
3511#define MIPS_NUM_OPCODES \
3512 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
3513const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
3514
3515/* const removed from the following to allow for dynamic extensions to the
3516 * built-in instruction set. */
3517struct mips_opcode *mips_opcodes =
3518 (struct mips_opcode *) mips_builtin_opcodes;
3519int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
3520#undef MIPS_NUM_OPCODES
3521
6643d27e
FB		 3522/* Mips instructions are at maximum this many bytes long. */
3523#define INSNLEN 4
3524
6643d27e
FB		 3525\f
3526/* FIXME: These should be shared with gdb somehow. */
3527
52da07d1
TS		 3528struct mips_cp0sel_name
3529{
3530 unsigned int cp0reg;
3531 unsigned int sel;
3532 const char * const name;
6643d27e
FB		 3533};
3534
8ef39152 3535#if 0
52da07d1
TS		 3536/* The mips16 registers. */
3537static const unsigned int mips16_to_32_reg_map[] =
3538{
3539 16, 17, 2, 3, 4, 5, 6, 7
6643d27e
FB		 3540};
3541
52da07d1 3542#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
8ef39152 3543#endif
52da07d1
TS		 3544
3545static const char * const mips_gpr_names_numeric[32] =
3546{
6643d27e
FB		 3547 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3548 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3549 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3550 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3551};
3552
52da07d1
TS		 3553static const char * const mips_gpr_names_oldabi[32] =
3554{
6643d27e
FB		 3555 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
3556 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
3557 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3558 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
3559};
3560
52da07d1
TS		 3561static const char * const mips_gpr_names_newabi[32] =
3562{
6643d27e
FB		 3563 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
3564 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
3565 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3566 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
3567};
3568
52da07d1
TS		 3569static const char * const mips_fpr_names_numeric[32] =
3570{
6643d27e
FB		 3571 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
3572 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
3573 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
3574 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
3575};
3576
52da07d1
TS		 3577static const char * const mips_fpr_names_32[32] =
3578{
6643d27e
FB		 3579 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
3580 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
3581 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
3582 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
3583};
3584
52da07d1
TS		 3585static const char * const mips_fpr_names_n32[32] =
3586{
6643d27e
FB		 3587 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
3588 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
3589 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
3590 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
3591};
3592
52da07d1
TS		 3593static const char * const mips_fpr_names_64[32] =
3594{
6643d27e
FB		 3595 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
3596 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
3597 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
3598 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
3599};
3600
ed8a933f
YK		 3601static const char * const mips_wr_names[32] = {
3602 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3603 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3604 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3605 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "w31"
3606};
3607
52da07d1
TS		 3608static const char * const mips_cp0_names_numeric[32] =
3609{
6643d27e
FB		 3610 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3611 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3612 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3613 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3614};
3615
52da07d1
TS		 3616static const char * const mips_cp0_names_mips3264[32] =
3617{
6643d27e
FB		 3618 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3619 "c0_context", "c0_pagemask", "c0_wired", "$7",
3620 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3621 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3622 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3623 "c0_xcontext", "$21", "$22", "c0_debug",
3624 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
3625 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
3626};
3627
52da07d1
TS		 3628static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3629{
3630 { 4, 1, "c0_contextconfig" },
3631 { 0, 1, "c0_mvpcontrol" },
3632 { 0, 2, "c0_mvpconf0" },
3633 { 0, 3, "c0_mvpconf1" },
3634 { 1, 1, "c0_vpecontrol" },
3635 { 1, 2, "c0_vpeconf0" },
3636 { 1, 3, "c0_vpeconf1" },
3637 { 1, 4, "c0_yqmask" },
3638 { 1, 5, "c0_vpeschedule" },
3639 { 1, 6, "c0_vpeschefback" },
3640 { 2, 1, "c0_tcstatus" },
3641 { 2, 2, "c0_tcbind" },
3642 { 2, 3, "c0_tcrestart" },
3643 { 2, 4, "c0_tchalt" },
3644 { 2, 5, "c0_tccontext" },
3645 { 2, 6, "c0_tcschedule" },
3646 { 2, 7, "c0_tcschefback" },
3647 { 5, 1, "c0_pagegrain" },
3648 { 6, 1, "c0_srsconf0" },
3649 { 6, 2, "c0_srsconf1" },
3650 { 6, 3, "c0_srsconf2" },
3651 { 6, 4, "c0_srsconf3" },
3652 { 6, 5, "c0_srsconf4" },
3653 { 12, 1, "c0_intctl" },
3654 { 12, 2, "c0_srsctl" },
3655 { 12, 3, "c0_srsmap" },
3656 { 15, 1, "c0_ebase" },
6643d27e
FB		 3657 { 16, 1, "c0_config1" },
3658 { 16, 2, "c0_config2" },
3659 { 16, 3, "c0_config3" },
3660 { 18, 1, "c0_watchlo,1" },
3661 { 18, 2, "c0_watchlo,2" },
3662 { 18, 3, "c0_watchlo,3" },
3663 { 18, 4, "c0_watchlo,4" },
3664 { 18, 5, "c0_watchlo,5" },
3665 { 18, 6, "c0_watchlo,6" },
3666 { 18, 7, "c0_watchlo,7" },
3667 { 19, 1, "c0_watchhi,1" },
3668 { 19, 2, "c0_watchhi,2" },
3669 { 19, 3, "c0_watchhi,3" },
3670 { 19, 4, "c0_watchhi,4" },
3671 { 19, 5, "c0_watchhi,5" },
3672 { 19, 6, "c0_watchhi,6" },
3673 { 19, 7, "c0_watchhi,7" },
52da07d1
TS		 3674 { 23, 1, "c0_tracecontrol" },
3675 { 23, 2, "c0_tracecontrol2" },
3676 { 23, 3, "c0_usertracedata" },
3677 { 23, 4, "c0_tracebpc" },
6643d27e
FB		 3678 { 25, 1, "c0_perfcnt,1" },
3679 { 25, 2, "c0_perfcnt,2" },
3680 { 25, 3, "c0_perfcnt,3" },
3681 { 25, 4, "c0_perfcnt,4" },
3682 { 25, 5, "c0_perfcnt,5" },
3683 { 25, 6, "c0_perfcnt,6" },
3684 { 25, 7, "c0_perfcnt,7" },
3685 { 27, 1, "c0_cacheerr,1" },
3686 { 27, 2, "c0_cacheerr,2" },
3687 { 27, 3, "c0_cacheerr,3" },
3688 { 28, 1, "c0_datalo" },
52da07d1
TS		 3689 { 28, 2, "c0_taglo1" },
3690 { 28, 3, "c0_datalo1" },
3691 { 28, 4, "c0_taglo2" },
3692 { 28, 5, "c0_datalo2" },
3693 { 28, 6, "c0_taglo3" },
3694 { 28, 7, "c0_datalo3" },
3695 { 29, 1, "c0_datahi" },
3696 { 29, 2, "c0_taghi1" },
3697 { 29, 3, "c0_datahi1" },
3698 { 29, 4, "c0_taghi2" },
3699 { 29, 5, "c0_datahi2" },
3700 { 29, 6, "c0_taghi3" },
3701 { 29, 7, "c0_datahi3" },
6643d27e
FB		 3702};
3703
52da07d1
TS		 3704static const char * const mips_cp0_names_mips3264r2[32] =
3705{
6643d27e
FB		 3706 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3707 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
3708 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3709 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3710 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3711 "c0_xcontext", "$21", "$22", "c0_debug",
3712 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
3713 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
3714};
3715
52da07d1
TS		 3716static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
3717{
6643d27e
FB		 3718 { 4, 1, "c0_contextconfig" },
3719 { 5, 1, "c0_pagegrain" },
3720 { 12, 1, "c0_intctl" },
3721 { 12, 2, "c0_srsctl" },
3722 { 12, 3, "c0_srsmap" },
3723 { 15, 1, "c0_ebase" },
3724 { 16, 1, "c0_config1" },
3725 { 16, 2, "c0_config2" },
3726 { 16, 3, "c0_config3" },
3727 { 18, 1, "c0_watchlo,1" },
3728 { 18, 2, "c0_watchlo,2" },
3729 { 18, 3, "c0_watchlo,3" },
3730 { 18, 4, "c0_watchlo,4" },
3731 { 18, 5, "c0_watchlo,5" },
3732 { 18, 6, "c0_watchlo,6" },
3733 { 18, 7, "c0_watchlo,7" },
3734 { 19, 1, "c0_watchhi,1" },
3735 { 19, 2, "c0_watchhi,2" },
3736 { 19, 3, "c0_watchhi,3" },
3737 { 19, 4, "c0_watchhi,4" },
3738 { 19, 5, "c0_watchhi,5" },
3739 { 19, 6, "c0_watchhi,6" },
3740 { 19, 7, "c0_watchhi,7" },
3741 { 23, 1, "c0_tracecontrol" },
3742 { 23, 2, "c0_tracecontrol2" },
3743 { 23, 3, "c0_usertracedata" },
3744 { 23, 4, "c0_tracebpc" },
3745 { 25, 1, "c0_perfcnt,1" },
3746 { 25, 2, "c0_perfcnt,2" },
3747 { 25, 3, "c0_perfcnt,3" },
3748 { 25, 4, "c0_perfcnt,4" },
3749 { 25, 5, "c0_perfcnt,5" },
3750 { 25, 6, "c0_perfcnt,6" },
3751 { 25, 7, "c0_perfcnt,7" },
3752 { 27, 1, "c0_cacheerr,1" },
3753 { 27, 2, "c0_cacheerr,2" },
3754 { 27, 3, "c0_cacheerr,3" },
3755 { 28, 1, "c0_datalo" },
3756 { 28, 2, "c0_taglo1" },
3757 { 28, 3, "c0_datalo1" },
3758 { 28, 4, "c0_taglo2" },
3759 { 28, 5, "c0_datalo2" },
3760 { 28, 6, "c0_taglo3" },
3761 { 28, 7, "c0_datalo3" },
3762 { 29, 1, "c0_datahi" },
3763 { 29, 2, "c0_taghi1" },
3764 { 29, 3, "c0_datahi1" },
3765 { 29, 4, "c0_taghi2" },
3766 { 29, 5, "c0_datahi2" },
3767 { 29, 6, "c0_taghi3" },
3768 { 29, 7, "c0_datahi3" },
3769};
3770
3771/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
52da07d1
TS		 3772static const char * const mips_cp0_names_sb1[32] =
3773{
6643d27e
FB		 3774 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3775 "c0_context", "c0_pagemask", "c0_wired", "$7",
3776 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3777 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3778 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3779 "c0_xcontext", "$21", "$22", "c0_debug",
3780 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
3781 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
3782};
3783
52da07d1
TS		 3784static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3785{
6643d27e
FB		 3786 { 16, 1, "c0_config1" },
3787 { 18, 1, "c0_watchlo,1" },
3788 { 19, 1, "c0_watchhi,1" },
3789 { 22, 0, "c0_perftrace" },
3790 { 23, 3, "c0_edebug" },
3791 { 25, 1, "c0_perfcnt,1" },
3792 { 25, 2, "c0_perfcnt,2" },
3793 { 25, 3, "c0_perfcnt,3" },
3794 { 25, 4, "c0_perfcnt,4" },
3795 { 25, 5, "c0_perfcnt,5" },
3796 { 25, 6, "c0_perfcnt,6" },
3797 { 25, 7, "c0_perfcnt,7" },
3798 { 26, 1, "c0_buserr_pa" },
3799 { 27, 1, "c0_cacheerr_d" },
3800 { 27, 3, "c0_cacheerr_d_pa" },
3801 { 28, 1, "c0_datalo_i" },
3802 { 28, 2, "c0_taglo_d" },
3803 { 28, 3, "c0_datalo_d" },
3804 { 29, 1, "c0_datahi_i" },
3805 { 29, 2, "c0_taghi_d" },
3806 { 29, 3, "c0_datahi_d" },
3807};
3808
52da07d1
TS		 3809static const char * const mips_hwr_names_numeric[32] =
3810{
6643d27e
FB		 3811 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3812 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3813 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3814 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3815};
3816
52da07d1
TS		 3817static const char * const mips_hwr_names_mips3264r2[32] =
3818{
6643d27e
FB		 3819 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
3820 "$4", "$5", "$6", "$7",
3821 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3822 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3823 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3824};
3825
ed8a933f
YK		 3826static const char * const mips_msa_control_names_mips3264r2[32] = {
3827 "MSAIR", "MSACSR", "$2", "$3", "$4", "$5", "$6", "$7",
3828 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3829 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3830 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3831};
3832
52da07d1
TS		 3833struct mips_abi_choice
3834{
6643d27e
FB		 3835 const char *name;
3836 const char * const *gpr_names;
3837 const char * const *fpr_names;
3838};
3839
72139e83 3840static struct mips_abi_choice mips_abi_choices[] =
52da07d1 3841{
6643d27e
FB		 3842 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3843 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3844 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3845 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3846};
3847
52da07d1
TS		 3848struct mips_arch_choice
3849{
6643d27e
FB		 3850 const char *name;
3851 int bfd_mach_valid;
3852 unsigned long bfd_mach;
3853 int processor;
3854 int isa;
3855 const char * const *cp0_names;
3856 const struct mips_cp0sel_name *cp0sel_names;
3857 unsigned int cp0sel_names_len;
3858 const char * const *hwr_names;
3859};
3860
3861#define bfd_mach_mips3000 3000
3862#define bfd_mach_mips3900 3900
3863#define bfd_mach_mips4000 4000
3864#define bfd_mach_mips4010 4010
3865#define bfd_mach_mips4100 4100
3866#define bfd_mach_mips4111 4111
3867#define bfd_mach_mips4120 4120
3868#define bfd_mach_mips4300 4300
3869#define bfd_mach_mips4400 4400
3870#define bfd_mach_mips4600 4600
3871#define bfd_mach_mips4650 4650
3872#define bfd_mach_mips5000 5000
3873#define bfd_mach_mips5400 5400
3874#define bfd_mach_mips5500 5500
3875#define bfd_mach_mips6000 6000
3876#define bfd_mach_mips7000 7000
3877#define bfd_mach_mips8000 8000
52da07d1 3878#define bfd_mach_mips9000 9000
6643d27e
FB		 3879#define bfd_mach_mips10000 10000
3880#define bfd_mach_mips12000 12000
3881#define bfd_mach_mips16 16
3882#define bfd_mach_mips5 5
3883#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
3884#define bfd_mach_mipsisa32 32
3885#define bfd_mach_mipsisa32r2 33
3886#define bfd_mach_mipsisa64 64
3887#define bfd_mach_mipsisa64r2 65
3888
72139e83 3889static const struct mips_arch_choice mips_arch_choices[] =
52da07d1 3890{
6643d27e
FB		 3891 { "numeric", 0, 0, 0, 0,
3892 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3893
3894 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3895 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3896 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3897 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3898 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3899 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3900 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3901 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3902 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3903 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3904 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3905 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3906 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3907 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3908 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3909 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3910 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3911 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3912 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3913 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3914 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3915 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3916 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3917 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3918 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3919 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3920 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3921 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3922 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3923 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3924 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3925 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3926 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3927 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3928 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3929 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3930 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3931 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3932 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3933 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3934 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3935 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3936
3937 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3938 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
3939 _MIPS32 Architecture For Programmers Volume I: Introduction to the
3940 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3941 page 1. */
3942 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
52da07d1 3943 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
6643d27e
FB		 3944 mips_cp0_names_mips3264,
3945 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3946 mips_hwr_names_numeric },
3947
3948 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
52da07d1 3949 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
ed8a933f 3950 | INSN_MIPS3D | INSN_MT | INSN_MSA),
6643d27e
FB		 3951 mips_cp0_names_mips3264r2,
3952 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3953 mips_hwr_names_mips3264r2 },
3954
3955 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
3956 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
3957 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3958 mips_cp0_names_mips3264,
3959 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3960 mips_hwr_names_numeric },
3961
3962 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
52da07d1
TS		 3963 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3964 | INSN_DSP64 | INSN_MT | INSN_MDMX),
6643d27e
FB		 3965 mips_cp0_names_mips3264r2,
3966 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3967 mips_hwr_names_mips3264r2 },
3968
3969 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
3970 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3971 mips_cp0_names_sb1,
3972 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3973 mips_hwr_names_numeric },
3974
3975 /* This entry, mips16, is here only for ISA/processor selection; do
3976 not print its name. */
3977 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3978 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3979};
3980
3981/* ISA and processor type to disassemble for, and register names to use.
3982 set_default_mips_dis_options and parse_mips_dis_options fill in these
3983 values. */
3984static int mips_processor;
3985static int mips_isa;
3986static const char * const *mips_gpr_names;
3987static const char * const *mips_fpr_names;
3988static const char * const *mips_cp0_names;
3989static const struct mips_cp0sel_name *mips_cp0sel_names;
3990static int mips_cp0sel_names_len;
3991static const char * const *mips_hwr_names;
3992
52da07d1
TS		 3993/* Other options */
3994static int no_aliases; /* If set disassemble as most general inst. */
6643d27e
FB		 3995\f
3996static const struct mips_abi_choice *
52da07d1 3997choose_abi_by_name (const char *name, unsigned int namelen)
6643d27e
FB		 3998{
3999 const struct mips_abi_choice *c;
4000 unsigned int i;
4001
4002 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
52da07d1
TS		 4003 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
4004 && strlen (mips_abi_choices[i].name) == namelen)
4005 c = &mips_abi_choices[i];
4006
6643d27e
FB		 4007 return c;
4008}
4009
4010static const struct mips_arch_choice *
52da07d1 4011choose_arch_by_name (const char *name, unsigned int namelen)
6643d27e
FB		 4012{
4013 const struct mips_arch_choice *c = NULL;
4014 unsigned int i;
4015
4016 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
52da07d1
TS		 4017 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
4018 && strlen (mips_arch_choices[i].name) == namelen)
4019 c = &mips_arch_choices[i];
4020
6643d27e
FB		 4021 return c;
4022}
4023
4024static const struct mips_arch_choice *
52da07d1 4025choose_arch_by_number (unsigned long mach)
6643d27e
FB		 4026{
4027 static unsigned long hint_bfd_mach;
4028 static const struct mips_arch_choice *hint_arch_choice;
4029 const struct mips_arch_choice *c;
4030 unsigned int i;
4031
4032 /* We optimize this because even if the user specifies no
4033 flags, this will be done for every instruction! */
4034 if (hint_bfd_mach == mach
4035 && hint_arch_choice != NULL
4036 && hint_arch_choice->bfd_mach == hint_bfd_mach)
4037 return hint_arch_choice;
4038
4039 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
4040 {
4041 if (mips_arch_choices[i].bfd_mach_valid
4042 && mips_arch_choices[i].bfd_mach == mach)
4043 {
4044 c = &mips_arch_choices[i];
4045 hint_bfd_mach = mach;
4046 hint_arch_choice = c;
4047 }
4048 }
4049 return c;
4050}
4051
f9480ffc 4052static void
52da07d1 4053set_default_mips_dis_options (struct disassemble_info *info)
6643d27e
FB		 4054{
4055 const struct mips_arch_choice *chosen_arch;
4056
4057 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
4058 and numeric FPR, CP0 register, and HWR names. */
4059 mips_isa = ISA_MIPS3;
4060 mips_processor = CPU_R3000;
4061 mips_gpr_names = mips_gpr_names_oldabi;
4062 mips_fpr_names = mips_fpr_names_numeric;
4063 mips_cp0_names = mips_cp0_names_numeric;
4064 mips_cp0sel_names = NULL;
4065 mips_cp0sel_names_len = 0;
4066 mips_hwr_names = mips_hwr_names_numeric;
52da07d1 4067 no_aliases = 0;
6643d27e
FB		 4068
4069 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
4070#if 0
4071 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
4072 {
4073 Elf_Internal_Ehdr *header;
4074
4075 header = elf_elfheader (info->section->owner);
4076 if (is_newabi (header))
4077 mips_gpr_names = mips_gpr_names_newabi;
4078 }
4079#endif
4080
4081 /* Set ISA, architecture, and cp0 register names as best we can. */
eb38c52c 4082#if !defined(SYMTAB_AVAILABLE) && 0
6643d27e
FB		 4083 /* This is running out on a target machine, not in a host tool.
4084 FIXME: Where does mips_target_info come from? */
4085 target_processor = mips_target_info.processor;
4086 mips_isa = mips_target_info.isa;
4087#else
4088 chosen_arch = choose_arch_by_number (info->mach);
4089 if (chosen_arch != NULL)
4090 {
4091 mips_processor = chosen_arch->processor;
4092 mips_isa = chosen_arch->isa;
4093 mips_cp0_names = chosen_arch->cp0_names;
4094 mips_cp0sel_names = chosen_arch->cp0sel_names;
4095 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4096 mips_hwr_names = chosen_arch->hwr_names;
4097 }
4098#endif
4099}
4100
f9480ffc 4101static void
a5f1b965 4102parse_mips_dis_option (const char *option, unsigned int len)
6643d27e
FB		 4103{
4104 unsigned int i, optionlen, vallen;
4105 const char *val;
4106 const struct mips_abi_choice *chosen_abi;
4107 const struct mips_arch_choice *chosen_arch;
4108
4109 /* Look for the = that delimits the end of the option name. */
4110 for (i = 0; i < len; i++)
4111 {
4112 if (option[i] == '=')
4113 break;
4114 }
4115 if (i == 0) /* Invalid option: no name before '='. */
4116 return;
4117 if (i == len) /* Invalid option: no '='. */
4118 return;
4119 if (i == (len - 1)) /* Invalid option: no value after '='. */
4120 return;
4121
4122 optionlen = i;
4123 val = option + (optionlen + 1);
4124 vallen = len - (optionlen + 1);
4125
4126 if (strncmp("gpr-names", option, optionlen) == 0
4127 && strlen("gpr-names") == optionlen)
4128 {
4129 chosen_abi = choose_abi_by_name (val, vallen);
4130 if (chosen_abi != NULL)
4131 mips_gpr_names = chosen_abi->gpr_names;
4132 return;
4133 }
4134
4135 if (strncmp("fpr-names", option, optionlen) == 0
4136 && strlen("fpr-names") == optionlen)
4137 {
4138 chosen_abi = choose_abi_by_name (val, vallen);
4139 if (chosen_abi != NULL)
4140 mips_fpr_names = chosen_abi->fpr_names;
4141 return;
4142 }
4143
4144 if (strncmp("cp0-names", option, optionlen) == 0
4145 && strlen("cp0-names") == optionlen)
4146 {
4147 chosen_arch = choose_arch_by_name (val, vallen);
4148 if (chosen_arch != NULL)
4149 {
4150 mips_cp0_names = chosen_arch->cp0_names;
4151 mips_cp0sel_names = chosen_arch->cp0sel_names;
4152 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4153 }
4154 return;
4155 }
4156
4157 if (strncmp("hwr-names", option, optionlen) == 0
4158 && strlen("hwr-names") == optionlen)
4159 {
4160 chosen_arch = choose_arch_by_name (val, vallen);
4161 if (chosen_arch != NULL)
4162 mips_hwr_names = chosen_arch->hwr_names;
4163 return;
4164 }
4165
4166 if (strncmp("reg-names", option, optionlen) == 0
4167 && strlen("reg-names") == optionlen)
4168 {
4169 /* We check both ABI and ARCH here unconditionally, so
4170 that "numeric" will do the desirable thing: select
4171 numeric register names for all registers. Other than
4172 that, a given name probably won't match both. */
4173 chosen_abi = choose_abi_by_name (val, vallen);
4174 if (chosen_abi != NULL)
4175 {
4176 mips_gpr_names = chosen_abi->gpr_names;
4177 mips_fpr_names = chosen_abi->fpr_names;
4178 }
4179 chosen_arch = choose_arch_by_name (val, vallen);
4180 if (chosen_arch != NULL)
4181 {
4182 mips_cp0_names = chosen_arch->cp0_names;
4183 mips_cp0sel_names = chosen_arch->cp0sel_names;
4184 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4185 mips_hwr_names = chosen_arch->hwr_names;
4186 }
4187 return;
4188 }
4189
4190 /* Invalid option. */
4191}
4192
52da07d1
TS		 4193static void
4194parse_mips_dis_options (const char *options)
6643d27e
FB		 4195{
4196 const char *option_end;
4197
4198 if (options == NULL)
4199 return;
4200
4201 while (*options != '\0')
4202 {
4203 /* Skip empty options. */
4204 if (*options == ',')
4205 {
4206 options++;
4207 continue;
4208 }
4209
4210 /* We know that *options is neither NUL or a comma. */
4211 option_end = options + 1;
4212 while (*option_end != ',' && *option_end != '\0')
4213 option_end++;
4214
4215 parse_mips_dis_option (options, option_end - options);
4216
4217 /* Go on to the next one. If option_end points to a comma, it
4218 will be skipped above. */
4219 options = option_end;
4220 }
4221}
4222
4223static const struct mips_cp0sel_name *
52da07d1
TS		 4224lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
4225 unsigned int len,
4226 unsigned int cp0reg,
4227 unsigned int sel)
6643d27e
FB		 4228{
4229 unsigned int i;
4230
4231 for (i = 0; i < len; i++)
4232 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
4233 return &names[i];
4234 return NULL;
4235}
4236\f
4237/* Print insn arguments for 32/64-bit code. */
4238
4239static void
52da07d1
TS		 4240print_insn_args (const char *d,
4241 register unsigned long int l,
4242 bfd_vma pc,
4243 struct disassemble_info *info,
4244 const struct mips_opcode *opp)
6643d27e
FB		 4245{
4246 int op, delta;
4247 unsigned int lsb, msb, msbd;
4248
4249 lsb = 0;
4250
4251 for (; *d != '\0'; d++)
4252 {
4253 switch (*d)
4254 {
4255 case ',':
4256 case '(':
4257 case ')':
4258 case '[':
4259 case ']':
4260 (*info->fprintf_func) (info->stream, "%c", *d);
4261 break;
4262
4263 case '+':
4264 /* Extension character; switch for second char. */
4265 d++;
4266 switch (*d)
4267 {
4268 case '\0':
4269 /* xgettext:c-format */
4270 (*info->fprintf_func) (info->stream,
ca66f1a1 4271 "# internal error, incomplete extension sequence (+)");
6643d27e
FB		 4272 return;
4273
4274 case 'A':
4275 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
4276 (*info->fprintf_func) (info->stream, "0x%x", lsb);
4277 break;
52da07d1 4278
6643d27e
FB		 4279 case 'B':
4280 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
4281 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4282 break;
4283
52da07d1
TS		 4284 case '1':
4285 (*info->fprintf_func) (info->stream, "0x%lx",
4286 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
4287 break;
4288
4289 case '2':
4290 (*info->fprintf_func) (info->stream, "0x%lx",
4291 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
4292 break;
4293
4294 case '3':
4295 (*info->fprintf_func) (info->stream, "0x%lx",
4296 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
4297 break;
4298
4299 case '4':
4300 (*info->fprintf_func) (info->stream, "0x%lx",
4301 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
4302 break;
4303
ed8a933f
YK		 4304 case '5': /* 5-bit signed immediate in bit 16 */
4305 delta = ((l >> OP_SH_RT) & OP_MASK_RT);
4306 if (delta & 0x10) { /* test sign bit */
4307 delta |= ~OP_MASK_RT;
4308 }
4309 (*info->fprintf_func) (info->stream, "%d", delta);
4310 break;
4311
4312 case '6':
4313 (*info->fprintf_func) (info->stream, "0x%lx",
4314 (l >> OP_SH_2BIT) & OP_MASK_2BIT);
4315 break;
4316
4317 case '7':
4318 (*info->fprintf_func) (info->stream, "0x%lx",
4319 (l >> OP_SH_3BIT) & OP_MASK_3BIT);
4320 break;
4321
4322 case '8':
4323 (*info->fprintf_func) (info->stream, "0x%lx",
4324 (l >> OP_SH_4BIT) & OP_MASK_4BIT);
4325 break;
4326
4327 case '9':
4328 (*info->fprintf_func) (info->stream, "0x%lx",
4329 (l >> OP_SH_5BIT) & OP_MASK_5BIT);
4330 break;
4331
4332 case ':':
4333 (*info->fprintf_func) (info->stream, "0x%lx",
4334 (l >> OP_SH_1BIT) & OP_MASK_1BIT);
4335 break;
4336
4337 case '!': /* 10-bit pc-relative target in bit 11 */
4338 delta = ((l >> OP_SH_10BIT) & OP_MASK_10BIT);
4339 if (delta & 0x200) { /* test sign bit */
4340 delta |= ~OP_MASK_10BIT;
4341 }
4342 info->target = (delta << 2) + pc + INSNLEN;
4343 (*info->print_address_func) (info->target, info);
4344 break;
4345
4346 case '~':
4347 (*info->fprintf_func) (info->stream, "0");
4348 break;
4349
4350 case '@':
4351 (*info->fprintf_func) (info->stream, "0x%lx",
4352 ((l >> OP_SH_1_TO_4) & OP_MASK_1_TO_4)+1);
4353 break;
4354
4355 case '^': /* 10-bit signed immediate << 0 in bit 16 */
4356 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4357 if (delta & 0x200) { /* test sign bit */
4358 delta |= ~OP_MASK_IMM10;
4359 }
4360 (*info->fprintf_func) (info->stream, "%d", delta);
4361 break;
4362
4363 case '#': /* 10-bit signed immediate << 1 in bit 16 */
4364 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4365 if (delta & 0x200) { /* test sign bit */
4366 delta |= ~OP_MASK_IMM10;
4367 }
4368 (*info->fprintf_func) (info->stream, "%d", delta << 1);
4369 break;
4370
4371 case '$': /* 10-bit signed immediate << 2 in bit 16 */
4372 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4373 if (delta & 0x200) { /* test sign bit */
4374 delta |= ~OP_MASK_IMM10;
4375 }
4376 (*info->fprintf_func) (info->stream, "%d", delta << 2);
4377 break;
4378
4379 case '%': /* 10-bit signed immediate << 3 in bit 16 */
4380 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4381 if (delta & 0x200) { /* test sign bit */
4382 delta |= ~OP_MASK_IMM10;
4383 }
4384 (*info->fprintf_func) (info->stream, "%d", delta << 3);
4385 break;
4386
6643d27e
FB		 4387 case 'C':
4388 case 'H':
4389 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
4390 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4391 break;
4392
4393 case 'D':
4394 {
4395 const struct mips_cp0sel_name *n;
4396 unsigned int cp0reg, sel;
4397
4398 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
4399 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4400
4401 /* CP0 register including 'sel' code for mtcN (et al.), to be
4402 printed textually if known. If not known, print both
4403 CP0 register name and sel numerically since CP0 register
4404 with sel 0 may have a name unrelated to register being
4405 printed. */
4406 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4407 mips_cp0sel_names_len, cp0reg, sel);
4408 if (n != NULL)
4409 (*info->fprintf_func) (info->stream, "%s", n->name);
4410 else
4411 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4412 break;
4413 }
4414
4415 case 'E':
4416 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
4417 (*info->fprintf_func) (info->stream, "0x%x", lsb);
4418 break;
5fafdf24 4419
6643d27e
FB		 4420 case 'F':
4421 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
4422 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4423 break;
4424
4425 case 'G':
4426 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
4427 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4428 break;
4429
31837be3 4430 case 'o':
d4ea6acd
LA		 4431 switch (*(d+1)) {
4432 case '1':
4433 d++;
4434 delta = l & ((1 << 18) - 1);
4435 if (delta & 0x20000) {
4436 delta |= ~0x1ffff;
4437 }
4438 break;
4439 case '2':
4440 d++;
4441 delta = l & ((1 << 19) - 1);
4442 if (delta & 0x40000) {
4443 delta |= ~0x3ffff;
4444 }
4445 break;
4446 default:
4447 delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
4448 if (delta & 0x8000) {
4449 delta |= ~0xffff;
4450 }
31837be3 4451 }
d4ea6acd 4452
31837be3
YK		 4453 (*info->fprintf_func) (info->stream, "%d", delta);
4454 break;
4455
4456 case 'p':
4457 /* Sign extend the displacement with 26 bits. */
4458 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
4459 if (delta & 0x2000000) {
4460 delta |= ~0x3FFFFFF;
4461 }
4462 info->target = (delta << 2) + pc + INSNLEN;
a6d89b45
DD		 4463 (*info->print_address_func) (info->target, info);
4464 break;
4465
4466 case 'q':
4467 /* Sign extend the displacement with 21 bits. */
4468 delta = sextract32(l, OP_SH_DELTA, 21);
4469 info->target = (delta << 2) + pc + INSNLEN;
31837be3
YK		 4470 (*info->print_address_func) (info->target, info);
4471 break;
4472
52da07d1
TS		 4473 case 't': /* Coprocessor 0 reg name */
4474 (*info->fprintf_func) (info->stream, "%s",
4475 mips_cp0_names[(l >> OP_SH_RT) &
4476 OP_MASK_RT]);
4477 break;
4478
4479 case 'T': /* Coprocessor 0 reg name */
4480 {
4481 const struct mips_cp0sel_name *n;
4482 unsigned int cp0reg, sel;
4483
4484 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
4485 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4486
4487 /* CP0 register including 'sel' code for mftc0, to be
4488 printed textually if known. If not known, print both
4489 CP0 register name and sel numerically since CP0 register
4490 with sel 0 may have a name unrelated to register being
4491 printed. */
4492 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4493 mips_cp0sel_names_len, cp0reg, sel);
4494 if (n != NULL)
4495 (*info->fprintf_func) (info->stream, "%s", n->name);
4496 else
4497 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4498 break;
4499 }
4500
ed8a933f
YK		 4501 case 'd':
4502 (*info->fprintf_func) (info->stream, "%s",
4503 mips_wr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4504 break;
4505
4506 case 'e':
4507 (*info->fprintf_func) (info->stream, "%s",
4508 mips_wr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4509 break;
4510
4511 case 'f':
4512 (*info->fprintf_func) (info->stream, "%s",
4513 mips_wr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4514 break;
4515
4516 case 'g':
4517 (*info->fprintf_func) (info->stream, "%s",
4518 mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR11)
4519 & OP_MASK_MSACR11]);
4520 break;
4521
4522 case 'h':
4523 (*info->fprintf_func) (info->stream, "%s",
4524 mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR6)
4525 & OP_MASK_MSACR6]);
4526 break;
4527
4528 case 'i':
4529 (*info->fprintf_func) (info->stream, "%s",
4530 mips_gpr_names[(l >> OP_SH_GPR) & OP_MASK_GPR]);
4531 break;
4532
6643d27e
FB		 4533 default:
4534 /* xgettext:c-format */
4535 (*info->fprintf_func) (info->stream,
ca66f1a1 4536 "# internal error, undefined extension sequence (+%c)",
6643d27e
FB		 4537 *d);
4538 return;
4539 }
4540 break;
4541
52da07d1
TS		 4542 case '2':
4543 (*info->fprintf_func) (info->stream, "0x%lx",
4544 (l >> OP_SH_BP) & OP_MASK_BP);
4545 break;
4546
4547 case '3':
4548 (*info->fprintf_func) (info->stream, "0x%lx",
4549 (l >> OP_SH_SA3) & OP_MASK_SA3);
4550 break;
4551
4552 case '4':
4553 (*info->fprintf_func) (info->stream, "0x%lx",
4554 (l >> OP_SH_SA4) & OP_MASK_SA4);
4555 break;
4556
4557 case '5':
4558 (*info->fprintf_func) (info->stream, "0x%lx",
4559 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
4560 break;
4561
4562 case '6':
4563 (*info->fprintf_func) (info->stream, "0x%lx",
4564 (l >> OP_SH_RS) & OP_MASK_RS);
4565 break;
4566
4567 case '7':
4568 (*info->fprintf_func) (info->stream, "$ac%ld",
4569 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
4570 break;
4571
4572 case '8':
4573 (*info->fprintf_func) (info->stream, "0x%lx",
4574 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
4575 break;
4576
4577 case '9':
4578 (*info->fprintf_func) (info->stream, "$ac%ld",
4579 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
4580 break;
4581
4582 case '0': /* dsp 6-bit signed immediate in bit 20 */
4583 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
4584 if (delta & 0x20) /* test sign bit */
4585 delta |= ~OP_MASK_DSPSFT;
4586 (*info->fprintf_func) (info->stream, "%d", delta);
4587 break;
4588
4589 case ':': /* dsp 7-bit signed immediate in bit 19 */
4590 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
4591 if (delta & 0x40) /* test sign bit */
4592 delta |= ~OP_MASK_DSPSFT_7;
4593 (*info->fprintf_func) (info->stream, "%d", delta);
4594 break;
4595
4596 case '\'':
4597 (*info->fprintf_func) (info->stream, "0x%lx",
4598 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
4599 break;
4600
4601 case '@': /* dsp 10-bit signed immediate in bit 16 */
4602 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4603 if (delta & 0x200) /* test sign bit */
4604 delta |= ~OP_MASK_IMM10;
4605 (*info->fprintf_func) (info->stream, "%d", delta);
4606 break;
4607
4608 case '!':
4609 (*info->fprintf_func) (info->stream, "%ld",
4610 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
4611 break;
4612
4613 case '$':
4614 (*info->fprintf_func) (info->stream, "%ld",
4615 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
4616 break;
4617
4618 case '*':
4619 (*info->fprintf_func) (info->stream, "$ac%ld",
4620 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
4621 break;
4622
4623 case '&':
4624 (*info->fprintf_func) (info->stream, "$ac%ld",
4625 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
4626 break;
4627
4628 case 'g':
4629 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
4630 (*info->fprintf_func) (info->stream, "$%ld",
4631 (l >> OP_SH_RD) & OP_MASK_RD);
4632 break;
4633
6643d27e
FB		 4634 case 's':
4635 case 'b':
4636 case 'r':
4637 case 'v':
4638 (*info->fprintf_func) (info->stream, "%s",
4639 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
4640 break;
4641
4642 case 't':
4643 case 'w':
4644 (*info->fprintf_func) (info->stream, "%s",
4645 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4646 break;
4647
4648 case 'i':
4649 case 'u':
52da07d1 4650 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4651 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
4652 break;
4653
4654 case 'j': /* Same as i, but sign-extended. */
4655 case 'o':
31837be3 4656 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4368b29a 4657
6643d27e
FB		 4658 if (delta & 0x8000)
4659 delta |= ~0xffff;
4660 (*info->fprintf_func) (info->stream, "%d",
4661 delta);
4662 break;
4663
4664 case 'h':
4665 (*info->fprintf_func) (info->stream, "0x%x",
4666 (unsigned int) ((l >> OP_SH_PREFX)
4667 & OP_MASK_PREFX));
4668 break;
4669
4670 case 'k':
4671 (*info->fprintf_func) (info->stream, "0x%x",
4672 (unsigned int) ((l >> OP_SH_CACHE)
4673 & OP_MASK_CACHE));
4674 break;
4675
4676 case 'a':
4677 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
4678 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
52da07d1
TS		 4679 /* For gdb disassembler, force odd address on jalx. */
4680 if (info->flavour == bfd_target_unknown_flavour
4681 && strcmp (opp->name, "jalx") == 0)
4682 info->target |= 1;
6643d27e
FB		 4683 (*info->print_address_func) (info->target, info);
4684 break;
4685
4686 case 'p':
4687 /* Sign extend the displacement. */
4688 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4689 if (delta & 0x8000)
4690 delta |= ~0xffff;
4691 info->target = (delta << 2) + pc + INSNLEN;
4692 (*info->print_address_func) (info->target, info);
4693 break;
4694
4695 case 'd':
4696 (*info->fprintf_func) (info->stream, "%s",
4697 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4698 break;
4699
4700 case 'U':
4701 {
4702 /* First check for both rd and rt being equal. */
4703 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
4704 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
4705 (*info->fprintf_func) (info->stream, "%s",
4706 mips_gpr_names[reg]);
4707 else
4708 {
4709 /* If one is zero use the other. */
4710 if (reg == 0)
4711 (*info->fprintf_func) (info->stream, "%s",
4712 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4713 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
4714 (*info->fprintf_func) (info->stream, "%s",
4715 mips_gpr_names[reg]);
4716 else /* Bogus, result depends on processor. */
4717 (*info->fprintf_func) (info->stream, "%s or %s",
4718 mips_gpr_names[reg],
4719 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4720 }
4721 }
4722 break;
4723
4724 case 'z':
4725 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4726 break;
4727
4728 case '<':
52da07d1 4729 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4730 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
4731 break;
4732
4733 case 'c':
52da07d1 4734 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4735 (l >> OP_SH_CODE) & OP_MASK_CODE);
4736 break;
4737
4738 case 'q':
52da07d1 4739 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4740 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
4741 break;
4742
4743 case 'C':
52da07d1 4744 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4745 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
4746 break;
4747
4748 case 'B':
52da07d1
TS		 4749 (*info->fprintf_func) (info->stream, "0x%lx",
4750
6643d27e
FB		 4751 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
4752 break;
4753
4754 case 'J':
52da07d1 4755 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4756 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
4757 break;
4758
4759 case 'S':
4760 case 'V':
4761 (*info->fprintf_func) (info->stream, "%s",
4762 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4763 break;
4764
4765 case 'T':
4766 case 'W':
4767 (*info->fprintf_func) (info->stream, "%s",
4768 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4769 break;
4770
4771 case 'D':
4772 (*info->fprintf_func) (info->stream, "%s",
4773 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4774 break;
4775
4776 case 'R':
4777 (*info->fprintf_func) (info->stream, "%s",
4778 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
4779 break;
4780
4781 case 'E':
4782 /* Coprocessor register for lwcN instructions, et al.
4783
4784 Note that there is no load/store cp0 instructions, and
4785 that FPU (cp1) instructions disassemble this field using
4786 'T' format. Therefore, until we gain understanding of
4787 cp2 register names, we can simply print the register
4788 numbers. */
52da07d1 4789 (*info->fprintf_func) (info->stream, "$%ld",
6643d27e
FB		 4790 (l >> OP_SH_RT) & OP_MASK_RT);
4791 break;
4792
4793 case 'G':
4794 /* Coprocessor register for mtcN instructions, et al. Note
4795 that FPU (cp1) instructions disassemble this field using
4796 'S' format. Therefore, we only need to worry about cp0,
4797 cp2, and cp3. */
4798 op = (l >> OP_SH_OP) & OP_MASK_OP;
4799 if (op == OP_OP_COP0)
4800 (*info->fprintf_func) (info->stream, "%s",
4801 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4802 else
52da07d1 4803 (*info->fprintf_func) (info->stream, "$%ld",
6643d27e
FB		 4804 (l >> OP_SH_RD) & OP_MASK_RD);
4805 break;
4806
4807 case 'K':
4808 (*info->fprintf_func) (info->stream, "%s",
4809 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4810 break;
4811
4812 case 'N':
52da07d1
TS		 4813 (*info->fprintf_func) (info->stream,
4814 ((opp->pinfo & (FP_D | FP_S)) != 0
4815 ? "$fcc%ld" : "$cc%ld"),
6643d27e
FB		 4816 (l >> OP_SH_BCC) & OP_MASK_BCC);
4817 break;
4818
4819 case 'M':
52da07d1 4820 (*info->fprintf_func) (info->stream, "$fcc%ld",
6643d27e
FB		 4821 (l >> OP_SH_CCC) & OP_MASK_CCC);
4822 break;
4823
4824 case 'P':
52da07d1 4825 (*info->fprintf_func) (info->stream, "%ld",
6643d27e
FB		 4826 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
4827 break;
4828
4829 case 'e':
52da07d1 4830 (*info->fprintf_func) (info->stream, "%ld",
6643d27e
FB		 4831 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
4832 break;
4833
4834 case '%':
52da07d1 4835 (*info->fprintf_func) (info->stream, "%ld",
6643d27e
FB		 4836 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
4837 break;
4838
4839 case 'H':
52da07d1 4840 (*info->fprintf_func) (info->stream, "%ld",
6643d27e
FB		 4841 (l >> OP_SH_SEL) & OP_MASK_SEL);
4842 break;
4843
4844 case 'O':
52da07d1 4845 (*info->fprintf_func) (info->stream, "%ld",
6643d27e
FB		 4846 (l >> OP_SH_ALN) & OP_MASK_ALN);
4847 break;
4848
4849 case 'Q':
4850 {
4851 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
52da07d1 4852
6643d27e
FB		 4853 if ((vsel & 0x10) == 0)
4854 {
4855 int fmt;
52da07d1 4856
6643d27e
FB		 4857 vsel &= 0x0f;
4858 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
4859 if ((vsel & 1) == 0)
4860 break;
52da07d1 4861 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
6643d27e
FB		 4862 (l >> OP_SH_FT) & OP_MASK_FT,
4863 vsel >> 1);
4864 }
4865 else if ((vsel & 0x08) == 0)
4866 {
52da07d1 4867 (*info->fprintf_func) (info->stream, "$v%ld",
6643d27e
FB		 4868 (l >> OP_SH_FT) & OP_MASK_FT);
4869 }
4870 else
4871 {
52da07d1 4872 (*info->fprintf_func) (info->stream, "0x%lx",
6643d27e
FB		 4873 (l >> OP_SH_FT) & OP_MASK_FT);
4874 }
4875 }
4876 break;
4877
4878 case 'X':
52da07d1 4879 (*info->fprintf_func) (info->stream, "$v%ld",
6643d27e
FB		 4880 (l >> OP_SH_FD) & OP_MASK_FD);
4881 break;
4882
4883 case 'Y':
52da07d1 4884 (*info->fprintf_func) (info->stream, "$v%ld",
6643d27e
FB		 4885 (l >> OP_SH_FS) & OP_MASK_FS);
4886 break;
4887
4888 case 'Z':
52da07d1 4889 (*info->fprintf_func) (info->stream, "$v%ld",
6643d27e
FB		 4890 (l >> OP_SH_FT) & OP_MASK_FT);
4891 break;
4892
4893 default:
4894 /* xgettext:c-format */
4895 (*info->fprintf_func) (info->stream,
ca66f1a1 4896 "# internal error, undefined modifier(%c)",
6643d27e
FB		 4897 *d);
4898 return;
4899 }
4900 }
4901}
4902\f
4903/* Check if the object uses NewABI conventions. */
4904#if 0
4905static int
4906is_newabi (header)
4907 Elf_Internal_Ehdr *header;
4908{
4909 /* There are no old-style ABIs which use 64-bit ELF. */
4910 if (header->e_ident[EI_CLASS] == ELFCLASS64)
4911 return 1;
4912
4913 /* If a 32-bit ELF file, n32 is a new-style ABI. */
4914 if ((header->e_flags & EF_MIPS_ABI2) != 0)
4915 return 1;
4916
4917 return 0;
4918}
4919#endif
4920\f
4921/* Print the mips instruction at address MEMADDR in debugged memory,
4922 on using INFO. Returns length of the instruction, in bytes, which is
4923 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
4924 this is little-endian code. */
4925
4926static int
52da07d1
TS		 4927print_insn_mips (bfd_vma memaddr,
4928 unsigned long int word,
4929 struct disassemble_info *info)
6643d27e 4930{
52da07d1 4931 const struct mips_opcode *op;
6643d27e
FB		 4932 static bfd_boolean init = 0;
4933 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4934
4935 /* Build a hash table to shorten the search time. */
4936 if (! init)
4937 {
4938 unsigned int i;
4939
4940 for (i = 0; i <= OP_MASK_OP; i++)
4941 {
4942 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4943 {
52da07d1
TS		 4944 if (op->pinfo == INSN_MACRO
4945 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
6643d27e
FB		 4946 continue;
4947 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4948 {
4949 mips_hash[i] = op;
4950 break;
4951 }
4952 }
4953 }
4954
4955 init = 1;
4956 }
4957
4958 info->bytes_per_chunk = INSNLEN;
4959 info->display_endian = info->endian;
4960 info->insn_info_valid = 1;
4961 info->branch_delay_insns = 0;
4962 info->data_size = 0;
4963 info->insn_type = dis_nonbranch;
4964 info->target = 0;
4965 info->target2 = 0;
4966
4967 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4968 if (op != NULL)
4969 {
4970 for (; op < &mips_opcodes[NUMOPCODES]; op++)
4971 {
52da07d1
TS		 4972 if (op->pinfo != INSN_MACRO
4973 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4974 && (word & op->mask) == op->match)
6643d27e 4975 {
52da07d1 4976 const char *d;
6643d27e
FB		 4977
4978 /* We always allow to disassemble the jalx instruction. */
4979 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4980 && strcmp (op->name, "jalx"))
4981 continue;
4982
31837be3
YK		 4983 if (strcmp(op->name, "bovc") == 0
4984 || strcmp(op->name, "bnvc") == 0) {
4985 if (((word >> OP_SH_RS) & OP_MASK_RS) <
4986 ((word >> OP_SH_RT) & OP_MASK_RT)) {
4987 continue;
4988 }
4989 }
4990 if (strcmp(op->name, "bgezc") == 0
4991 || strcmp(op->name, "bltzc") == 0
4992 || strcmp(op->name, "bgezalc") == 0
4993 || strcmp(op->name, "bltzalc") == 0) {
4994 if (((word >> OP_SH_RS) & OP_MASK_RS) !=
4995 ((word >> OP_SH_RT) & OP_MASK_RT)) {
4996 continue;
4997 }
4998 }
4999
6643d27e
FB		 5000 /* Figure out instruction type and branch delay information. */
5001 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
5002 {
5003 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
5004 info->insn_type = dis_jsr;
5005 else
5006 info->insn_type = dis_branch;
5007 info->branch_delay_insns = 1;
5008 }
5009 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
5010 | INSN_COND_BRANCH_LIKELY)) != 0)
5011 {
5012 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
5013 info->insn_type = dis_condjsr;
5014 else
5015 info->insn_type = dis_condbranch;
5016 info->branch_delay_insns = 1;
5017 }
5018 else if ((op->pinfo & (INSN_STORE_MEMORY
5019 | INSN_LOAD_MEMORY_DELAY)) != 0)
5020 info->insn_type = dis_dref;
5021
5022 (*info->fprintf_func) (info->stream, "%s", op->name);
5023
5024 d = op->args;
5025 if (d != NULL && *d != '\0')
5026 {
5027 (*info->fprintf_func) (info->stream, "\t");
52da07d1 5028 print_insn_args (d, word, memaddr, info, op);
6643d27e
FB		 5029 }
5030
5031 return INSNLEN;
5032 }
5033 }
5034 }
5035
5036 /* Handle undefined instructions. */
5037 info->insn_type = dis_noninsn;
52da07d1 5038 (*info->fprintf_func) (info->stream, "0x%lx", word);
6643d27e
FB		 5039 return INSNLEN;
5040}
5041\f
5042/* In an environment where we do not know the symbol type of the
5043 instruction we are forced to assume that the low order bit of the
5044 instructions' address may mark it as a mips16 instruction. If we
5045 are single stepping, or the pc is within the disassembled function,
5046 this works. Otherwise, we need a clue. Sometimes. */
5047
6643d27e 5048static int
52da07d1
TS		 5049_print_insn_mips (bfd_vma memaddr,
5050 struct disassemble_info *info,
5051 enum bfd_endian endianness)
6643d27e
FB		 5052{
5053 bfd_byte buffer[INSNLEN];
5054 int status;
5055
5056 set_default_mips_dis_options (info);
5057 parse_mips_dis_options (info->disassembler_options);
5058
5059#if 0
5060#if 1
5061 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
5062 /* Only a few tools will work this way. */
5063 if (memaddr & 0x01)
5064 return print_insn_mips16 (memaddr, info);
5065#endif
5066
5067#if SYMTAB_AVAILABLE
5068 if (info->mach == bfd_mach_mips16
5069 || (info->flavour == bfd_target_elf_flavour
5070 && info->symbols != NULL
5071 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
5072 == STO_MIPS16)))
5073 return print_insn_mips16 (memaddr, info);
5074#endif
5075#endif
5076
5077 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
5078 if (status == 0)
5079 {
5080 unsigned long insn;
5081
5082 if (endianness == BFD_ENDIAN_BIG)
5083 insn = (unsigned long) bfd_getb32 (buffer);
5084 else
5085 insn = (unsigned long) bfd_getl32 (buffer);
5086
5087 return print_insn_mips (memaddr, insn, info);
5088 }
5089 else
5090 {
5091 (*info->memory_error_func) (status, memaddr, info);
5092 return -1;
5093 }
5094}
5095
5096int
52da07d1 5097print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
6643d27e
FB		 5098{
5099 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
5100}
5101
5102int
52da07d1 5103print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
6643d27e
FB		 5104{
5105 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
5106}
5107\f
5108/* Disassemble mips16 instructions. */
5109#if 0
5110static int
52da07d1 5111print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
6643d27e
FB		 5112{
5113 int status;
5114 bfd_byte buffer[2];
5115 int length;
5116 int insn;
5117 bfd_boolean use_extend;
5118 int extend = 0;
5119 const struct mips_opcode *op, *opend;
5120
5121 info->bytes_per_chunk = 2;
5122 info->display_endian = info->endian;
5123 info->insn_info_valid = 1;
5124 info->branch_delay_insns = 0;
5125 info->data_size = 0;
5126 info->insn_type = dis_nonbranch;
5127 info->target = 0;
5128 info->target2 = 0;
5129
5130 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5131 if (status != 0)
5132 {
5133 (*info->memory_error_func) (status, memaddr, info);
5134 return -1;
5135 }
5136
5137 length = 2;
5138
5139 if (info->endian == BFD_ENDIAN_BIG)
5140 insn = bfd_getb16 (buffer);
5141 else
5142 insn = bfd_getl16 (buffer);
5143
5144 /* Handle the extend opcode specially. */
5145 use_extend = FALSE;
5146 if ((insn & 0xf800) == 0xf000)
5147 {
5148 use_extend = TRUE;
5149 extend = insn & 0x7ff;
5150
5151 memaddr += 2;
5152
5153 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5154 if (status != 0)
5155 {
5156 (*info->fprintf_func) (info->stream, "extend 0x%x",
5157 (unsigned int) extend);
5158 (*info->memory_error_func) (status, memaddr, info);
5159 return -1;
5160 }
5161
5162 if (info->endian == BFD_ENDIAN_BIG)
5163 insn = bfd_getb16 (buffer);
5164 else
5165 insn = bfd_getl16 (buffer);
5166
5167 /* Check for an extend opcode followed by an extend opcode. */
5168 if ((insn & 0xf800) == 0xf000)
5169 {
5170 (*info->fprintf_func) (info->stream, "extend 0x%x",
5171 (unsigned int) extend);
5172 info->insn_type = dis_noninsn;
5173 return length;
5174 }
5175
5176 length += 2;
5177 }
5178
5179 /* FIXME: Should probably use a hash table on the major opcode here. */
5180
5181 opend = mips16_opcodes + bfd_mips16_num_opcodes;
5182 for (op = mips16_opcodes; op < opend; op++)
5183 {
52da07d1
TS		 5184 if (op->pinfo != INSN_MACRO
5185 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
5186 && (insn & op->mask) == op->match)
6643d27e
FB		 5187 {
5188 const char *s;
5189
5190 if (strchr (op->args, 'a') != NULL)
5191 {
5192 if (use_extend)
5193 {
5194 (*info->fprintf_func) (info->stream, "extend 0x%x",
5195 (unsigned int) extend);
5196 info->insn_type = dis_noninsn;
5197 return length - 2;
5198 }
5199
5200 use_extend = FALSE;
5201
5202 memaddr += 2;
5203
5204 status = (*info->read_memory_func) (memaddr, buffer, 2,
5205 info);
5206 if (status == 0)
5207 {
5208 use_extend = TRUE;
5209 if (info->endian == BFD_ENDIAN_BIG)
5210 extend = bfd_getb16 (buffer);
5211 else
5212 extend = bfd_getl16 (buffer);
5213 length += 2;
5214 }
5215 }
5216
5217 (*info->fprintf_func) (info->stream, "%s", op->name);
5218 if (op->args[0] != '\0')
5219 (*info->fprintf_func) (info->stream, "\t");
5220
5221 for (s = op->args; *s != '\0'; s++)
5222 {
5223 if (*s == ','
5224 && s[1] == 'w'
5225 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
5226 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
5227 {
5228 /* Skip the register and the comma. */
5229 ++s;
5230 continue;
5231 }
5232 if (*s == ','
5233 && s[1] == 'v'
5234 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
5235 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
5236 {
5237 /* Skip the register and the comma. */
5238 ++s;
5239 continue;
5240 }
5241 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
5242 info);
5243 }
5244
5245 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
5246 {
5247 info->branch_delay_insns = 1;
5248 if (info->insn_type != dis_jsr)
5249 info->insn_type = dis_branch;
5250 }
5251
5252 return length;
5253 }
5254 }
5255
5256 if (use_extend)
5257 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
5258 (*info->fprintf_func) (info->stream, "0x%x", insn);
5259 info->insn_type = dis_noninsn;
5260
5261 return length;
5262}
5263
5264/* Disassemble an operand for a mips16 instruction. */
5265
5266static void
52da07d1
TS		 5267print_mips16_insn_arg (char type,
5268 const struct mips_opcode *op,
5269 int l,
5270 bfd_boolean use_extend,
5271 int extend,
5272 bfd_vma memaddr,
5273 struct disassemble_info *info)
6643d27e
FB		 5274{
5275 switch (type)
5276 {
5277 case ',':
5278 case '(':
5279 case ')':
5280 (*info->fprintf_func) (info->stream, "%c", type);
5281 break;
5282
5283 case 'y':
5284 case 'w':
5285 (*info->fprintf_func) (info->stream, "%s",
52da07d1
TS		 5286 mips16_reg_names(((l >> MIPS16OP_SH_RY)
5287 & MIPS16OP_MASK_RY)));
6643d27e
FB		 5288 break;
5289
5290 case 'x':
5291 case 'v':
5292 (*info->fprintf_func) (info->stream, "%s",
52da07d1
TS		 5293 mips16_reg_names(((l >> MIPS16OP_SH_RX)
5294 & MIPS16OP_MASK_RX)));
6643d27e
FB		 5295 break;
5296
5297 case 'z':
5298 (*info->fprintf_func) (info->stream, "%s",
52da07d1
TS		 5299 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
5300 & MIPS16OP_MASK_RZ)));
6643d27e
FB		 5301 break;
5302
5303 case 'Z':
5304 (*info->fprintf_func) (info->stream, "%s",
52da07d1
TS		 5305 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
5306 & MIPS16OP_MASK_MOVE32Z)));
6643d27e
FB		 5307 break;
5308
5309 case '0':
5310 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
5311 break;
5312
5313 case 'S':
5314 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
5315 break;
5316
5317 case 'P':
5318 (*info->fprintf_func) (info->stream, "$pc");
5319 break;
5320
5321 case 'R':
5322 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
5323 break;
5324
5325 case 'X':
5326 (*info->fprintf_func) (info->stream, "%s",
5327 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
5328 & MIPS16OP_MASK_REGR32)]);
5329 break;
5330
5331 case 'Y':
5332 (*info->fprintf_func) (info->stream, "%s",
5333 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
5334 break;
5335
5336 case '<':
5337 case '>':
5338 case '[':
5339 case ']':
5340 case '4':
5341 case '5':
5342 case 'H':
5343 case 'W':
5344 case 'D':
5345 case 'j':
5346 case '6':
5347 case '8':
5348 case 'V':
5349 case 'C':
5350 case 'U':
5351 case 'k':
5352 case 'K':
5353 case 'p':
5354 case 'q':
5355 case 'A':
5356 case 'B':
5357 case 'E':
5358 {
5359 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
5360
5361 shift = 0;
5362 signedp = 0;
5363 extbits = 16;
5364 pcrel = 0;
5365 extu = 0;
5366 branch = 0;
5367 switch (type)
5368 {
5369 case '<':
5370 nbits = 3;
5371 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5372 extbits = 5;
5373 extu = 1;
5374 break;
5375 case '>':
5376 nbits = 3;
5377 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5378 extbits = 5;
5379 extu = 1;
5380 break;
5381 case '[':
5382 nbits = 3;
5383 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5384 extbits = 6;
5385 extu = 1;
5386 break;
5387 case ']':
5388 nbits = 3;
5389 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5390 extbits = 6;
5391 extu = 1;
5392 break;
5393 case '4':
5394 nbits = 4;
5395 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
5396 signedp = 1;
5397 extbits = 15;
5398 break;
5399 case '5':
5400 nbits = 5;
5401 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5402 info->insn_type = dis_dref;
5403 info->data_size = 1;
5404 break;
5405 case 'H':
5406 nbits = 5;
5407 shift = 1;
5408 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5409 info->insn_type = dis_dref;
5410 info->data_size = 2;
5411 break;
5412 case 'W':
5413 nbits = 5;
5414 shift = 2;
5415 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5416 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
5417 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
5418 {
5419 info->insn_type = dis_dref;
5420 info->data_size = 4;
5421 }
5422 break;
5423 case 'D':
5424 nbits = 5;
5425 shift = 3;
5426 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5427 info->insn_type = dis_dref;
5428 info->data_size = 8;
5429 break;
5430 case 'j':
5431 nbits = 5;
5432 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5433 signedp = 1;
5434 break;
5435 case '6':
5436 nbits = 6;
5437 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5438 break;
5439 case '8':
5440 nbits = 8;
5441 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5442 break;
5443 case 'V':
5444 nbits = 8;
5445 shift = 2;
5446 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5447 /* FIXME: This might be lw, or it might be addiu to $sp or
5448 $pc. We assume it's load. */
5449 info->insn_type = dis_dref;
5450 info->data_size = 4;
5451 break;
5452 case 'C':
5453 nbits = 8;
5454 shift = 3;
5455 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5456 info->insn_type = dis_dref;
5457 info->data_size = 8;
5458 break;
5459 case 'U':
5460 nbits = 8;
5461 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5462 extu = 1;
5463 break;
5464 case 'k':
5465 nbits = 8;
5466 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5467 signedp = 1;
5468 break;
5469 case 'K':
5470 nbits = 8;
5471 shift = 3;
5472 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5473 signedp = 1;
5474 break;
5475 case 'p':
5476 nbits = 8;
5477 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5478 signedp = 1;
5479 pcrel = 1;
5480 branch = 1;
5481 info->insn_type = dis_condbranch;
5482 break;
5483 case 'q':
5484 nbits = 11;
5485 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
5486 signedp = 1;
5487 pcrel = 1;
5488 branch = 1;
5489 info->insn_type = dis_branch;
5490 break;
5491 case 'A':
5492 nbits = 8;
5493 shift = 2;
5494 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5495 pcrel = 1;
5496 /* FIXME: This can be lw or la. We assume it is lw. */
5497 info->insn_type = dis_dref;
5498 info->data_size = 4;
5499 break;
5500 case 'B':
5501 nbits = 5;
5502 shift = 3;
5503 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5504 pcrel = 1;
5505 info->insn_type = dis_dref;
5506 info->data_size = 8;
5507 break;
5508 case 'E':
5509 nbits = 5;
5510 shift = 2;
5511 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5512 pcrel = 1;
5513 break;
5514 default:
5515 abort ();
5516 }
5517
5518 if (! use_extend)
5519 {
5520 if (signedp && immed >= (1 << (nbits - 1)))
5521 immed -= 1 << nbits;
5522 immed <<= shift;
5523 if ((type == '<' || type == '>' || type == '[' || type == ']')
5524 && immed == 0)
5525 immed = 8;
5526 }
5527 else
5528 {
5529 if (extbits == 16)
5530 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
5531 else if (extbits == 15)
5532 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
5533 else
5534 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
5535 immed &= (1 << extbits) - 1;
5536 if (! extu && immed >= (1 << (extbits - 1)))
5537 immed -= 1 << extbits;
5538 }
5539
5540 if (! pcrel)
5541 (*info->fprintf_func) (info->stream, "%d", immed);
5542 else
5543 {
5544 bfd_vma baseaddr;
5545
5546 if (branch)
5547 {
5548 immed *= 2;
5549 baseaddr = memaddr + 2;
5550 }
5551 else if (use_extend)
5552 baseaddr = memaddr - 2;
5553 else
5554 {
5555 int status;
5556 bfd_byte buffer[2];
5557
5558 baseaddr = memaddr;
5559
5560 /* If this instruction is in the delay slot of a jr
5561 instruction, the base address is the address of the
5562 jr instruction. If it is in the delay slot of jalr
5563 instruction, the base address is the address of the
5564 jalr instruction. This test is unreliable: we have
5565 no way of knowing whether the previous word is
5566 instruction or data. */
5567 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
5568 info);
5569 if (status == 0
5570 && (((info->endian == BFD_ENDIAN_BIG
5571 ? bfd_getb16 (buffer)
5572 : bfd_getl16 (buffer))
5573 & 0xf800) == 0x1800))
5574 baseaddr = memaddr - 4;
5575 else
5576 {
5577 status = (*info->read_memory_func) (memaddr - 2, buffer,
5578 2, info);
5579 if (status == 0
5580 && (((info->endian == BFD_ENDIAN_BIG
5581 ? bfd_getb16 (buffer)
5582 : bfd_getl16 (buffer))
5583 & 0xf81f) == 0xe800))
5584 baseaddr = memaddr - 2;
5585 }
5586 }
5587 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
52da07d1
TS		 5588 if (pcrel && branch
5589 && info->flavour == bfd_target_unknown_flavour)
5590 /* For gdb disassembler, maintain odd address. */
5591 info->target |= 1;
6643d27e
FB		 5592 (*info->print_address_func) (info->target, info);
5593 }
5594 }
5595 break;
5596
5597 case 'a':
52da07d1
TS		 5598 {
5599 int jalx = l & 0x400;
5600
5601 if (! use_extend)
5602 extend = 0;
5603 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
5604 if (!jalx && info->flavour == bfd_target_unknown_flavour)
5605 /* For gdb disassembler, maintain odd address. */
5606 l |= 1;
5607 }
6643d27e
FB		 5608 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
5609 (*info->print_address_func) (info->target, info);
5610 info->insn_type = dis_jsr;
5611 info->branch_delay_insns = 1;
5612 break;
5613
5614 case 'l':
5615 case 'L':
5616 {
5617 int need_comma, amask, smask;
5618
5619 need_comma = 0;
5620
5621 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5622
5623 amask = (l >> 3) & 7;
5624
5625 if (amask > 0 && amask < 5)
5626 {
5627 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5628 if (amask > 1)
5629 (*info->fprintf_func) (info->stream, "-%s",
5630 mips_gpr_names[amask + 3]);
5631 need_comma = 1;
5632 }
5633
5634 smask = (l >> 1) & 3;
5635 if (smask == 3)
5636 {
5637 (*info->fprintf_func) (info->stream, "%s??",
5638 need_comma ? "," : "");
5639 need_comma = 1;
5640 }
5641 else if (smask > 0)
5642 {
5643 (*info->fprintf_func) (info->stream, "%s%s",
5644 need_comma ? "," : "",
5645 mips_gpr_names[16]);
5646 if (smask > 1)
5647 (*info->fprintf_func) (info->stream, "-%s",
5648 mips_gpr_names[smask + 15]);
5649 need_comma = 1;
5650 }
5651
5652 if (l & 1)
5653 {
5654 (*info->fprintf_func) (info->stream, "%s%s",
5655 need_comma ? "," : "",
5656 mips_gpr_names[31]);
5657 need_comma = 1;
5658 }
5659
5660 if (amask == 5 || amask == 6)
5661 {
5662 (*info->fprintf_func) (info->stream, "%s$f0",
5663 need_comma ? "," : "");
5664 if (amask == 6)
5665 (*info->fprintf_func) (info->stream, "-$f1");
5666 }
5667 }
5668 break;
5669
52da07d1
TS		 5670 case 'm':
5671 case 'M':
5672 /* MIPS16e save/restore. */
5673 {
5674 int need_comma = 0;
5675 int amask, args, statics;
5676 int nsreg, smask;
5677 int framesz;
5678 int i, j;
5679
5680 l = l & 0x7f;
5681 if (use_extend)
5682 l |= extend << 16;
5683
5684 amask = (l >> 16) & 0xf;
5685 if (amask == MIPS16_ALL_ARGS)
5686 {
5687 args = 4;
5688 statics = 0;
5689 }
5690 else if (amask == MIPS16_ALL_STATICS)
5691 {
5692 args = 0;
5693 statics = 4;
5694 }
5695 else
5696 {
5697 args = amask >> 2;
5698 statics = amask & 3;
5699 }
5700
5701 if (args > 0) {
5702 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5703 if (args > 1)
5704 (*info->fprintf_func) (info->stream, "-%s",
5705 mips_gpr_names[4 + args - 1]);
5706 need_comma = 1;
5707 }
5708
5709 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
5710 if (framesz == 0 && !use_extend)
5711 framesz = 128;
5712
5713 (*info->fprintf_func) (info->stream, "%s%d",
5714 need_comma ? "," : "",
5715 framesz);
5716
5717 if (l & 0x40) /* $ra */
5718 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
5719
5720 nsreg = (l >> 24) & 0x7;
5721 smask = 0;
5722 if (l & 0x20) /* $s0 */
5723 smask |= 1 << 0;
5724 if (l & 0x10) /* $s1 */
5725 smask |= 1 << 1;
5726 if (nsreg > 0) /* $s2-$s8 */
5727 smask |= ((1 << nsreg) - 1) << 2;
5728
5729 /* Find first set static reg bit. */
5730 for (i = 0; i < 9; i++)
5731 {
5732 if (smask & (1 << i))
5733 {
5734 (*info->fprintf_func) (info->stream, ",%s",
5735 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
5736 /* Skip over string of set bits. */
5737 for (j = i; smask & (2 << j); j++)
5738 continue;
5739 if (j > i)
5740 (*info->fprintf_func) (info->stream, "-%s",
5741 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
5742 i = j + 1;
5743 }
5744 }
5745
5746 /* Statics $ax - $a3. */
5747 if (statics == 1)
5748 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
5749 else if (statics > 0)
5750 (*info->fprintf_func) (info->stream, ",%s-%s",
5751 mips_gpr_names[7 - statics + 1],
5752 mips_gpr_names[7]);
5753 }
5754 break;
5755
6643d27e
FB		 5756 default:
5757 /* xgettext:c-format */
5758 (*info->fprintf_func)
5759 (info->stream,
ca66f1a1 5760 "# internal disassembler error, unrecognised modifier (%c)",
6643d27e
FB		 5761 type);
5762 abort ();
5763 }
5764}
6643d27e
FB		 5765
5766void
52da07d1 5767print_mips_disassembler_options (FILE *stream)
6643d27e
FB		 5768{
5769 unsigned int i;
5770
ca66f1a1 5771 fprintf (stream, "\n\
6643d27e 5772The following MIPS specific disassembler options are supported for use\n\
ca66f1a1 5773with the -M switch (multiple options should be separated by commas):\n");
6643d27e 5774
ca66f1a1 5775 fprintf (stream, "\n\
6643d27e 5776 gpr-names=ABI Print GPR names according to specified ABI.\n\
ca66f1a1 5777 Default: based on binary being disassembled.\n");
6643d27e 5778
ca66f1a1 5779 fprintf (stream, "\n\
6643d27e 5780 fpr-names=ABI Print FPR names according to specified ABI.\n\
ca66f1a1 5781 Default: numeric.\n");
6643d27e 5782
ca66f1a1 5783 fprintf (stream, "\n\
6643d27e
FB		 5784 cp0-names=ARCH Print CP0 register names according to\n\
5785 specified architecture.\n\
ca66f1a1 5786 Default: based on binary being disassembled.\n");
6643d27e 5787
ca66f1a1 5788 fprintf (stream, "\n\
b2bedb21 5789 hwr-names=ARCH Print HWR names according to specified\n\
6643d27e 5790 architecture.\n\
ca66f1a1 5791 Default: based on binary being disassembled.\n");
6643d27e 5792
ca66f1a1 5793 fprintf (stream, "\n\
6643d27e 5794 reg-names=ABI Print GPR and FPR names according to\n\
ca66f1a1 5795 specified ABI.\n");
6643d27e 5796
ca66f1a1 5797 fprintf (stream, "\n\
6643d27e 5798 reg-names=ARCH Print CP0 register and HWR names according to\n\
ca66f1a1 5799 specified architecture.\n");
6643d27e 5800
ca66f1a1 5801 fprintf (stream, "\n\
6643d27e 5802 For the options above, the following values are supported for \"ABI\":\n\
ca66f1a1 5803 ");
6643d27e
FB		 5804 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
5805 fprintf (stream, " %s", mips_abi_choices[i].name);
ca66f1a1 5806 fprintf (stream, "\n");
6643d27e 5807
ca66f1a1 5808 fprintf (stream, "\n\
6643d27e 5809 For the options above, The following values are supported for \"ARCH\":\n\
ca66f1a1 5810 ");
6643d27e
FB		 5811 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
5812 if (*mips_arch_choices[i].name != '\0')
5813 fprintf (stream, " %s", mips_arch_choices[i].name);
ca66f1a1 5814 fprintf (stream, "\n");
6643d27e 5815
ca66f1a1 5816 fprintf (stream, "\n");
6643d27e 5817}
f9480ffc 5818#endif
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