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6643d27e FB |
1 | /* Print mips instructions for GDB, the GNU debugger, or for objdump. |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, | |
3 | 2000, 2001, 2002, 2003 | |
4 | Free Software Foundation, Inc. | |
5 | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). | |
6 | ||
7 | This file is part of GDB, GAS, and the GNU binutils. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
8167ee88 | 20 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
6643d27e | 21 | |
76cad711 | 22 | #include "disas/bfd.h" |
6643d27e FB |
23 | |
24 | /* mips.h. Mips opcode list for GDB, the GNU debugger. | |
25 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 | |
26 | Free Software Foundation, Inc. | |
27 | Contributed by Ralph Campbell and OSF | |
28 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
29 | ||
30 | This file is part of GDB, GAS, and the GNU binutils. | |
31 | ||
32 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
33 | them and/or modify them under the terms of the GNU General Public | |
34 | License as published by the Free Software Foundation; either version | |
35 | 1, or (at your option) any later version. | |
36 | ||
37 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
38 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
39 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
40 | the GNU General Public License for more details. | |
41 | ||
42 | You should have received a copy of the GNU General Public License | |
8167ee88 BS |
43 | along with this file; see the file COPYING. If not, |
44 | see <http://www.gnu.org/licenses/>. */ | |
6643d27e FB |
45 | |
46 | /* These are bit masks and shift counts to use to access the various | |
47 | fields of an instruction. To retrieve the X field of an | |
48 | instruction, use the expression | |
49 | (i >> OP_SH_X) & OP_MASK_X | |
50 | To set the same field (to j), use | |
51 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) | |
52 | ||
53 | Make sure you use fields that are appropriate for the instruction, | |
54 | of course. | |
55 | ||
56 | The 'i' format uses OP, RS, RT and IMMEDIATE. | |
57 | ||
58 | The 'j' format uses OP and TARGET. | |
59 | ||
60 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. | |
61 | ||
62 | The 'b' format uses OP, RS, RT and DELTA. | |
63 | ||
64 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. | |
65 | ||
66 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. | |
67 | ||
68 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the | |
69 | breakpoint instruction are not defined; Kane says the breakpoint | |
70 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers | |
71 | only use ten bits). An optional two-operand form of break/sdbbp | |
72 | allows the lower ten bits to be set too, and MIPS32 and later | |
73 | architectures allow 20 bits to be set with a signal operand | |
74 | (using CODE20). | |
75 | ||
76 | The syscall instruction uses CODE20. | |
77 | ||
78 | The general coprocessor instructions use COPZ. */ | |
79 | ||
80 | #define OP_MASK_OP 0x3f | |
81 | #define OP_SH_OP 26 | |
82 | #define OP_MASK_RS 0x1f | |
83 | #define OP_SH_RS 21 | |
84 | #define OP_MASK_FR 0x1f | |
85 | #define OP_SH_FR 21 | |
86 | #define OP_MASK_FMT 0x1f | |
87 | #define OP_SH_FMT 21 | |
88 | #define OP_MASK_BCC 0x7 | |
89 | #define OP_SH_BCC 18 | |
90 | #define OP_MASK_CODE 0x3ff | |
91 | #define OP_SH_CODE 16 | |
92 | #define OP_MASK_CODE2 0x3ff | |
93 | #define OP_SH_CODE2 6 | |
94 | #define OP_MASK_RT 0x1f | |
95 | #define OP_SH_RT 16 | |
96 | #define OP_MASK_FT 0x1f | |
97 | #define OP_SH_FT 16 | |
98 | #define OP_MASK_CACHE 0x1f | |
99 | #define OP_SH_CACHE 16 | |
100 | #define OP_MASK_RD 0x1f | |
101 | #define OP_SH_RD 11 | |
102 | #define OP_MASK_FS 0x1f | |
103 | #define OP_SH_FS 11 | |
104 | #define OP_MASK_PREFX 0x1f | |
105 | #define OP_SH_PREFX 11 | |
106 | #define OP_MASK_CCC 0x7 | |
107 | #define OP_SH_CCC 8 | |
108 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ | |
109 | #define OP_SH_CODE20 6 | |
110 | #define OP_MASK_SHAMT 0x1f | |
111 | #define OP_SH_SHAMT 6 | |
112 | #define OP_MASK_FD 0x1f | |
113 | #define OP_SH_FD 6 | |
114 | #define OP_MASK_TARGET 0x3ffffff | |
115 | #define OP_SH_TARGET 0 | |
116 | #define OP_MASK_COPZ 0x1ffffff | |
117 | #define OP_SH_COPZ 0 | |
118 | #define OP_MASK_IMMEDIATE 0xffff | |
119 | #define OP_SH_IMMEDIATE 0 | |
120 | #define OP_MASK_DELTA 0xffff | |
121 | #define OP_SH_DELTA 0 | |
4368b29a LA |
122 | #define OP_MASK_DELTA_R6 0x1ff |
123 | #define OP_SH_DELTA_R6 7 | |
6643d27e FB |
124 | #define OP_MASK_FUNCT 0x3f |
125 | #define OP_SH_FUNCT 0 | |
126 | #define OP_MASK_SPEC 0x3f | |
127 | #define OP_SH_SPEC 0 | |
128 | #define OP_SH_LOCC 8 /* FP condition code. */ | |
129 | #define OP_SH_HICC 18 /* FP condition code. */ | |
130 | #define OP_MASK_CC 0x7 | |
131 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ | |
132 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ | |
133 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ | |
134 | #define OP_MASK_COP1SPEC 0xf | |
135 | #define OP_MASK_COP1SCLR 0x4 | |
136 | #define OP_MASK_COP1CMP 0x3 | |
137 | #define OP_SH_COP1CMP 4 | |
138 | #define OP_SH_FORMAT 21 /* FP short format field. */ | |
139 | #define OP_MASK_FORMAT 0x7 | |
140 | #define OP_SH_TRUE 16 | |
141 | #define OP_MASK_TRUE 0x1 | |
142 | #define OP_SH_GE 17 | |
143 | #define OP_MASK_GE 0x01 | |
144 | #define OP_SH_UNSIGNED 16 | |
145 | #define OP_MASK_UNSIGNED 0x1 | |
146 | #define OP_SH_HINT 16 | |
147 | #define OP_MASK_HINT 0x1f | |
148 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ | |
149 | #define OP_MASK_MMI 0x3f | |
150 | #define OP_SH_MMISUB 6 | |
151 | #define OP_MASK_MMISUB 0x1f | |
152 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ | |
153 | #define OP_SH_PERFREG 1 | |
154 | #define OP_SH_SEL 0 /* Coprocessor select field. */ | |
155 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ | |
156 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ | |
157 | #define OP_MASK_CODE19 0x7ffff | |
158 | #define OP_SH_ALN 21 | |
159 | #define OP_MASK_ALN 0x7 | |
160 | #define OP_SH_VSEL 21 | |
161 | #define OP_MASK_VSEL 0x1f | |
162 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, | |
163 | but 0x8-0xf don't select bytes. */ | |
164 | #define OP_SH_VECBYTE 22 | |
165 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ | |
166 | #define OP_SH_VECALIGN 21 | |
167 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ | |
168 | #define OP_SH_INSMSB 11 | |
169 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
170 | #define OP_SH_EXTMSBD 11 | |
171 | ||
172 | #define OP_OP_COP0 0x10 | |
173 | #define OP_OP_COP1 0x11 | |
174 | #define OP_OP_COP2 0x12 | |
175 | #define OP_OP_COP3 0x13 | |
176 | #define OP_OP_LWC1 0x31 | |
177 | #define OP_OP_LWC2 0x32 | |
178 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ | |
179 | #define OP_OP_LDC1 0x35 | |
180 | #define OP_OP_LDC2 0x36 | |
181 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ | |
182 | #define OP_OP_SWC1 0x39 | |
183 | #define OP_OP_SWC2 0x3a | |
184 | #define OP_OP_SWC3 0x3b | |
185 | #define OP_OP_SDC1 0x3d | |
186 | #define OP_OP_SDC2 0x3e | |
187 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ | |
188 | ||
29490584 TS |
189 | /* MIPS DSP ASE */ |
190 | #define OP_SH_DSPACC 11 | |
191 | #define OP_MASK_DSPACC 0x3 | |
192 | #define OP_SH_DSPACC_S 21 | |
193 | #define OP_MASK_DSPACC_S 0x3 | |
194 | #define OP_SH_DSPSFT 20 | |
195 | #define OP_MASK_DSPSFT 0x3f | |
196 | #define OP_SH_DSPSFT_7 19 | |
197 | #define OP_MASK_DSPSFT_7 0x7f | |
198 | #define OP_SH_SA3 21 | |
199 | #define OP_MASK_SA3 0x7 | |
200 | #define OP_SH_SA4 21 | |
201 | #define OP_MASK_SA4 0xf | |
202 | #define OP_SH_IMM8 16 | |
203 | #define OP_MASK_IMM8 0xff | |
204 | #define OP_SH_IMM10 16 | |
205 | #define OP_MASK_IMM10 0x3ff | |
206 | #define OP_SH_WRDSP 11 | |
207 | #define OP_MASK_WRDSP 0x3f | |
208 | #define OP_SH_RDDSP 16 | |
209 | #define OP_MASK_RDDSP 0x3f | |
210 | #define OP_SH_BP 11 | |
211 | #define OP_MASK_BP 0x3 | |
212 | ||
213 | /* MIPS MT ASE */ | |
214 | #define OP_SH_MT_U 5 | |
215 | #define OP_MASK_MT_U 0x1 | |
216 | #define OP_SH_MT_H 4 | |
217 | #define OP_MASK_MT_H 0x1 | |
218 | #define OP_SH_MTACC_T 18 | |
219 | #define OP_MASK_MTACC_T 0x3 | |
220 | #define OP_SH_MTACC_D 13 | |
221 | #define OP_MASK_MTACC_D 0x3 | |
222 | ||
223 | #define OP_OP_COP0 0x10 | |
224 | #define OP_OP_COP1 0x11 | |
225 | #define OP_OP_COP2 0x12 | |
226 | #define OP_OP_COP3 0x13 | |
227 | #define OP_OP_LWC1 0x31 | |
228 | #define OP_OP_LWC2 0x32 | |
229 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ | |
230 | #define OP_OP_LDC1 0x35 | |
231 | #define OP_OP_LDC2 0x36 | |
232 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ | |
233 | #define OP_OP_SWC1 0x39 | |
234 | #define OP_OP_SWC2 0x3a | |
235 | #define OP_OP_SWC3 0x3b | |
236 | #define OP_OP_SDC1 0x3d | |
237 | #define OP_OP_SDC2 0x3e | |
238 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ | |
239 | ||
6643d27e FB |
240 | /* Values in the 'VSEL' field. */ |
241 | #define MDMX_FMTSEL_IMM_QH 0x1d | |
242 | #define MDMX_FMTSEL_IMM_OB 0x1e | |
243 | #define MDMX_FMTSEL_VEC_QH 0x15 | |
244 | #define MDMX_FMTSEL_VEC_OB 0x16 | |
245 | ||
29490584 TS |
246 | /* UDI */ |
247 | #define OP_SH_UDI1 6 | |
248 | #define OP_MASK_UDI1 0x1f | |
249 | #define OP_SH_UDI2 6 | |
250 | #define OP_MASK_UDI2 0x3ff | |
251 | #define OP_SH_UDI3 6 | |
252 | #define OP_MASK_UDI3 0x7fff | |
253 | #define OP_SH_UDI4 6 | |
254 | #define OP_MASK_UDI4 0xfffff | |
6643d27e FB |
255 | /* This structure holds information for a particular instruction. */ |
256 | ||
257 | struct mips_opcode | |
258 | { | |
259 | /* The name of the instruction. */ | |
260 | const char *name; | |
261 | /* A string describing the arguments for this instruction. */ | |
262 | const char *args; | |
263 | /* The basic opcode for the instruction. When assembling, this | |
264 | opcode is modified by the arguments to produce the actual opcode | |
265 | that is used. If pinfo is INSN_MACRO, then this is 0. */ | |
266 | unsigned long match; | |
267 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
268 | relevant portions of the opcode when disassembling. If the | |
269 | actual opcode anded with the match field equals the opcode field, | |
270 | then we have found the correct instruction. If pinfo is | |
271 | INSN_MACRO, then this field is the macro identifier. */ | |
272 | unsigned long mask; | |
273 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
274 | of bits describing the instruction, notably any relevant hazard | |
275 | information. */ | |
276 | unsigned long pinfo; | |
29490584 TS |
277 | /* A collection of additional bits describing the instruction. */ |
278 | unsigned long pinfo2; | |
6643d27e FB |
279 | /* A collection of bits describing the instruction sets of which this |
280 | instruction or macro is a member. */ | |
281 | unsigned long membership; | |
282 | }; | |
283 | ||
284 | /* These are the characters which may appear in the args field of an | |
285 | instruction. They appear in the order in which the fields appear | |
286 | when the instruction is used. Commas and parentheses in the args | |
287 | string are ignored when assembling, and written into the output | |
288 | when disassembling. | |
289 | ||
290 | Each of these characters corresponds to a mask field defined above. | |
291 | ||
292 | "<" 5 bit shift amount (OP_*_SHAMT) | |
293 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) | |
294 | "a" 26 bit target address (OP_*_TARGET) | |
295 | "b" 5 bit base register (OP_*_RS) | |
296 | "c" 10 bit breakpoint code (OP_*_CODE) | |
297 | "d" 5 bit destination register specifier (OP_*_RD) | |
298 | "h" 5 bit prefx hint (OP_*_PREFX) | |
299 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) | |
300 | "j" 16 bit signed immediate (OP_*_DELTA) | |
301 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) | |
302 | Also used for immediate operands in vr5400 vector insns. | |
303 | "o" 16 bit signed offset (OP_*_DELTA) | |
304 | "p" 16 bit PC relative branch target address (OP_*_DELTA) | |
305 | "q" 10 bit extra breakpoint code (OP_*_CODE2) | |
306 | "r" 5 bit same register used as both source and target (OP_*_RS) | |
307 | "s" 5 bit source register specifier (OP_*_RS) | |
308 | "t" 5 bit target register (OP_*_RT) | |
309 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) | |
310 | "v" 5 bit same register used as both source and destination (OP_*_RS) | |
311 | "w" 5 bit same register used as both target and destination (OP_*_RT) | |
312 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT | |
313 | (used by clo and clz) | |
314 | "C" 25 bit coprocessor function code (OP_*_COPZ) | |
315 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) | |
316 | "J" 19 bit wait function code (OP_*_CODE19) | |
317 | "x" accept and ignore register name | |
318 | "z" must be zero register | |
319 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) | |
29490584 TS |
320 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
321 | LSB (OP_*_SHAMT). | |
6643d27e | 322 | Enforces: 0 <= pos < 32. |
29490584 | 323 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
6643d27e FB |
324 | Requires that "+A" or "+E" occur first to set position. |
325 | Enforces: 0 < (pos+size) <= 32. | |
29490584 | 326 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
6643d27e FB |
327 | Requires that "+A" or "+E" occur first to set position. |
328 | Enforces: 0 < (pos+size) <= 32. | |
329 | (Also used by "dext" w/ different limits, but limits for | |
330 | that are checked by the M_DEXT macro.) | |
29490584 | 331 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
6643d27e | 332 | Enforces: 32 <= pos < 64. |
29490584 | 333 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
6643d27e FB |
334 | Requires that "+A" or "+E" occur first to set position. |
335 | Enforces: 32 < (pos+size) <= 64. | |
336 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). | |
337 | Requires that "+A" or "+E" occur first to set position. | |
338 | Enforces: 32 < (pos+size) <= 64. | |
339 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). | |
340 | Requires that "+A" or "+E" occur first to set position. | |
341 | Enforces: 32 < (pos+size) <= 64. | |
342 | ||
343 | Floating point instructions: | |
344 | "D" 5 bit destination register (OP_*_FD) | |
345 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) | |
346 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) | |
347 | "S" 5 bit fs source 1 register (OP_*_FS) | |
348 | "T" 5 bit ft source 2 register (OP_*_FT) | |
349 | "R" 5 bit fr source 3 register (OP_*_FR) | |
350 | "V" 5 bit same register used as floating source and destination (OP_*_FS) | |
351 | "W" 5 bit same register used as floating target and destination (OP_*_FT) | |
352 | ||
353 | Coprocessor instructions: | |
354 | "E" 5 bit target register (OP_*_RT) | |
355 | "G" 5 bit destination register (OP_*_RD) | |
356 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) | |
357 | "P" 5 bit performance-monitor register (OP_*_PERFREG) | |
358 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) | |
359 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) | |
360 | see also "k" above | |
361 | "+D" Combined destination register ("G") and sel ("H") for CP0 ops, | |
362 | for pretty-printing in disassembly only. | |
363 | ||
364 | Macro instructions: | |
365 | "A" General 32 bit expression | |
366 | "I" 32 bit immediate (value placed in imm_expr). | |
367 | "+I" 32 bit immediate (value placed in imm2_expr). | |
368 | "F" 64 bit floating point constant in .rdata | |
369 | "L" 64 bit floating point constant in .lit8 | |
370 | "f" 32 bit floating point constant | |
371 | "l" 32 bit floating point constant in .lit4 | |
372 | ||
373 | MDMX instruction operands (note that while these use the FP register | |
3b46e624 | 374 | fields, they accept both $fN and $vN names for the registers): |
6643d27e FB |
375 | "O" MDMX alignment offset (OP_*_ALN) |
376 | "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) | |
5fafdf24 | 377 | "X" MDMX destination register (OP_*_FD) |
6643d27e FB |
378 | "Y" MDMX source register (OP_*_FS) |
379 | "Z" MDMX source register (OP_*_FT) | |
380 | ||
29490584 TS |
381 | DSP ASE usage: |
382 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) | |
383 | "3" 3 bit unsigned immediate (OP_*_SA3) | |
384 | "4" 4 bit unsigned immediate (OP_*_SA4) | |
385 | "5" 8 bit unsigned immediate (OP_*_IMM8) | |
386 | "6" 5 bit unsigned immediate (OP_*_RS) | |
387 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) | |
388 | "8" 6 bit unsigned immediate (OP_*_WRDSP) | |
389 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) | |
390 | "0" 6 bit signed immediate (OP_*_DSPSFT) | |
391 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) | |
392 | "'" 6 bit unsigned immediate (OP_*_RDDSP) | |
393 | "@" 10 bit signed immediate (OP_*_IMM10) | |
394 | ||
395 | MT ASE usage: | |
396 | "!" 1 bit usermode flag (OP_*_MT_U) | |
397 | "$" 1 bit load high flag (OP_*_MT_H) | |
398 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) | |
399 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) | |
400 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) | |
401 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) | |
402 | "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only | |
403 | ||
404 | UDI immediates: | |
405 | "+1" UDI immediate bits 6-10 | |
406 | "+2" UDI immediate bits 6-15 | |
407 | "+3" UDI immediate bits 6-20 | |
408 | "+4" UDI immediate bits 6-25 | |
409 | ||
6643d27e FB |
410 | Other: |
411 | "()" parens surrounding optional value | |
412 | "," separates operands | |
413 | "[]" brackets around index for vector-op scalar operand specifier (vr5400) | |
414 | "+" Start of extension sequence. | |
415 | ||
416 | Characters used so far, for quick reference when adding more: | |
29490584 TS |
417 | "234567890" |
418 | "%[]<>(),+:'@!$*&" | |
6643d27e | 419 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
29490584 | 420 | "abcdefghijklopqrstuvwxz" |
6643d27e FB |
421 | |
422 | Extension character sequences used so far ("+" followed by the | |
423 | following), for quick reference when adding more: | |
29490584 TS |
424 | "1234" |
425 | "ABCDEFGHIT" | |
426 | "t" | |
6643d27e FB |
427 | */ |
428 | ||
429 | /* These are the bits which may be set in the pinfo field of an | |
430 | instructions, if it is not equal to INSN_MACRO. */ | |
431 | ||
432 | /* Modifies the general purpose register in OP_*_RD. */ | |
433 | #define INSN_WRITE_GPR_D 0x00000001 | |
434 | /* Modifies the general purpose register in OP_*_RT. */ | |
435 | #define INSN_WRITE_GPR_T 0x00000002 | |
436 | /* Modifies general purpose register 31. */ | |
437 | #define INSN_WRITE_GPR_31 0x00000004 | |
438 | /* Modifies the floating point register in OP_*_FD. */ | |
439 | #define INSN_WRITE_FPR_D 0x00000008 | |
440 | /* Modifies the floating point register in OP_*_FS. */ | |
441 | #define INSN_WRITE_FPR_S 0x00000010 | |
442 | /* Modifies the floating point register in OP_*_FT. */ | |
443 | #define INSN_WRITE_FPR_T 0x00000020 | |
444 | /* Reads the general purpose register in OP_*_RS. */ | |
445 | #define INSN_READ_GPR_S 0x00000040 | |
446 | /* Reads the general purpose register in OP_*_RT. */ | |
447 | #define INSN_READ_GPR_T 0x00000080 | |
448 | /* Reads the floating point register in OP_*_FS. */ | |
449 | #define INSN_READ_FPR_S 0x00000100 | |
450 | /* Reads the floating point register in OP_*_FT. */ | |
451 | #define INSN_READ_FPR_T 0x00000200 | |
452 | /* Reads the floating point register in OP_*_FR. */ | |
453 | #define INSN_READ_FPR_R 0x00000400 | |
454 | /* Modifies coprocessor condition code. */ | |
455 | #define INSN_WRITE_COND_CODE 0x00000800 | |
456 | /* Reads coprocessor condition code. */ | |
457 | #define INSN_READ_COND_CODE 0x00001000 | |
458 | /* TLB operation. */ | |
459 | #define INSN_TLB 0x00002000 | |
460 | /* Reads coprocessor register other than floating point register. */ | |
461 | #define INSN_COP 0x00004000 | |
462 | /* Instruction loads value from memory, requiring delay. */ | |
463 | #define INSN_LOAD_MEMORY_DELAY 0x00008000 | |
464 | /* Instruction loads value from coprocessor, requiring delay. */ | |
465 | #define INSN_LOAD_COPROC_DELAY 0x00010000 | |
466 | /* Instruction has unconditional branch delay slot. */ | |
467 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 | |
468 | /* Instruction has conditional branch delay slot. */ | |
469 | #define INSN_COND_BRANCH_DELAY 0x00040000 | |
470 | /* Conditional branch likely: if branch not taken, insn nullified. */ | |
471 | #define INSN_COND_BRANCH_LIKELY 0x00080000 | |
472 | /* Moves to coprocessor register, requiring delay. */ | |
473 | #define INSN_COPROC_MOVE_DELAY 0x00100000 | |
474 | /* Loads coprocessor register from memory, requiring delay. */ | |
475 | #define INSN_COPROC_MEMORY_DELAY 0x00200000 | |
476 | /* Reads the HI register. */ | |
477 | #define INSN_READ_HI 0x00400000 | |
478 | /* Reads the LO register. */ | |
479 | #define INSN_READ_LO 0x00800000 | |
480 | /* Modifies the HI register. */ | |
481 | #define INSN_WRITE_HI 0x01000000 | |
482 | /* Modifies the LO register. */ | |
483 | #define INSN_WRITE_LO 0x02000000 | |
484 | /* Takes a trap (easier to keep out of delay slot). */ | |
485 | #define INSN_TRAP 0x04000000 | |
486 | /* Instruction stores value into memory. */ | |
487 | #define INSN_STORE_MEMORY 0x08000000 | |
488 | /* Instruction uses single precision floating point. */ | |
489 | #define FP_S 0x10000000 | |
490 | /* Instruction uses double precision floating point. */ | |
491 | #define FP_D 0x20000000 | |
492 | /* Instruction is part of the tx39's integer multiply family. */ | |
493 | #define INSN_MULT 0x40000000 | |
494 | /* Instruction synchronize shared memory. */ | |
495 | #define INSN_SYNC 0x80000000 | |
29490584 TS |
496 | |
497 | /* These are the bits which may be set in the pinfo2 field of an | |
498 | instruction. */ | |
499 | ||
500 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ | |
501 | #define INSN2_ALIAS 0x00000001 | |
502 | /* Instruction reads MDMX accumulator. */ | |
503 | #define INSN2_READ_MDMX_ACC 0x00000002 | |
504 | /* Instruction writes MDMX accumulator. */ | |
505 | #define INSN2_WRITE_MDMX_ACC 0x00000004 | |
6643d27e FB |
506 | |
507 | /* Instruction is actually a macro. It should be ignored by the | |
508 | disassembler, and requires special treatment by the assembler. */ | |
509 | #define INSN_MACRO 0xffffffff | |
510 | ||
511 | /* Masks used to mark instructions to indicate which MIPS ISA level | |
512 | they were introduced in. ISAs, as defined below, are logical | |
513 | ORs of these bits, indicating that they support the instructions | |
514 | defined at the given level. */ | |
515 | ||
516 | #define INSN_ISA_MASK 0x00000fff | |
517 | #define INSN_ISA1 0x00000001 | |
518 | #define INSN_ISA2 0x00000002 | |
519 | #define INSN_ISA3 0x00000004 | |
520 | #define INSN_ISA4 0x00000008 | |
521 | #define INSN_ISA5 0x00000010 | |
522 | #define INSN_ISA32 0x00000020 | |
523 | #define INSN_ISA64 0x00000040 | |
524 | #define INSN_ISA32R2 0x00000080 | |
525 | #define INSN_ISA64R2 0x00000100 | |
b691d9d2 LA |
526 | #define INSN_ISA32R6 0x00000200 |
527 | #define INSN_ISA64R6 0x00000400 | |
6643d27e FB |
528 | |
529 | /* Masks used for MIPS-defined ASEs. */ | |
530 | #define INSN_ASE_MASK 0x0000f000 | |
531 | ||
29490584 TS |
532 | /* DSP ASE */ |
533 | #define INSN_DSP 0x00001000 | |
534 | #define INSN_DSP64 0x00002000 | |
6643d27e | 535 | /* MIPS 16 ASE */ |
29490584 | 536 | #define INSN_MIPS16 0x00004000 |
6643d27e | 537 | /* MIPS-3D ASE */ |
29490584 | 538 | #define INSN_MIPS3D 0x00008000 |
6643d27e FB |
539 | |
540 | /* Chip specific instructions. These are bitmasks. */ | |
541 | ||
542 | /* MIPS R4650 instruction. */ | |
543 | #define INSN_4650 0x00010000 | |
544 | /* LSI R4010 instruction. */ | |
545 | #define INSN_4010 0x00020000 | |
546 | /* NEC VR4100 instruction. */ | |
547 | #define INSN_4100 0x00040000 | |
548 | /* Toshiba R3900 instruction. */ | |
549 | #define INSN_3900 0x00080000 | |
550 | /* MIPS R10000 instruction. */ | |
551 | #define INSN_10000 0x00100000 | |
552 | /* Broadcom SB-1 instruction. */ | |
553 | #define INSN_SB1 0x00200000 | |
554 | /* NEC VR4111/VR4181 instruction. */ | |
555 | #define INSN_4111 0x00400000 | |
556 | /* NEC VR4120 instruction. */ | |
557 | #define INSN_4120 0x00800000 | |
558 | /* NEC VR5400 instruction. */ | |
559 | #define INSN_5400 0x01000000 | |
560 | /* NEC VR5500 instruction. */ | |
561 | #define INSN_5500 0x02000000 | |
562 | ||
29490584 TS |
563 | /* MDMX ASE */ |
564 | #define INSN_MDMX 0x04000000 | |
565 | /* MT ASE */ | |
566 | #define INSN_MT 0x08000000 | |
567 | /* SmartMIPS ASE */ | |
568 | #define INSN_SMARTMIPS 0x10000000 | |
569 | /* DSP R2 ASE */ | |
570 | #define INSN_DSPR2 0x20000000 | |
571 | ||
15656e09 AJ |
572 | /* ST Microelectronics Loongson 2E. */ |
573 | #define INSN_LOONGSON_2E 0x40000000 | |
574 | /* ST Microelectronics Loongson 2F. */ | |
575 | #define INSN_LOONGSON_2F 0x80000000 | |
576 | ||
6643d27e FB |
577 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
578 | ||
579 | #define ISA_UNKNOWN 0 /* Gas internal use. */ | |
580 | #define ISA_MIPS1 (INSN_ISA1) | |
581 | #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) | |
582 | #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) | |
583 | #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) | |
584 | #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) | |
585 | ||
586 | #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) | |
587 | #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) | |
588 | ||
589 | #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) | |
590 | #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) | |
591 | ||
b691d9d2 LA |
592 | #define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6) |
593 | #define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6) | |
6643d27e FB |
594 | |
595 | /* CPU defines, use instead of hardcoding processor number. Keep this | |
596 | in sync with bfd/archures.c in order for machine selection to work. */ | |
597 | #define CPU_UNKNOWN 0 /* Gas internal use. */ | |
598 | #define CPU_R3000 3000 | |
599 | #define CPU_R3900 3900 | |
600 | #define CPU_R4000 4000 | |
601 | #define CPU_R4010 4010 | |
602 | #define CPU_VR4100 4100 | |
603 | #define CPU_R4111 4111 | |
604 | #define CPU_VR4120 4120 | |
605 | #define CPU_R4300 4300 | |
606 | #define CPU_R4400 4400 | |
607 | #define CPU_R4600 4600 | |
608 | #define CPU_R4650 4650 | |
609 | #define CPU_R5000 5000 | |
610 | #define CPU_VR5400 5400 | |
611 | #define CPU_VR5500 5500 | |
612 | #define CPU_R6000 6000 | |
613 | #define CPU_RM7000 7000 | |
614 | #define CPU_R8000 8000 | |
615 | #define CPU_R10000 10000 | |
616 | #define CPU_R12000 12000 | |
617 | #define CPU_MIPS16 16 | |
618 | #define CPU_MIPS32 32 | |
619 | #define CPU_MIPS32R2 33 | |
620 | #define CPU_MIPS5 5 | |
621 | #define CPU_MIPS64 64 | |
622 | #define CPU_MIPS64R2 65 | |
623 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ | |
624 | ||
625 | /* Test for membership in an ISA including chip specific ISAs. INSN | |
626 | is pointer to an element of the opcode table; ISA is the specified | |
627 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to | |
628 | test, or zero if no CPU specific ISA test is desired. */ | |
629 | ||
42fe4044 | 630 | #if 0 |
6643d27e FB |
631 | #define OPCODE_IS_MEMBER(insn, isa, cpu) \ |
632 | (((insn)->membership & isa) != 0 \ | |
633 | || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ | |
634 | || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ | |
29490584 | 635 | || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ |
6643d27e FB |
636 | || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
637 | || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ | |
638 | || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ | |
639 | || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ | |
640 | && ((insn)->membership & INSN_10000) != 0) \ | |
641 | || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ | |
642 | || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ | |
643 | || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ | |
644 | || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ | |
645 | || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ | |
646 | || 0) /* Please keep this term for easier source merging. */ | |
42fe4044 FB |
647 | #else |
648 | #define OPCODE_IS_MEMBER(insn, isa, cpu) \ | |
649 | (1 != 0) | |
650 | #endif | |
6643d27e FB |
651 | |
652 | /* This is a list of macro expanded instructions. | |
653 | ||
654 | _I appended means immediate | |
655 | _A appended means address | |
656 | _AB appended means address with base register | |
657 | _D appended means 64 bit floating point constant | |
658 | _S appended means 32 bit floating point constant. */ | |
659 | ||
660 | enum | |
661 | { | |
662 | M_ABS, | |
663 | M_ADD_I, | |
664 | M_ADDU_I, | |
665 | M_AND_I, | |
29490584 | 666 | M_BALIGN, |
6643d27e FB |
667 | M_BEQ, |
668 | M_BEQ_I, | |
669 | M_BEQL_I, | |
670 | M_BGE, | |
671 | M_BGEL, | |
672 | M_BGE_I, | |
673 | M_BGEL_I, | |
674 | M_BGEU, | |
675 | M_BGEUL, | |
676 | M_BGEU_I, | |
677 | M_BGEUL_I, | |
678 | M_BGT, | |
679 | M_BGTL, | |
680 | M_BGT_I, | |
681 | M_BGTL_I, | |
682 | M_BGTU, | |
683 | M_BGTUL, | |
684 | M_BGTU_I, | |
685 | M_BGTUL_I, | |
686 | M_BLE, | |
687 | M_BLEL, | |
688 | M_BLE_I, | |
689 | M_BLEL_I, | |
690 | M_BLEU, | |
691 | M_BLEUL, | |
692 | M_BLEU_I, | |
693 | M_BLEUL_I, | |
694 | M_BLT, | |
695 | M_BLTL, | |
696 | M_BLT_I, | |
697 | M_BLTL_I, | |
698 | M_BLTU, | |
699 | M_BLTUL, | |
700 | M_BLTU_I, | |
701 | M_BLTUL_I, | |
702 | M_BNE, | |
703 | M_BNE_I, | |
704 | M_BNEL_I, | |
29490584 | 705 | M_CACHE_AB, |
6643d27e FB |
706 | M_DABS, |
707 | M_DADD_I, | |
708 | M_DADDU_I, | |
709 | M_DDIV_3, | |
710 | M_DDIV_3I, | |
711 | M_DDIVU_3, | |
712 | M_DDIVU_3I, | |
713 | M_DEXT, | |
714 | M_DINS, | |
715 | M_DIV_3, | |
716 | M_DIV_3I, | |
717 | M_DIVU_3, | |
718 | M_DIVU_3I, | |
719 | M_DLA_AB, | |
720 | M_DLCA_AB, | |
721 | M_DLI, | |
722 | M_DMUL, | |
723 | M_DMUL_I, | |
724 | M_DMULO, | |
725 | M_DMULO_I, | |
726 | M_DMULOU, | |
727 | M_DMULOU_I, | |
728 | M_DREM_3, | |
729 | M_DREM_3I, | |
730 | M_DREMU_3, | |
731 | M_DREMU_3I, | |
732 | M_DSUB_I, | |
733 | M_DSUBU_I, | |
734 | M_DSUBU_I_2, | |
735 | M_J_A, | |
736 | M_JAL_1, | |
737 | M_JAL_2, | |
738 | M_JAL_A, | |
739 | M_L_DOB, | |
740 | M_L_DAB, | |
741 | M_LA_AB, | |
742 | M_LB_A, | |
743 | M_LB_AB, | |
744 | M_LBU_A, | |
745 | M_LBU_AB, | |
746 | M_LCA_AB, | |
747 | M_LD_A, | |
748 | M_LD_OB, | |
749 | M_LD_AB, | |
750 | M_LDC1_AB, | |
751 | M_LDC2_AB, | |
752 | M_LDC3_AB, | |
753 | M_LDL_AB, | |
754 | M_LDR_AB, | |
755 | M_LH_A, | |
756 | M_LH_AB, | |
757 | M_LHU_A, | |
758 | M_LHU_AB, | |
759 | M_LI, | |
760 | M_LI_D, | |
761 | M_LI_DD, | |
762 | M_LI_S, | |
763 | M_LI_SS, | |
764 | M_LL_AB, | |
765 | M_LLD_AB, | |
766 | M_LS_A, | |
767 | M_LW_A, | |
768 | M_LW_AB, | |
769 | M_LWC0_A, | |
770 | M_LWC0_AB, | |
771 | M_LWC1_A, | |
772 | M_LWC1_AB, | |
773 | M_LWC2_A, | |
774 | M_LWC2_AB, | |
775 | M_LWC3_A, | |
776 | M_LWC3_AB, | |
777 | M_LWL_A, | |
778 | M_LWL_AB, | |
779 | M_LWR_A, | |
780 | M_LWR_AB, | |
781 | M_LWU_AB, | |
782 | M_MOVE, | |
783 | M_MUL, | |
784 | M_MUL_I, | |
785 | M_MULO, | |
786 | M_MULO_I, | |
787 | M_MULOU, | |
788 | M_MULOU_I, | |
789 | M_NOR_I, | |
790 | M_OR_I, | |
791 | M_REM_3, | |
792 | M_REM_3I, | |
793 | M_REMU_3, | |
794 | M_REMU_3I, | |
795 | M_DROL, | |
796 | M_ROL, | |
797 | M_DROL_I, | |
798 | M_ROL_I, | |
799 | M_DROR, | |
800 | M_ROR, | |
801 | M_DROR_I, | |
802 | M_ROR_I, | |
803 | M_S_DA, | |
804 | M_S_DOB, | |
805 | M_S_DAB, | |
806 | M_S_S, | |
807 | M_SC_AB, | |
808 | M_SCD_AB, | |
809 | M_SD_A, | |
810 | M_SD_OB, | |
811 | M_SD_AB, | |
812 | M_SDC1_AB, | |
813 | M_SDC2_AB, | |
814 | M_SDC3_AB, | |
815 | M_SDL_AB, | |
816 | M_SDR_AB, | |
817 | M_SEQ, | |
818 | M_SEQ_I, | |
819 | M_SGE, | |
820 | M_SGE_I, | |
821 | M_SGEU, | |
822 | M_SGEU_I, | |
823 | M_SGT, | |
824 | M_SGT_I, | |
825 | M_SGTU, | |
826 | M_SGTU_I, | |
827 | M_SLE, | |
828 | M_SLE_I, | |
829 | M_SLEU, | |
830 | M_SLEU_I, | |
831 | M_SLT_I, | |
832 | M_SLTU_I, | |
833 | M_SNE, | |
834 | M_SNE_I, | |
835 | M_SB_A, | |
836 | M_SB_AB, | |
837 | M_SH_A, | |
838 | M_SH_AB, | |
839 | M_SW_A, | |
840 | M_SW_AB, | |
841 | M_SWC0_A, | |
842 | M_SWC0_AB, | |
843 | M_SWC1_A, | |
844 | M_SWC1_AB, | |
845 | M_SWC2_A, | |
846 | M_SWC2_AB, | |
847 | M_SWC3_A, | |
848 | M_SWC3_AB, | |
849 | M_SWL_A, | |
850 | M_SWL_AB, | |
851 | M_SWR_A, | |
852 | M_SWR_AB, | |
853 | M_SUB_I, | |
854 | M_SUBU_I, | |
855 | M_SUBU_I_2, | |
856 | M_TEQ_I, | |
857 | M_TGE_I, | |
858 | M_TGEU_I, | |
859 | M_TLT_I, | |
860 | M_TLTU_I, | |
861 | M_TNE_I, | |
862 | M_TRUNCWD, | |
863 | M_TRUNCWS, | |
864 | M_ULD, | |
865 | M_ULD_A, | |
866 | M_ULH, | |
867 | M_ULH_A, | |
868 | M_ULHU, | |
869 | M_ULHU_A, | |
870 | M_ULW, | |
871 | M_ULW_A, | |
872 | M_USH, | |
873 | M_USH_A, | |
874 | M_USW, | |
875 | M_USW_A, | |
876 | M_USD, | |
877 | M_USD_A, | |
878 | M_XOR_I, | |
879 | M_COP0, | |
880 | M_COP1, | |
881 | M_COP2, | |
882 | M_COP3, | |
883 | M_NUM_MACROS | |
884 | }; | |
885 | ||
886 | ||
887 | /* The order of overloaded instructions matters. Label arguments and | |
888 | register arguments look the same. Instructions that can have either | |
889 | for arguments must apear in the correct order in this table for the | |
890 | assembler to pick the right one. In other words, entries with | |
891 | immediate operands must apear after the same instruction with | |
892 | registers. | |
893 | ||
894 | Many instructions are short hand for other instructions (i.e., The | |
895 | jal <register> instruction is short for jalr <register>). */ | |
896 | ||
897 | extern const struct mips_opcode mips_builtin_opcodes[]; | |
898 | extern const int bfd_mips_num_builtin_opcodes; | |
899 | extern struct mips_opcode *mips_opcodes; | |
900 | extern int bfd_mips_num_opcodes; | |
901 | #define NUMOPCODES bfd_mips_num_opcodes | |
902 | ||
903 | \f | |
904 | /* The rest of this file adds definitions for the mips16 TinyRISC | |
905 | processor. */ | |
906 | ||
907 | /* These are the bitmasks and shift counts used for the different | |
908 | fields in the instruction formats. Other than OP, no masks are | |
909 | provided for the fixed portions of an instruction, since they are | |
910 | not needed. | |
911 | ||
912 | The I format uses IMM11. | |
913 | ||
914 | The RI format uses RX and IMM8. | |
915 | ||
916 | The RR format uses RX, and RY. | |
917 | ||
918 | The RRI format uses RX, RY, and IMM5. | |
919 | ||
920 | The RRR format uses RX, RY, and RZ. | |
921 | ||
922 | The RRI_A format uses RX, RY, and IMM4. | |
923 | ||
924 | The SHIFT format uses RX, RY, and SHAMT. | |
925 | ||
926 | The I8 format uses IMM8. | |
927 | ||
928 | The I8_MOVR32 format uses RY and REGR32. | |
929 | ||
930 | The IR_MOV32R format uses REG32R and MOV32Z. | |
931 | ||
932 | The I64 format uses IMM8. | |
933 | ||
934 | The RI64 format uses RY and IMM5. | |
935 | */ | |
936 | ||
937 | #define MIPS16OP_MASK_OP 0x1f | |
938 | #define MIPS16OP_SH_OP 11 | |
939 | #define MIPS16OP_MASK_IMM11 0x7ff | |
940 | #define MIPS16OP_SH_IMM11 0 | |
941 | #define MIPS16OP_MASK_RX 0x7 | |
942 | #define MIPS16OP_SH_RX 8 | |
943 | #define MIPS16OP_MASK_IMM8 0xff | |
944 | #define MIPS16OP_SH_IMM8 0 | |
945 | #define MIPS16OP_MASK_RY 0x7 | |
946 | #define MIPS16OP_SH_RY 5 | |
947 | #define MIPS16OP_MASK_IMM5 0x1f | |
948 | #define MIPS16OP_SH_IMM5 0 | |
949 | #define MIPS16OP_MASK_RZ 0x7 | |
950 | #define MIPS16OP_SH_RZ 2 | |
951 | #define MIPS16OP_MASK_IMM4 0xf | |
952 | #define MIPS16OP_SH_IMM4 0 | |
953 | #define MIPS16OP_MASK_REGR32 0x1f | |
954 | #define MIPS16OP_SH_REGR32 0 | |
955 | #define MIPS16OP_MASK_REG32R 0x1f | |
956 | #define MIPS16OP_SH_REG32R 3 | |
957 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) | |
958 | #define MIPS16OP_MASK_MOVE32Z 0x7 | |
959 | #define MIPS16OP_SH_MOVE32Z 0 | |
960 | #define MIPS16OP_MASK_IMM6 0x3f | |
961 | #define MIPS16OP_SH_IMM6 5 | |
962 | ||
963 | /* These are the characters which may appears in the args field of an | |
964 | instruction. They appear in the order in which the fields appear | |
965 | when the instruction is used. Commas and parentheses in the args | |
966 | string are ignored when assembling, and written into the output | |
967 | when disassembling. | |
968 | ||
969 | "y" 3 bit register (MIPS16OP_*_RY) | |
970 | "x" 3 bit register (MIPS16OP_*_RX) | |
971 | "z" 3 bit register (MIPS16OP_*_RZ) | |
972 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) | |
973 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) | |
974 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) | |
975 | "0" zero register ($0) | |
976 | "S" stack pointer ($sp or $29) | |
977 | "P" program counter | |
978 | "R" return address register ($ra or $31) | |
979 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) | |
980 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) | |
981 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) | |
982 | "a" 26 bit jump address | |
983 | "e" 11 bit extension value | |
984 | "l" register list for entry instruction | |
985 | "L" register list for exit instruction | |
986 | ||
987 | The remaining codes may be extended. Except as otherwise noted, | |
988 | the full extended operand is a 16 bit signed value. | |
989 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) | |
990 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) | |
991 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) | |
992 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) | |
993 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) | |
994 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) | |
995 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) | |
996 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) | |
997 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) | |
998 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) | |
999 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) | |
1000 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) | |
1001 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) | |
1002 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) | |
1003 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) | |
1004 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) | |
1005 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) | |
1006 | "q" 11 bit branch address (MIPS16OP_*_IMM11) | |
1007 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) | |
1008 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) | |
1009 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) | |
1010 | */ | |
1011 | ||
29490584 TS |
1012 | /* Save/restore encoding for the args field when all 4 registers are |
1013 | either saved as arguments or saved/restored as statics. */ | |
1014 | #define MIPS16_ALL_ARGS 0xe | |
1015 | #define MIPS16_ALL_STATICS 0xb | |
1016 | ||
6643d27e FB |
1017 | /* For the mips16, we use the same opcode table format and a few of |
1018 | the same flags. However, most of the flags are different. */ | |
1019 | ||
1020 | /* Modifies the register in MIPS16OP_*_RX. */ | |
1021 | #define MIPS16_INSN_WRITE_X 0x00000001 | |
1022 | /* Modifies the register in MIPS16OP_*_RY. */ | |
1023 | #define MIPS16_INSN_WRITE_Y 0x00000002 | |
1024 | /* Modifies the register in MIPS16OP_*_RZ. */ | |
1025 | #define MIPS16_INSN_WRITE_Z 0x00000004 | |
1026 | /* Modifies the T ($24) register. */ | |
1027 | #define MIPS16_INSN_WRITE_T 0x00000008 | |
1028 | /* Modifies the SP ($29) register. */ | |
1029 | #define MIPS16_INSN_WRITE_SP 0x00000010 | |
1030 | /* Modifies the RA ($31) register. */ | |
1031 | #define MIPS16_INSN_WRITE_31 0x00000020 | |
1032 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ | |
1033 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 | |
1034 | /* Reads the register in MIPS16OP_*_RX. */ | |
1035 | #define MIPS16_INSN_READ_X 0x00000080 | |
1036 | /* Reads the register in MIPS16OP_*_RY. */ | |
1037 | #define MIPS16_INSN_READ_Y 0x00000100 | |
1038 | /* Reads the register in MIPS16OP_*_MOVE32Z. */ | |
1039 | #define MIPS16_INSN_READ_Z 0x00000200 | |
1040 | /* Reads the T ($24) register. */ | |
1041 | #define MIPS16_INSN_READ_T 0x00000400 | |
1042 | /* Reads the SP ($29) register. */ | |
1043 | #define MIPS16_INSN_READ_SP 0x00000800 | |
1044 | /* Reads the RA ($31) register. */ | |
1045 | #define MIPS16_INSN_READ_31 0x00001000 | |
1046 | /* Reads the program counter. */ | |
1047 | #define MIPS16_INSN_READ_PC 0x00002000 | |
1048 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */ | |
1049 | #define MIPS16_INSN_READ_GPR_X 0x00004000 | |
1050 | /* Is a branch insn. */ | |
1051 | #define MIPS16_INSN_BRANCH 0x00010000 | |
1052 | ||
1053 | /* The following flags have the same value for the mips16 opcode | |
1054 | table: | |
1055 | INSN_UNCOND_BRANCH_DELAY | |
1056 | INSN_COND_BRANCH_DELAY | |
1057 | INSN_COND_BRANCH_LIKELY (never used) | |
1058 | INSN_READ_HI | |
1059 | INSN_READ_LO | |
1060 | INSN_WRITE_HI | |
1061 | INSN_WRITE_LO | |
1062 | INSN_TRAP | |
1063 | INSN_ISA3 | |
1064 | */ | |
1065 | ||
1066 | extern const struct mips_opcode mips16_opcodes[]; | |
1067 | extern const int bfd_mips16_num_opcodes; | |
1068 | ||
1069 | /* Short hand so the lines aren't too long. */ | |
1070 | ||
1071 | #define LDD INSN_LOAD_MEMORY_DELAY | |
1072 | #define LCD INSN_LOAD_COPROC_DELAY | |
1073 | #define UBD INSN_UNCOND_BRANCH_DELAY | |
1074 | #define CBD INSN_COND_BRANCH_DELAY | |
1075 | #define COD INSN_COPROC_MOVE_DELAY | |
1076 | #define CLD INSN_COPROC_MEMORY_DELAY | |
1077 | #define CBL INSN_COND_BRANCH_LIKELY | |
1078 | #define TRAP INSN_TRAP | |
1079 | #define SM INSN_STORE_MEMORY | |
1080 | ||
1081 | #define WR_d INSN_WRITE_GPR_D | |
1082 | #define WR_t INSN_WRITE_GPR_T | |
1083 | #define WR_31 INSN_WRITE_GPR_31 | |
1084 | #define WR_D INSN_WRITE_FPR_D | |
1085 | #define WR_T INSN_WRITE_FPR_T | |
1086 | #define WR_S INSN_WRITE_FPR_S | |
1087 | #define RD_s INSN_READ_GPR_S | |
1088 | #define RD_b INSN_READ_GPR_S | |
1089 | #define RD_t INSN_READ_GPR_T | |
1090 | #define RD_S INSN_READ_FPR_S | |
1091 | #define RD_T INSN_READ_FPR_T | |
1092 | #define RD_R INSN_READ_FPR_R | |
1093 | #define WR_CC INSN_WRITE_COND_CODE | |
1094 | #define RD_CC INSN_READ_COND_CODE | |
1095 | #define RD_C0 INSN_COP | |
1096 | #define RD_C1 INSN_COP | |
1097 | #define RD_C2 INSN_COP | |
1098 | #define RD_C3 INSN_COP | |
1099 | #define WR_C0 INSN_COP | |
1100 | #define WR_C1 INSN_COP | |
1101 | #define WR_C2 INSN_COP | |
1102 | #define WR_C3 INSN_COP | |
1103 | ||
1104 | #define WR_HI INSN_WRITE_HI | |
1105 | #define RD_HI INSN_READ_HI | |
1106 | #define MOD_HI WR_HI|RD_HI | |
1107 | ||
1108 | #define WR_LO INSN_WRITE_LO | |
1109 | #define RD_LO INSN_READ_LO | |
1110 | #define MOD_LO WR_LO|RD_LO | |
1111 | ||
1112 | #define WR_HILO WR_HI|WR_LO | |
1113 | #define RD_HILO RD_HI|RD_LO | |
1114 | #define MOD_HILO WR_HILO|RD_HILO | |
1115 | ||
1116 | #define IS_M INSN_MULT | |
1117 | ||
29490584 TS |
1118 | #define WR_MACC INSN2_WRITE_MDMX_ACC |
1119 | #define RD_MACC INSN2_READ_MDMX_ACC | |
6643d27e FB |
1120 | |
1121 | #define I1 INSN_ISA1 | |
1122 | #define I2 INSN_ISA2 | |
1123 | #define I3 INSN_ISA3 | |
1124 | #define I4 INSN_ISA4 | |
1125 | #define I5 INSN_ISA5 | |
1126 | #define I32 INSN_ISA32 | |
1127 | #define I64 INSN_ISA64 | |
1128 | #define I33 INSN_ISA32R2 | |
1129 | #define I65 INSN_ISA64R2 | |
b691d9d2 LA |
1130 | #define I32R6 INSN_ISA32R6 |
1131 | #define I64R6 INSN_ISA64R6 | |
6643d27e FB |
1132 | |
1133 | /* MIPS64 MIPS-3D ASE support. */ | |
1134 | #define I16 INSN_MIPS16 | |
1135 | ||
29490584 TS |
1136 | /* MIPS32 SmartMIPS ASE support. */ |
1137 | #define SMT INSN_SMARTMIPS | |
1138 | ||
6643d27e FB |
1139 | /* MIPS64 MIPS-3D ASE support. */ |
1140 | #define M3D INSN_MIPS3D | |
1141 | ||
1142 | /* MIPS64 MDMX ASE support. */ | |
1143 | #define MX INSN_MDMX | |
1144 | ||
15656e09 AJ |
1145 | #define IL2E (INSN_LOONGSON_2E) |
1146 | #define IL2F (INSN_LOONGSON_2F) | |
1147 | ||
6643d27e FB |
1148 | #define P3 INSN_4650 |
1149 | #define L1 INSN_4010 | |
1150 | #define V1 (INSN_4100 | INSN_4111 | INSN_4120) | |
1151 | #define T3 INSN_3900 | |
1152 | #define M1 INSN_10000 | |
1153 | #define SB1 INSN_SB1 | |
1154 | #define N411 INSN_4111 | |
1155 | #define N412 INSN_4120 | |
1156 | #define N5 (INSN_5400 | INSN_5500) | |
1157 | #define N54 INSN_5400 | |
1158 | #define N55 INSN_5500 | |
1159 | ||
1160 | #define G1 (T3 \ | |
1161 | ) | |
1162 | ||
1163 | #define G2 (T3 \ | |
1164 | ) | |
1165 | ||
1166 | #define G3 (I4 \ | |
1167 | ) | |
1168 | ||
29490584 TS |
1169 | /* MIPS DSP ASE support. |
1170 | NOTE: | |
1171 | 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair | |
1172 | of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have | |
1173 | the same structure as $ac0 (HI + LO). For DSP instructions that write or | |
1174 | read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a | |
1175 | (RD_HILO) attributes, such that HILO dependencies are maintained | |
1176 | conservatively. | |
1177 | ||
1178 | 2. For some mul. instructions that use integer registers as destinations | |
1179 | but destroy HI+LO as side-effect, we add WR_HILO to their attributes. | |
1180 | ||
1181 | 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields | |
1182 | (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write | |
1183 | certain fields of the DSP control register. For simplicity, we decide not | |
1184 | to track dependencies of these fields. | |
1185 | However, "bposge32" is a branch instruction that depends on the "pos" | |
1186 | field. In order to make sure that GAS does not reorder DSP instructions | |
1187 | that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) | |
1188 | attribute to those instructions that write the "pos" field. */ | |
1189 | ||
1190 | #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ | |
1191 | #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ | |
1192 | #define MOD_a WR_a|RD_a | |
1193 | #define DSP_VOLA INSN_TRAP | |
1194 | #define D32 INSN_DSP | |
1195 | #define D33 INSN_DSPR2 | |
1196 | #define D64 INSN_DSP64 | |
1197 | ||
1198 | /* MIPS MT ASE support. */ | |
1199 | #define MT32 INSN_MT | |
1200 | ||
6643d27e FB |
1201 | /* The order of overloaded instructions matters. Label arguments and |
1202 | register arguments look the same. Instructions that can have either | |
1203 | for arguments must apear in the correct order in this table for the | |
1204 | assembler to pick the right one. In other words, entries with | |
1205 | immediate operands must apear after the same instruction with | |
1206 | registers. | |
1207 | ||
1208 | Because of the lookup algorithm used, entries with the same opcode | |
1209 | name must be contiguous. | |
5fafdf24 | 1210 | |
6643d27e FB |
1211 | Many instructions are short hand for other instructions (i.e., The |
1212 | jal <register> instruction is short for jalr <register>). */ | |
1213 | ||
1214 | const struct mips_opcode mips_builtin_opcodes[] = | |
1215 | { | |
1216 | /* These instructions appear first so that the disassembler will find | |
1217 | them first. The assemblers uses a hash table based on the | |
1218 | instruction name anyhow. */ | |
1219 | /* name, args, match, mask, pinfo, membership */ | |
4267d3e6 LA |
1220 | {"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6}, |
1221 | {"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6}, | |
1222 | {"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6}, | |
1223 | {"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6}, | |
1224 | {"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6}, | |
b42ee5e1 LA |
1225 | {"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, |
1226 | {"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1227 | {"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1228 | {"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1229 | {"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1230 | {"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1231 | {"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1232 | {"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
1233 | {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1234 | {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1235 | {"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1236 | {"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1237 | {"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1238 | {"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1239 | {"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
1240 | {"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, | |
4368b29a LA |
1241 | {"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, |
1242 | {"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, | |
bf7910c6 LA |
1243 | {"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, |
1244 | {"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, | |
1245 | {"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6}, | |
1246 | {"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6}, | |
b691d9d2 LA |
1247 | {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, |
1248 | {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, | |
29490584 TS |
1249 | {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, |
1250 | {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, | |
1251 | {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ | |
1252 | {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ | |
1253 | {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ | |
1254 | {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ | |
1255 | {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ | |
1256 | {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, | |
1257 | {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, | |
1258 | {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ | |
1259 | {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ | |
1260 | {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ | |
1261 | {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ | |
1262 | {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ | |
1263 | {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ | |
1264 | ||
1265 | {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, | |
1266 | {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, | |
1267 | {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, | |
1268 | {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, | |
1269 | {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
1270 | {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, | |
1271 | {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, | |
1272 | {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, | |
1273 | {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1274 | {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1275 | {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1276 | {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1277 | {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
1278 | {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1279 | {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
1280 | {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
1281 | {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
1282 | {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
1283 | {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
1284 | {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
1285 | {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, | |
1286 | {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
1287 | {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, | |
1288 | {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1289 | {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1290 | {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1291 | {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
1292 | {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, | |
1293 | {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, | |
1294 | {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
1295 | {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, | |
1296 | {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1297 | {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1298 | {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1299 | {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1300 | {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1301 | {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
6643d27e FB |
1302 | /* b is at the top of the table. */ |
1303 | /* bal is at the top of the table. */ | |
29490584 TS |
1304 | /* bc0[tf]l? are at the bottom of the table. */ |
1305 | {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, | |
1306 | {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, | |
1307 | {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, | |
1308 | {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, | |
1309 | {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, | |
1310 | {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, | |
1311 | {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, | |
1312 | {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, | |
1313 | {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, | |
1314 | {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, | |
1315 | {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, | |
1316 | {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, | |
6643d27e | 1317 | /* bc2* are at the bottom of the table. */ |
29490584 TS |
1318 | /* bc3* are at the bottom of the table. */ |
1319 | {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1320 | {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1321 | {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, | |
1322 | {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, | |
1323 | {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, | |
1324 | {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, | |
1325 | {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, | |
1326 | {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, | |
1327 | {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, | |
1328 | {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, | |
1329 | {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, | |
1330 | {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, | |
1331 | {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, | |
1332 | {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, | |
1333 | {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1334 | {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1335 | {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, | |
1336 | {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, | |
1337 | {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, | |
1338 | {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, | |
1339 | {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, | |
1340 | {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, | |
1341 | {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, | |
1342 | {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, | |
1343 | {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, | |
1344 | {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, | |
1345 | {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1346 | {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1347 | {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, | |
1348 | {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, | |
1349 | {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, | |
1350 | {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, | |
1351 | {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, | |
1352 | {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, | |
1353 | {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, | |
1354 | {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, | |
1355 | {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1356 | {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1357 | {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, | |
1358 | {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, | |
1359 | {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, | |
1360 | {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, | |
1361 | {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, | |
1362 | {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, | |
1363 | {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, | |
1364 | {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, | |
1365 | {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1366 | {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1367 | {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, | |
1368 | {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, | |
1369 | {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, | |
1370 | {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, | |
1371 | {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, | |
1372 | {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, | |
1373 | {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, | |
1374 | {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, | |
1375 | {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, | |
1376 | {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, | |
1377 | {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, | |
1378 | {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1379 | {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1380 | {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1381 | {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1382 | {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1383 | {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1384 | {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1385 | {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1386 | {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1387 | {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1388 | {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1389 | {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1390 | {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1391 | {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1392 | {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1393 | {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1394 | {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1395 | {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1396 | {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1397 | {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1398 | {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1399 | {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1400 | {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, | |
1401 | {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1402 | {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1403 | {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1404 | {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1405 | {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1406 | {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1407 | {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1408 | {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1409 | {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1410 | {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1411 | {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1412 | {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1413 | {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1414 | {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1415 | {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1416 | {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1417 | {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1418 | {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1419 | {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1420 | {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1421 | {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1422 | {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1423 | {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1424 | {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1425 | {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1426 | {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1427 | {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1428 | {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1429 | {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1430 | {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1431 | {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1432 | {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1433 | {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1434 | {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1435 | {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1436 | {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1437 | {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1438 | {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1439 | {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1440 | {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1441 | {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1442 | {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1443 | {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1444 | {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1445 | {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1446 | {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1447 | {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1448 | {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1449 | {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1450 | {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1451 | {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1452 | {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1453 | {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1454 | {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1455 | {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1456 | {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1457 | {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1458 | {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1459 | {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1460 | {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1461 | {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1462 | {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1463 | {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1464 | {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1465 | {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, | |
1466 | {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1467 | {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1468 | {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1469 | {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1470 | {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1471 | {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1472 | {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1473 | {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1474 | {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1475 | {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1476 | {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1477 | {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1478 | {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1479 | {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1480 | {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1481 | {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1482 | {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, | |
1483 | {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, | |
1484 | {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, | |
1485 | {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, | |
1486 | {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, | |
1487 | {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1488 | {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, | |
1489 | {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1490 | {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1491 | {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1492 | {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1493 | {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1494 | {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1495 | {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1496 | {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1497 | {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1498 | {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1499 | {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1500 | {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1501 | {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1502 | {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1503 | {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1504 | {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1505 | {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1506 | {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1507 | {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1508 | {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1509 | {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1510 | {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1511 | {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1512 | {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1513 | {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1514 | {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1515 | {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1516 | {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1517 | {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1518 | {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1519 | {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1520 | {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1521 | {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1522 | {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1523 | {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1524 | {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1525 | {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1526 | {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1527 | {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1528 | {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1529 | {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1530 | {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1531 | {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1532 | {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1533 | {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1534 | {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1535 | {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, | |
1536 | {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, | |
1537 | /* CW4010 instructions which are aliases for the cache instruction. */ | |
1538 | {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, | |
1539 | {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, | |
1540 | {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, | |
1541 | {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, | |
1542 | {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, | |
1543 | {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, | |
1544 | {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
1545 | {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
1546 | {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, | |
1547 | {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
1548 | {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, | |
1549 | {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, | |
1550 | {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, | |
6643d27e | 1551 | /* cfc2 is at the bottom of the table. */ |
29490584 TS |
1552 | /* cfc3 is at the bottom of the table. */ |
1553 | {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, | |
1554 | {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, | |
1555 | {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, | |
1556 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, | |
1557 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, | |
1558 | {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, | |
1559 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, | |
1560 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, | |
6643d27e | 1561 | /* ctc2 is at the bottom of the table. */ |
29490584 TS |
1562 | /* ctc3 is at the bottom of the table. */ |
1563 | {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, | |
1564 | {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, | |
1565 | {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, | |
1566 | {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
1567 | {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, | |
1568 | {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, | |
1569 | {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
1570 | {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
1571 | {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
1572 | {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, | |
1573 | {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, | |
1574 | {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, | |
1575 | {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, | |
1576 | {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, | |
1577 | {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, | |
1578 | {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, | |
1579 | {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, | |
1580 | {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, | |
1581 | {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, | |
1582 | {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, | |
1583 | {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, | |
1584 | {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, | |
1585 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, | |
1586 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, | |
1587 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, | |
1588 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, | |
1589 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, | |
1590 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, | |
6643d27e | 1591 | /* dctr and dctw are used on the r5000. */ |
29490584 TS |
1592 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, |
1593 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, | |
1594 | {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, | |
1595 | {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, | |
1596 | {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
1597 | {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
1598 | {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
6643d27e | 1599 | /* For ddiv, see the comments about div. */ |
29490584 TS |
1600 | {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1601 | {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, | |
1602 | {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, | |
6643d27e | 1603 | /* For ddivu, see the comments about div. */ |
29490584 TS |
1604 | {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, |
1605 | {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, | |
1606 | {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, | |
1607 | {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, | |
1608 | {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, | |
1609 | {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, | |
1610 | {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
1611 | {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
1612 | {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, | |
6643d27e FB |
1613 | /* The MIPS assembler treats the div opcode with two operands as |
1614 | though the first operand appeared twice (the first operand is both | |
1615 | a source and a destination). To get the div machine instruction, | |
1616 | you must use an explicit destination of $0. */ | |
29490584 TS |
1617 | {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1618 | {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, | |
1619 | {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, | |
1620 | {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, | |
1621 | {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, | |
1622 | {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, | |
1623 | {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, | |
6643d27e | 1624 | /* For divu, see the comments about div. */ |
29490584 TS |
1625 | {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, |
1626 | {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, | |
1627 | {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, | |
1628 | {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, | |
1629 | {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, | |
1630 | {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, | |
1631 | {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ | |
1632 | {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ | |
1633 | {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, | |
1634 | {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1635 | {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1636 | {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1637 | {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1638 | {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1639 | {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1640 | {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1641 | {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, | |
1642 | {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, | |
1643 | {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, | |
1644 | {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, | |
1645 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, | |
1646 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, | |
1647 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, | |
1648 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, | |
1649 | {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, | |
1650 | {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, | |
1651 | {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, | |
1652 | {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, | |
1653 | {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, | |
1654 | {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, | |
6643d27e FB |
1655 | /* dmfc2 is at the bottom of the table. */ |
1656 | /* dmtc2 is at the bottom of the table. */ | |
29490584 TS |
1657 | /* dmfc3 is at the bottom of the table. */ |
1658 | /* dmtc3 is at the bottom of the table. */ | |
1659 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, | |
1660 | {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, | |
1661 | {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, | |
1662 | {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, | |
1663 | {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, | |
1664 | {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, | |
1665 | {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, | |
1666 | {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, | |
1667 | {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ | |
1668 | {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ | |
1669 | {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, | |
1670 | {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, | |
1671 | {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, | |
1672 | {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, | |
1673 | {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, | |
1674 | {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, | |
1675 | {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, | |
1676 | {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, | |
1677 | {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, | |
1678 | {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, | |
1679 | {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, | |
1680 | {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, | |
1681 | {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, | |
1682 | {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, | |
1683 | {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, | |
1684 | {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, | |
1685 | {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, | |
1686 | {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, | |
1687 | {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, | |
1688 | {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, | |
1689 | {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, | |
1690 | {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, | |
1691 | {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, | |
1692 | {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1693 | {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ | |
1694 | {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ | |
1695 | {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1696 | {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, | |
1697 | {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1698 | {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ | |
1699 | {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ | |
1700 | {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1701 | {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, | |
1702 | {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1703 | {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ | |
1704 | {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ | |
1705 | {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, | |
1706 | {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, | |
1707 | {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, | |
1708 | {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, | |
1709 | {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, | |
1710 | {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, | |
1711 | {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, | |
1712 | {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, | |
1713 | {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, | |
1714 | {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, | |
1715 | {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, | |
1716 | {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, | |
1717 | {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, | |
1718 | {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, | |
1719 | {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, | |
1720 | {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
1721 | {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
1722 | {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, | |
1723 | {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
1724 | {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, | |
1725 | {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, | |
1726 | {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, | |
1727 | /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with | |
1728 | the same hazard barrier effect. */ | |
1729 | {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, | |
1730 | {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ | |
6643d27e FB |
1731 | /* SVR4 PIC code requires special handling for j, so it must be a |
1732 | macro. */ | |
29490584 | 1733 | {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, |
6643d27e FB |
1734 | /* This form of j is used by the disassembler and internally by the |
1735 | assembler, but will never match user input (because the line above | |
1736 | will match first). */ | |
29490584 TS |
1737 | {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, |
1738 | {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, | |
1739 | {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, | |
1740 | /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr | |
1741 | with the same hazard barrier effect. */ | |
1742 | {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, | |
1743 | {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, | |
6643d27e FB |
1744 | /* SVR4 PIC code requires special handling for jal, so it must be a |
1745 | macro. */ | |
29490584 TS |
1746 | {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, |
1747 | {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, | |
1748 | {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, | |
6643d27e FB |
1749 | /* This form of jal is used by the disassembler and internally by the |
1750 | assembler, but will never match user input (because the line above | |
1751 | will match first). */ | |
29490584 TS |
1752 | {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, |
1753 | {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, | |
1754 | {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, | |
1755 | {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1756 | {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, | |
1757 | {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1758 | {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, | |
1759 | {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, | |
1760 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, | |
1761 | {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, | |
1762 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, | |
1763 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, | |
1764 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, | |
1765 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, | |
1766 | {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, | |
1767 | {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ | |
1768 | {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, | |
1769 | {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, | |
1770 | {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, | |
1771 | {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, | |
1772 | {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, | |
1773 | {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, | |
1774 | {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, | |
1775 | {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, | |
1776 | {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, | |
1777 | {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, | |
1778 | {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, | |
1779 | {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1780 | {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, | |
1781 | {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1782 | {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, | |
6643d27e | 1783 | /* li is at the start of the table. */ |
29490584 TS |
1784 | {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, |
1785 | {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, | |
1786 | {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, | |
1787 | {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, | |
1788 | {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, | |
1789 | {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, | |
1790 | {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, | |
1791 | {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, | |
1792 | {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, | |
1793 | {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, | |
1794 | {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1795 | {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, | |
1796 | {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, | |
1797 | {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, | |
1798 | {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, | |
1799 | {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, | |
1800 | {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, | |
1801 | {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, | |
1802 | {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ | |
1803 | {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, | |
1804 | {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, | |
1805 | {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, | |
1806 | {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, | |
1807 | {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, | |
1808 | {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1809 | {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, | |
1810 | {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ | |
1811 | {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ | |
1812 | {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, | |
1813 | {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, | |
1814 | {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ | |
1815 | {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ | |
1816 | {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, | |
1817 | {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, | |
1818 | {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, | |
1819 | {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, | |
1820 | {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, | |
1821 | {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1822 | {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1823 | {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1824 | {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1825 | {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1826 | {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1827 | {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1828 | {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1829 | {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1830 | {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1831 | {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1832 | {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, | |
1833 | {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, | |
1834 | {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, | |
1835 | {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, | |
1836 | {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, | |
1837 | {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, | |
1838 | {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, | |
1839 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, | |
1840 | {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, | |
1841 | {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
1842 | {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, | |
1843 | {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, | |
1844 | {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, | |
1845 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, | |
1846 | {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, | |
1847 | {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
1848 | {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, | |
1849 | {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, | |
1850 | {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1851 | {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1852 | {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1853 | {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1854 | {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1855 | {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, | |
1856 | {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, | |
1857 | {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1858 | {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1859 | {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, | |
1860 | {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, | |
1861 | {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, | |
1862 | {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, | |
1863 | {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, | |
1864 | {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, | |
1865 | {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, | |
1866 | {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, | |
1867 | {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, | |
1868 | {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, | |
1869 | {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, | |
1870 | {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1871 | {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1872 | {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1873 | {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, | |
1874 | {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, | |
1875 | {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, | |
1876 | {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, | |
1877 | {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, | |
1878 | {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, | |
1879 | {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, | |
1880 | {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, | |
1881 | {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, | |
6643d27e FB |
1882 | /* mfc2 is at the bottom of the table. */ |
1883 | /* mfhc2 is at the bottom of the table. */ | |
29490584 TS |
1884 | /* mfc3 is at the bottom of the table. */ |
1885 | {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, | |
1886 | {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, | |
1887 | {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, | |
1888 | {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, | |
1889 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, | |
1890 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, | |
1891 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1892 | {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1893 | {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1894 | {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1895 | {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1896 | {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, | |
1897 | {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, | |
1898 | {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, | |
1899 | {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, | |
1900 | {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, | |
1901 | {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, | |
1902 | {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, | |
1903 | {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, | |
1904 | {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, | |
1905 | {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, | |
1906 | {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, | |
1907 | {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, | |
1908 | {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, | |
1909 | {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, | |
1910 | {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, | |
1911 | {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, | |
1912 | {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, | |
1913 | {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, | |
1914 | {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, | |
1915 | {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, | |
1916 | {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, | |
1917 | {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, | |
1918 | {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, | |
1919 | {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, | |
1920 | {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, | |
1921 | {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, | |
1922 | {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, | |
1923 | {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, | |
1924 | {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, | |
1925 | {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1926 | {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1927 | {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1928 | {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
6643d27e | 1929 | /* move is at the top of the table. */ |
29490584 TS |
1930 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, |
1931 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, | |
1932 | {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, | |
1933 | {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, | |
1934 | {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, | |
1935 | {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, | |
1936 | {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
1937 | {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, | |
1938 | {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, | |
1939 | {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
1940 | {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, | |
1941 | {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, | |
1942 | {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, | |
1943 | {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, | |
1944 | {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, | |
1945 | {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, | |
1946 | {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, | |
1947 | {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, | |
1948 | {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, | |
6643d27e FB |
1949 | /* mtc2 is at the bottom of the table. */ |
1950 | /* mthc2 is at the bottom of the table. */ | |
29490584 TS |
1951 | /* mtc3 is at the bottom of the table. */ |
1952 | {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, | |
1953 | {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, | |
1954 | {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, | |
1955 | {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, | |
1956 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, | |
1957 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, | |
1958 | {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, | |
1959 | {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, | |
1960 | {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, | |
1961 | {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, | |
1962 | {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, | |
1963 | {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, | |
1964 | {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1965 | {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1966 | {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, | |
1967 | {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, | |
1968 | {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, | |
1969 | {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, | |
1970 | {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, | |
1971 | {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1972 | {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1973 | {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1974 | {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, | |
1975 | {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, | |
1976 | {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, | |
1977 | {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, | |
1978 | {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
1979 | {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1980 | {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1981 | {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
1982 | {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
1983 | {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
1984 | {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, | |
1985 | {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, | |
1986 | {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, | |
1987 | {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, | |
1988 | {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
1989 | {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1990 | {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1991 | {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1992 | {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
1993 | {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1994 | {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
1995 | {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
1996 | {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1997 | {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1998 | {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
1999 | {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2000 | {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, | |
2001 | {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, | |
2002 | {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, | |
2003 | {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, | |
2004 | {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, | |
2005 | {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
2006 | {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
2007 | {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
2008 | {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
2009 | {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
2010 | {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2011 | {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2012 | {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2013 | {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2014 | {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
2015 | {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2016 | {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2017 | {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, | |
2018 | {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2019 | {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, | |
2020 | {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, | |
2021 | {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, | |
2022 | {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, | |
2023 | {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, | |
2024 | {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, | |
2025 | {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, | |
2026 | {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, | |
2027 | {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ | |
2028 | {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ | |
2029 | {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, | |
2030 | {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, | |
2031 | {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, | |
2032 | {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, | |
2033 | {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, | |
2034 | {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, | |
2035 | {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, | |
2036 | {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, | |
2037 | {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, | |
6643d27e | 2038 | /* nop is at the start of the table. */ |
29490584 TS |
2039 | {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, |
2040 | {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, | |
2041 | {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2042 | {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2043 | {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2044 | {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2045 | {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2046 | {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ | |
2047 | {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2048 | {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, | |
2049 | {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2050 | {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2051 | {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2052 | {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2053 | {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2054 | {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
2055 | {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, | |
2056 | {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, | |
2057 | {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, | |
2058 | {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2059 | {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2060 | {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2061 | {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2062 | {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2063 | {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2064 | {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2065 | {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2066 | {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2067 | {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2068 | {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
2069 | {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
6643d27e | 2070 | /* pref and prefx are at the start of the table. */ |
29490584 TS |
2071 | {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, |
2072 | {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
2073 | {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, | |
2074 | {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, | |
2075 | {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, | |
2076 | {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, | |
2077 | {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, | |
2078 | {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, | |
2079 | {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, | |
2080 | {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, | |
2081 | {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, | |
2082 | {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, | |
2083 | {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, | |
2084 | {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, | |
2085 | {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, | |
2086 | {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, | |
2087 | {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, | |
2088 | {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, | |
2089 | {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, | |
2090 | {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, | |
2091 | {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, | |
2092 | {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, | |
2093 | {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, | |
2094 | {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, | |
2095 | {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, | |
2096 | {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, | |
2097 | {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, | |
2098 | {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, | |
2099 | {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, | |
2100 | {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, | |
2101 | {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2102 | {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, | |
2103 | {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2104 | {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2105 | {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, | |
2106 | {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2107 | {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, | |
2108 | {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, | |
2109 | {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, | |
2110 | {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, | |
2111 | {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, | |
2112 | {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, | |
2113 | {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, | |
2114 | {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, | |
2115 | {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, | |
2116 | {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, | |
2117 | {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, | |
2118 | {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
2119 | {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
2120 | {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, | |
2121 | {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
2122 | {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, | |
2123 | {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, | |
2124 | {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, | |
2125 | {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, | |
2126 | {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, | |
2127 | {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, | |
2128 | {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, | |
2129 | {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, | |
2130 | {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, | |
2131 | {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2132 | {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, | |
2133 | {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, | |
2134 | {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, | |
2135 | {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, | |
2136 | {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, | |
2137 | {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, | |
2138 | {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, | |
2139 | {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, | |
2140 | {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, | |
2141 | {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, | |
2142 | {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, | |
2143 | {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, | |
2144 | {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, | |
2145 | {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, | |
2146 | {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, | |
2147 | {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, | |
2148 | {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, | |
2149 | {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, | |
2150 | {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, | |
2151 | {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, | |
2152 | {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, | |
2153 | {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, | |
2154 | {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, | |
2155 | {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, | |
2156 | {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, | |
2157 | {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, | |
2158 | {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, | |
2159 | {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, | |
2160 | {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, | |
2161 | {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, | |
2162 | {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, | |
2163 | {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, | |
2164 | {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, | |
2165 | {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, | |
2166 | {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, | |
2167 | {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, | |
2168 | {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, | |
2169 | {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, | |
2170 | {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, | |
2171 | {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, | |
2172 | {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, | |
2173 | {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, | |
2174 | {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, | |
2175 | {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, | |
2176 | {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, | |
2177 | {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, | |
2178 | {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, | |
2179 | {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, | |
2180 | {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, | |
2181 | {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2182 | {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2183 | {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2184 | {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2185 | {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2186 | {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2187 | {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2188 | {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2189 | {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2190 | {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2191 | {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2192 | {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2193 | {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2194 | {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2195 | {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, | |
2196 | {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, | |
2197 | {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, | |
2198 | {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, | |
2199 | {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, | |
2200 | {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ | |
2201 | {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, | |
2202 | {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2203 | {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2204 | {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2205 | {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2206 | {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2207 | {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, | |
2208 | {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
2209 | {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
2210 | {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2211 | {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, | |
2212 | {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, | |
2213 | {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, | |
2214 | {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, | |
2215 | {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
2216 | {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, | |
2217 | {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, | |
2218 | {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ | |
2219 | {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, | |
2220 | {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2221 | {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, | |
2222 | {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ | |
2223 | {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, | |
2224 | {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2225 | {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2226 | {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2227 | {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
6643d27e | 2228 | /* ssnop is at the start of the table. */ |
29490584 TS |
2229 | {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, |
2230 | {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2231 | {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, | |
2232 | {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, | |
2233 | {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, | |
2234 | {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2235 | {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2236 | {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2237 | {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2238 | {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, | |
2239 | {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2240 | {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
2241 | {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2242 | {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
2243 | {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2244 | {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2245 | {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, | |
2246 | {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, | |
2247 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, | |
2248 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, | |
2249 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, | |
2250 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, | |
2251 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, | |
2252 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, | |
2253 | {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, | |
2254 | {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, | |
2255 | {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, | |
2256 | {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ | |
2257 | {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, | |
2258 | {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, | |
2259 | {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, | |
2260 | {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, | |
2261 | {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, | |
2262 | {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, | |
2263 | {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, | |
2264 | {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ | |
2265 | {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ | |
2266 | {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, | |
2267 | {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, | |
2268 | {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ | |
2269 | {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ | |
2270 | {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, | |
2271 | {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, | |
2272 | {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, | |
2273 | {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, | |
2274 | {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, | |
2275 | {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, | |
2276 | {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, | |
2277 | {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2278 | {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2279 | {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2280 | {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ | |
2281 | {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, | |
2282 | {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2283 | {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2284 | {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2285 | {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ | |
2286 | {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, | |
2287 | {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2288 | {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2289 | {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2290 | {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ | |
2291 | {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, | |
2292 | {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, | |
2293 | {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, | |
2294 | {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, | |
2295 | {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, | |
2296 | {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2297 | {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2298 | {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2299 | {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ | |
2300 | {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, | |
2301 | {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2302 | {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2303 | {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2304 | {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ | |
2305 | {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, | |
2306 | {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, | |
2307 | {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, | |
2308 | {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, | |
2309 | {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ | |
2310 | {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, | |
2311 | {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, | |
2312 | {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, | |
2313 | {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, | |
2314 | {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, | |
2315 | {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, | |
2316 | {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
2317 | {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, | |
2318 | {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, | |
2319 | {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, | |
2320 | {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, | |
2321 | {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, | |
2322 | {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, | |
2323 | {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, | |
2324 | {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, | |
2325 | {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, | |
2326 | {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, | |
2327 | {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, | |
2328 | {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, | |
2329 | {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, | |
2330 | {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, | |
2331 | {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, | |
2332 | {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, | |
2333 | {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, | |
2334 | {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, | |
2335 | {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, | |
2336 | {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, | |
2337 | {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, | |
2338 | {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, | |
2339 | {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, | |
2340 | {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, | |
2341 | {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, | |
2342 | {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, | |
2343 | {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, | |
2344 | {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, | |
2345 | {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, | |
2346 | {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, | |
2347 | {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2348 | {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2349 | {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, | |
2350 | {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, | |
2351 | {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, | |
2352 | {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, | |
2353 | {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, | |
2354 | ||
2355 | /* User Defined Instruction. */ | |
2356 | {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2357 | {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2358 | {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2359 | {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2360 | {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2361 | {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2362 | {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2363 | {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2364 | {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2365 | {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2366 | {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2367 | {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2368 | {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2369 | {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2370 | {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2371 | {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2372 | {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2373 | {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2374 | {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2375 | {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2376 | {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2377 | {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2378 | {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2379 | {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2380 | {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2381 | {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2382 | {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2383 | {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2384 | {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2385 | {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2386 | {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2387 | {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2388 | {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2389 | {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2390 | {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2391 | {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2392 | {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2393 | {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2394 | {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2395 | {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2396 | {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2397 | {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2398 | {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2399 | {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2400 | {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2401 | {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2402 | {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2403 | {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2404 | {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2405 | {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2406 | {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2407 | {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2408 | {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2409 | {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2410 | {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2411 | {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2412 | {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2413 | {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2414 | {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2415 | {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2416 | {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2417 | {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2418 | {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
2419 | {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, | |
6643d27e FB |
2420 | |
2421 | /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format | |
2422 | instructions so they are here for the latters to take precedence. */ | |
29490584 TS |
2423 | {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, |
2424 | {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, | |
2425 | {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
2426 | {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, | |
2427 | {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, | |
2428 | {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, | |
2429 | {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
2430 | {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, | |
2431 | {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, | |
2432 | {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, | |
2433 | {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, | |
2434 | {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, | |
2435 | {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, | |
2436 | {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, | |
2437 | {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, | |
2438 | {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, | |
2439 | {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, | |
2440 | {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, | |
2441 | {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, | |
2442 | {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, | |
2443 | {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, | |
2444 | {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, | |
2445 | {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, | |
2446 | {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, | |
2447 | ||
2448 | /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X | |
2449 | instructions, so they are here for the latters to take precedence. */ | |
2450 | {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, | |
2451 | {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
2452 | {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, | |
2453 | {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
2454 | {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, | |
2455 | {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, | |
2456 | {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, | |
2457 | {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, | |
2458 | {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, | |
2459 | {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, | |
2460 | {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, | |
2461 | {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, | |
6643d27e FB |
2462 | |
2463 | /* No hazard protection on coprocessor instructions--they shouldn't | |
2464 | change the state of the processor and if they do it's up to the | |
2465 | user to put in nops as necessary. These are at the end so that the | |
2466 | disassembler recognizes more specific versions first. */ | |
29490584 TS |
2467 | {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, |
2468 | {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, | |
2469 | {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, | |
2470 | {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, | |
2471 | {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, | |
2472 | {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, | |
2473 | {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, | |
2474 | {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, | |
6643d27e FB |
2475 | /* Conflicts with the 4650's "mul" instruction. Nobody's using the |
2476 | 4010 any more, so move this insn out of the way. If the object | |
2477 | format gave us more info, we could do this right. */ | |
29490584 TS |
2478 | {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, |
2479 | /* MIPS DSP ASE */ | |
2480 | {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2481 | {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2482 | {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2483 | {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2484 | {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2485 | {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2486 | {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2487 | {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2488 | {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2489 | {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2490 | {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2491 | {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2492 | {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2493 | {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2494 | {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2495 | {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2496 | {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2497 | {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2498 | {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, | |
2499 | {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, | |
2500 | {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2501 | {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2502 | {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2503 | {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2504 | {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2505 | {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2506 | {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2507 | {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2508 | {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2509 | {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2510 | {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2511 | {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2512 | {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2513 | {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2514 | {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2515 | {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2516 | {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2517 | {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2518 | {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2519 | {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, | |
2520 | {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, | |
2521 | {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, | |
2522 | {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, | |
2523 | {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2524 | {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2525 | {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2526 | {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2527 | {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2528 | {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2529 | {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2530 | {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2531 | {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2532 | {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2533 | {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2534 | {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2535 | {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2536 | {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2537 | {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, | |
2538 | {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, | |
2539 | {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, | |
2540 | {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2541 | {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2542 | {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2543 | {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2544 | {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, | |
2545 | {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2546 | {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2547 | {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2548 | {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2549 | {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2550 | {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2551 | {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2552 | {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2553 | {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2554 | {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2555 | {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2556 | {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2557 | {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2558 | {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2559 | {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2560 | {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2561 | {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, | |
2562 | {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, | |
2563 | {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, | |
2564 | {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, | |
2565 | {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, | |
2566 | {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, | |
2567 | {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, | |
2568 | {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, | |
2569 | {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, | |
2570 | {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, | |
2571 | {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, | |
2572 | {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, | |
2573 | {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, | |
2574 | {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, | |
2575 | {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, | |
2576 | {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, | |
2577 | {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, | |
2578 | {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, | |
2579 | {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, | |
2580 | {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2581 | {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2582 | {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2583 | {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2584 | {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2585 | {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2586 | {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2587 | {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2588 | {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2589 | {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2590 | {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2591 | {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2592 | {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2593 | {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2594 | {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2595 | {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, | |
2596 | {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, | |
2597 | {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, | |
2598 | {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, | |
2599 | {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, | |
2600 | {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, | |
2601 | {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, | |
2602 | {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, | |
2603 | {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, | |
2604 | {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, | |
2605 | {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, | |
2606 | {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2607 | {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, | |
2608 | {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, | |
2609 | {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2610 | {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2611 | {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2612 | {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2613 | {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2614 | {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2615 | {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2616 | {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2617 | {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2618 | {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2619 | {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2620 | {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2621 | {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2622 | {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2623 | {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2624 | {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2625 | {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2626 | {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2627 | {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2628 | {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2629 | {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2630 | {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2631 | {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2632 | {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2633 | {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2634 | {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2635 | {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2636 | {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2637 | {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2638 | {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2639 | {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2640 | {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2641 | {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2642 | {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2643 | {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2644 | {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2645 | {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2646 | {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2647 | {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2648 | {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2649 | {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, | |
2650 | {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, | |
2651 | {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, | |
2652 | {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, | |
2653 | {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, | |
2654 | {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, | |
2655 | {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, | |
2656 | {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, | |
2657 | {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, | |
2658 | {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2659 | {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2660 | {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2661 | {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, | |
2662 | {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, | |
2663 | {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, | |
2664 | {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, | |
2665 | {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, | |
2666 | {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, | |
2667 | {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, | |
2668 | {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, | |
2669 | {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, | |
2670 | {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, | |
2671 | {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, | |
2672 | {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, | |
2673 | {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, | |
2674 | {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2675 | {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2676 | {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2677 | {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2678 | {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2679 | {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2680 | {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2681 | {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2682 | {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2683 | {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, | |
2684 | {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, | |
2685 | {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, | |
2686 | {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, | |
2687 | {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, | |
2688 | {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, | |
2689 | {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, | |
2690 | {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2691 | {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2692 | {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2693 | {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2694 | {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2695 | {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2696 | {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2697 | {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, | |
2698 | {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, | |
2699 | {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2700 | {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2701 | {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2702 | {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2703 | {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2704 | {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2705 | {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2706 | {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2707 | {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2708 | {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2709 | {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2710 | {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, | |
2711 | {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, | |
2712 | {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, | |
2713 | {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, | |
2714 | /* MIPS DSP ASE Rev2 */ | |
2715 | {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, | |
2716 | {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2717 | {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2718 | {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2719 | {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2720 | {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, | |
2721 | {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, | |
2722 | {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, | |
2723 | {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2724 | {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2725 | {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2726 | {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2727 | {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2728 | {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, | |
2729 | {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, | |
2730 | {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, | |
2731 | {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, | |
2732 | {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, | |
2733 | {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2734 | {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2735 | {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, | |
2736 | {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, | |
2737 | {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, | |
2738 | {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, | |
2739 | {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, | |
2740 | {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2741 | {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2742 | {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, | |
2743 | {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2744 | {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2745 | {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2746 | {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2747 | {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2748 | {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2749 | {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2750 | {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2751 | {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2752 | {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2753 | {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2754 | {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2755 | {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, | |
2756 | {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2757 | {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2758 | {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2759 | {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2760 | {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2761 | {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, | |
2762 | /* Move bc0* after mftr and mttr to avoid opcode collision. */ | |
2763 | {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, | |
2764 | {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
2765 | {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, | |
2766 | {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, | |
15656e09 AJ |
2767 | /* ST Microelectronics Loongson-2E and -2F. */ |
2768 | {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2769 | {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2770 | {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2771 | {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2772 | {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2773 | {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2774 | {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2775 | {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2776 | {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2777 | {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2778 | {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2779 | {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2780 | {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2781 | {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2782 | {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2783 | {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2784 | {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2785 | {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2786 | {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2787 | {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2788 | {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2789 | {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
2790 | {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, | |
2791 | {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, | |
6643d27e FB |
2792 | }; |
2793 | ||
2794 | #define MIPS_NUM_OPCODES \ | |
2795 | ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) | |
2796 | const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; | |
2797 | ||
2798 | /* const removed from the following to allow for dynamic extensions to the | |
2799 | * built-in instruction set. */ | |
2800 | struct mips_opcode *mips_opcodes = | |
2801 | (struct mips_opcode *) mips_builtin_opcodes; | |
2802 | int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; | |
2803 | #undef MIPS_NUM_OPCODES | |
2804 | ||
6643d27e FB |
2805 | /* Mips instructions are at maximum this many bytes long. */ |
2806 | #define INSNLEN 4 | |
2807 | ||
6643d27e FB |
2808 | \f |
2809 | /* FIXME: These should be shared with gdb somehow. */ | |
2810 | ||
52da07d1 TS |
2811 | struct mips_cp0sel_name |
2812 | { | |
2813 | unsigned int cp0reg; | |
2814 | unsigned int sel; | |
2815 | const char * const name; | |
6643d27e FB |
2816 | }; |
2817 | ||
52da07d1 TS |
2818 | /* The mips16 registers. */ |
2819 | static const unsigned int mips16_to_32_reg_map[] = | |
2820 | { | |
2821 | 16, 17, 2, 3, 4, 5, 6, 7 | |
6643d27e FB |
2822 | }; |
2823 | ||
52da07d1 TS |
2824 | #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] |
2825 | ||
2826 | ||
2827 | static const char * const mips_gpr_names_numeric[32] = | |
2828 | { | |
6643d27e FB |
2829 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
2830 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
2831 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
2832 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
2833 | }; | |
2834 | ||
52da07d1 TS |
2835 | static const char * const mips_gpr_names_oldabi[32] = |
2836 | { | |
6643d27e FB |
2837 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
2838 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
2839 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
2840 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
2841 | }; | |
2842 | ||
52da07d1 TS |
2843 | static const char * const mips_gpr_names_newabi[32] = |
2844 | { | |
6643d27e FB |
2845 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
2846 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
2847 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
2848 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
2849 | }; | |
2850 | ||
52da07d1 TS |
2851 | static const char * const mips_fpr_names_numeric[32] = |
2852 | { | |
6643d27e FB |
2853 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
2854 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
2855 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
2856 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" | |
2857 | }; | |
2858 | ||
52da07d1 TS |
2859 | static const char * const mips_fpr_names_32[32] = |
2860 | { | |
6643d27e FB |
2861 | "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", |
2862 | "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", | |
2863 | "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", | |
2864 | "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" | |
2865 | }; | |
2866 | ||
52da07d1 TS |
2867 | static const char * const mips_fpr_names_n32[32] = |
2868 | { | |
6643d27e FB |
2869 | "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", |
2870 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
2871 | "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", | |
2872 | "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" | |
2873 | }; | |
2874 | ||
52da07d1 TS |
2875 | static const char * const mips_fpr_names_64[32] = |
2876 | { | |
6643d27e FB |
2877 | "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", |
2878 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
2879 | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", | |
2880 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" | |
2881 | }; | |
2882 | ||
52da07d1 TS |
2883 | static const char * const mips_cp0_names_numeric[32] = |
2884 | { | |
6643d27e FB |
2885 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
2886 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
2887 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
2888 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
2889 | }; | |
2890 | ||
52da07d1 TS |
2891 | static const char * const mips_cp0_names_mips3264[32] = |
2892 | { | |
6643d27e FB |
2893 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
2894 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
2895 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
2896 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
2897 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
2898 | "c0_xcontext", "$21", "$22", "c0_debug", | |
2899 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
2900 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
2901 | }; | |
2902 | ||
52da07d1 TS |
2903 | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = |
2904 | { | |
2905 | { 4, 1, "c0_contextconfig" }, | |
2906 | { 0, 1, "c0_mvpcontrol" }, | |
2907 | { 0, 2, "c0_mvpconf0" }, | |
2908 | { 0, 3, "c0_mvpconf1" }, | |
2909 | { 1, 1, "c0_vpecontrol" }, | |
2910 | { 1, 2, "c0_vpeconf0" }, | |
2911 | { 1, 3, "c0_vpeconf1" }, | |
2912 | { 1, 4, "c0_yqmask" }, | |
2913 | { 1, 5, "c0_vpeschedule" }, | |
2914 | { 1, 6, "c0_vpeschefback" }, | |
2915 | { 2, 1, "c0_tcstatus" }, | |
2916 | { 2, 2, "c0_tcbind" }, | |
2917 | { 2, 3, "c0_tcrestart" }, | |
2918 | { 2, 4, "c0_tchalt" }, | |
2919 | { 2, 5, "c0_tccontext" }, | |
2920 | { 2, 6, "c0_tcschedule" }, | |
2921 | { 2, 7, "c0_tcschefback" }, | |
2922 | { 5, 1, "c0_pagegrain" }, | |
2923 | { 6, 1, "c0_srsconf0" }, | |
2924 | { 6, 2, "c0_srsconf1" }, | |
2925 | { 6, 3, "c0_srsconf2" }, | |
2926 | { 6, 4, "c0_srsconf3" }, | |
2927 | { 6, 5, "c0_srsconf4" }, | |
2928 | { 12, 1, "c0_intctl" }, | |
2929 | { 12, 2, "c0_srsctl" }, | |
2930 | { 12, 3, "c0_srsmap" }, | |
2931 | { 15, 1, "c0_ebase" }, | |
6643d27e FB |
2932 | { 16, 1, "c0_config1" }, |
2933 | { 16, 2, "c0_config2" }, | |
2934 | { 16, 3, "c0_config3" }, | |
2935 | { 18, 1, "c0_watchlo,1" }, | |
2936 | { 18, 2, "c0_watchlo,2" }, | |
2937 | { 18, 3, "c0_watchlo,3" }, | |
2938 | { 18, 4, "c0_watchlo,4" }, | |
2939 | { 18, 5, "c0_watchlo,5" }, | |
2940 | { 18, 6, "c0_watchlo,6" }, | |
2941 | { 18, 7, "c0_watchlo,7" }, | |
2942 | { 19, 1, "c0_watchhi,1" }, | |
2943 | { 19, 2, "c0_watchhi,2" }, | |
2944 | { 19, 3, "c0_watchhi,3" }, | |
2945 | { 19, 4, "c0_watchhi,4" }, | |
2946 | { 19, 5, "c0_watchhi,5" }, | |
2947 | { 19, 6, "c0_watchhi,6" }, | |
2948 | { 19, 7, "c0_watchhi,7" }, | |
52da07d1 TS |
2949 | { 23, 1, "c0_tracecontrol" }, |
2950 | { 23, 2, "c0_tracecontrol2" }, | |
2951 | { 23, 3, "c0_usertracedata" }, | |
2952 | { 23, 4, "c0_tracebpc" }, | |
6643d27e FB |
2953 | { 25, 1, "c0_perfcnt,1" }, |
2954 | { 25, 2, "c0_perfcnt,2" }, | |
2955 | { 25, 3, "c0_perfcnt,3" }, | |
2956 | { 25, 4, "c0_perfcnt,4" }, | |
2957 | { 25, 5, "c0_perfcnt,5" }, | |
2958 | { 25, 6, "c0_perfcnt,6" }, | |
2959 | { 25, 7, "c0_perfcnt,7" }, | |
2960 | { 27, 1, "c0_cacheerr,1" }, | |
2961 | { 27, 2, "c0_cacheerr,2" }, | |
2962 | { 27, 3, "c0_cacheerr,3" }, | |
2963 | { 28, 1, "c0_datalo" }, | |
52da07d1 TS |
2964 | { 28, 2, "c0_taglo1" }, |
2965 | { 28, 3, "c0_datalo1" }, | |
2966 | { 28, 4, "c0_taglo2" }, | |
2967 | { 28, 5, "c0_datalo2" }, | |
2968 | { 28, 6, "c0_taglo3" }, | |
2969 | { 28, 7, "c0_datalo3" }, | |
2970 | { 29, 1, "c0_datahi" }, | |
2971 | { 29, 2, "c0_taghi1" }, | |
2972 | { 29, 3, "c0_datahi1" }, | |
2973 | { 29, 4, "c0_taghi2" }, | |
2974 | { 29, 5, "c0_datahi2" }, | |
2975 | { 29, 6, "c0_taghi3" }, | |
2976 | { 29, 7, "c0_datahi3" }, | |
6643d27e FB |
2977 | }; |
2978 | ||
52da07d1 TS |
2979 | static const char * const mips_cp0_names_mips3264r2[32] = |
2980 | { | |
6643d27e FB |
2981 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
2982 | "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", | |
2983 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
2984 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
2985 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
2986 | "c0_xcontext", "$21", "$22", "c0_debug", | |
2987 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
2988 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
2989 | }; | |
2990 | ||
52da07d1 TS |
2991 | static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = |
2992 | { | |
6643d27e FB |
2993 | { 4, 1, "c0_contextconfig" }, |
2994 | { 5, 1, "c0_pagegrain" }, | |
2995 | { 12, 1, "c0_intctl" }, | |
2996 | { 12, 2, "c0_srsctl" }, | |
2997 | { 12, 3, "c0_srsmap" }, | |
2998 | { 15, 1, "c0_ebase" }, | |
2999 | { 16, 1, "c0_config1" }, | |
3000 | { 16, 2, "c0_config2" }, | |
3001 | { 16, 3, "c0_config3" }, | |
3002 | { 18, 1, "c0_watchlo,1" }, | |
3003 | { 18, 2, "c0_watchlo,2" }, | |
3004 | { 18, 3, "c0_watchlo,3" }, | |
3005 | { 18, 4, "c0_watchlo,4" }, | |
3006 | { 18, 5, "c0_watchlo,5" }, | |
3007 | { 18, 6, "c0_watchlo,6" }, | |
3008 | { 18, 7, "c0_watchlo,7" }, | |
3009 | { 19, 1, "c0_watchhi,1" }, | |
3010 | { 19, 2, "c0_watchhi,2" }, | |
3011 | { 19, 3, "c0_watchhi,3" }, | |
3012 | { 19, 4, "c0_watchhi,4" }, | |
3013 | { 19, 5, "c0_watchhi,5" }, | |
3014 | { 19, 6, "c0_watchhi,6" }, | |
3015 | { 19, 7, "c0_watchhi,7" }, | |
3016 | { 23, 1, "c0_tracecontrol" }, | |
3017 | { 23, 2, "c0_tracecontrol2" }, | |
3018 | { 23, 3, "c0_usertracedata" }, | |
3019 | { 23, 4, "c0_tracebpc" }, | |
3020 | { 25, 1, "c0_perfcnt,1" }, | |
3021 | { 25, 2, "c0_perfcnt,2" }, | |
3022 | { 25, 3, "c0_perfcnt,3" }, | |
3023 | { 25, 4, "c0_perfcnt,4" }, | |
3024 | { 25, 5, "c0_perfcnt,5" }, | |
3025 | { 25, 6, "c0_perfcnt,6" }, | |
3026 | { 25, 7, "c0_perfcnt,7" }, | |
3027 | { 27, 1, "c0_cacheerr,1" }, | |
3028 | { 27, 2, "c0_cacheerr,2" }, | |
3029 | { 27, 3, "c0_cacheerr,3" }, | |
3030 | { 28, 1, "c0_datalo" }, | |
3031 | { 28, 2, "c0_taglo1" }, | |
3032 | { 28, 3, "c0_datalo1" }, | |
3033 | { 28, 4, "c0_taglo2" }, | |
3034 | { 28, 5, "c0_datalo2" }, | |
3035 | { 28, 6, "c0_taglo3" }, | |
3036 | { 28, 7, "c0_datalo3" }, | |
3037 | { 29, 1, "c0_datahi" }, | |
3038 | { 29, 2, "c0_taghi1" }, | |
3039 | { 29, 3, "c0_datahi1" }, | |
3040 | { 29, 4, "c0_taghi2" }, | |
3041 | { 29, 5, "c0_datahi2" }, | |
3042 | { 29, 6, "c0_taghi3" }, | |
3043 | { 29, 7, "c0_datahi3" }, | |
3044 | }; | |
3045 | ||
3046 | /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ | |
52da07d1 TS |
3047 | static const char * const mips_cp0_names_sb1[32] = |
3048 | { | |
6643d27e FB |
3049 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", |
3050 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
3051 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
3052 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
3053 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
3054 | "c0_xcontext", "$21", "$22", "c0_debug", | |
3055 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", | |
3056 | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", | |
3057 | }; | |
3058 | ||
52da07d1 TS |
3059 | static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = |
3060 | { | |
6643d27e FB |
3061 | { 16, 1, "c0_config1" }, |
3062 | { 18, 1, "c0_watchlo,1" }, | |
3063 | { 19, 1, "c0_watchhi,1" }, | |
3064 | { 22, 0, "c0_perftrace" }, | |
3065 | { 23, 3, "c0_edebug" }, | |
3066 | { 25, 1, "c0_perfcnt,1" }, | |
3067 | { 25, 2, "c0_perfcnt,2" }, | |
3068 | { 25, 3, "c0_perfcnt,3" }, | |
3069 | { 25, 4, "c0_perfcnt,4" }, | |
3070 | { 25, 5, "c0_perfcnt,5" }, | |
3071 | { 25, 6, "c0_perfcnt,6" }, | |
3072 | { 25, 7, "c0_perfcnt,7" }, | |
3073 | { 26, 1, "c0_buserr_pa" }, | |
3074 | { 27, 1, "c0_cacheerr_d" }, | |
3075 | { 27, 3, "c0_cacheerr_d_pa" }, | |
3076 | { 28, 1, "c0_datalo_i" }, | |
3077 | { 28, 2, "c0_taglo_d" }, | |
3078 | { 28, 3, "c0_datalo_d" }, | |
3079 | { 29, 1, "c0_datahi_i" }, | |
3080 | { 29, 2, "c0_taghi_d" }, | |
3081 | { 29, 3, "c0_datahi_d" }, | |
3082 | }; | |
3083 | ||
52da07d1 TS |
3084 | static const char * const mips_hwr_names_numeric[32] = |
3085 | { | |
6643d27e FB |
3086 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", |
3087 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
3088 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
3089 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
3090 | }; | |
3091 | ||
52da07d1 TS |
3092 | static const char * const mips_hwr_names_mips3264r2[32] = |
3093 | { | |
6643d27e FB |
3094 | "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", |
3095 | "$4", "$5", "$6", "$7", | |
3096 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
3097 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
3098 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
3099 | }; | |
3100 | ||
52da07d1 TS |
3101 | struct mips_abi_choice |
3102 | { | |
6643d27e FB |
3103 | const char *name; |
3104 | const char * const *gpr_names; | |
3105 | const char * const *fpr_names; | |
3106 | }; | |
3107 | ||
72139e83 | 3108 | static struct mips_abi_choice mips_abi_choices[] = |
52da07d1 | 3109 | { |
6643d27e FB |
3110 | { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, |
3111 | { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, | |
3112 | { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, | |
3113 | { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, | |
3114 | }; | |
3115 | ||
52da07d1 TS |
3116 | struct mips_arch_choice |
3117 | { | |
6643d27e FB |
3118 | const char *name; |
3119 | int bfd_mach_valid; | |
3120 | unsigned long bfd_mach; | |
3121 | int processor; | |
3122 | int isa; | |
3123 | const char * const *cp0_names; | |
3124 | const struct mips_cp0sel_name *cp0sel_names; | |
3125 | unsigned int cp0sel_names_len; | |
3126 | const char * const *hwr_names; | |
3127 | }; | |
3128 | ||
3129 | #define bfd_mach_mips3000 3000 | |
3130 | #define bfd_mach_mips3900 3900 | |
3131 | #define bfd_mach_mips4000 4000 | |
3132 | #define bfd_mach_mips4010 4010 | |
3133 | #define bfd_mach_mips4100 4100 | |
3134 | #define bfd_mach_mips4111 4111 | |
3135 | #define bfd_mach_mips4120 4120 | |
3136 | #define bfd_mach_mips4300 4300 | |
3137 | #define bfd_mach_mips4400 4400 | |
3138 | #define bfd_mach_mips4600 4600 | |
3139 | #define bfd_mach_mips4650 4650 | |
3140 | #define bfd_mach_mips5000 5000 | |
3141 | #define bfd_mach_mips5400 5400 | |
3142 | #define bfd_mach_mips5500 5500 | |
3143 | #define bfd_mach_mips6000 6000 | |
3144 | #define bfd_mach_mips7000 7000 | |
3145 | #define bfd_mach_mips8000 8000 | |
52da07d1 | 3146 | #define bfd_mach_mips9000 9000 |
6643d27e FB |
3147 | #define bfd_mach_mips10000 10000 |
3148 | #define bfd_mach_mips12000 12000 | |
3149 | #define bfd_mach_mips16 16 | |
3150 | #define bfd_mach_mips5 5 | |
3151 | #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ | |
3152 | #define bfd_mach_mipsisa32 32 | |
3153 | #define bfd_mach_mipsisa32r2 33 | |
3154 | #define bfd_mach_mipsisa64 64 | |
3155 | #define bfd_mach_mipsisa64r2 65 | |
3156 | ||
72139e83 | 3157 | static const struct mips_arch_choice mips_arch_choices[] = |
52da07d1 | 3158 | { |
6643d27e FB |
3159 | { "numeric", 0, 0, 0, 0, |
3160 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3161 | ||
3162 | { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, | |
3163 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3164 | { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, | |
3165 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3166 | { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, | |
3167 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3168 | { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, | |
3169 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3170 | { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, | |
3171 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3172 | { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, | |
3173 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3174 | { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, | |
3175 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3176 | { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, | |
3177 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3178 | { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, | |
3179 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3180 | { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, | |
3181 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3182 | { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, | |
3183 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3184 | { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, | |
3185 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3186 | { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, | |
3187 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3188 | { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, | |
3189 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3190 | { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, | |
3191 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3192 | { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, | |
3193 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3194 | { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, | |
3195 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3196 | { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, | |
3197 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3198 | { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, | |
3199 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3200 | { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, | |
3201 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3202 | { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, | |
3203 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3204 | ||
3205 | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. | |
3206 | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See | |
3207 | _MIPS32 Architecture For Programmers Volume I: Introduction to the | |
3208 | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), | |
3209 | page 1. */ | |
3210 | { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, | |
52da07d1 | 3211 | ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, |
6643d27e FB |
3212 | mips_cp0_names_mips3264, |
3213 | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), | |
3214 | mips_hwr_names_numeric }, | |
3215 | ||
3216 | { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, | |
52da07d1 TS |
3217 | (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 |
3218 | | INSN_MIPS3D | INSN_MT), | |
6643d27e FB |
3219 | mips_cp0_names_mips3264r2, |
3220 | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), | |
3221 | mips_hwr_names_mips3264r2 }, | |
3222 | ||
3223 | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ | |
3224 | { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, | |
3225 | ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, | |
3226 | mips_cp0_names_mips3264, | |
3227 | mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), | |
3228 | mips_hwr_names_numeric }, | |
3229 | ||
3230 | { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, | |
52da07d1 TS |
3231 | (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 |
3232 | | INSN_DSP64 | INSN_MT | INSN_MDMX), | |
6643d27e FB |
3233 | mips_cp0_names_mips3264r2, |
3234 | mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), | |
3235 | mips_hwr_names_mips3264r2 }, | |
3236 | ||
3237 | { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, | |
3238 | ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, | |
3239 | mips_cp0_names_sb1, | |
3240 | mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), | |
3241 | mips_hwr_names_numeric }, | |
3242 | ||
3243 | /* This entry, mips16, is here only for ISA/processor selection; do | |
3244 | not print its name. */ | |
3245 | { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, | |
3246 | mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, | |
3247 | }; | |
3248 | ||
3249 | /* ISA and processor type to disassemble for, and register names to use. | |
3250 | set_default_mips_dis_options and parse_mips_dis_options fill in these | |
3251 | values. */ | |
3252 | static int mips_processor; | |
3253 | static int mips_isa; | |
3254 | static const char * const *mips_gpr_names; | |
3255 | static const char * const *mips_fpr_names; | |
3256 | static const char * const *mips_cp0_names; | |
3257 | static const struct mips_cp0sel_name *mips_cp0sel_names; | |
3258 | static int mips_cp0sel_names_len; | |
3259 | static const char * const *mips_hwr_names; | |
3260 | ||
52da07d1 TS |
3261 | /* Other options */ |
3262 | static int no_aliases; /* If set disassemble as most general inst. */ | |
6643d27e FB |
3263 | \f |
3264 | static const struct mips_abi_choice * | |
52da07d1 | 3265 | choose_abi_by_name (const char *name, unsigned int namelen) |
6643d27e FB |
3266 | { |
3267 | const struct mips_abi_choice *c; | |
3268 | unsigned int i; | |
3269 | ||
3270 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) | |
52da07d1 TS |
3271 | if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 |
3272 | && strlen (mips_abi_choices[i].name) == namelen) | |
3273 | c = &mips_abi_choices[i]; | |
3274 | ||
6643d27e FB |
3275 | return c; |
3276 | } | |
3277 | ||
3278 | static const struct mips_arch_choice * | |
52da07d1 | 3279 | choose_arch_by_name (const char *name, unsigned int namelen) |
6643d27e FB |
3280 | { |
3281 | const struct mips_arch_choice *c = NULL; | |
3282 | unsigned int i; | |
3283 | ||
3284 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
52da07d1 TS |
3285 | if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 |
3286 | && strlen (mips_arch_choices[i].name) == namelen) | |
3287 | c = &mips_arch_choices[i]; | |
3288 | ||
6643d27e FB |
3289 | return c; |
3290 | } | |
3291 | ||
3292 | static const struct mips_arch_choice * | |
52da07d1 | 3293 | choose_arch_by_number (unsigned long mach) |
6643d27e FB |
3294 | { |
3295 | static unsigned long hint_bfd_mach; | |
3296 | static const struct mips_arch_choice *hint_arch_choice; | |
3297 | const struct mips_arch_choice *c; | |
3298 | unsigned int i; | |
3299 | ||
3300 | /* We optimize this because even if the user specifies no | |
3301 | flags, this will be done for every instruction! */ | |
3302 | if (hint_bfd_mach == mach | |
3303 | && hint_arch_choice != NULL | |
3304 | && hint_arch_choice->bfd_mach == hint_bfd_mach) | |
3305 | return hint_arch_choice; | |
3306 | ||
3307 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
3308 | { | |
3309 | if (mips_arch_choices[i].bfd_mach_valid | |
3310 | && mips_arch_choices[i].bfd_mach == mach) | |
3311 | { | |
3312 | c = &mips_arch_choices[i]; | |
3313 | hint_bfd_mach = mach; | |
3314 | hint_arch_choice = c; | |
3315 | } | |
3316 | } | |
3317 | return c; | |
3318 | } | |
3319 | ||
f9480ffc | 3320 | static void |
52da07d1 | 3321 | set_default_mips_dis_options (struct disassemble_info *info) |
6643d27e FB |
3322 | { |
3323 | const struct mips_arch_choice *chosen_arch; | |
3324 | ||
3325 | /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, | |
3326 | and numeric FPR, CP0 register, and HWR names. */ | |
3327 | mips_isa = ISA_MIPS3; | |
3328 | mips_processor = CPU_R3000; | |
3329 | mips_gpr_names = mips_gpr_names_oldabi; | |
3330 | mips_fpr_names = mips_fpr_names_numeric; | |
3331 | mips_cp0_names = mips_cp0_names_numeric; | |
3332 | mips_cp0sel_names = NULL; | |
3333 | mips_cp0sel_names_len = 0; | |
3334 | mips_hwr_names = mips_hwr_names_numeric; | |
52da07d1 | 3335 | no_aliases = 0; |
6643d27e FB |
3336 | |
3337 | /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ | |
3338 | #if 0 | |
3339 | if (info->flavour == bfd_target_elf_flavour && info->section != NULL) | |
3340 | { | |
3341 | Elf_Internal_Ehdr *header; | |
3342 | ||
3343 | header = elf_elfheader (info->section->owner); | |
3344 | if (is_newabi (header)) | |
3345 | mips_gpr_names = mips_gpr_names_newabi; | |
3346 | } | |
3347 | #endif | |
3348 | ||
3349 | /* Set ISA, architecture, and cp0 register names as best we can. */ | |
eb38c52c | 3350 | #if !defined(SYMTAB_AVAILABLE) && 0 |
6643d27e FB |
3351 | /* This is running out on a target machine, not in a host tool. |
3352 | FIXME: Where does mips_target_info come from? */ | |
3353 | target_processor = mips_target_info.processor; | |
3354 | mips_isa = mips_target_info.isa; | |
3355 | #else | |
3356 | chosen_arch = choose_arch_by_number (info->mach); | |
3357 | if (chosen_arch != NULL) | |
3358 | { | |
3359 | mips_processor = chosen_arch->processor; | |
3360 | mips_isa = chosen_arch->isa; | |
3361 | mips_cp0_names = chosen_arch->cp0_names; | |
3362 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
3363 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
3364 | mips_hwr_names = chosen_arch->hwr_names; | |
3365 | } | |
3366 | #endif | |
3367 | } | |
3368 | ||
f9480ffc | 3369 | static void |
a5f1b965 | 3370 | parse_mips_dis_option (const char *option, unsigned int len) |
6643d27e FB |
3371 | { |
3372 | unsigned int i, optionlen, vallen; | |
3373 | const char *val; | |
3374 | const struct mips_abi_choice *chosen_abi; | |
3375 | const struct mips_arch_choice *chosen_arch; | |
3376 | ||
3377 | /* Look for the = that delimits the end of the option name. */ | |
3378 | for (i = 0; i < len; i++) | |
3379 | { | |
3380 | if (option[i] == '=') | |
3381 | break; | |
3382 | } | |
3383 | if (i == 0) /* Invalid option: no name before '='. */ | |
3384 | return; | |
3385 | if (i == len) /* Invalid option: no '='. */ | |
3386 | return; | |
3387 | if (i == (len - 1)) /* Invalid option: no value after '='. */ | |
3388 | return; | |
3389 | ||
3390 | optionlen = i; | |
3391 | val = option + (optionlen + 1); | |
3392 | vallen = len - (optionlen + 1); | |
3393 | ||
3394 | if (strncmp("gpr-names", option, optionlen) == 0 | |
3395 | && strlen("gpr-names") == optionlen) | |
3396 | { | |
3397 | chosen_abi = choose_abi_by_name (val, vallen); | |
3398 | if (chosen_abi != NULL) | |
3399 | mips_gpr_names = chosen_abi->gpr_names; | |
3400 | return; | |
3401 | } | |
3402 | ||
3403 | if (strncmp("fpr-names", option, optionlen) == 0 | |
3404 | && strlen("fpr-names") == optionlen) | |
3405 | { | |
3406 | chosen_abi = choose_abi_by_name (val, vallen); | |
3407 | if (chosen_abi != NULL) | |
3408 | mips_fpr_names = chosen_abi->fpr_names; | |
3409 | return; | |
3410 | } | |
3411 | ||
3412 | if (strncmp("cp0-names", option, optionlen) == 0 | |
3413 | && strlen("cp0-names") == optionlen) | |
3414 | { | |
3415 | chosen_arch = choose_arch_by_name (val, vallen); | |
3416 | if (chosen_arch != NULL) | |
3417 | { | |
3418 | mips_cp0_names = chosen_arch->cp0_names; | |
3419 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
3420 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
3421 | } | |
3422 | return; | |
3423 | } | |
3424 | ||
3425 | if (strncmp("hwr-names", option, optionlen) == 0 | |
3426 | && strlen("hwr-names") == optionlen) | |
3427 | { | |
3428 | chosen_arch = choose_arch_by_name (val, vallen); | |
3429 | if (chosen_arch != NULL) | |
3430 | mips_hwr_names = chosen_arch->hwr_names; | |
3431 | return; | |
3432 | } | |
3433 | ||
3434 | if (strncmp("reg-names", option, optionlen) == 0 | |
3435 | && strlen("reg-names") == optionlen) | |
3436 | { | |
3437 | /* We check both ABI and ARCH here unconditionally, so | |
3438 | that "numeric" will do the desirable thing: select | |
3439 | numeric register names for all registers. Other than | |
3440 | that, a given name probably won't match both. */ | |
3441 | chosen_abi = choose_abi_by_name (val, vallen); | |
3442 | if (chosen_abi != NULL) | |
3443 | { | |
3444 | mips_gpr_names = chosen_abi->gpr_names; | |
3445 | mips_fpr_names = chosen_abi->fpr_names; | |
3446 | } | |
3447 | chosen_arch = choose_arch_by_name (val, vallen); | |
3448 | if (chosen_arch != NULL) | |
3449 | { | |
3450 | mips_cp0_names = chosen_arch->cp0_names; | |
3451 | mips_cp0sel_names = chosen_arch->cp0sel_names; | |
3452 | mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; | |
3453 | mips_hwr_names = chosen_arch->hwr_names; | |
3454 | } | |
3455 | return; | |
3456 | } | |
3457 | ||
3458 | /* Invalid option. */ | |
3459 | } | |
3460 | ||
52da07d1 TS |
3461 | static void |
3462 | parse_mips_dis_options (const char *options) | |
6643d27e FB |
3463 | { |
3464 | const char *option_end; | |
3465 | ||
3466 | if (options == NULL) | |
3467 | return; | |
3468 | ||
3469 | while (*options != '\0') | |
3470 | { | |
3471 | /* Skip empty options. */ | |
3472 | if (*options == ',') | |
3473 | { | |
3474 | options++; | |
3475 | continue; | |
3476 | } | |
3477 | ||
3478 | /* We know that *options is neither NUL or a comma. */ | |
3479 | option_end = options + 1; | |
3480 | while (*option_end != ',' && *option_end != '\0') | |
3481 | option_end++; | |
3482 | ||
3483 | parse_mips_dis_option (options, option_end - options); | |
3484 | ||
3485 | /* Go on to the next one. If option_end points to a comma, it | |
3486 | will be skipped above. */ | |
3487 | options = option_end; | |
3488 | } | |
3489 | } | |
3490 | ||
3491 | static const struct mips_cp0sel_name * | |
52da07d1 TS |
3492 | lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, |
3493 | unsigned int len, | |
3494 | unsigned int cp0reg, | |
3495 | unsigned int sel) | |
6643d27e FB |
3496 | { |
3497 | unsigned int i; | |
3498 | ||
3499 | for (i = 0; i < len; i++) | |
3500 | if (names[i].cp0reg == cp0reg && names[i].sel == sel) | |
3501 | return &names[i]; | |
3502 | return NULL; | |
3503 | } | |
3504 | \f | |
3505 | /* Print insn arguments for 32/64-bit code. */ | |
3506 | ||
3507 | static void | |
52da07d1 TS |
3508 | print_insn_args (const char *d, |
3509 | register unsigned long int l, | |
3510 | bfd_vma pc, | |
3511 | struct disassemble_info *info, | |
3512 | const struct mips_opcode *opp) | |
6643d27e FB |
3513 | { |
3514 | int op, delta; | |
3515 | unsigned int lsb, msb, msbd; | |
3516 | ||
3517 | lsb = 0; | |
3518 | ||
3519 | for (; *d != '\0'; d++) | |
3520 | { | |
3521 | switch (*d) | |
3522 | { | |
3523 | case ',': | |
3524 | case '(': | |
3525 | case ')': | |
3526 | case '[': | |
3527 | case ']': | |
3528 | (*info->fprintf_func) (info->stream, "%c", *d); | |
3529 | break; | |
3530 | ||
3531 | case '+': | |
3532 | /* Extension character; switch for second char. */ | |
3533 | d++; | |
3534 | switch (*d) | |
3535 | { | |
3536 | case '\0': | |
3537 | /* xgettext:c-format */ | |
3538 | (*info->fprintf_func) (info->stream, | |
3539 | _("# internal error, incomplete extension sequence (+)")); | |
3540 | return; | |
3541 | ||
3542 | case 'A': | |
3543 | lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; | |
3544 | (*info->fprintf_func) (info->stream, "0x%x", lsb); | |
3545 | break; | |
52da07d1 | 3546 | |
6643d27e FB |
3547 | case 'B': |
3548 | msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; | |
3549 | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); | |
3550 | break; | |
3551 | ||
52da07d1 TS |
3552 | case '1': |
3553 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3554 | (l >> OP_SH_UDI1) & OP_MASK_UDI1); | |
3555 | break; | |
3556 | ||
3557 | case '2': | |
3558 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3559 | (l >> OP_SH_UDI2) & OP_MASK_UDI2); | |
3560 | break; | |
3561 | ||
3562 | case '3': | |
3563 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3564 | (l >> OP_SH_UDI3) & OP_MASK_UDI3); | |
3565 | break; | |
3566 | ||
3567 | case '4': | |
3568 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3569 | (l >> OP_SH_UDI4) & OP_MASK_UDI4); | |
3570 | break; | |
3571 | ||
6643d27e FB |
3572 | case 'C': |
3573 | case 'H': | |
3574 | msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; | |
3575 | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); | |
3576 | break; | |
3577 | ||
3578 | case 'D': | |
3579 | { | |
3580 | const struct mips_cp0sel_name *n; | |
3581 | unsigned int cp0reg, sel; | |
3582 | ||
3583 | cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
3584 | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; | |
3585 | ||
3586 | /* CP0 register including 'sel' code for mtcN (et al.), to be | |
3587 | printed textually if known. If not known, print both | |
3588 | CP0 register name and sel numerically since CP0 register | |
3589 | with sel 0 may have a name unrelated to register being | |
3590 | printed. */ | |
3591 | n = lookup_mips_cp0sel_name(mips_cp0sel_names, | |
3592 | mips_cp0sel_names_len, cp0reg, sel); | |
3593 | if (n != NULL) | |
3594 | (*info->fprintf_func) (info->stream, "%s", n->name); | |
3595 | else | |
3596 | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); | |
3597 | break; | |
3598 | } | |
3599 | ||
3600 | case 'E': | |
3601 | lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; | |
3602 | (*info->fprintf_func) (info->stream, "0x%x", lsb); | |
3603 | break; | |
5fafdf24 | 3604 | |
6643d27e FB |
3605 | case 'F': |
3606 | msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; | |
3607 | (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); | |
3608 | break; | |
3609 | ||
3610 | case 'G': | |
3611 | msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; | |
3612 | (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); | |
3613 | break; | |
3614 | ||
52da07d1 TS |
3615 | case 't': /* Coprocessor 0 reg name */ |
3616 | (*info->fprintf_func) (info->stream, "%s", | |
3617 | mips_cp0_names[(l >> OP_SH_RT) & | |
3618 | OP_MASK_RT]); | |
3619 | break; | |
3620 | ||
3621 | case 'T': /* Coprocessor 0 reg name */ | |
3622 | { | |
3623 | const struct mips_cp0sel_name *n; | |
3624 | unsigned int cp0reg, sel; | |
3625 | ||
3626 | cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; | |
3627 | sel = (l >> OP_SH_SEL) & OP_MASK_SEL; | |
3628 | ||
3629 | /* CP0 register including 'sel' code for mftc0, to be | |
3630 | printed textually if known. If not known, print both | |
3631 | CP0 register name and sel numerically since CP0 register | |
3632 | with sel 0 may have a name unrelated to register being | |
3633 | printed. */ | |
3634 | n = lookup_mips_cp0sel_name(mips_cp0sel_names, | |
3635 | mips_cp0sel_names_len, cp0reg, sel); | |
3636 | if (n != NULL) | |
3637 | (*info->fprintf_func) (info->stream, "%s", n->name); | |
3638 | else | |
3639 | (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); | |
3640 | break; | |
3641 | } | |
3642 | ||
6643d27e FB |
3643 | default: |
3644 | /* xgettext:c-format */ | |
3645 | (*info->fprintf_func) (info->stream, | |
3646 | _("# internal error, undefined extension sequence (+%c)"), | |
3647 | *d); | |
3648 | return; | |
3649 | } | |
3650 | break; | |
3651 | ||
52da07d1 TS |
3652 | case '2': |
3653 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3654 | (l >> OP_SH_BP) & OP_MASK_BP); | |
3655 | break; | |
3656 | ||
3657 | case '3': | |
3658 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3659 | (l >> OP_SH_SA3) & OP_MASK_SA3); | |
3660 | break; | |
3661 | ||
3662 | case '4': | |
3663 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3664 | (l >> OP_SH_SA4) & OP_MASK_SA4); | |
3665 | break; | |
3666 | ||
3667 | case '5': | |
3668 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3669 | (l >> OP_SH_IMM8) & OP_MASK_IMM8); | |
3670 | break; | |
3671 | ||
3672 | case '6': | |
3673 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3674 | (l >> OP_SH_RS) & OP_MASK_RS); | |
3675 | break; | |
3676 | ||
3677 | case '7': | |
3678 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
3679 | (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); | |
3680 | break; | |
3681 | ||
3682 | case '8': | |
3683 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3684 | (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); | |
3685 | break; | |
3686 | ||
3687 | case '9': | |
3688 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
3689 | (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); | |
3690 | break; | |
3691 | ||
3692 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
3693 | delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); | |
3694 | if (delta & 0x20) /* test sign bit */ | |
3695 | delta |= ~OP_MASK_DSPSFT; | |
3696 | (*info->fprintf_func) (info->stream, "%d", delta); | |
3697 | break; | |
3698 | ||
3699 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
3700 | delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); | |
3701 | if (delta & 0x40) /* test sign bit */ | |
3702 | delta |= ~OP_MASK_DSPSFT_7; | |
3703 | (*info->fprintf_func) (info->stream, "%d", delta); | |
3704 | break; | |
3705 | ||
3706 | case '\'': | |
3707 | (*info->fprintf_func) (info->stream, "0x%lx", | |
3708 | (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); | |
3709 | break; | |
3710 | ||
3711 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
3712 | delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); | |
3713 | if (delta & 0x200) /* test sign bit */ | |
3714 | delta |= ~OP_MASK_IMM10; | |
3715 | (*info->fprintf_func) (info->stream, "%d", delta); | |
3716 | break; | |
3717 | ||
3718 | case '!': | |
3719 | (*info->fprintf_func) (info->stream, "%ld", | |
3720 | (l >> OP_SH_MT_U) & OP_MASK_MT_U); | |
3721 | break; | |
3722 | ||
3723 | case '$': | |
3724 | (*info->fprintf_func) (info->stream, "%ld", | |
3725 | (l >> OP_SH_MT_H) & OP_MASK_MT_H); | |
3726 | break; | |
3727 | ||
3728 | case '*': | |
3729 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
3730 | (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); | |
3731 | break; | |
3732 | ||
3733 | case '&': | |
3734 | (*info->fprintf_func) (info->stream, "$ac%ld", | |
3735 | (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); | |
3736 | break; | |
3737 | ||
3738 | case 'g': | |
3739 | /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ | |
3740 | (*info->fprintf_func) (info->stream, "$%ld", | |
3741 | (l >> OP_SH_RD) & OP_MASK_RD); | |
3742 | break; | |
3743 | ||
6643d27e FB |
3744 | case 's': |
3745 | case 'b': | |
3746 | case 'r': | |
3747 | case 'v': | |
3748 | (*info->fprintf_func) (info->stream, "%s", | |
3749 | mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); | |
3750 | break; | |
3751 | ||
3752 | case 't': | |
3753 | case 'w': | |
3754 | (*info->fprintf_func) (info->stream, "%s", | |
3755 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
3756 | break; | |
3757 | ||
3758 | case 'i': | |
3759 | case 'u': | |
52da07d1 | 3760 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3761 | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
3762 | break; | |
3763 | ||
3764 | case 'j': /* Same as i, but sign-extended. */ | |
3765 | case 'o': | |
4368b29a LA |
3766 | delta = (opp->membership == I32R6) ? |
3767 | (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6 : | |
3768 | (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
3769 | ||
6643d27e FB |
3770 | if (delta & 0x8000) |
3771 | delta |= ~0xffff; | |
3772 | (*info->fprintf_func) (info->stream, "%d", | |
3773 | delta); | |
3774 | break; | |
3775 | ||
3776 | case 'h': | |
3777 | (*info->fprintf_func) (info->stream, "0x%x", | |
3778 | (unsigned int) ((l >> OP_SH_PREFX) | |
3779 | & OP_MASK_PREFX)); | |
3780 | break; | |
3781 | ||
3782 | case 'k': | |
3783 | (*info->fprintf_func) (info->stream, "0x%x", | |
3784 | (unsigned int) ((l >> OP_SH_CACHE) | |
3785 | & OP_MASK_CACHE)); | |
3786 | break; | |
3787 | ||
3788 | case 'a': | |
3789 | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) | |
3790 | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); | |
52da07d1 TS |
3791 | /* For gdb disassembler, force odd address on jalx. */ |
3792 | if (info->flavour == bfd_target_unknown_flavour | |
3793 | && strcmp (opp->name, "jalx") == 0) | |
3794 | info->target |= 1; | |
6643d27e FB |
3795 | (*info->print_address_func) (info->target, info); |
3796 | break; | |
3797 | ||
3798 | case 'p': | |
3799 | /* Sign extend the displacement. */ | |
3800 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
3801 | if (delta & 0x8000) | |
3802 | delta |= ~0xffff; | |
3803 | info->target = (delta << 2) + pc + INSNLEN; | |
3804 | (*info->print_address_func) (info->target, info); | |
3805 | break; | |
3806 | ||
3807 | case 'd': | |
3808 | (*info->fprintf_func) (info->stream, "%s", | |
3809 | mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
3810 | break; | |
3811 | ||
3812 | case 'U': | |
3813 | { | |
3814 | /* First check for both rd and rt being equal. */ | |
3815 | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
3816 | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) | |
3817 | (*info->fprintf_func) (info->stream, "%s", | |
3818 | mips_gpr_names[reg]); | |
3819 | else | |
3820 | { | |
3821 | /* If one is zero use the other. */ | |
3822 | if (reg == 0) | |
3823 | (*info->fprintf_func) (info->stream, "%s", | |
3824 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
3825 | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) | |
3826 | (*info->fprintf_func) (info->stream, "%s", | |
3827 | mips_gpr_names[reg]); | |
3828 | else /* Bogus, result depends on processor. */ | |
3829 | (*info->fprintf_func) (info->stream, "%s or %s", | |
3830 | mips_gpr_names[reg], | |
3831 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
3832 | } | |
3833 | } | |
3834 | break; | |
3835 | ||
3836 | case 'z': | |
3837 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); | |
3838 | break; | |
3839 | ||
3840 | case '<': | |
52da07d1 | 3841 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3842 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); |
3843 | break; | |
3844 | ||
3845 | case 'c': | |
52da07d1 | 3846 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3847 | (l >> OP_SH_CODE) & OP_MASK_CODE); |
3848 | break; | |
3849 | ||
3850 | case 'q': | |
52da07d1 | 3851 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3852 | (l >> OP_SH_CODE2) & OP_MASK_CODE2); |
3853 | break; | |
3854 | ||
3855 | case 'C': | |
52da07d1 | 3856 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3857 | (l >> OP_SH_COPZ) & OP_MASK_COPZ); |
3858 | break; | |
3859 | ||
3860 | case 'B': | |
52da07d1 TS |
3861 | (*info->fprintf_func) (info->stream, "0x%lx", |
3862 | ||
6643d27e FB |
3863 | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
3864 | break; | |
3865 | ||
3866 | case 'J': | |
52da07d1 | 3867 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3868 | (l >> OP_SH_CODE19) & OP_MASK_CODE19); |
3869 | break; | |
3870 | ||
3871 | case 'S': | |
3872 | case 'V': | |
3873 | (*info->fprintf_func) (info->stream, "%s", | |
3874 | mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); | |
3875 | break; | |
3876 | ||
3877 | case 'T': | |
3878 | case 'W': | |
3879 | (*info->fprintf_func) (info->stream, "%s", | |
3880 | mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); | |
3881 | break; | |
3882 | ||
3883 | case 'D': | |
3884 | (*info->fprintf_func) (info->stream, "%s", | |
3885 | mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); | |
3886 | break; | |
3887 | ||
3888 | case 'R': | |
3889 | (*info->fprintf_func) (info->stream, "%s", | |
3890 | mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); | |
3891 | break; | |
3892 | ||
3893 | case 'E': | |
3894 | /* Coprocessor register for lwcN instructions, et al. | |
3895 | ||
3896 | Note that there is no load/store cp0 instructions, and | |
3897 | that FPU (cp1) instructions disassemble this field using | |
3898 | 'T' format. Therefore, until we gain understanding of | |
3899 | cp2 register names, we can simply print the register | |
3900 | numbers. */ | |
52da07d1 | 3901 | (*info->fprintf_func) (info->stream, "$%ld", |
6643d27e FB |
3902 | (l >> OP_SH_RT) & OP_MASK_RT); |
3903 | break; | |
3904 | ||
3905 | case 'G': | |
3906 | /* Coprocessor register for mtcN instructions, et al. Note | |
3907 | that FPU (cp1) instructions disassemble this field using | |
3908 | 'S' format. Therefore, we only need to worry about cp0, | |
3909 | cp2, and cp3. */ | |
3910 | op = (l >> OP_SH_OP) & OP_MASK_OP; | |
3911 | if (op == OP_OP_COP0) | |
3912 | (*info->fprintf_func) (info->stream, "%s", | |
3913 | mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
3914 | else | |
52da07d1 | 3915 | (*info->fprintf_func) (info->stream, "$%ld", |
6643d27e FB |
3916 | (l >> OP_SH_RD) & OP_MASK_RD); |
3917 | break; | |
3918 | ||
3919 | case 'K': | |
3920 | (*info->fprintf_func) (info->stream, "%s", | |
3921 | mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
3922 | break; | |
3923 | ||
3924 | case 'N': | |
52da07d1 TS |
3925 | (*info->fprintf_func) (info->stream, |
3926 | ((opp->pinfo & (FP_D | FP_S)) != 0 | |
3927 | ? "$fcc%ld" : "$cc%ld"), | |
6643d27e FB |
3928 | (l >> OP_SH_BCC) & OP_MASK_BCC); |
3929 | break; | |
3930 | ||
3931 | case 'M': | |
52da07d1 | 3932 | (*info->fprintf_func) (info->stream, "$fcc%ld", |
6643d27e FB |
3933 | (l >> OP_SH_CCC) & OP_MASK_CCC); |
3934 | break; | |
3935 | ||
3936 | case 'P': | |
52da07d1 | 3937 | (*info->fprintf_func) (info->stream, "%ld", |
6643d27e FB |
3938 | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); |
3939 | break; | |
3940 | ||
3941 | case 'e': | |
52da07d1 | 3942 | (*info->fprintf_func) (info->stream, "%ld", |
6643d27e FB |
3943 | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); |
3944 | break; | |
3945 | ||
3946 | case '%': | |
52da07d1 | 3947 | (*info->fprintf_func) (info->stream, "%ld", |
6643d27e FB |
3948 | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); |
3949 | break; | |
3950 | ||
3951 | case 'H': | |
52da07d1 | 3952 | (*info->fprintf_func) (info->stream, "%ld", |
6643d27e FB |
3953 | (l >> OP_SH_SEL) & OP_MASK_SEL); |
3954 | break; | |
3955 | ||
3956 | case 'O': | |
52da07d1 | 3957 | (*info->fprintf_func) (info->stream, "%ld", |
6643d27e FB |
3958 | (l >> OP_SH_ALN) & OP_MASK_ALN); |
3959 | break; | |
3960 | ||
3961 | case 'Q': | |
3962 | { | |
3963 | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; | |
52da07d1 | 3964 | |
6643d27e FB |
3965 | if ((vsel & 0x10) == 0) |
3966 | { | |
3967 | int fmt; | |
52da07d1 | 3968 | |
6643d27e FB |
3969 | vsel &= 0x0f; |
3970 | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) | |
3971 | if ((vsel & 1) == 0) | |
3972 | break; | |
52da07d1 | 3973 | (*info->fprintf_func) (info->stream, "$v%ld[%d]", |
6643d27e FB |
3974 | (l >> OP_SH_FT) & OP_MASK_FT, |
3975 | vsel >> 1); | |
3976 | } | |
3977 | else if ((vsel & 0x08) == 0) | |
3978 | { | |
52da07d1 | 3979 | (*info->fprintf_func) (info->stream, "$v%ld", |
6643d27e FB |
3980 | (l >> OP_SH_FT) & OP_MASK_FT); |
3981 | } | |
3982 | else | |
3983 | { | |
52da07d1 | 3984 | (*info->fprintf_func) (info->stream, "0x%lx", |
6643d27e FB |
3985 | (l >> OP_SH_FT) & OP_MASK_FT); |
3986 | } | |
3987 | } | |
3988 | break; | |
3989 | ||
3990 | case 'X': | |
52da07d1 | 3991 | (*info->fprintf_func) (info->stream, "$v%ld", |
6643d27e FB |
3992 | (l >> OP_SH_FD) & OP_MASK_FD); |
3993 | break; | |
3994 | ||
3995 | case 'Y': | |
52da07d1 | 3996 | (*info->fprintf_func) (info->stream, "$v%ld", |
6643d27e FB |
3997 | (l >> OP_SH_FS) & OP_MASK_FS); |
3998 | break; | |
3999 | ||
4000 | case 'Z': | |
52da07d1 | 4001 | (*info->fprintf_func) (info->stream, "$v%ld", |
6643d27e FB |
4002 | (l >> OP_SH_FT) & OP_MASK_FT); |
4003 | break; | |
4004 | ||
4005 | default: | |
4006 | /* xgettext:c-format */ | |
4007 | (*info->fprintf_func) (info->stream, | |
4008 | _("# internal error, undefined modifier(%c)"), | |
4009 | *d); | |
4010 | return; | |
4011 | } | |
4012 | } | |
4013 | } | |
4014 | \f | |
4015 | /* Check if the object uses NewABI conventions. */ | |
4016 | #if 0 | |
4017 | static int | |
4018 | is_newabi (header) | |
4019 | Elf_Internal_Ehdr *header; | |
4020 | { | |
4021 | /* There are no old-style ABIs which use 64-bit ELF. */ | |
4022 | if (header->e_ident[EI_CLASS] == ELFCLASS64) | |
4023 | return 1; | |
4024 | ||
4025 | /* If a 32-bit ELF file, n32 is a new-style ABI. */ | |
4026 | if ((header->e_flags & EF_MIPS_ABI2) != 0) | |
4027 | return 1; | |
4028 | ||
4029 | return 0; | |
4030 | } | |
4031 | #endif | |
4032 | \f | |
4033 | /* Print the mips instruction at address MEMADDR in debugged memory, | |
4034 | on using INFO. Returns length of the instruction, in bytes, which is | |
4035 | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if | |
4036 | this is little-endian code. */ | |
4037 | ||
4038 | static int | |
52da07d1 TS |
4039 | print_insn_mips (bfd_vma memaddr, |
4040 | unsigned long int word, | |
4041 | struct disassemble_info *info) | |
6643d27e | 4042 | { |
52da07d1 | 4043 | const struct mips_opcode *op; |
6643d27e FB |
4044 | static bfd_boolean init = 0; |
4045 | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; | |
4046 | ||
4047 | /* Build a hash table to shorten the search time. */ | |
4048 | if (! init) | |
4049 | { | |
4050 | unsigned int i; | |
4051 | ||
4052 | for (i = 0; i <= OP_MASK_OP; i++) | |
4053 | { | |
4054 | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) | |
4055 | { | |
52da07d1 TS |
4056 | if (op->pinfo == INSN_MACRO |
4057 | || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) | |
6643d27e FB |
4058 | continue; |
4059 | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) | |
4060 | { | |
4061 | mips_hash[i] = op; | |
4062 | break; | |
4063 | } | |
4064 | } | |
4065 | } | |
4066 | ||
4067 | init = 1; | |
4068 | } | |
4069 | ||
4070 | info->bytes_per_chunk = INSNLEN; | |
4071 | info->display_endian = info->endian; | |
4072 | info->insn_info_valid = 1; | |
4073 | info->branch_delay_insns = 0; | |
4074 | info->data_size = 0; | |
4075 | info->insn_type = dis_nonbranch; | |
4076 | info->target = 0; | |
4077 | info->target2 = 0; | |
4078 | ||
4079 | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; | |
4080 | if (op != NULL) | |
4081 | { | |
4082 | for (; op < &mips_opcodes[NUMOPCODES]; op++) | |
4083 | { | |
52da07d1 TS |
4084 | if (op->pinfo != INSN_MACRO |
4085 | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) | |
4086 | && (word & op->mask) == op->match) | |
6643d27e | 4087 | { |
52da07d1 | 4088 | const char *d; |
6643d27e FB |
4089 | |
4090 | /* We always allow to disassemble the jalx instruction. */ | |
4091 | if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) | |
4092 | && strcmp (op->name, "jalx")) | |
4093 | continue; | |
4094 | ||
4095 | /* Figure out instruction type and branch delay information. */ | |
4096 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
4097 | { | |
4098 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
4099 | info->insn_type = dis_jsr; | |
4100 | else | |
4101 | info->insn_type = dis_branch; | |
4102 | info->branch_delay_insns = 1; | |
4103 | } | |
4104 | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY | |
4105 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
4106 | { | |
4107 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
4108 | info->insn_type = dis_condjsr; | |
4109 | else | |
4110 | info->insn_type = dis_condbranch; | |
4111 | info->branch_delay_insns = 1; | |
4112 | } | |
4113 | else if ((op->pinfo & (INSN_STORE_MEMORY | |
4114 | | INSN_LOAD_MEMORY_DELAY)) != 0) | |
4115 | info->insn_type = dis_dref; | |
4116 | ||
4117 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
4118 | ||
4119 | d = op->args; | |
4120 | if (d != NULL && *d != '\0') | |
4121 | { | |
4122 | (*info->fprintf_func) (info->stream, "\t"); | |
52da07d1 | 4123 | print_insn_args (d, word, memaddr, info, op); |
6643d27e FB |
4124 | } |
4125 | ||
4126 | return INSNLEN; | |
4127 | } | |
4128 | } | |
4129 | } | |
4130 | ||
4131 | /* Handle undefined instructions. */ | |
4132 | info->insn_type = dis_noninsn; | |
52da07d1 | 4133 | (*info->fprintf_func) (info->stream, "0x%lx", word); |
6643d27e FB |
4134 | return INSNLEN; |
4135 | } | |
4136 | \f | |
4137 | /* In an environment where we do not know the symbol type of the | |
4138 | instruction we are forced to assume that the low order bit of the | |
4139 | instructions' address may mark it as a mips16 instruction. If we | |
4140 | are single stepping, or the pc is within the disassembled function, | |
4141 | this works. Otherwise, we need a clue. Sometimes. */ | |
4142 | ||
6643d27e | 4143 | static int |
52da07d1 TS |
4144 | _print_insn_mips (bfd_vma memaddr, |
4145 | struct disassemble_info *info, | |
4146 | enum bfd_endian endianness) | |
6643d27e FB |
4147 | { |
4148 | bfd_byte buffer[INSNLEN]; | |
4149 | int status; | |
4150 | ||
4151 | set_default_mips_dis_options (info); | |
4152 | parse_mips_dis_options (info->disassembler_options); | |
4153 | ||
4154 | #if 0 | |
4155 | #if 1 | |
4156 | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ | |
4157 | /* Only a few tools will work this way. */ | |
4158 | if (memaddr & 0x01) | |
4159 | return print_insn_mips16 (memaddr, info); | |
4160 | #endif | |
4161 | ||
4162 | #if SYMTAB_AVAILABLE | |
4163 | if (info->mach == bfd_mach_mips16 | |
4164 | || (info->flavour == bfd_target_elf_flavour | |
4165 | && info->symbols != NULL | |
4166 | && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other | |
4167 | == STO_MIPS16))) | |
4168 | return print_insn_mips16 (memaddr, info); | |
4169 | #endif | |
4170 | #endif | |
4171 | ||
4172 | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); | |
4173 | if (status == 0) | |
4174 | { | |
4175 | unsigned long insn; | |
4176 | ||
4177 | if (endianness == BFD_ENDIAN_BIG) | |
4178 | insn = (unsigned long) bfd_getb32 (buffer); | |
4179 | else | |
4180 | insn = (unsigned long) bfd_getl32 (buffer); | |
4181 | ||
4182 | return print_insn_mips (memaddr, insn, info); | |
4183 | } | |
4184 | else | |
4185 | { | |
4186 | (*info->memory_error_func) (status, memaddr, info); | |
4187 | return -1; | |
4188 | } | |
4189 | } | |
4190 | ||
4191 | int | |
52da07d1 | 4192 | print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) |
6643d27e FB |
4193 | { |
4194 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); | |
4195 | } | |
4196 | ||
4197 | int | |
52da07d1 | 4198 | print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) |
6643d27e FB |
4199 | { |
4200 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); | |
4201 | } | |
4202 | \f | |
4203 | /* Disassemble mips16 instructions. */ | |
4204 | #if 0 | |
4205 | static int | |
52da07d1 | 4206 | print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) |
6643d27e FB |
4207 | { |
4208 | int status; | |
4209 | bfd_byte buffer[2]; | |
4210 | int length; | |
4211 | int insn; | |
4212 | bfd_boolean use_extend; | |
4213 | int extend = 0; | |
4214 | const struct mips_opcode *op, *opend; | |
4215 | ||
4216 | info->bytes_per_chunk = 2; | |
4217 | info->display_endian = info->endian; | |
4218 | info->insn_info_valid = 1; | |
4219 | info->branch_delay_insns = 0; | |
4220 | info->data_size = 0; | |
4221 | info->insn_type = dis_nonbranch; | |
4222 | info->target = 0; | |
4223 | info->target2 = 0; | |
4224 | ||
4225 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
4226 | if (status != 0) | |
4227 | { | |
4228 | (*info->memory_error_func) (status, memaddr, info); | |
4229 | return -1; | |
4230 | } | |
4231 | ||
4232 | length = 2; | |
4233 | ||
4234 | if (info->endian == BFD_ENDIAN_BIG) | |
4235 | insn = bfd_getb16 (buffer); | |
4236 | else | |
4237 | insn = bfd_getl16 (buffer); | |
4238 | ||
4239 | /* Handle the extend opcode specially. */ | |
4240 | use_extend = FALSE; | |
4241 | if ((insn & 0xf800) == 0xf000) | |
4242 | { | |
4243 | use_extend = TRUE; | |
4244 | extend = insn & 0x7ff; | |
4245 | ||
4246 | memaddr += 2; | |
4247 | ||
4248 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
4249 | if (status != 0) | |
4250 | { | |
4251 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
4252 | (unsigned int) extend); | |
4253 | (*info->memory_error_func) (status, memaddr, info); | |
4254 | return -1; | |
4255 | } | |
4256 | ||
4257 | if (info->endian == BFD_ENDIAN_BIG) | |
4258 | insn = bfd_getb16 (buffer); | |
4259 | else | |
4260 | insn = bfd_getl16 (buffer); | |
4261 | ||
4262 | /* Check for an extend opcode followed by an extend opcode. */ | |
4263 | if ((insn & 0xf800) == 0xf000) | |
4264 | { | |
4265 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
4266 | (unsigned int) extend); | |
4267 | info->insn_type = dis_noninsn; | |
4268 | return length; | |
4269 | } | |
4270 | ||
4271 | length += 2; | |
4272 | } | |
4273 | ||
4274 | /* FIXME: Should probably use a hash table on the major opcode here. */ | |
4275 | ||
4276 | opend = mips16_opcodes + bfd_mips16_num_opcodes; | |
4277 | for (op = mips16_opcodes; op < opend; op++) | |
4278 | { | |
52da07d1 TS |
4279 | if (op->pinfo != INSN_MACRO |
4280 | && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) | |
4281 | && (insn & op->mask) == op->match) | |
6643d27e FB |
4282 | { |
4283 | const char *s; | |
4284 | ||
4285 | if (strchr (op->args, 'a') != NULL) | |
4286 | { | |
4287 | if (use_extend) | |
4288 | { | |
4289 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
4290 | (unsigned int) extend); | |
4291 | info->insn_type = dis_noninsn; | |
4292 | return length - 2; | |
4293 | } | |
4294 | ||
4295 | use_extend = FALSE; | |
4296 | ||
4297 | memaddr += 2; | |
4298 | ||
4299 | status = (*info->read_memory_func) (memaddr, buffer, 2, | |
4300 | info); | |
4301 | if (status == 0) | |
4302 | { | |
4303 | use_extend = TRUE; | |
4304 | if (info->endian == BFD_ENDIAN_BIG) | |
4305 | extend = bfd_getb16 (buffer); | |
4306 | else | |
4307 | extend = bfd_getl16 (buffer); | |
4308 | length += 2; | |
4309 | } | |
4310 | } | |
4311 | ||
4312 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
4313 | if (op->args[0] != '\0') | |
4314 | (*info->fprintf_func) (info->stream, "\t"); | |
4315 | ||
4316 | for (s = op->args; *s != '\0'; s++) | |
4317 | { | |
4318 | if (*s == ',' | |
4319 | && s[1] == 'w' | |
4320 | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) | |
4321 | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) | |
4322 | { | |
4323 | /* Skip the register and the comma. */ | |
4324 | ++s; | |
4325 | continue; | |
4326 | } | |
4327 | if (*s == ',' | |
4328 | && s[1] == 'v' | |
4329 | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) | |
4330 | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) | |
4331 | { | |
4332 | /* Skip the register and the comma. */ | |
4333 | ++s; | |
4334 | continue; | |
4335 | } | |
4336 | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, | |
4337 | info); | |
4338 | } | |
4339 | ||
4340 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
4341 | { | |
4342 | info->branch_delay_insns = 1; | |
4343 | if (info->insn_type != dis_jsr) | |
4344 | info->insn_type = dis_branch; | |
4345 | } | |
4346 | ||
4347 | return length; | |
4348 | } | |
4349 | } | |
4350 | ||
4351 | if (use_extend) | |
4352 | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); | |
4353 | (*info->fprintf_func) (info->stream, "0x%x", insn); | |
4354 | info->insn_type = dis_noninsn; | |
4355 | ||
4356 | return length; | |
4357 | } | |
4358 | ||
4359 | /* Disassemble an operand for a mips16 instruction. */ | |
4360 | ||
4361 | static void | |
52da07d1 TS |
4362 | print_mips16_insn_arg (char type, |
4363 | const struct mips_opcode *op, | |
4364 | int l, | |
4365 | bfd_boolean use_extend, | |
4366 | int extend, | |
4367 | bfd_vma memaddr, | |
4368 | struct disassemble_info *info) | |
6643d27e FB |
4369 | { |
4370 | switch (type) | |
4371 | { | |
4372 | case ',': | |
4373 | case '(': | |
4374 | case ')': | |
4375 | (*info->fprintf_func) (info->stream, "%c", type); | |
4376 | break; | |
4377 | ||
4378 | case 'y': | |
4379 | case 'w': | |
4380 | (*info->fprintf_func) (info->stream, "%s", | |
52da07d1 TS |
4381 | mips16_reg_names(((l >> MIPS16OP_SH_RY) |
4382 | & MIPS16OP_MASK_RY))); | |
6643d27e FB |
4383 | break; |
4384 | ||
4385 | case 'x': | |
4386 | case 'v': | |
4387 | (*info->fprintf_func) (info->stream, "%s", | |
52da07d1 TS |
4388 | mips16_reg_names(((l >> MIPS16OP_SH_RX) |
4389 | & MIPS16OP_MASK_RX))); | |
6643d27e FB |
4390 | break; |
4391 | ||
4392 | case 'z': | |
4393 | (*info->fprintf_func) (info->stream, "%s", | |
52da07d1 TS |
4394 | mips16_reg_names(((l >> MIPS16OP_SH_RZ) |
4395 | & MIPS16OP_MASK_RZ))); | |
6643d27e FB |
4396 | break; |
4397 | ||
4398 | case 'Z': | |
4399 | (*info->fprintf_func) (info->stream, "%s", | |
52da07d1 TS |
4400 | mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) |
4401 | & MIPS16OP_MASK_MOVE32Z))); | |
6643d27e FB |
4402 | break; |
4403 | ||
4404 | case '0': | |
4405 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); | |
4406 | break; | |
4407 | ||
4408 | case 'S': | |
4409 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); | |
4410 | break; | |
4411 | ||
4412 | case 'P': | |
4413 | (*info->fprintf_func) (info->stream, "$pc"); | |
4414 | break; | |
4415 | ||
4416 | case 'R': | |
4417 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); | |
4418 | break; | |
4419 | ||
4420 | case 'X': | |
4421 | (*info->fprintf_func) (info->stream, "%s", | |
4422 | mips_gpr_names[((l >> MIPS16OP_SH_REGR32) | |
4423 | & MIPS16OP_MASK_REGR32)]); | |
4424 | break; | |
4425 | ||
4426 | case 'Y': | |
4427 | (*info->fprintf_func) (info->stream, "%s", | |
4428 | mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); | |
4429 | break; | |
4430 | ||
4431 | case '<': | |
4432 | case '>': | |
4433 | case '[': | |
4434 | case ']': | |
4435 | case '4': | |
4436 | case '5': | |
4437 | case 'H': | |
4438 | case 'W': | |
4439 | case 'D': | |
4440 | case 'j': | |
4441 | case '6': | |
4442 | case '8': | |
4443 | case 'V': | |
4444 | case 'C': | |
4445 | case 'U': | |
4446 | case 'k': | |
4447 | case 'K': | |
4448 | case 'p': | |
4449 | case 'q': | |
4450 | case 'A': | |
4451 | case 'B': | |
4452 | case 'E': | |
4453 | { | |
4454 | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; | |
4455 | ||
4456 | shift = 0; | |
4457 | signedp = 0; | |
4458 | extbits = 16; | |
4459 | pcrel = 0; | |
4460 | extu = 0; | |
4461 | branch = 0; | |
4462 | switch (type) | |
4463 | { | |
4464 | case '<': | |
4465 | nbits = 3; | |
4466 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
4467 | extbits = 5; | |
4468 | extu = 1; | |
4469 | break; | |
4470 | case '>': | |
4471 | nbits = 3; | |
4472 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
4473 | extbits = 5; | |
4474 | extu = 1; | |
4475 | break; | |
4476 | case '[': | |
4477 | nbits = 3; | |
4478 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
4479 | extbits = 6; | |
4480 | extu = 1; | |
4481 | break; | |
4482 | case ']': | |
4483 | nbits = 3; | |
4484 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
4485 | extbits = 6; | |
4486 | extu = 1; | |
4487 | break; | |
4488 | case '4': | |
4489 | nbits = 4; | |
4490 | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; | |
4491 | signedp = 1; | |
4492 | extbits = 15; | |
4493 | break; | |
4494 | case '5': | |
4495 | nbits = 5; | |
4496 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4497 | info->insn_type = dis_dref; | |
4498 | info->data_size = 1; | |
4499 | break; | |
4500 | case 'H': | |
4501 | nbits = 5; | |
4502 | shift = 1; | |
4503 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4504 | info->insn_type = dis_dref; | |
4505 | info->data_size = 2; | |
4506 | break; | |
4507 | case 'W': | |
4508 | nbits = 5; | |
4509 | shift = 2; | |
4510 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4511 | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 | |
4512 | && (op->pinfo & MIPS16_INSN_READ_SP) == 0) | |
4513 | { | |
4514 | info->insn_type = dis_dref; | |
4515 | info->data_size = 4; | |
4516 | } | |
4517 | break; | |
4518 | case 'D': | |
4519 | nbits = 5; | |
4520 | shift = 3; | |
4521 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4522 | info->insn_type = dis_dref; | |
4523 | info->data_size = 8; | |
4524 | break; | |
4525 | case 'j': | |
4526 | nbits = 5; | |
4527 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4528 | signedp = 1; | |
4529 | break; | |
4530 | case '6': | |
4531 | nbits = 6; | |
4532 | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
4533 | break; | |
4534 | case '8': | |
4535 | nbits = 8; | |
4536 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4537 | break; | |
4538 | case 'V': | |
4539 | nbits = 8; | |
4540 | shift = 2; | |
4541 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4542 | /* FIXME: This might be lw, or it might be addiu to $sp or | |
4543 | $pc. We assume it's load. */ | |
4544 | info->insn_type = dis_dref; | |
4545 | info->data_size = 4; | |
4546 | break; | |
4547 | case 'C': | |
4548 | nbits = 8; | |
4549 | shift = 3; | |
4550 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4551 | info->insn_type = dis_dref; | |
4552 | info->data_size = 8; | |
4553 | break; | |
4554 | case 'U': | |
4555 | nbits = 8; | |
4556 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4557 | extu = 1; | |
4558 | break; | |
4559 | case 'k': | |
4560 | nbits = 8; | |
4561 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4562 | signedp = 1; | |
4563 | break; | |
4564 | case 'K': | |
4565 | nbits = 8; | |
4566 | shift = 3; | |
4567 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4568 | signedp = 1; | |
4569 | break; | |
4570 | case 'p': | |
4571 | nbits = 8; | |
4572 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4573 | signedp = 1; | |
4574 | pcrel = 1; | |
4575 | branch = 1; | |
4576 | info->insn_type = dis_condbranch; | |
4577 | break; | |
4578 | case 'q': | |
4579 | nbits = 11; | |
4580 | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; | |
4581 | signedp = 1; | |
4582 | pcrel = 1; | |
4583 | branch = 1; | |
4584 | info->insn_type = dis_branch; | |
4585 | break; | |
4586 | case 'A': | |
4587 | nbits = 8; | |
4588 | shift = 2; | |
4589 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
4590 | pcrel = 1; | |
4591 | /* FIXME: This can be lw or la. We assume it is lw. */ | |
4592 | info->insn_type = dis_dref; | |
4593 | info->data_size = 4; | |
4594 | break; | |
4595 | case 'B': | |
4596 | nbits = 5; | |
4597 | shift = 3; | |
4598 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4599 | pcrel = 1; | |
4600 | info->insn_type = dis_dref; | |
4601 | info->data_size = 8; | |
4602 | break; | |
4603 | case 'E': | |
4604 | nbits = 5; | |
4605 | shift = 2; | |
4606 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
4607 | pcrel = 1; | |
4608 | break; | |
4609 | default: | |
4610 | abort (); | |
4611 | } | |
4612 | ||
4613 | if (! use_extend) | |
4614 | { | |
4615 | if (signedp && immed >= (1 << (nbits - 1))) | |
4616 | immed -= 1 << nbits; | |
4617 | immed <<= shift; | |
4618 | if ((type == '<' || type == '>' || type == '[' || type == ']') | |
4619 | && immed == 0) | |
4620 | immed = 8; | |
4621 | } | |
4622 | else | |
4623 | { | |
4624 | if (extbits == 16) | |
4625 | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); | |
4626 | else if (extbits == 15) | |
4627 | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); | |
4628 | else | |
4629 | immed = ((extend >> 6) & 0x1f) | (extend & 0x20); | |
4630 | immed &= (1 << extbits) - 1; | |
4631 | if (! extu && immed >= (1 << (extbits - 1))) | |
4632 | immed -= 1 << extbits; | |
4633 | } | |
4634 | ||
4635 | if (! pcrel) | |
4636 | (*info->fprintf_func) (info->stream, "%d", immed); | |
4637 | else | |
4638 | { | |
4639 | bfd_vma baseaddr; | |
4640 | ||
4641 | if (branch) | |
4642 | { | |
4643 | immed *= 2; | |
4644 | baseaddr = memaddr + 2; | |
4645 | } | |
4646 | else if (use_extend) | |
4647 | baseaddr = memaddr - 2; | |
4648 | else | |
4649 | { | |
4650 | int status; | |
4651 | bfd_byte buffer[2]; | |
4652 | ||
4653 | baseaddr = memaddr; | |
4654 | ||
4655 | /* If this instruction is in the delay slot of a jr | |
4656 | instruction, the base address is the address of the | |
4657 | jr instruction. If it is in the delay slot of jalr | |
4658 | instruction, the base address is the address of the | |
4659 | jalr instruction. This test is unreliable: we have | |
4660 | no way of knowing whether the previous word is | |
4661 | instruction or data. */ | |
4662 | status = (*info->read_memory_func) (memaddr - 4, buffer, 2, | |
4663 | info); | |
4664 | if (status == 0 | |
4665 | && (((info->endian == BFD_ENDIAN_BIG | |
4666 | ? bfd_getb16 (buffer) | |
4667 | : bfd_getl16 (buffer)) | |
4668 | & 0xf800) == 0x1800)) | |
4669 | baseaddr = memaddr - 4; | |
4670 | else | |
4671 | { | |
4672 | status = (*info->read_memory_func) (memaddr - 2, buffer, | |
4673 | 2, info); | |
4674 | if (status == 0 | |
4675 | && (((info->endian == BFD_ENDIAN_BIG | |
4676 | ? bfd_getb16 (buffer) | |
4677 | : bfd_getl16 (buffer)) | |
4678 | & 0xf81f) == 0xe800)) | |
4679 | baseaddr = memaddr - 2; | |
4680 | } | |
4681 | } | |
4682 | info->target = (baseaddr & ~((1 << shift) - 1)) + immed; | |
52da07d1 TS |
4683 | if (pcrel && branch |
4684 | && info->flavour == bfd_target_unknown_flavour) | |
4685 | /* For gdb disassembler, maintain odd address. */ | |
4686 | info->target |= 1; | |
6643d27e FB |
4687 | (*info->print_address_func) (info->target, info); |
4688 | } | |
4689 | } | |
4690 | break; | |
4691 | ||
4692 | case 'a': | |
52da07d1 TS |
4693 | { |
4694 | int jalx = l & 0x400; | |
4695 | ||
4696 | if (! use_extend) | |
4697 | extend = 0; | |
4698 | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); | |
4699 | if (!jalx && info->flavour == bfd_target_unknown_flavour) | |
4700 | /* For gdb disassembler, maintain odd address. */ | |
4701 | l |= 1; | |
4702 | } | |
6643d27e FB |
4703 | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
4704 | (*info->print_address_func) (info->target, info); | |
4705 | info->insn_type = dis_jsr; | |
4706 | info->branch_delay_insns = 1; | |
4707 | break; | |
4708 | ||
4709 | case 'l': | |
4710 | case 'L': | |
4711 | { | |
4712 | int need_comma, amask, smask; | |
4713 | ||
4714 | need_comma = 0; | |
4715 | ||
4716 | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
4717 | ||
4718 | amask = (l >> 3) & 7; | |
4719 | ||
4720 | if (amask > 0 && amask < 5) | |
4721 | { | |
4722 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); | |
4723 | if (amask > 1) | |
4724 | (*info->fprintf_func) (info->stream, "-%s", | |
4725 | mips_gpr_names[amask + 3]); | |
4726 | need_comma = 1; | |
4727 | } | |
4728 | ||
4729 | smask = (l >> 1) & 3; | |
4730 | if (smask == 3) | |
4731 | { | |
4732 | (*info->fprintf_func) (info->stream, "%s??", | |
4733 | need_comma ? "," : ""); | |
4734 | need_comma = 1; | |
4735 | } | |
4736 | else if (smask > 0) | |
4737 | { | |
4738 | (*info->fprintf_func) (info->stream, "%s%s", | |
4739 | need_comma ? "," : "", | |
4740 | mips_gpr_names[16]); | |
4741 | if (smask > 1) | |
4742 | (*info->fprintf_func) (info->stream, "-%s", | |
4743 | mips_gpr_names[smask + 15]); | |
4744 | need_comma = 1; | |
4745 | } | |
4746 | ||
4747 | if (l & 1) | |
4748 | { | |
4749 | (*info->fprintf_func) (info->stream, "%s%s", | |
4750 | need_comma ? "," : "", | |
4751 | mips_gpr_names[31]); | |
4752 | need_comma = 1; | |
4753 | } | |
4754 | ||
4755 | if (amask == 5 || amask == 6) | |
4756 | { | |
4757 | (*info->fprintf_func) (info->stream, "%s$f0", | |
4758 | need_comma ? "," : ""); | |
4759 | if (amask == 6) | |
4760 | (*info->fprintf_func) (info->stream, "-$f1"); | |
4761 | } | |
4762 | } | |
4763 | break; | |
4764 | ||
52da07d1 TS |
4765 | case 'm': |
4766 | case 'M': | |
4767 | /* MIPS16e save/restore. */ | |
4768 | { | |
4769 | int need_comma = 0; | |
4770 | int amask, args, statics; | |
4771 | int nsreg, smask; | |
4772 | int framesz; | |
4773 | int i, j; | |
4774 | ||
4775 | l = l & 0x7f; | |
4776 | if (use_extend) | |
4777 | l |= extend << 16; | |
4778 | ||
4779 | amask = (l >> 16) & 0xf; | |
4780 | if (amask == MIPS16_ALL_ARGS) | |
4781 | { | |
4782 | args = 4; | |
4783 | statics = 0; | |
4784 | } | |
4785 | else if (amask == MIPS16_ALL_STATICS) | |
4786 | { | |
4787 | args = 0; | |
4788 | statics = 4; | |
4789 | } | |
4790 | else | |
4791 | { | |
4792 | args = amask >> 2; | |
4793 | statics = amask & 3; | |
4794 | } | |
4795 | ||
4796 | if (args > 0) { | |
4797 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); | |
4798 | if (args > 1) | |
4799 | (*info->fprintf_func) (info->stream, "-%s", | |
4800 | mips_gpr_names[4 + args - 1]); | |
4801 | need_comma = 1; | |
4802 | } | |
4803 | ||
4804 | framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; | |
4805 | if (framesz == 0 && !use_extend) | |
4806 | framesz = 128; | |
4807 | ||
4808 | (*info->fprintf_func) (info->stream, "%s%d", | |
4809 | need_comma ? "," : "", | |
4810 | framesz); | |
4811 | ||
4812 | if (l & 0x40) /* $ra */ | |
4813 | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); | |
4814 | ||
4815 | nsreg = (l >> 24) & 0x7; | |
4816 | smask = 0; | |
4817 | if (l & 0x20) /* $s0 */ | |
4818 | smask |= 1 << 0; | |
4819 | if (l & 0x10) /* $s1 */ | |
4820 | smask |= 1 << 1; | |
4821 | if (nsreg > 0) /* $s2-$s8 */ | |
4822 | smask |= ((1 << nsreg) - 1) << 2; | |
4823 | ||
4824 | /* Find first set static reg bit. */ | |
4825 | for (i = 0; i < 9; i++) | |
4826 | { | |
4827 | if (smask & (1 << i)) | |
4828 | { | |
4829 | (*info->fprintf_func) (info->stream, ",%s", | |
4830 | mips_gpr_names[i == 8 ? 30 : (16 + i)]); | |
4831 | /* Skip over string of set bits. */ | |
4832 | for (j = i; smask & (2 << j); j++) | |
4833 | continue; | |
4834 | if (j > i) | |
4835 | (*info->fprintf_func) (info->stream, "-%s", | |
4836 | mips_gpr_names[j == 8 ? 30 : (16 + j)]); | |
4837 | i = j + 1; | |
4838 | } | |
4839 | } | |
4840 | ||
4841 | /* Statics $ax - $a3. */ | |
4842 | if (statics == 1) | |
4843 | (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); | |
4844 | else if (statics > 0) | |
4845 | (*info->fprintf_func) (info->stream, ",%s-%s", | |
4846 | mips_gpr_names[7 - statics + 1], | |
4847 | mips_gpr_names[7]); | |
4848 | } | |
4849 | break; | |
4850 | ||
6643d27e FB |
4851 | default: |
4852 | /* xgettext:c-format */ | |
4853 | (*info->fprintf_func) | |
4854 | (info->stream, | |
4855 | _("# internal disassembler error, unrecognised modifier (%c)"), | |
4856 | type); | |
4857 | abort (); | |
4858 | } | |
4859 | } | |
6643d27e FB |
4860 | |
4861 | void | |
52da07d1 | 4862 | print_mips_disassembler_options (FILE *stream) |
6643d27e FB |
4863 | { |
4864 | unsigned int i; | |
4865 | ||
4866 | fprintf (stream, _("\n\ | |
4867 | The following MIPS specific disassembler options are supported for use\n\ | |
4868 | with the -M switch (multiple options should be separated by commas):\n")); | |
4869 | ||
4870 | fprintf (stream, _("\n\ | |
4871 | gpr-names=ABI Print GPR names according to specified ABI.\n\ | |
4872 | Default: based on binary being disassembled.\n")); | |
4873 | ||
4874 | fprintf (stream, _("\n\ | |
4875 | fpr-names=ABI Print FPR names according to specified ABI.\n\ | |
4876 | Default: numeric.\n")); | |
4877 | ||
4878 | fprintf (stream, _("\n\ | |
4879 | cp0-names=ARCH Print CP0 register names according to\n\ | |
4880 | specified architecture.\n\ | |
4881 | Default: based on binary being disassembled.\n")); | |
4882 | ||
4883 | fprintf (stream, _("\n\ | |
b2bedb21 | 4884 | hwr-names=ARCH Print HWR names according to specified\n\ |
6643d27e FB |
4885 | architecture.\n\ |
4886 | Default: based on binary being disassembled.\n")); | |
4887 | ||
4888 | fprintf (stream, _("\n\ | |
4889 | reg-names=ABI Print GPR and FPR names according to\n\ | |
4890 | specified ABI.\n")); | |
4891 | ||
4892 | fprintf (stream, _("\n\ | |
4893 | reg-names=ARCH Print CP0 register and HWR names according to\n\ | |
4894 | specified architecture.\n")); | |
4895 | ||
4896 | fprintf (stream, _("\n\ | |
4897 | For the options above, the following values are supported for \"ABI\":\n\ | |
4898 | ")); | |
4899 | for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) | |
4900 | fprintf (stream, " %s", mips_abi_choices[i].name); | |
4901 | fprintf (stream, _("\n")); | |
4902 | ||
4903 | fprintf (stream, _("\n\ | |
4904 | For the options above, The following values are supported for \"ARCH\":\n\ | |
4905 | ")); | |
4906 | for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) | |
4907 | if (*mips_arch_choices[i].name != '\0') | |
4908 | fprintf (stream, " %s", mips_arch_choices[i].name); | |
4909 | fprintf (stream, _("\n")); | |
4910 | ||
4911 | fprintf (stream, _("\n")); | |
4912 | } | |
f9480ffc | 4913 | #endif |