[mirror_qemu.git] / disas / riscv-xventana.h

/*
 * QEMU disassembler -- RISC-V specific header (xventana*).
 *
 * Copyright (c) 2023 VRULL GmbH
 *
 * SPDX-License-Identifier: GPL-2.0-or-later
 */

#ifndef DISAS_RISCV_XVENTANA_H
#define DISAS_RISCV_XVENTANA_H

#include "disas/riscv.h"

extern const rv_opcode_data ventana_opcode_data[];

void decode_xventanacondops(rv_decode*, rv_isa);

#endif /* DISAS_RISCV_XVENTANA_H */
Commit	Line	Data
f6f72338 CM	1	/*
	2	* QEMU disassembler -- RISC-V specific header (xventana*).
	3	*
	4	* Copyright (c) 2023 VRULL GmbH
	5	*
	6	* SPDX-License-Identifier: GPL-2.0-or-later
	7	*/
	8
	9	#ifndef DISAS_RISCV_XVENTANA_H
	10	#define DISAS_RISCV_XVENTANA_H
	11
	12	#include "disas/riscv.h"
	13
	14	extern const rv_opcode_data ventana_opcode_data[];
	15
	16	void decode_xventanacondops(rv_decode*, rv_isa);
	17
	18	#endif /* DISAS_RISCV_XVENTANA_H */