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Define DMA address and direction types
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1/*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
10#include "dma.h"
59a703eb 11#include "block_int.h"
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12
13void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint)
14{
7267c094 15 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
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16 qsg->nsg = 0;
17 qsg->nalloc = alloc_hint;
18 qsg->size = 0;
19}
20
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21void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
22 target_phys_addr_t len)
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23{
24 if (qsg->nsg == qsg->nalloc) {
25 qsg->nalloc = 2 * qsg->nalloc + 1;
7267c094 26 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
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27 }
28 qsg->sg[qsg->nsg].base = base;
29 qsg->sg[qsg->nsg].len = len;
30 qsg->size += len;
31 ++qsg->nsg;
32}
33
34void qemu_sglist_destroy(QEMUSGList *qsg)
35{
7267c094 36 g_free(qsg->sg);
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37}
38
59a703eb 39typedef struct {
37b7842c 40 BlockDriverAIOCB common;
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41 BlockDriverState *bs;
42 BlockDriverAIOCB *acb;
43 QEMUSGList *sg;
44 uint64_t sector_num;
bbca72c6 45 bool to_dev;
c3adb5b9 46 bool in_cancel;
59a703eb 47 int sg_cur_index;
c227f099 48 target_phys_addr_t sg_cur_byte;
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49 QEMUIOVector iov;
50 QEMUBH *bh;
cb144ccb 51 DMAIOFunc *io_func;
37b7842c 52} DMAAIOCB;
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53
54static void dma_bdrv_cb(void *opaque, int ret);
55
56static void reschedule_dma(void *opaque)
57{
37b7842c 58 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
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59
60 qemu_bh_delete(dbs->bh);
61 dbs->bh = NULL;
c3adb5b9 62 dma_bdrv_cb(dbs, 0);
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63}
64
65static void continue_after_map_failure(void *opaque)
66{
37b7842c 67 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
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68
69 dbs->bh = qemu_bh_new(reschedule_dma, dbs);
70 qemu_bh_schedule(dbs->bh);
71}
72
7403b14e 73static void dma_bdrv_unmap(DMAAIOCB *dbs)
59a703eb 74{
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75 int i;
76
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77 for (i = 0; i < dbs->iov.niov; ++i) {
78 cpu_physical_memory_unmap(dbs->iov.iov[i].iov_base,
bbca72c6 79 dbs->iov.iov[i].iov_len, !dbs->to_dev,
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80 dbs->iov.iov[i].iov_len);
81 }
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82 qemu_iovec_reset(&dbs->iov);
83}
84
85static void dma_complete(DMAAIOCB *dbs, int ret)
86{
87 dma_bdrv_unmap(dbs);
88 if (dbs->common.cb) {
89 dbs->common.cb(dbs->common.opaque, ret);
90 }
91 qemu_iovec_destroy(&dbs->iov);
92 if (dbs->bh) {
93 qemu_bh_delete(dbs->bh);
94 dbs->bh = NULL;
95 }
96 if (!dbs->in_cancel) {
97 /* Requests may complete while dma_aio_cancel is in progress. In
98 * this case, the AIOCB should not be released because it is still
99 * referenced by dma_aio_cancel. */
100 qemu_aio_release(dbs);
101 }
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102}
103
856ae5c3 104static void dma_bdrv_cb(void *opaque, int ret)
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105{
106 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
c227f099 107 target_phys_addr_t cur_addr, cur_len;
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108 void *mem;
109
110 dbs->acb = NULL;
111 dbs->sector_num += dbs->iov.size / 512;
112 dma_bdrv_unmap(dbs);
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113
114 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
c3adb5b9 115 dma_complete(dbs, ret);
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116 return;
117 }
118
119 while (dbs->sg_cur_index < dbs->sg->nsg) {
120 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
121 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
bbca72c6 122 mem = cpu_physical_memory_map(cur_addr, &cur_len, !dbs->to_dev);
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123 if (!mem)
124 break;
125 qemu_iovec_add(&dbs->iov, mem, cur_len);
126 dbs->sg_cur_byte += cur_len;
127 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
128 dbs->sg_cur_byte = 0;
129 ++dbs->sg_cur_index;
130 }
131 }
132
133 if (dbs->iov.size == 0) {
134 cpu_register_map_client(dbs, continue_after_map_failure);
135 return;
136 }
137
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138 dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov,
139 dbs->iov.size / 512, dma_bdrv_cb, dbs);
7403b14e 140 if (!dbs->acb) {
c3adb5b9 141 dma_complete(dbs, -EIO);
7403b14e 142 }
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143}
144
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145static void dma_aio_cancel(BlockDriverAIOCB *acb)
146{
147 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
148
149 if (dbs->acb) {
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150 BlockDriverAIOCB *acb = dbs->acb;
151 dbs->acb = NULL;
152 dbs->in_cancel = true;
153 bdrv_aio_cancel(acb);
154 dbs->in_cancel = false;
c16b5a2c 155 }
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156 dbs->common.cb = NULL;
157 dma_complete(dbs, 0);
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158}
159
160static AIOPool dma_aio_pool = {
161 .aiocb_size = sizeof(DMAAIOCB),
162 .cancel = dma_aio_cancel,
163};
164
cb144ccb 165BlockDriverAIOCB *dma_bdrv_io(
59a703eb 166 BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num,
cb144ccb 167 DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
bbca72c6 168 void *opaque, bool to_dev)
59a703eb 169{
cb144ccb 170 DMAAIOCB *dbs = qemu_aio_get(&dma_aio_pool, bs, cb, opaque);
59a703eb 171
37b7842c 172 dbs->acb = NULL;
59a703eb 173 dbs->bs = bs;
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174 dbs->sg = sg;
175 dbs->sector_num = sector_num;
176 dbs->sg_cur_index = 0;
177 dbs->sg_cur_byte = 0;
bbca72c6 178 dbs->to_dev = to_dev;
cb144ccb 179 dbs->io_func = io_func;
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180 dbs->bh = NULL;
181 qemu_iovec_init(&dbs->iov, sg->nsg);
182 dma_bdrv_cb(dbs, 0);
37b7842c 183 return &dbs->common;
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184}
185
186
187BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
188 QEMUSGList *sg, uint64_t sector,
189 void (*cb)(void *opaque, int ret), void *opaque)
190{
bbca72c6 191 return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque, false);
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192}
193
194BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
195 QEMUSGList *sg, uint64_t sector,
196 void (*cb)(void *opaque, int ret), void *opaque)
197{
bbca72c6 198 return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque, true);
59a703eb 199}