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a0a6754b AB |
1 | .. _Arm Emulation: |
2 | ||
741292fa PM |
3 | A-profile CPU architecture support |
4 | ================================== | |
5 | ||
6 | QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and | |
7 | Armv8 versions of the A-profile architecture. It also has support for | |
8 | the following architecture extensions: | |
9 | ||
10 | - FEAT_AA32BF16 (AArch32 BFloat16 instructions) | |
11 | - FEAT_AA32HPD (AArch32 hierarchical permission disables) | |
12 | - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) | |
13 | - FEAT_AES (AESD and AESE instructions) | |
75d08a40 | 14 | - FEAT_BBM at level 2 (Translation table break-before-make levels) |
741292fa PM |
15 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
16 | - FEAT_BTI (Branch Target Identification) | |
9e771a2f | 17 | - FEAT_CRC32 (CRC32 instructions) |
74b17e16 | 18 | - FEAT_CSV2 (Cache speculation variant 2) |
7cb1e618 RH |
19 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
20 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | |
21 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | |
3082b86b | 22 | - FEAT_CSV3 (Cache speculation variant 3) |
6d965019 | 23 | - FEAT_DGH (Data gathering hint) |
741292fa PM |
24 | - FEAT_DIT (Data Independent Timing instructions) |
25 | - FEAT_DPB (DC CVAP instruction) | |
033a4f15 | 26 | - FEAT_Debugv8p2 (Debug changes for v8.2) |
8fc756b6 | 27 | - FEAT_Debugv8p4 (Debug changes for v8.4) |
741292fa | 28 | - FEAT_DotProd (Advanced SIMD dot product instructions) |
7ac61020 | 29 | - FEAT_DoubleFault (Double Fault Extension) |
e4c93e44 | 30 | - FEAT_E0PD (Preventing EL0 access to halves of address maps) |
c3ccd566 | 31 | - FEAT_EPAC (Enhanced pointer authentication) |
3fe72e21 | 32 | - FEAT_ETS (Enhanced Translation Synchronization) |
41654f12 | 33 | - FEAT_EVT (Enhanced Virtualization Traps) |
741292fa | 34 | - FEAT_FCMA (Floating-point complex number instructions) |
bb18151d | 35 | - FEAT_FGT (Fine-Grained Traps) |
741292fa PM |
36 | - FEAT_FHM (Floating-point half-precision multiplication instructions) |
37 | - FEAT_FP16 (Half-precision floating-point data processing) | |
8a69a423 AL |
38 | - FEAT_FPAC (Faulting on AUT* instructions) |
39 | - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) | |
741292fa PM |
40 | - FEAT_FRINTTS (Floating-point to integer instructions) |
41 | - FEAT_FlagM (Flag manipulation instructions v2) | |
42 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) | |
915f6284 | 43 | - FEAT_GTG (Guest translation granule size) |
71943a1e | 44 | - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) |
3039b090 | 45 | - FEAT_HBC (Hinted conditional branches) |
95d0f1d8 | 46 | - FEAT_HCX (Support for the HCRX_EL2 register) |
741292fa | 47 | - FEAT_HPDS (Hierarchical permission disables) |
df9a3917 | 48 | - FEAT_HPDS2 (Translation table page-based hardware attributes) |
3d80bbf1 | 49 | - FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero) |
741292fa | 50 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) |
75662f36 | 51 | - FEAT_IDST (ID space trap handling) |
880cd10e | 52 | - FEAT_IESB (Implicit error synchronization event) |
741292fa PM |
53 | - FEAT_JSCVT (JavaScript conversion instructions) |
54 | - FEAT_LOR (Limited ordering regions) | |
7a928f43 | 55 | - FEAT_LPA (Large Physical Address space) |
ef56c242 | 56 | - FEAT_LPA2 (Large Physical and virtual Address space v2) |
741292fa PM |
57 | - FEAT_LRCPC (Load-acquire RCpc instructions) |
58 | - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) | |
59 | - FEAT_LSE (Large System Extensions) | |
59b6b42c | 60 | - FEAT_LSE2 (Large System Extensions v2) |
0af312b6 | 61 | - FEAT_LVA (Large Virtual Address space) |
706a92fb | 62 | - FEAT_MOPS (Standardization of memory operations) |
741292fa PM |
63 | - FEAT_MTE (Memory Tagging Extension) |
64 | - FEAT_MTE2 (Memory Tagging Extension) | |
86f0d4c7 | 65 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) |
1274a47f | 66 | - FEAT_NV (Nested Virtualization) |
399e5e71 RH |
67 | - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) |
68 | - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) | |
69 | - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) | |
741292fa PM |
70 | - FEAT_PAN (Privileged access never) |
71 | - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) | |
dd17143f | 72 | - FEAT_PAN3 (Support for SCTLR_ELx.EPAN) |
741292fa | 73 | - FEAT_PAuth (Pointer authentication) |
eb12e929 | 74 | - FEAT_PAuth2 (Enhancements to pointer authentication) |
741292fa PM |
75 | - FEAT_PMULL (PMULL, PMULL2 instructions) |
76 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | |
77 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | |
e31e0f56 | 78 | - FEAT_PMUv3p5 (PMU Extensions v3.5) |
e95c74c5 | 79 | - FEAT_RAS (Reliability, availability, and serviceability) |
d507bc3b | 80 | - FEAT_RASv1p1 (RAS Extension v1.1) |
741292fa | 81 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) |
57223a4c | 82 | - FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental) |
741292fa | 83 | - FEAT_RNG (Random number generator) |
e04bf5a7 | 84 | - FEAT_S2FWB (Stage 2 forced Write-Back) |
741292fa PM |
85 | - FEAT_SB (Speculation Barrier) |
86 | - FEAT_SEL2 (Secure EL2) | |
87 | - FEAT_SHA1 (SHA1 instructions) | |
88 | - FEAT_SHA256 (SHA256 instructions) | |
89 | - FEAT_SHA3 (Advanced SIMD SHA3 instructions) | |
90 | - FEAT_SHA512 (Advanced SIMD SHA512 instructions) | |
91 | - FEAT_SM3 (Advanced SIMD SM3 instructions) | |
92 | - FEAT_SM4 (Advanced SIMD SM4 instructions) | |
78cb9776 RH |
93 | - FEAT_SME (Scalable Matrix Extension) |
94 | - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) | |
95 | - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) | |
96 | - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) | |
741292fa PM |
97 | - FEAT_SPECRES (Speculation restriction instructions) |
98 | - FEAT_SSBS (Speculative Store Bypass Safe) | |
9cd0c0de | 99 | - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) |
741292fa PM |
100 | - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) |
101 | - FEAT_TLBIRANGE (TLB invalidate range instructions) | |
102 | - FEAT_TTCNP (Translation table Common not private translations) | |
f81c60c2 | 103 | - FEAT_TTL (Translation Table Level) |
741292fa PM |
104 | - FEAT_TTST (Small translation tables) |
105 | - FEAT_UAO (Unprivileged Access Override control) | |
106 | - FEAT_VHE (Virtualization Host Extensions) | |
107 | - FEAT_VMID16 (16-bit VMID) | |
108 | - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) | |
109 | - SVE (The Scalable Vector Extension) | |
110 | - SVE2 (The Scalable Vector Extension v2) | |
111 | ||
112 | For information on the specifics of these extensions, please refer | |
113 | to the `Armv8-A Arm Architecture Reference Manual | |
114 | <https://developer.arm.com/documentation/ddi0487/latest>`_. | |
115 | ||
116 | When a specific named CPU is being emulated, only those features which | |
117 | are present in hardware for that CPU are emulated. (If a feature is | |
118 | not in the list above then it is not supported, even if the real | |
119 | hardware should have it.) The ``max`` CPU enables all features. | |
120 | ||
121 | R-profile CPU architecture support | |
122 | ================================== | |
123 | ||
124 | QEMU's TCG emulation support for R-profile CPUs is currently limited. | |
125 | We emulate only the Cortex-R5 and Cortex-R5F CPUs. | |
126 | ||
127 | M-profile CPU architecture support | |
128 | ================================== | |
129 | ||
130 | QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and | |
131 | Armv8.1-M versions of the M-profile architucture. It also has support | |
132 | for the following architecture extensions: | |
133 | ||
134 | - FP (Floating-point Extension) | |
135 | - FPCXT (FPCXT access instructions) | |
136 | - HP (Half-precision floating-point instructions) | |
137 | - LOB (Low Overhead loops and Branch future) | |
138 | - M (Main Extension) | |
139 | - MPU (Memory Protection Unit Extension) | |
140 | - PXN (Privileged Execute Never) | |
141 | - RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only | |
142 | - S (Security Extension) | |
143 | - ST (System Timer Extension) | |
144 | ||
145 | For information on the specifics of these extensions, please refer | |
146 | to the `Armv8-M Arm Architecture Reference Manual | |
147 | <https://developer.arm.com/documentation/ddi0553/latest>`_. | |
148 | ||
149 | When a specific named CPU is being emulated, only those features which | |
150 | are present in hardware for that CPU are emulated. (If a feature is | |
151 | not in the list above then it is not supported, even if the real | |
152 | hardware should have it.) There is no equivalent of the ``max`` CPU for | |
153 | M-profile. |