]>
Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
80a7581f | 21 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 22 | #include <linux/pm_domain.h> |
2e0f8822 | 23 | #include <linux/pm_runtime.h> |
bf7696a1 | 24 | #include <linux/pwm.h> |
c78b0830 | 25 | #include <linux/delay.h> |
f58b082a RW |
26 | |
27 | #include "internal.h" | |
28 | ||
29 | ACPI_MODULE_NAME("acpi_lpss"); | |
30 | ||
d6ddaaac RW |
31 | #ifdef CONFIG_X86_INTEL_LPSS |
32 | ||
eebb3e8d | 33 | #include <asm/cpu_device_id.h> |
4626d840 | 34 | #include <asm/intel-family.h> |
eebb3e8d | 35 | #include <asm/iosf_mbi.h> |
eebb3e8d | 36 | |
d6ddaaac RW |
37 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
38 | ||
f58b082a | 39 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
40 | #define LPSS_LTR_SIZE 0x18 |
41 | ||
42 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 43 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
44 | #define LPSS_RESETS 0x04 |
45 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
46 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
47 | #define LPSS_GENERAL 0x08 |
48 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 49 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
50 | #define LPSS_SW_LTR 0x10 |
51 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
52 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
53 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
54 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
55 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
56 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
57 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
58 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
59 | #define LPSS_TX_INT 0x20 |
60 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 61 | |
c78b0830 HK |
62 | #define LPSS_PRV_REG_COUNT 9 |
63 | ||
ff8c1af5 HK |
64 | /* LPSS Flags */ |
65 | #define LPSS_CLK BIT(0) | |
66 | #define LPSS_CLK_GATE BIT(1) | |
67 | #define LPSS_CLK_DIVIDER BIT(2) | |
68 | #define LPSS_LTR BIT(3) | |
69 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 70 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 71 | |
06d86415 | 72 | struct lpss_private_data; |
f58b082a RW |
73 | |
74 | struct lpss_device_desc { | |
ff8c1af5 | 75 | unsigned int flags; |
fcf0789a | 76 | const char *clk_con_id; |
2e0f8822 | 77 | unsigned int prv_offset; |
958c4eb2 | 78 | size_t prv_size_override; |
a5565cf2 | 79 | struct property_entry *properties; |
06d86415 | 80 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
81 | }; |
82 | ||
eebb3e8d | 83 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 84 | .flags = LPSS_CLK, |
b59cc200 RW |
85 | }; |
86 | ||
f58b082a | 87 | struct lpss_private_data { |
dd242a08 | 88 | struct acpi_device *adev; |
f58b082a RW |
89 | void __iomem *mmio_base; |
90 | resource_size_t mmio_size; | |
03f09f73 | 91 | unsigned int fixed_clk_rate; |
f58b082a RW |
92 | struct clk *clk; |
93 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 94 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
95 | }; |
96 | ||
eebb3e8d AS |
97 | /* LPSS run time quirks */ |
98 | static unsigned int lpss_quirks; | |
99 | ||
100 | /* | |
101 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
102 | * | |
fa9e93b1 | 103 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
104 | * it can be powered off automatically whenever the last LPSS device goes down. |
105 | * In case of no power any access to the DMA controller will hang the system. | |
106 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
107 | * well as on ASuS T100TA transformer. | |
108 | * | |
109 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
110 | * on whenever we have at least one other device in use. | |
111 | */ | |
112 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
113 | ||
1f47a77c HK |
114 | /* UART Component Parameter Register */ |
115 | #define LPSS_UART_CPR 0xF4 | |
116 | #define LPSS_UART_CPR_AFCE BIT(4) | |
117 | ||
06d86415 HK |
118 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
119 | { | |
088f1fd2 | 120 | unsigned int offset; |
1f47a77c | 121 | u32 val; |
06d86415 | 122 | |
088f1fd2 | 123 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
124 | val = readl(pdata->mmio_base + offset); |
125 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
126 | ||
127 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
128 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
129 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
130 | val = readl(pdata->mmio_base + offset); | |
131 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
132 | writel(val, pdata->mmio_base + offset); | |
133 | } | |
06d86415 HK |
134 | } |
135 | ||
3095794a | 136 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
137 | { |
138 | unsigned int offset; | |
139 | u32 val; | |
140 | ||
141 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
142 | val = readl(pdata->mmio_base + offset); | |
143 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
144 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
145 | } |
146 | ||
04434ab5 HG |
147 | /* |
148 | * BYT PWM used for backlight control by the i915 driver on systems without | |
149 | * the Crystal Cove PMIC. | |
150 | */ | |
151 | static struct pwm_lookup byt_pwm_lookup[] = { | |
152 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
153 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
154 | "pwm-lpss-platform"), | |
155 | }; | |
156 | ||
157 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
158 | { | |
dd242a08 HG |
159 | struct acpi_device *adev = pdata->adev; |
160 | ||
161 | /* Only call pwm_add_table for the first PWM controller */ | |
162 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
163 | return; | |
164 | ||
04434ab5 HG |
165 | if (!acpi_dev_present("INT33FD", NULL, -1)) |
166 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); | |
167 | } | |
168 | ||
3095794a MW |
169 | #define LPSS_I2C_ENABLE 0x6c |
170 | ||
171 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
172 | { | |
173 | lpss_deassert_reset(pdata); | |
765bdd4e | 174 | |
03f09f73 HK |
175 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
176 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
177 | |
178 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 179 | } |
43218a1b | 180 | |
bf7696a1 HG |
181 | /* BSW PWM used for backlight control by the i915 driver */ |
182 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
183 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
184 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
185 | "pwm-lpss-platform"), | |
186 | }; | |
187 | ||
188 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
189 | { | |
dd242a08 HG |
190 | struct acpi_device *adev = pdata->adev; |
191 | ||
192 | /* Only call pwm_add_table for the first PWM controller */ | |
193 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
194 | return; | |
195 | ||
bf7696a1 HG |
196 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
197 | } | |
198 | ||
b2687cd7 | 199 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 200 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 201 | .prv_offset = 0x800, |
ed3a872e HK |
202 | }; |
203 | ||
b2687cd7 | 204 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 205 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 206 | .prv_offset = 0x800, |
2e0f8822 RW |
207 | }; |
208 | ||
a5565cf2 HK |
209 | static struct property_entry uart_properties[] = { |
210 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
211 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
212 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
213 | { }, | |
214 | }; | |
215 | ||
b2687cd7 | 216 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 217 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 218 | .clk_con_id = "baudclk", |
06d86415 | 219 | .prv_offset = 0x800, |
06d86415 | 220 | .setup = lpss_uart_setup, |
a5565cf2 | 221 | .properties = uart_properties, |
2e0f8822 RW |
222 | }; |
223 | ||
b2687cd7 | 224 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 225 | .flags = LPSS_LTR, |
2e0f8822 | 226 | .prv_offset = 0x1000, |
958c4eb2 | 227 | .prv_size_override = 0x1018, |
e1c74817 CCE |
228 | }; |
229 | ||
b2687cd7 | 230 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 231 | .flags = LPSS_SAVE_CTX, |
04434ab5 | 232 | .setup = byt_pwm_setup, |
e1c74817 CCE |
233 | }; |
234 | ||
b00855ae SK |
235 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
236 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
bf7696a1 | 237 | .setup = bsw_pwm_setup, |
b00855ae SK |
238 | }; |
239 | ||
b2687cd7 | 240 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 241 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 242 | .clk_con_id = "baudclk", |
f6272170 | 243 | .prv_offset = 0x800, |
06d86415 | 244 | .setup = lpss_uart_setup, |
a5565cf2 | 245 | .properties = uart_properties, |
f6272170 MW |
246 | }; |
247 | ||
b00855ae SK |
248 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
249 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
250 | | LPSS_NO_D3_DELAY, | |
251 | .clk_con_id = "baudclk", | |
252 | .prv_offset = 0x800, | |
253 | .setup = lpss_uart_setup, | |
a5565cf2 | 254 | .properties = uart_properties, |
b00855ae SK |
255 | }; |
256 | ||
b2687cd7 | 257 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 258 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 259 | .prv_offset = 0x400, |
f6272170 MW |
260 | }; |
261 | ||
b2687cd7 | 262 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 263 | .flags = LPSS_CLK, |
f6272170 MW |
264 | }; |
265 | ||
b2687cd7 | 266 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 267 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 268 | .prv_offset = 0x800, |
03f09f73 | 269 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
270 | }; |
271 | ||
b00855ae SK |
272 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
273 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
274 | .prv_offset = 0x800, | |
275 | .setup = byt_i2c_setup, | |
276 | }; | |
277 | ||
eebb3e8d | 278 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
279 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
280 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
281 | .prv_offset = 0x400, |
282 | .setup = lpss_deassert_reset, | |
283 | }; | |
284 | ||
eebb3e8d AS |
285 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
286 | ||
287 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
4626d840 DH |
288 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */ |
289 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ | |
eebb3e8d AS |
290 | {} |
291 | }; | |
292 | ||
d6ddaaac RW |
293 | #else |
294 | ||
295 | #define LPSS_ADDR(desc) (0UL) | |
296 | ||
297 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
298 | ||
f58b082a | 299 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 300 | /* Generic LPSS devices */ |
d6ddaaac | 301 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 302 | |
f58b082a | 303 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
304 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
305 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
306 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
307 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
308 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
309 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
310 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
311 | { "INT33C7", }, |
312 | ||
f6272170 | 313 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
314 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
315 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
316 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
317 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
318 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 319 | { "INT33B2", }, |
20482d32 | 320 | { "INT33FC", }, |
f6272170 | 321 | |
1bfbd8eb | 322 | /* Braswell LPSS devices */ |
b00855ae SK |
323 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
324 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 325 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 326 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 327 | |
b00855ae | 328 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
329 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
330 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
331 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
332 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
333 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
334 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
335 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
336 | { "INT3437", }, |
337 | ||
ff8c1af5 HK |
338 | /* Wildcat Point LPSS devices */ |
339 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 340 | |
f58b082a RW |
341 | { } |
342 | }; | |
343 | ||
d6ddaaac RW |
344 | #ifdef CONFIG_X86_INTEL_LPSS |
345 | ||
f58b082a RW |
346 | static int is_memory(struct acpi_resource *res, void *not_used) |
347 | { | |
348 | struct resource r; | |
349 | return !acpi_dev_resource_memory(res, &r); | |
350 | } | |
351 | ||
352 | /* LPSS main clock device. */ | |
353 | static struct platform_device *lpss_clk_dev; | |
354 | ||
355 | static inline void lpt_register_clock_device(void) | |
356 | { | |
357 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
358 | } | |
359 | ||
360 | static int register_device_clock(struct acpi_device *adev, | |
361 | struct lpss_private_data *pdata) | |
362 | { | |
363 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 364 | const char *devname = dev_name(&adev->dev); |
f6272170 | 365 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 366 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
367 | const char *parent, *clk_name; |
368 | void __iomem *prv_base; | |
f58b082a RW |
369 | |
370 | if (!lpss_clk_dev) | |
371 | lpt_register_clock_device(); | |
372 | ||
b59cc200 RW |
373 | clk_data = platform_get_drvdata(lpss_clk_dev); |
374 | if (!clk_data) | |
375 | return -ENODEV; | |
b0d00f8b | 376 | clk = clk_data->clk; |
b59cc200 RW |
377 | |
378 | if (!pdata->mmio_base | |
2e0f8822 | 379 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
380 | return -ENODATA; |
381 | ||
f6272170 | 382 | parent = clk_data->name; |
ed3a872e | 383 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 384 | |
03f09f73 HK |
385 | if (pdata->fixed_clk_rate) { |
386 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
387 | pdata->fixed_clk_rate); | |
388 | goto out; | |
f6272170 MW |
389 | } |
390 | ||
ff8c1af5 | 391 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
392 | clk = clk_register_gate(NULL, devname, parent, 0, |
393 | prv_base, 0, 0, NULL); | |
394 | parent = devname; | |
395 | } | |
396 | ||
ff8c1af5 | 397 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
398 | /* Prevent division by zero */ |
399 | if (!readl(prv_base)) | |
400 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
401 | ||
402 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
403 | if (!clk_name) | |
404 | return -ENOMEM; | |
405 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
406 | 0, prv_base, | |
407 | 1, 15, 16, 15, 0, NULL); | |
408 | parent = clk_name; | |
409 | ||
410 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
411 | if (!clk_name) { | |
412 | kfree(parent); | |
413 | return -ENOMEM; | |
414 | } | |
415 | clk = clk_register_gate(NULL, clk_name, parent, | |
416 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
417 | prv_base, 31, 0, NULL); | |
418 | kfree(parent); | |
419 | kfree(clk_name); | |
f6272170 | 420 | } |
03f09f73 | 421 | out: |
f6272170 MW |
422 | if (IS_ERR(clk)) |
423 | return PTR_ERR(clk); | |
f58b082a | 424 | |
ed3a872e | 425 | pdata->clk = clk; |
fcf0789a | 426 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
427 | return 0; |
428 | } | |
429 | ||
430 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
431 | const struct acpi_device_id *id) | |
432 | { | |
b2687cd7 | 433 | const struct lpss_device_desc *dev_desc; |
f58b082a | 434 | struct lpss_private_data *pdata; |
90e97820 | 435 | struct resource_entry *rentry; |
f58b082a | 436 | struct list_head resource_list; |
8ce62f85 | 437 | struct platform_device *pdev; |
f58b082a RW |
438 | int ret; |
439 | ||
b2687cd7 | 440 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 441 | if (!dev_desc) { |
1571875b | 442 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
443 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
444 | } | |
f58b082a RW |
445 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
446 | if (!pdata) | |
447 | return -ENOMEM; | |
448 | ||
449 | INIT_LIST_HEAD(&resource_list); | |
450 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
451 | if (ret < 0) | |
452 | goto err_out; | |
453 | ||
454 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 455 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
456 | if (dev_desc->prv_size_override) |
457 | pdata->mmio_size = dev_desc->prv_size_override; | |
458 | else | |
90e97820 JL |
459 | pdata->mmio_size = resource_size(rentry->res); |
460 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 461 | pdata->mmio_size); |
f58b082a RW |
462 | break; |
463 | } | |
464 | ||
465 | acpi_dev_free_resource_list(&resource_list); | |
466 | ||
d3e13ff3 RW |
467 | if (!pdata->mmio_base) { |
468 | ret = -ENOMEM; | |
469 | goto err_out; | |
470 | } | |
471 | ||
dd242a08 | 472 | pdata->adev = adev; |
af65cfe9 MW |
473 | pdata->dev_desc = dev_desc; |
474 | ||
03f09f73 HK |
475 | if (dev_desc->setup) |
476 | dev_desc->setup(pdata); | |
477 | ||
ff8c1af5 | 478 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
479 | ret = register_device_clock(adev, pdata); |
480 | if (ret) { | |
b9e95fc6 RW |
481 | /* Skip the device, but continue the namespace scan. */ |
482 | ret = 0; | |
483 | goto err_out; | |
f58b082a RW |
484 | } |
485 | } | |
486 | ||
b9e95fc6 RW |
487 | /* |
488 | * This works around a known issue in ACPI tables where LPSS devices | |
489 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
490 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
491 | */ | |
492 | ret = acpi_device_fix_up_power(adev); | |
493 | if (ret) { | |
494 | /* Skip the device, but continue the namespace scan. */ | |
495 | ret = 0; | |
496 | goto err_out; | |
497 | } | |
498 | ||
f58b082a | 499 | adev->driver_data = pdata; |
1571875b | 500 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 501 | if (!IS_ERR_OR_NULL(pdev)) { |
8ce62f85 RW |
502 | return 1; |
503 | } | |
f58b082a | 504 | |
8ce62f85 | 505 | ret = PTR_ERR(pdev); |
f58b082a RW |
506 | adev->driver_data = NULL; |
507 | ||
508 | err_out: | |
509 | kfree(pdata); | |
510 | return ret; | |
511 | } | |
512 | ||
1a8f8351 RW |
513 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
514 | { | |
515 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
516 | } | |
517 | ||
518 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
519 | unsigned int reg) | |
520 | { | |
521 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
522 | } | |
523 | ||
2e0f8822 RW |
524 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
525 | { | |
526 | struct acpi_device *adev; | |
527 | struct lpss_private_data *pdata; | |
528 | unsigned long flags; | |
529 | int ret; | |
530 | ||
531 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
532 | if (WARN_ON(ret)) | |
533 | return ret; | |
534 | ||
535 | spin_lock_irqsave(&dev->power.lock, flags); | |
536 | if (pm_runtime_suspended(dev)) { | |
537 | ret = -EAGAIN; | |
538 | goto out; | |
539 | } | |
540 | pdata = acpi_driver_data(adev); | |
541 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
542 | ret = -ENODEV; | |
543 | goto out; | |
544 | } | |
1a8f8351 | 545 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
546 | |
547 | out: | |
548 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
549 | return ret; | |
550 | } | |
551 | ||
552 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
553 | char *buf) | |
554 | { | |
555 | u32 ltr_value = 0; | |
556 | unsigned int reg; | |
557 | int ret; | |
558 | ||
559 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
560 | ret = lpss_reg_read(dev, reg, <r_value); | |
561 | if (ret) | |
562 | return ret; | |
563 | ||
564 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
565 | } | |
566 | ||
567 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
568 | struct device_attribute *attr, char *buf) | |
569 | { | |
570 | u32 ltr_mode = 0; | |
571 | char *outstr; | |
572 | int ret; | |
573 | ||
574 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
575 | if (ret) | |
576 | return ret; | |
577 | ||
578 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
579 | return sprintf(buf, "%s\n", outstr); | |
580 | } | |
581 | ||
582 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
583 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
584 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
585 | ||
586 | static struct attribute *lpss_attrs[] = { | |
587 | &dev_attr_auto_ltr.attr, | |
588 | &dev_attr_sw_ltr.attr, | |
589 | &dev_attr_ltr_mode.attr, | |
590 | NULL, | |
591 | }; | |
592 | ||
31945d0e | 593 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
594 | .attrs = lpss_attrs, |
595 | .name = "lpss_ltr", | |
596 | }; | |
597 | ||
1a8f8351 RW |
598 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
599 | { | |
600 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
601 | u32 ltr_mode, ltr_val; | |
602 | ||
603 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
604 | if (val < 0) { | |
605 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
606 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
607 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
608 | } | |
609 | return; | |
610 | } | |
611 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
612 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
613 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
614 | val = LPSS_LTR_MAX_VAL; | |
615 | } else if (val > LPSS_LTR_MAX_VAL) { | |
616 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
617 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
618 | } else { | |
619 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
620 | } | |
621 | ltr_val |= val; | |
622 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
623 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
624 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
625 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
626 | } | |
627 | } | |
628 | ||
c78b0830 HK |
629 | #ifdef CONFIG_PM |
630 | /** | |
631 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
632 | * @dev: LPSS device | |
cb39dcdd | 633 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
634 | * |
635 | * Most LPSS devices have private registers which may loose their context when | |
636 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
637 | * prv_reg_ctx array. | |
638 | */ | |
cb39dcdd AS |
639 | static void acpi_lpss_save_ctx(struct device *dev, |
640 | struct lpss_private_data *pdata) | |
c78b0830 | 641 | { |
c78b0830 HK |
642 | unsigned int i; |
643 | ||
644 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
645 | unsigned long offset = i * sizeof(u32); | |
646 | ||
647 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
648 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
649 | pdata->prv_reg_ctx[i], offset); | |
650 | } | |
651 | } | |
652 | ||
653 | /** | |
654 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
655 | * @dev: LPSS device | |
cb39dcdd | 656 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
657 | * |
658 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
659 | */ | |
cb39dcdd AS |
660 | static void acpi_lpss_restore_ctx(struct device *dev, |
661 | struct lpss_private_data *pdata) | |
c78b0830 | 662 | { |
c78b0830 HK |
663 | unsigned int i; |
664 | ||
02b98540 AS |
665 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
666 | unsigned long offset = i * sizeof(u32); | |
667 | ||
668 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
669 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
670 | pdata->prv_reg_ctx[i], offset); | |
671 | } | |
672 | } | |
673 | ||
674 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
675 | { | |
c78b0830 HK |
676 | /* |
677 | * The following delay is needed or the subsequent write operations may | |
678 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
679 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 680 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 681 | */ |
b00855ae SK |
682 | unsigned int delay = 10; /* default 10ms delay */ |
683 | ||
684 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
685 | delay = 0; | |
686 | ||
687 | msleep(delay); | |
c78b0830 HK |
688 | } |
689 | ||
c3a49cf3 AS |
690 | static int acpi_lpss_activate(struct device *dev) |
691 | { | |
692 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
693 | int ret; | |
694 | ||
695 | ret = acpi_dev_runtime_resume(dev); | |
696 | if (ret) | |
697 | return ret; | |
698 | ||
699 | acpi_lpss_d3_to_d0_delay(pdata); | |
700 | ||
701 | /* | |
702 | * This is called only on ->probe() stage where a device is either in | |
703 | * known state defined by BIOS or most likely powered off. Due to this | |
704 | * we have to deassert reset line to be sure that ->probe() will | |
705 | * recognize the device. | |
706 | */ | |
707 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
708 | lpss_deassert_reset(pdata); | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static void acpi_lpss_dismiss(struct device *dev) | |
714 | { | |
715 | acpi_dev_runtime_suspend(dev); | |
716 | } | |
717 | ||
c78b0830 HK |
718 | #ifdef CONFIG_PM_SLEEP |
719 | static int acpi_lpss_suspend_late(struct device *dev) | |
720 | { | |
cb39dcdd AS |
721 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
722 | int ret; | |
c78b0830 | 723 | |
cb39dcdd | 724 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
725 | if (ret) |
726 | return ret; | |
727 | ||
cb39dcdd AS |
728 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
729 | acpi_lpss_save_ctx(dev, pdata); | |
730 | ||
c78b0830 HK |
731 | return acpi_dev_suspend_late(dev); |
732 | } | |
733 | ||
f4168b61 | 734 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 735 | { |
cb39dcdd AS |
736 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
737 | int ret; | |
c78b0830 | 738 | |
cb39dcdd | 739 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
740 | if (ret) |
741 | return ret; | |
742 | ||
02b98540 AS |
743 | acpi_lpss_d3_to_d0_delay(pdata); |
744 | ||
cb39dcdd AS |
745 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
746 | acpi_lpss_restore_ctx(dev, pdata); | |
747 | ||
c78b0830 HK |
748 | return pm_generic_resume_early(dev); |
749 | } | |
750 | #endif /* CONFIG_PM_SLEEP */ | |
751 | ||
eebb3e8d AS |
752 | /* IOSF SB for LPSS island */ |
753 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
754 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
755 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
756 | ||
757 | #define LPSS_IOSF_PMCSR 0x84 | |
758 | #define LPSS_PMCSR_D0 0 | |
759 | #define LPSS_PMCSR_D3hot 3 | |
760 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
761 | ||
762 | #define LPSS_IOSF_GPIODEF0 0x154 | |
763 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
764 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
765 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 766 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
767 | |
768 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
769 | ||
770 | static void lpss_iosf_enter_d3_state(void) | |
771 | { | |
772 | u32 value1 = 0; | |
d132d6d5 | 773 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
774 | u32 value2 = LPSS_PMCSR_D3hot; |
775 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
776 | /* | |
777 | * PMC provides an information about actual status of the LPSS devices. | |
778 | * Here we read the values related to LPSS power island, i.e. LPSS | |
779 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
780 | */ | |
781 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
782 | int ret; | |
783 | ||
784 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
785 | if (ret) | |
786 | return; | |
787 | ||
788 | mutex_lock(&lpss_iosf_mutex); | |
789 | ||
790 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
791 | if (ret) | |
792 | goto exit; | |
793 | ||
794 | /* | |
795 | * Get the status of entire LPSS power island per device basis. | |
796 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
797 | * are already in D3hot. | |
798 | */ | |
799 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
800 | if (pmc_status) | |
801 | goto exit; | |
802 | ||
803 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
804 | LPSS_IOSF_PMCSR, value2, mask2); | |
805 | ||
806 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
807 | LPSS_IOSF_PMCSR, value2, mask2); | |
808 | ||
809 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
810 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
811 | exit: | |
812 | mutex_unlock(&lpss_iosf_mutex); | |
813 | } | |
814 | ||
815 | static void lpss_iosf_exit_d3_state(void) | |
816 | { | |
d132d6d5 AS |
817 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
818 | LPSS_GPIODEF0_DMA_LLP; | |
819 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
820 | u32 value2 = LPSS_PMCSR_D0; |
821 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
822 | ||
823 | mutex_lock(&lpss_iosf_mutex); | |
824 | ||
825 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
826 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
827 | ||
828 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
829 | LPSS_IOSF_PMCSR, value2, mask2); | |
830 | ||
831 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
832 | LPSS_IOSF_PMCSR, value2, mask2); | |
833 | ||
834 | mutex_unlock(&lpss_iosf_mutex); | |
835 | } | |
836 | ||
c78b0830 HK |
837 | static int acpi_lpss_runtime_suspend(struct device *dev) |
838 | { | |
cb39dcdd AS |
839 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
840 | int ret; | |
c78b0830 | 841 | |
cb39dcdd | 842 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
843 | if (ret) |
844 | return ret; | |
845 | ||
cb39dcdd AS |
846 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
847 | acpi_lpss_save_ctx(dev, pdata); | |
848 | ||
eebb3e8d AS |
849 | ret = acpi_dev_runtime_suspend(dev); |
850 | ||
851 | /* | |
852 | * This call must be last in the sequence, otherwise PMC will return | |
853 | * wrong status for devices being about to be powered off. See | |
854 | * lpss_iosf_enter_d3_state() for further information. | |
855 | */ | |
856 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
857 | lpss_iosf_enter_d3_state(); | |
858 | ||
859 | return ret; | |
c78b0830 HK |
860 | } |
861 | ||
862 | static int acpi_lpss_runtime_resume(struct device *dev) | |
863 | { | |
cb39dcdd AS |
864 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
865 | int ret; | |
c78b0830 | 866 | |
eebb3e8d AS |
867 | /* |
868 | * This call is kept first to be in symmetry with | |
869 | * acpi_lpss_runtime_suspend() one. | |
870 | */ | |
871 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
872 | lpss_iosf_exit_d3_state(); | |
873 | ||
cb39dcdd | 874 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
875 | if (ret) |
876 | return ret; | |
877 | ||
02b98540 AS |
878 | acpi_lpss_d3_to_d0_delay(pdata); |
879 | ||
cb39dcdd AS |
880 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
881 | acpi_lpss_restore_ctx(dev, pdata); | |
882 | ||
c78b0830 HK |
883 | return pm_generic_runtime_resume(dev); |
884 | } | |
c78b0830 HK |
885 | #endif /* CONFIG_PM */ |
886 | ||
887 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
888 | #ifdef CONFIG_PM |
889 | .activate = acpi_lpss_activate, | |
890 | .dismiss = acpi_lpss_dismiss, | |
891 | #endif | |
c78b0830 | 892 | .ops = { |
5de21bb9 | 893 | #ifdef CONFIG_PM |
c78b0830 | 894 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 895 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 896 | .complete = pm_complete_with_resume_check, |
c78b0830 | 897 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
898 | .suspend_late = acpi_lpss_suspend_late, |
899 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
900 | .freeze = acpi_subsys_freeze, |
901 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
902 | .poweroff_late = acpi_lpss_suspend_late, |
903 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 904 | #endif |
c78b0830 HK |
905 | .runtime_suspend = acpi_lpss_runtime_suspend, |
906 | .runtime_resume = acpi_lpss_runtime_resume, | |
907 | #endif | |
908 | }, | |
909 | }; | |
910 | ||
2e0f8822 RW |
911 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
912 | unsigned long action, void *data) | |
913 | { | |
914 | struct platform_device *pdev = to_platform_device(data); | |
915 | struct lpss_private_data *pdata; | |
916 | struct acpi_device *adev; | |
917 | const struct acpi_device_id *id; | |
2e0f8822 RW |
918 | |
919 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
920 | if (!id || !id->driver_data) | |
921 | return 0; | |
922 | ||
923 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
924 | return 0; | |
925 | ||
926 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 927 | if (!pdata) |
2e0f8822 RW |
928 | return 0; |
929 | ||
cb39dcdd AS |
930 | if (pdata->mmio_base && |
931 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
932 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
933 | return 0; | |
934 | } | |
935 | ||
c78b0830 | 936 | switch (action) { |
de16d552 | 937 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 938 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 939 | break; |
de16d552 | 940 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 941 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 942 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
943 | break; |
944 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 945 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 946 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
947 | return sysfs_create_group(&pdev->dev.kobj, |
948 | &lpss_attr_group); | |
01ac170b | 949 | break; |
c78b0830 | 950 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 951 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 952 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 953 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 954 | break; |
c78b0830 HK |
955 | default: |
956 | break; | |
957 | } | |
2e0f8822 | 958 | |
c78b0830 | 959 | return 0; |
2e0f8822 RW |
960 | } |
961 | ||
962 | static struct notifier_block acpi_lpss_nb = { | |
963 | .notifier_call = acpi_lpss_platform_notify, | |
964 | }; | |
965 | ||
1a8f8351 RW |
966 | static void acpi_lpss_bind(struct device *dev) |
967 | { | |
968 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
969 | ||
ff8c1af5 | 970 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
971 | return; |
972 | ||
973 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
974 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
975 | else | |
976 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
977 | } | |
978 | ||
979 | static void acpi_lpss_unbind(struct device *dev) | |
980 | { | |
981 | dev->power.set_latency_tolerance = NULL; | |
982 | } | |
983 | ||
f58b082a RW |
984 | static struct acpi_scan_handler lpss_handler = { |
985 | .ids = acpi_lpss_device_ids, | |
986 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
987 | .bind = acpi_lpss_bind, |
988 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
989 | }; |
990 | ||
991 | void __init acpi_lpss_init(void) | |
992 | { | |
eebb3e8d AS |
993 | const struct x86_cpu_id *id; |
994 | int ret; | |
995 | ||
996 | ret = lpt_clk_init(); | |
997 | if (ret) | |
998 | return; | |
999 | ||
1000 | id = x86_match_cpu(lpss_cpu_ids); | |
1001 | if (id) | |
1002 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1003 | ||
1004 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1005 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1006 | } |
d6ddaaac RW |
1007 | |
1008 | #else | |
1009 | ||
1010 | static struct acpi_scan_handler lpss_handler = { | |
1011 | .ids = acpi_lpss_device_ids, | |
1012 | }; | |
1013 | ||
1014 | void __init acpi_lpss_init(void) | |
1015 | { | |
1016 | acpi_scan_add_handler(&lpss_handler); | |
1017 | } | |
1018 | ||
1019 | #endif /* CONFIG_X86_INTEL_LPSS */ |