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Commit | Line | Data |
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f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
80a7581f | 21 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 22 | #include <linux/pm_domain.h> |
2e0f8822 | 23 | #include <linux/pm_runtime.h> |
c78b0830 | 24 | #include <linux/delay.h> |
f58b082a RW |
25 | |
26 | #include "internal.h" | |
27 | ||
28 | ACPI_MODULE_NAME("acpi_lpss"); | |
29 | ||
d6ddaaac RW |
30 | #ifdef CONFIG_X86_INTEL_LPSS |
31 | ||
eebb3e8d | 32 | #include <asm/cpu_device_id.h> |
4626d840 | 33 | #include <asm/intel-family.h> |
eebb3e8d | 34 | #include <asm/iosf_mbi.h> |
eebb3e8d | 35 | |
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 69 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 70 | |
06d86415 | 71 | struct lpss_private_data; |
f58b082a RW |
72 | |
73 | struct lpss_device_desc { | |
ff8c1af5 | 74 | unsigned int flags; |
fcf0789a | 75 | const char *clk_con_id; |
2e0f8822 | 76 | unsigned int prv_offset; |
958c4eb2 | 77 | size_t prv_size_override; |
a5565cf2 | 78 | struct property_entry *properties; |
06d86415 | 79 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
80 | }; |
81 | ||
eebb3e8d | 82 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 83 | .flags = LPSS_CLK, |
b59cc200 RW |
84 | }; |
85 | ||
f58b082a RW |
86 | struct lpss_private_data { |
87 | void __iomem *mmio_base; | |
88 | resource_size_t mmio_size; | |
03f09f73 | 89 | unsigned int fixed_clk_rate; |
f58b082a RW |
90 | struct clk *clk; |
91 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 92 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
93 | }; |
94 | ||
eebb3e8d AS |
95 | /* LPSS run time quirks */ |
96 | static unsigned int lpss_quirks; | |
97 | ||
98 | /* | |
99 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
100 | * | |
fa9e93b1 | 101 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
102 | * it can be powered off automatically whenever the last LPSS device goes down. |
103 | * In case of no power any access to the DMA controller will hang the system. | |
104 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
105 | * well as on ASuS T100TA transformer. | |
106 | * | |
107 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
108 | * on whenever we have at least one other device in use. | |
109 | */ | |
110 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
111 | ||
1f47a77c HK |
112 | /* UART Component Parameter Register */ |
113 | #define LPSS_UART_CPR 0xF4 | |
114 | #define LPSS_UART_CPR_AFCE BIT(4) | |
115 | ||
06d86415 HK |
116 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
117 | { | |
088f1fd2 | 118 | unsigned int offset; |
1f47a77c | 119 | u32 val; |
06d86415 | 120 | |
088f1fd2 | 121 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
122 | val = readl(pdata->mmio_base + offset); |
123 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
124 | ||
125 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
126 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
127 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
128 | val = readl(pdata->mmio_base + offset); | |
129 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
130 | writel(val, pdata->mmio_base + offset); | |
131 | } | |
06d86415 HK |
132 | } |
133 | ||
3095794a | 134 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
135 | { |
136 | unsigned int offset; | |
137 | u32 val; | |
138 | ||
139 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
140 | val = readl(pdata->mmio_base + offset); | |
141 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
142 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
143 | } |
144 | ||
145 | #define LPSS_I2C_ENABLE 0x6c | |
146 | ||
147 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
148 | { | |
149 | lpss_deassert_reset(pdata); | |
765bdd4e | 150 | |
03f09f73 HK |
151 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
152 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
153 | |
154 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 155 | } |
43218a1b | 156 | |
b2687cd7 | 157 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 158 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 159 | .prv_offset = 0x800, |
ed3a872e HK |
160 | }; |
161 | ||
b2687cd7 | 162 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 163 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 164 | .prv_offset = 0x800, |
2e0f8822 RW |
165 | }; |
166 | ||
a5565cf2 HK |
167 | static struct property_entry uart_properties[] = { |
168 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
169 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
170 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
171 | { }, | |
172 | }; | |
173 | ||
b2687cd7 | 174 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 175 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 176 | .clk_con_id = "baudclk", |
06d86415 | 177 | .prv_offset = 0x800, |
06d86415 | 178 | .setup = lpss_uart_setup, |
a5565cf2 | 179 | .properties = uart_properties, |
2e0f8822 RW |
180 | }; |
181 | ||
b2687cd7 | 182 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 183 | .flags = LPSS_LTR, |
2e0f8822 | 184 | .prv_offset = 0x1000, |
958c4eb2 | 185 | .prv_size_override = 0x1018, |
e1c74817 CCE |
186 | }; |
187 | ||
b2687cd7 | 188 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 189 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
190 | }; |
191 | ||
b00855ae SK |
192 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
193 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
194 | }; | |
195 | ||
b2687cd7 | 196 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 197 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 198 | .clk_con_id = "baudclk", |
f6272170 | 199 | .prv_offset = 0x800, |
06d86415 | 200 | .setup = lpss_uart_setup, |
a5565cf2 | 201 | .properties = uart_properties, |
f6272170 MW |
202 | }; |
203 | ||
b00855ae SK |
204 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
205 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
206 | | LPSS_NO_D3_DELAY, | |
207 | .clk_con_id = "baudclk", | |
208 | .prv_offset = 0x800, | |
209 | .setup = lpss_uart_setup, | |
a5565cf2 | 210 | .properties = uart_properties, |
b00855ae SK |
211 | }; |
212 | ||
b2687cd7 | 213 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 214 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 215 | .prv_offset = 0x400, |
f6272170 MW |
216 | }; |
217 | ||
b2687cd7 | 218 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 219 | .flags = LPSS_CLK, |
f6272170 MW |
220 | }; |
221 | ||
b2687cd7 | 222 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 223 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 224 | .prv_offset = 0x800, |
03f09f73 | 225 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
226 | }; |
227 | ||
b00855ae SK |
228 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
229 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
230 | .prv_offset = 0x800, | |
231 | .setup = byt_i2c_setup, | |
232 | }; | |
233 | ||
eebb3e8d | 234 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
235 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
236 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
237 | .prv_offset = 0x400, |
238 | .setup = lpss_deassert_reset, | |
239 | }; | |
240 | ||
eebb3e8d AS |
241 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
242 | ||
243 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
4626d840 DH |
244 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */ |
245 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ | |
eebb3e8d AS |
246 | {} |
247 | }; | |
248 | ||
d6ddaaac RW |
249 | #else |
250 | ||
251 | #define LPSS_ADDR(desc) (0UL) | |
252 | ||
253 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
254 | ||
f58b082a | 255 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 256 | /* Generic LPSS devices */ |
d6ddaaac | 257 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 258 | |
f58b082a | 259 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
260 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
261 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
262 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
263 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
264 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
265 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
266 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
267 | { "INT33C7", }, |
268 | ||
f6272170 | 269 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
270 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
271 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
272 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
273 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
274 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 275 | { "INT33B2", }, |
20482d32 | 276 | { "INT33FC", }, |
f6272170 | 277 | |
1bfbd8eb | 278 | /* Braswell LPSS devices */ |
b00855ae SK |
279 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
280 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 281 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 282 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 283 | |
b00855ae | 284 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
285 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
286 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
287 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
288 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
289 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
290 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
291 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
292 | { "INT3437", }, |
293 | ||
ff8c1af5 HK |
294 | /* Wildcat Point LPSS devices */ |
295 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 296 | |
f58b082a RW |
297 | { } |
298 | }; | |
299 | ||
d6ddaaac RW |
300 | #ifdef CONFIG_X86_INTEL_LPSS |
301 | ||
f58b082a RW |
302 | static int is_memory(struct acpi_resource *res, void *not_used) |
303 | { | |
304 | struct resource r; | |
305 | return !acpi_dev_resource_memory(res, &r); | |
306 | } | |
307 | ||
308 | /* LPSS main clock device. */ | |
309 | static struct platform_device *lpss_clk_dev; | |
310 | ||
311 | static inline void lpt_register_clock_device(void) | |
312 | { | |
313 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
314 | } | |
315 | ||
316 | static int register_device_clock(struct acpi_device *adev, | |
317 | struct lpss_private_data *pdata) | |
318 | { | |
319 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 320 | const char *devname = dev_name(&adev->dev); |
f6272170 | 321 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 322 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
323 | const char *parent, *clk_name; |
324 | void __iomem *prv_base; | |
f58b082a RW |
325 | |
326 | if (!lpss_clk_dev) | |
327 | lpt_register_clock_device(); | |
328 | ||
b59cc200 RW |
329 | clk_data = platform_get_drvdata(lpss_clk_dev); |
330 | if (!clk_data) | |
331 | return -ENODEV; | |
b0d00f8b | 332 | clk = clk_data->clk; |
b59cc200 RW |
333 | |
334 | if (!pdata->mmio_base | |
2e0f8822 | 335 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
336 | return -ENODATA; |
337 | ||
f6272170 | 338 | parent = clk_data->name; |
ed3a872e | 339 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 340 | |
03f09f73 HK |
341 | if (pdata->fixed_clk_rate) { |
342 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
343 | pdata->fixed_clk_rate); | |
344 | goto out; | |
f6272170 MW |
345 | } |
346 | ||
ff8c1af5 | 347 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
348 | clk = clk_register_gate(NULL, devname, parent, 0, |
349 | prv_base, 0, 0, NULL); | |
350 | parent = devname; | |
351 | } | |
352 | ||
ff8c1af5 | 353 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
354 | /* Prevent division by zero */ |
355 | if (!readl(prv_base)) | |
356 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
357 | ||
358 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
359 | if (!clk_name) | |
360 | return -ENOMEM; | |
361 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
362 | 0, prv_base, | |
363 | 1, 15, 16, 15, 0, NULL); | |
364 | parent = clk_name; | |
365 | ||
366 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
367 | if (!clk_name) { | |
368 | kfree(parent); | |
369 | return -ENOMEM; | |
370 | } | |
371 | clk = clk_register_gate(NULL, clk_name, parent, | |
372 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
373 | prv_base, 31, 0, NULL); | |
374 | kfree(parent); | |
375 | kfree(clk_name); | |
f6272170 | 376 | } |
03f09f73 | 377 | out: |
f6272170 MW |
378 | if (IS_ERR(clk)) |
379 | return PTR_ERR(clk); | |
f58b082a | 380 | |
ed3a872e | 381 | pdata->clk = clk; |
fcf0789a | 382 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
383 | return 0; |
384 | } | |
385 | ||
386 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
387 | const struct acpi_device_id *id) | |
388 | { | |
b2687cd7 | 389 | const struct lpss_device_desc *dev_desc; |
f58b082a | 390 | struct lpss_private_data *pdata; |
90e97820 | 391 | struct resource_entry *rentry; |
f58b082a | 392 | struct list_head resource_list; |
8ce62f85 | 393 | struct platform_device *pdev; |
f58b082a RW |
394 | int ret; |
395 | ||
b2687cd7 | 396 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 397 | if (!dev_desc) { |
1571875b | 398 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
399 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
400 | } | |
f58b082a RW |
401 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
402 | if (!pdata) | |
403 | return -ENOMEM; | |
404 | ||
405 | INIT_LIST_HEAD(&resource_list); | |
406 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
407 | if (ret < 0) | |
408 | goto err_out; | |
409 | ||
410 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 411 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
412 | if (dev_desc->prv_size_override) |
413 | pdata->mmio_size = dev_desc->prv_size_override; | |
414 | else | |
90e97820 JL |
415 | pdata->mmio_size = resource_size(rentry->res); |
416 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 417 | pdata->mmio_size); |
f58b082a RW |
418 | break; |
419 | } | |
420 | ||
421 | acpi_dev_free_resource_list(&resource_list); | |
422 | ||
d3e13ff3 RW |
423 | if (!pdata->mmio_base) { |
424 | ret = -ENOMEM; | |
425 | goto err_out; | |
426 | } | |
427 | ||
af65cfe9 MW |
428 | pdata->dev_desc = dev_desc; |
429 | ||
03f09f73 HK |
430 | if (dev_desc->setup) |
431 | dev_desc->setup(pdata); | |
432 | ||
ff8c1af5 | 433 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
434 | ret = register_device_clock(adev, pdata); |
435 | if (ret) { | |
b9e95fc6 RW |
436 | /* Skip the device, but continue the namespace scan. */ |
437 | ret = 0; | |
438 | goto err_out; | |
f58b082a RW |
439 | } |
440 | } | |
441 | ||
b9e95fc6 RW |
442 | /* |
443 | * This works around a known issue in ACPI tables where LPSS devices | |
444 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
445 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
446 | */ | |
447 | ret = acpi_device_fix_up_power(adev); | |
448 | if (ret) { | |
449 | /* Skip the device, but continue the namespace scan. */ | |
450 | ret = 0; | |
451 | goto err_out; | |
452 | } | |
453 | ||
f58b082a | 454 | adev->driver_data = pdata; |
1571875b | 455 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 456 | if (!IS_ERR_OR_NULL(pdev)) { |
8ce62f85 RW |
457 | return 1; |
458 | } | |
f58b082a | 459 | |
8ce62f85 | 460 | ret = PTR_ERR(pdev); |
f58b082a RW |
461 | adev->driver_data = NULL; |
462 | ||
463 | err_out: | |
464 | kfree(pdata); | |
465 | return ret; | |
466 | } | |
467 | ||
1a8f8351 RW |
468 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
469 | { | |
470 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
471 | } | |
472 | ||
473 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
474 | unsigned int reg) | |
475 | { | |
476 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
477 | } | |
478 | ||
2e0f8822 RW |
479 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
480 | { | |
481 | struct acpi_device *adev; | |
482 | struct lpss_private_data *pdata; | |
483 | unsigned long flags; | |
484 | int ret; | |
485 | ||
486 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
487 | if (WARN_ON(ret)) | |
488 | return ret; | |
489 | ||
490 | spin_lock_irqsave(&dev->power.lock, flags); | |
491 | if (pm_runtime_suspended(dev)) { | |
492 | ret = -EAGAIN; | |
493 | goto out; | |
494 | } | |
495 | pdata = acpi_driver_data(adev); | |
496 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
497 | ret = -ENODEV; | |
498 | goto out; | |
499 | } | |
1a8f8351 | 500 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
501 | |
502 | out: | |
503 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
504 | return ret; | |
505 | } | |
506 | ||
507 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
508 | char *buf) | |
509 | { | |
510 | u32 ltr_value = 0; | |
511 | unsigned int reg; | |
512 | int ret; | |
513 | ||
514 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
515 | ret = lpss_reg_read(dev, reg, <r_value); | |
516 | if (ret) | |
517 | return ret; | |
518 | ||
519 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
520 | } | |
521 | ||
522 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
523 | struct device_attribute *attr, char *buf) | |
524 | { | |
525 | u32 ltr_mode = 0; | |
526 | char *outstr; | |
527 | int ret; | |
528 | ||
529 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
530 | if (ret) | |
531 | return ret; | |
532 | ||
533 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
534 | return sprintf(buf, "%s\n", outstr); | |
535 | } | |
536 | ||
537 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
538 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
539 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
540 | ||
541 | static struct attribute *lpss_attrs[] = { | |
542 | &dev_attr_auto_ltr.attr, | |
543 | &dev_attr_sw_ltr.attr, | |
544 | &dev_attr_ltr_mode.attr, | |
545 | NULL, | |
546 | }; | |
547 | ||
548 | static struct attribute_group lpss_attr_group = { | |
549 | .attrs = lpss_attrs, | |
550 | .name = "lpss_ltr", | |
551 | }; | |
552 | ||
1a8f8351 RW |
553 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
554 | { | |
555 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
556 | u32 ltr_mode, ltr_val; | |
557 | ||
558 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
559 | if (val < 0) { | |
560 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
561 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
562 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
563 | } | |
564 | return; | |
565 | } | |
566 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
567 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
568 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
569 | val = LPSS_LTR_MAX_VAL; | |
570 | } else if (val > LPSS_LTR_MAX_VAL) { | |
571 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
572 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
573 | } else { | |
574 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
575 | } | |
576 | ltr_val |= val; | |
577 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
578 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
579 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
580 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
581 | } | |
582 | } | |
583 | ||
c78b0830 HK |
584 | #ifdef CONFIG_PM |
585 | /** | |
586 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
587 | * @dev: LPSS device | |
cb39dcdd | 588 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
589 | * |
590 | * Most LPSS devices have private registers which may loose their context when | |
591 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
592 | * prv_reg_ctx array. | |
593 | */ | |
cb39dcdd AS |
594 | static void acpi_lpss_save_ctx(struct device *dev, |
595 | struct lpss_private_data *pdata) | |
c78b0830 | 596 | { |
c78b0830 HK |
597 | unsigned int i; |
598 | ||
599 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
600 | unsigned long offset = i * sizeof(u32); | |
601 | ||
602 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
603 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
604 | pdata->prv_reg_ctx[i], offset); | |
605 | } | |
606 | } | |
607 | ||
608 | /** | |
609 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
610 | * @dev: LPSS device | |
cb39dcdd | 611 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
612 | * |
613 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
614 | */ | |
cb39dcdd AS |
615 | static void acpi_lpss_restore_ctx(struct device *dev, |
616 | struct lpss_private_data *pdata) | |
c78b0830 | 617 | { |
c78b0830 HK |
618 | unsigned int i; |
619 | ||
02b98540 AS |
620 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
621 | unsigned long offset = i * sizeof(u32); | |
622 | ||
623 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
624 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
625 | pdata->prv_reg_ctx[i], offset); | |
626 | } | |
627 | } | |
628 | ||
629 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
630 | { | |
c78b0830 HK |
631 | /* |
632 | * The following delay is needed or the subsequent write operations may | |
633 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
634 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 635 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 636 | */ |
b00855ae SK |
637 | unsigned int delay = 10; /* default 10ms delay */ |
638 | ||
639 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
640 | delay = 0; | |
641 | ||
642 | msleep(delay); | |
c78b0830 HK |
643 | } |
644 | ||
c3a49cf3 AS |
645 | static int acpi_lpss_activate(struct device *dev) |
646 | { | |
647 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
648 | int ret; | |
649 | ||
650 | ret = acpi_dev_runtime_resume(dev); | |
651 | if (ret) | |
652 | return ret; | |
653 | ||
654 | acpi_lpss_d3_to_d0_delay(pdata); | |
655 | ||
656 | /* | |
657 | * This is called only on ->probe() stage where a device is either in | |
658 | * known state defined by BIOS or most likely powered off. Due to this | |
659 | * we have to deassert reset line to be sure that ->probe() will | |
660 | * recognize the device. | |
661 | */ | |
662 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
663 | lpss_deassert_reset(pdata); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | static void acpi_lpss_dismiss(struct device *dev) | |
669 | { | |
670 | acpi_dev_runtime_suspend(dev); | |
671 | } | |
672 | ||
c78b0830 HK |
673 | #ifdef CONFIG_PM_SLEEP |
674 | static int acpi_lpss_suspend_late(struct device *dev) | |
675 | { | |
cb39dcdd AS |
676 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
677 | int ret; | |
c78b0830 | 678 | |
cb39dcdd | 679 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
680 | if (ret) |
681 | return ret; | |
682 | ||
cb39dcdd AS |
683 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
684 | acpi_lpss_save_ctx(dev, pdata); | |
685 | ||
c78b0830 HK |
686 | return acpi_dev_suspend_late(dev); |
687 | } | |
688 | ||
f4168b61 | 689 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 690 | { |
cb39dcdd AS |
691 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
692 | int ret; | |
c78b0830 | 693 | |
cb39dcdd | 694 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
695 | if (ret) |
696 | return ret; | |
697 | ||
02b98540 AS |
698 | acpi_lpss_d3_to_d0_delay(pdata); |
699 | ||
cb39dcdd AS |
700 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
701 | acpi_lpss_restore_ctx(dev, pdata); | |
702 | ||
c78b0830 HK |
703 | return pm_generic_resume_early(dev); |
704 | } | |
705 | #endif /* CONFIG_PM_SLEEP */ | |
706 | ||
eebb3e8d AS |
707 | /* IOSF SB for LPSS island */ |
708 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
709 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
710 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
711 | ||
712 | #define LPSS_IOSF_PMCSR 0x84 | |
713 | #define LPSS_PMCSR_D0 0 | |
714 | #define LPSS_PMCSR_D3hot 3 | |
715 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
716 | ||
717 | #define LPSS_IOSF_GPIODEF0 0x154 | |
718 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
719 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
720 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 721 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
722 | |
723 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
724 | ||
725 | static void lpss_iosf_enter_d3_state(void) | |
726 | { | |
727 | u32 value1 = 0; | |
d132d6d5 | 728 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
729 | u32 value2 = LPSS_PMCSR_D3hot; |
730 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
731 | /* | |
732 | * PMC provides an information about actual status of the LPSS devices. | |
733 | * Here we read the values related to LPSS power island, i.e. LPSS | |
734 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
735 | */ | |
736 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
737 | int ret; | |
738 | ||
739 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
740 | if (ret) | |
741 | return; | |
742 | ||
743 | mutex_lock(&lpss_iosf_mutex); | |
744 | ||
745 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
746 | if (ret) | |
747 | goto exit; | |
748 | ||
749 | /* | |
750 | * Get the status of entire LPSS power island per device basis. | |
751 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
752 | * are already in D3hot. | |
753 | */ | |
754 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
755 | if (pmc_status) | |
756 | goto exit; | |
757 | ||
758 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
759 | LPSS_IOSF_PMCSR, value2, mask2); | |
760 | ||
761 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
762 | LPSS_IOSF_PMCSR, value2, mask2); | |
763 | ||
764 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
765 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
766 | exit: | |
767 | mutex_unlock(&lpss_iosf_mutex); | |
768 | } | |
769 | ||
770 | static void lpss_iosf_exit_d3_state(void) | |
771 | { | |
d132d6d5 AS |
772 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
773 | LPSS_GPIODEF0_DMA_LLP; | |
774 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
775 | u32 value2 = LPSS_PMCSR_D0; |
776 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
777 | ||
778 | mutex_lock(&lpss_iosf_mutex); | |
779 | ||
780 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
781 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
782 | ||
783 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
784 | LPSS_IOSF_PMCSR, value2, mask2); | |
785 | ||
786 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
787 | LPSS_IOSF_PMCSR, value2, mask2); | |
788 | ||
789 | mutex_unlock(&lpss_iosf_mutex); | |
790 | } | |
791 | ||
c78b0830 HK |
792 | static int acpi_lpss_runtime_suspend(struct device *dev) |
793 | { | |
cb39dcdd AS |
794 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
795 | int ret; | |
c78b0830 | 796 | |
cb39dcdd | 797 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
798 | if (ret) |
799 | return ret; | |
800 | ||
cb39dcdd AS |
801 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
802 | acpi_lpss_save_ctx(dev, pdata); | |
803 | ||
eebb3e8d AS |
804 | ret = acpi_dev_runtime_suspend(dev); |
805 | ||
806 | /* | |
807 | * This call must be last in the sequence, otherwise PMC will return | |
808 | * wrong status for devices being about to be powered off. See | |
809 | * lpss_iosf_enter_d3_state() for further information. | |
810 | */ | |
811 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
812 | lpss_iosf_enter_d3_state(); | |
813 | ||
814 | return ret; | |
c78b0830 HK |
815 | } |
816 | ||
817 | static int acpi_lpss_runtime_resume(struct device *dev) | |
818 | { | |
cb39dcdd AS |
819 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
820 | int ret; | |
c78b0830 | 821 | |
eebb3e8d AS |
822 | /* |
823 | * This call is kept first to be in symmetry with | |
824 | * acpi_lpss_runtime_suspend() one. | |
825 | */ | |
826 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
827 | lpss_iosf_exit_d3_state(); | |
828 | ||
cb39dcdd | 829 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
830 | if (ret) |
831 | return ret; | |
832 | ||
02b98540 AS |
833 | acpi_lpss_d3_to_d0_delay(pdata); |
834 | ||
cb39dcdd AS |
835 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
836 | acpi_lpss_restore_ctx(dev, pdata); | |
837 | ||
c78b0830 HK |
838 | return pm_generic_runtime_resume(dev); |
839 | } | |
c78b0830 HK |
840 | #endif /* CONFIG_PM */ |
841 | ||
842 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
843 | #ifdef CONFIG_PM |
844 | .activate = acpi_lpss_activate, | |
845 | .dismiss = acpi_lpss_dismiss, | |
846 | #endif | |
c78b0830 | 847 | .ops = { |
5de21bb9 | 848 | #ifdef CONFIG_PM |
c78b0830 | 849 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 850 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 851 | .complete = pm_complete_with_resume_check, |
c78b0830 | 852 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
853 | .suspend_late = acpi_lpss_suspend_late, |
854 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
855 | .freeze = acpi_subsys_freeze, |
856 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
857 | .poweroff_late = acpi_lpss_suspend_late, |
858 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 859 | #endif |
c78b0830 HK |
860 | .runtime_suspend = acpi_lpss_runtime_suspend, |
861 | .runtime_resume = acpi_lpss_runtime_resume, | |
862 | #endif | |
863 | }, | |
864 | }; | |
865 | ||
2e0f8822 RW |
866 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
867 | unsigned long action, void *data) | |
868 | { | |
869 | struct platform_device *pdev = to_platform_device(data); | |
870 | struct lpss_private_data *pdata; | |
871 | struct acpi_device *adev; | |
872 | const struct acpi_device_id *id; | |
2e0f8822 RW |
873 | |
874 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
875 | if (!id || !id->driver_data) | |
876 | return 0; | |
877 | ||
878 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
879 | return 0; | |
880 | ||
881 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 882 | if (!pdata) |
2e0f8822 RW |
883 | return 0; |
884 | ||
cb39dcdd AS |
885 | if (pdata->mmio_base && |
886 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
887 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
888 | return 0; | |
889 | } | |
890 | ||
c78b0830 | 891 | switch (action) { |
de16d552 | 892 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 893 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 894 | break; |
de16d552 | 895 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 896 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 897 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
898 | break; |
899 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 900 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 901 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
902 | return sysfs_create_group(&pdev->dev.kobj, |
903 | &lpss_attr_group); | |
01ac170b | 904 | break; |
c78b0830 | 905 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 906 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 907 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 908 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 909 | break; |
c78b0830 HK |
910 | default: |
911 | break; | |
912 | } | |
2e0f8822 | 913 | |
c78b0830 | 914 | return 0; |
2e0f8822 RW |
915 | } |
916 | ||
917 | static struct notifier_block acpi_lpss_nb = { | |
918 | .notifier_call = acpi_lpss_platform_notify, | |
919 | }; | |
920 | ||
1a8f8351 RW |
921 | static void acpi_lpss_bind(struct device *dev) |
922 | { | |
923 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
924 | ||
ff8c1af5 | 925 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
926 | return; |
927 | ||
928 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
929 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
930 | else | |
931 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
932 | } | |
933 | ||
934 | static void acpi_lpss_unbind(struct device *dev) | |
935 | { | |
936 | dev->power.set_latency_tolerance = NULL; | |
937 | } | |
938 | ||
f58b082a RW |
939 | static struct acpi_scan_handler lpss_handler = { |
940 | .ids = acpi_lpss_device_ids, | |
941 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
942 | .bind = acpi_lpss_bind, |
943 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
944 | }; |
945 | ||
946 | void __init acpi_lpss_init(void) | |
947 | { | |
eebb3e8d AS |
948 | const struct x86_cpu_id *id; |
949 | int ret; | |
950 | ||
951 | ret = lpt_clk_init(); | |
952 | if (ret) | |
953 | return; | |
954 | ||
955 | id = x86_match_cpu(lpss_cpu_ids); | |
956 | if (id) | |
957 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
958 | ||
959 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
960 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 961 | } |
d6ddaaac RW |
962 | |
963 | #else | |
964 | ||
965 | static struct acpi_scan_handler lpss_handler = { | |
966 | .ids = acpi_lpss_device_ids, | |
967 | }; | |
968 | ||
969 | void __init acpi_lpss_init(void) | |
970 | { | |
971 | acpi_scan_add_handler(&lpss_handler); | |
972 | } | |
973 | ||
974 | #endif /* CONFIG_X86_INTEL_LPSS */ |