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1da177e4 LT |
1 | |
2 | /******************************************************************************* | |
3 | * | |
4 | * Module Name: hwregs - Read/write access functions for the various ACPI | |
5 | * control and status registers. | |
6 | * | |
7 | ******************************************************************************/ | |
8 | ||
9 | /* | |
75a44ce0 | 10 | * Copyright (C) 2000 - 2008, Intel Corp. |
1da177e4 LT |
11 | * All rights reserved. |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or without | |
14 | * modification, are permitted provided that the following conditions | |
15 | * are met: | |
16 | * 1. Redistributions of source code must retain the above copyright | |
17 | * notice, this list of conditions, and the following disclaimer, | |
18 | * without modification. | |
19 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
20 | * substantially similar to the "NO WARRANTY" disclaimer below | |
21 | * ("Disclaimer") and any redistribution must be conditioned upon | |
22 | * including a substantially similar Disclaimer requirement for further | |
23 | * binary redistribution. | |
24 | * 3. Neither the names of the above-listed copyright holders nor the names | |
25 | * of any contributors may be used to endorse or promote products derived | |
26 | * from this software without specific prior written permission. | |
27 | * | |
28 | * Alternatively, this software may be distributed under the terms of the | |
29 | * GNU General Public License ("GPL") version 2 as published by the Free | |
30 | * Software Foundation. | |
31 | * | |
32 | * NO WARRANTY | |
33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
34 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
35 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
36 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
37 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
38 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
39 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
40 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
41 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
42 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
43 | * POSSIBILITY OF SUCH DAMAGES. | |
44 | */ | |
45 | ||
1da177e4 | 46 | #include <acpi/acpi.h> |
e2f7a777 LB |
47 | #include "accommon.h" |
48 | #include "acnamesp.h" | |
49 | #include "acevents.h" | |
1da177e4 LT |
50 | |
51 | #define _COMPONENT ACPI_HARDWARE | |
4be44fcd | 52 | ACPI_MODULE_NAME("hwregs") |
1da177e4 | 53 | |
c520abad BM |
54 | /* Local Prototypes */ |
55 | static acpi_status | |
56 | acpi_hw_read_multiple(u32 *value, | |
57 | struct acpi_generic_address *register_a, | |
58 | struct acpi_generic_address *register_b); | |
59 | ||
60 | static acpi_status | |
61 | acpi_hw_write_multiple(u32 value, | |
62 | struct acpi_generic_address *register_a, | |
63 | struct acpi_generic_address *register_b); | |
64 | ||
1da177e4 LT |
65 | /******************************************************************************* |
66 | * | |
67 | * FUNCTION: acpi_hw_clear_acpi_status | |
68 | * | |
d8c71b6d | 69 | * PARAMETERS: None |
1da177e4 | 70 | * |
7db5d82d | 71 | * RETURN: Status |
1da177e4 LT |
72 | * |
73 | * DESCRIPTION: Clears all fixed and general purpose status bits | |
1da177e4 LT |
74 | * |
75 | ******************************************************************************/ | |
c520abad | 76 | |
d8c71b6d | 77 | acpi_status acpi_hw_clear_acpi_status(void) |
1da177e4 | 78 | { |
4be44fcd | 79 | acpi_status status; |
4c90ece2 | 80 | acpi_cpu_flags lock_flags = 0; |
1da177e4 | 81 | |
b229cf92 | 82 | ACPI_FUNCTION_TRACE(hw_clear_acpi_status); |
1da177e4 | 83 | |
227243a0 | 84 | ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %0llX\n", |
4be44fcd | 85 | ACPI_BITMASK_ALL_FIXED_STATUS, |
227243a0 | 86 | acpi_gbl_xpm1a_status.address)); |
1da177e4 | 87 | |
4c90ece2 | 88 | lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); |
1da177e4 | 89 | |
227243a0 | 90 | /* Clear the fixed events in PM1 A/B */ |
531c633d | 91 | |
d30dc9ab | 92 | status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS, |
4be44fcd LB |
93 | ACPI_BITMASK_ALL_FIXED_STATUS); |
94 | if (ACPI_FAILURE(status)) { | |
1da177e4 LT |
95 | goto unlock_and_exit; |
96 | } | |
97 | ||
1da177e4 LT |
98 | /* Clear the GPE Bits in all GPE registers in all GPE blocks */ |
99 | ||
e97d6bf1 | 100 | status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL); |
1da177e4 | 101 | |
4be44fcd | 102 | unlock_and_exit: |
4c90ece2 | 103 | acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); |
4be44fcd | 104 | return_ACPI_STATUS(status); |
1da177e4 LT |
105 | } |
106 | ||
1da177e4 LT |
107 | /******************************************************************************* |
108 | * | |
109 | * FUNCTION: acpi_hw_get_register_bit_mask | |
110 | * | |
111 | * PARAMETERS: register_id - Index of ACPI Register to access | |
112 | * | |
44f6c012 | 113 | * RETURN: The bitmask to be used when accessing the register |
1da177e4 | 114 | * |
44f6c012 | 115 | * DESCRIPTION: Map register_id into a register bitmask. |
1da177e4 LT |
116 | * |
117 | ******************************************************************************/ | |
7db5d82d | 118 | |
4be44fcd | 119 | struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id) |
1da177e4 | 120 | { |
4a90c7e8 | 121 | ACPI_FUNCTION_ENTRY(); |
1da177e4 LT |
122 | |
123 | if (register_id > ACPI_BITREG_MAX) { | |
b229cf92 | 124 | ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: %X", |
b8e4d893 | 125 | register_id)); |
1da177e4 LT |
126 | return (NULL); |
127 | } | |
128 | ||
129 | return (&acpi_gbl_bit_register_info[register_id]); | |
130 | } | |
131 | ||
32c9ef99 BM |
132 | /****************************************************************************** |
133 | * | |
134 | * FUNCTION: acpi_hw_write_pm1_control | |
135 | * | |
136 | * PARAMETERS: pm1a_control - Value to be written to PM1A control | |
137 | * pm1b_control - Value to be written to PM1B control | |
138 | * | |
139 | * RETURN: Status | |
140 | * | |
141 | * DESCRIPTION: Write the PM1 A/B control registers. These registers are | |
142 | * different than than the PM1 A/B status and enable registers | |
143 | * in that different values can be written to the A/B registers. | |
144 | * Most notably, the SLP_TYP bits can be different, as per the | |
145 | * values returned from the _Sx predefined methods. | |
146 | * | |
147 | ******************************************************************************/ | |
148 | ||
149 | acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control) | |
150 | { | |
151 | acpi_status status; | |
152 | ||
153 | ACPI_FUNCTION_TRACE(hw_write_pm1_control); | |
154 | ||
155 | status = acpi_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block); | |
156 | if (ACPI_FAILURE(status)) { | |
157 | return_ACPI_STATUS(status); | |
158 | } | |
159 | ||
160 | if (acpi_gbl_FADT.xpm1b_control_block.address) { | |
161 | status = | |
162 | acpi_write(pm1b_control, | |
163 | &acpi_gbl_FADT.xpm1b_control_block); | |
164 | } | |
165 | return_ACPI_STATUS(status); | |
166 | } | |
167 | ||
1da177e4 LT |
168 | /****************************************************************************** |
169 | * | |
170 | * FUNCTION: acpi_hw_register_read | |
171 | * | |
d30dc9ab | 172 | * PARAMETERS: register_id - ACPI Register ID |
44f6c012 | 173 | * return_value - Where the register value is returned |
1da177e4 LT |
174 | * |
175 | * RETURN: Status and the value read. | |
176 | * | |
967440e3 | 177 | * DESCRIPTION: Read from the specified ACPI register |
1da177e4 LT |
178 | * |
179 | ******************************************************************************/ | |
1da177e4 | 180 | acpi_status |
d30dc9ab | 181 | acpi_hw_register_read(u32 register_id, u32 * return_value) |
1da177e4 | 182 | { |
c520abad | 183 | u32 value = 0; |
4be44fcd | 184 | acpi_status status; |
1da177e4 | 185 | |
b229cf92 | 186 | ACPI_FUNCTION_TRACE(hw_register_read); |
1da177e4 | 187 | |
1da177e4 | 188 | switch (register_id) { |
c520abad | 189 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
1da177e4 | 190 | |
c520abad BM |
191 | status = acpi_hw_read_multiple(&value, |
192 | &acpi_gbl_xpm1a_status, | |
193 | &acpi_gbl_xpm1b_status); | |
1da177e4 LT |
194 | break; |
195 | ||
c520abad | 196 | case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ |
1da177e4 | 197 | |
c520abad BM |
198 | status = acpi_hw_read_multiple(&value, |
199 | &acpi_gbl_xpm1a_enable, | |
200 | &acpi_gbl_xpm1b_enable); | |
1da177e4 LT |
201 | break; |
202 | ||
c520abad | 203 | case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ |
1da177e4 | 204 | |
c520abad BM |
205 | status = acpi_hw_read_multiple(&value, |
206 | &acpi_gbl_FADT. | |
207 | xpm1a_control_block, | |
208 | &acpi_gbl_FADT. | |
209 | xpm1b_control_block); | |
1da177e4 LT |
210 | break; |
211 | ||
4be44fcd | 212 | case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ |
1da177e4 | 213 | |
c520abad | 214 | status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block); |
1da177e4 LT |
215 | break; |
216 | ||
4be44fcd | 217 | case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ |
1da177e4 | 218 | |
c520abad | 219 | status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block); |
1da177e4 LT |
220 | break; |
221 | ||
4be44fcd | 222 | case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ |
1da177e4 | 223 | |
f3d2e786 | 224 | status = |
c520abad | 225 | acpi_os_read_port(acpi_gbl_FADT.smi_command, &value, 8); |
1da177e4 LT |
226 | break; |
227 | ||
228 | default: | |
b8e4d893 | 229 | ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id)); |
1da177e4 LT |
230 | status = AE_BAD_PARAMETER; |
231 | break; | |
232 | } | |
233 | ||
4be44fcd | 234 | if (ACPI_SUCCESS(status)) { |
c520abad | 235 | *return_value = value; |
1da177e4 LT |
236 | } |
237 | ||
4be44fcd | 238 | return_ACPI_STATUS(status); |
1da177e4 LT |
239 | } |
240 | ||
1da177e4 LT |
241 | /****************************************************************************** |
242 | * | |
243 | * FUNCTION: acpi_hw_register_write | |
244 | * | |
d30dc9ab | 245 | * PARAMETERS: register_id - ACPI Register ID |
1da177e4 LT |
246 | * Value - The value to write |
247 | * | |
248 | * RETURN: Status | |
249 | * | |
967440e3 BM |
250 | * DESCRIPTION: Write to the specified ACPI register |
251 | * | |
252 | * NOTE: In accordance with the ACPI specification, this function automatically | |
253 | * preserves the value of the following bits, meaning that these bits cannot be | |
254 | * changed via this interface: | |
255 | * | |
256 | * PM1_CONTROL[0] = SCI_EN | |
257 | * PM1_CONTROL[9] | |
258 | * PM1_STATUS[11] | |
259 | * | |
260 | * ACPI References: | |
261 | * 1) Hardware Ignored Bits: When software writes to a register with ignored | |
262 | * bit fields, it preserves the ignored bit fields | |
263 | * 2) SCI_EN: OSPM always preserves this bit position | |
1da177e4 LT |
264 | * |
265 | ******************************************************************************/ | |
266 | ||
d30dc9ab | 267 | acpi_status acpi_hw_register_write(u32 register_id, u32 value) |
1da177e4 | 268 | { |
4be44fcd | 269 | acpi_status status; |
967440e3 | 270 | u32 read_value; |
1da177e4 | 271 | |
b229cf92 | 272 | ACPI_FUNCTION_TRACE(hw_register_write); |
1da177e4 | 273 | |
1da177e4 | 274 | switch (register_id) { |
c520abad | 275 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
8636f8d2 BM |
276 | /* |
277 | * Handle the "ignored" bit in PM1 Status. According to the ACPI | |
278 | * specification, ignored bits are to be preserved when writing. | |
279 | * Normally, this would mean a read/modify/write sequence. However, | |
280 | * preserving a bit in the status register is different. Writing a | |
281 | * one clears the status, and writing a zero preserves the status. | |
282 | * Therefore, we must always write zero to the ignored bit. | |
283 | * | |
284 | * This behavior is clarified in the ACPI 4.0 specification. | |
285 | */ | |
286 | value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; | |
967440e3 | 287 | |
c520abad BM |
288 | status = acpi_hw_write_multiple(value, |
289 | &acpi_gbl_xpm1a_status, | |
290 | &acpi_gbl_xpm1b_status); | |
1da177e4 LT |
291 | break; |
292 | ||
c520abad | 293 | case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */ |
1da177e4 | 294 | |
c520abad BM |
295 | status = acpi_hw_write_multiple(value, |
296 | &acpi_gbl_xpm1a_enable, | |
297 | &acpi_gbl_xpm1b_enable); | |
1da177e4 LT |
298 | break; |
299 | ||
c520abad | 300 | case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ |
1da177e4 | 301 | |
967440e3 BM |
302 | /* |
303 | * Perform a read first to preserve certain bits (per ACPI spec) | |
c520abad | 304 | * Note: This includes SCI_EN, we never want to change this bit |
967440e3 | 305 | */ |
c520abad BM |
306 | status = acpi_hw_read_multiple(&read_value, |
307 | &acpi_gbl_FADT. | |
308 | xpm1a_control_block, | |
309 | &acpi_gbl_FADT. | |
310 | xpm1b_control_block); | |
967440e3 | 311 | if (ACPI_FAILURE(status)) { |
d30dc9ab | 312 | goto exit; |
967440e3 BM |
313 | } |
314 | ||
315 | /* Insert the bits to be preserved */ | |
316 | ||
317 | ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS, | |
318 | read_value); | |
319 | ||
320 | /* Now we can write the data */ | |
321 | ||
c520abad BM |
322 | status = acpi_hw_write_multiple(value, |
323 | &acpi_gbl_FADT. | |
324 | xpm1a_control_block, | |
325 | &acpi_gbl_FADT. | |
326 | xpm1b_control_block); | |
1da177e4 LT |
327 | break; |
328 | ||
4be44fcd | 329 | case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ |
1da177e4 | 330 | |
20869dcf BM |
331 | /* |
332 | * For control registers, all reserved bits must be preserved, | |
333 | * as per the ACPI spec. | |
334 | */ | |
335 | status = | |
336 | acpi_read(&read_value, &acpi_gbl_FADT.xpm2_control_block); | |
337 | if (ACPI_FAILURE(status)) { | |
338 | goto exit; | |
339 | } | |
340 | ||
341 | /* Insert the bits to be preserved */ | |
342 | ||
343 | ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS, | |
344 | read_value); | |
345 | ||
ecfbbc7b | 346 | status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block); |
1da177e4 LT |
347 | break; |
348 | ||
4be44fcd | 349 | case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ |
1da177e4 | 350 | |
ecfbbc7b | 351 | status = acpi_write(value, &acpi_gbl_FADT.xpm_timer_block); |
1da177e4 LT |
352 | break; |
353 | ||
4be44fcd | 354 | case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ |
1da177e4 LT |
355 | |
356 | /* SMI_CMD is currently always in IO space */ | |
357 | ||
f3d2e786 BM |
358 | status = |
359 | acpi_os_write_port(acpi_gbl_FADT.smi_command, value, 8); | |
1da177e4 LT |
360 | break; |
361 | ||
1da177e4 | 362 | default: |
c520abad | 363 | ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id)); |
1da177e4 LT |
364 | status = AE_BAD_PARAMETER; |
365 | break; | |
366 | } | |
367 | ||
d30dc9ab | 368 | exit: |
4be44fcd | 369 | return_ACPI_STATUS(status); |
1da177e4 | 370 | } |
c520abad BM |
371 | |
372 | /****************************************************************************** | |
373 | * | |
374 | * FUNCTION: acpi_hw_read_multiple | |
375 | * | |
376 | * PARAMETERS: Value - Where the register value is returned | |
377 | * register_a - First ACPI register (required) | |
378 | * register_b - Second ACPI register (optional) | |
379 | * | |
380 | * RETURN: Status | |
381 | * | |
382 | * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) | |
383 | * | |
384 | ******************************************************************************/ | |
385 | ||
386 | static acpi_status | |
387 | acpi_hw_read_multiple(u32 *value, | |
388 | struct acpi_generic_address *register_a, | |
389 | struct acpi_generic_address *register_b) | |
390 | { | |
391 | u32 value_a = 0; | |
392 | u32 value_b = 0; | |
393 | acpi_status status; | |
394 | ||
395 | /* The first register is always required */ | |
396 | ||
397 | status = acpi_read(&value_a, register_a); | |
398 | if (ACPI_FAILURE(status)) { | |
399 | return (status); | |
400 | } | |
401 | ||
402 | /* Second register is optional */ | |
403 | ||
404 | if (register_b->address) { | |
405 | status = acpi_read(&value_b, register_b); | |
406 | if (ACPI_FAILURE(status)) { | |
407 | return (status); | |
408 | } | |
409 | } | |
410 | ||
aefc7f9a BM |
411 | /* |
412 | * OR the two return values together. No shifting or masking is necessary, | |
413 | * because of how the PM1 registers are defined in the ACPI specification: | |
414 | * | |
415 | * "Although the bits can be split between the two register blocks (each | |
416 | * register block has a unique pointer within the FADT), the bit positions | |
417 | * are maintained. The register block with unimplemented bits (that is, | |
418 | * those implemented in the other register block) always returns zeros, | |
419 | * and writes have no side effects" | |
420 | */ | |
421 | *value = (value_a | value_b); | |
c520abad BM |
422 | return (AE_OK); |
423 | } | |
424 | ||
425 | /****************************************************************************** | |
426 | * | |
427 | * FUNCTION: acpi_hw_write_multiple | |
428 | * | |
429 | * PARAMETERS: Value - The value to write | |
430 | * register_a - First ACPI register (required) | |
431 | * register_b - Second ACPI register (optional) | |
432 | * | |
433 | * RETURN: Status | |
434 | * | |
435 | * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) | |
436 | * | |
437 | ******************************************************************************/ | |
438 | ||
439 | static acpi_status | |
440 | acpi_hw_write_multiple(u32 value, | |
441 | struct acpi_generic_address *register_a, | |
442 | struct acpi_generic_address *register_b) | |
443 | { | |
444 | acpi_status status; | |
445 | ||
446 | /* The first register is always required */ | |
447 | ||
448 | status = acpi_write(value, register_a); | |
449 | if (ACPI_FAILURE(status)) { | |
450 | return (status); | |
451 | } | |
452 | ||
aefc7f9a BM |
453 | /* |
454 | * Second register is optional | |
455 | * | |
456 | * No bit shifting or clearing is necessary, because of how the PM1 | |
457 | * registers are defined in the ACPI specification: | |
458 | * | |
459 | * "Although the bits can be split between the two register blocks (each | |
460 | * register block has a unique pointer within the FADT), the bit positions | |
461 | * are maintained. The register block with unimplemented bits (that is, | |
462 | * those implemented in the other register block) always returns zeros, | |
463 | * and writes have no side effects" | |
464 | */ | |
c520abad | 465 | if (register_b->address) { |
aefc7f9a | 466 | status = acpi_write(value, register_b); |
c520abad BM |
467 | } |
468 | ||
469 | return (status); | |
470 | } |