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337aadff AC |
1 | /* |
2 | * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. | |
3 | * | |
4 | * (C) Copyright 2014, 2015 Linaro Ltd. | |
5 | * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * CPPC describes a few methods for controlling CPU performance using | |
13 | * information from a per CPU table called CPC. This table is described in | |
14 | * the ACPI v5.0+ specification. The table consists of a list of | |
15 | * registers which may be memory mapped or hardware registers and also may | |
16 | * include some static integer values. | |
17 | * | |
18 | * CPU performance is on an abstract continuous scale as against a discretized | |
19 | * P-state scale which is tied to CPU frequency only. In brief, the basic | |
20 | * operation involves: | |
21 | * | |
22 | * - OS makes a CPU performance request. (Can provide min and max bounds) | |
23 | * | |
24 | * - Platform (such as BMC) is free to optimize request within requested bounds | |
25 | * depending on power/thermal budgets etc. | |
26 | * | |
27 | * - Platform conveys its decision back to OS | |
28 | * | |
29 | * The communication between OS and platform occurs through another medium | |
30 | * called (PCC) Platform Communication Channel. This is a generic mailbox like | |
31 | * mechanism which includes doorbell semantics to indicate register updates. | |
32 | * See drivers/mailbox/pcc.c for details on PCC. | |
33 | * | |
34 | * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and | |
35 | * above specifications. | |
36 | */ | |
37 | ||
38 | #define pr_fmt(fmt) "ACPI CPPC: " fmt | |
39 | ||
40 | #include <linux/cpufreq.h> | |
41 | #include <linux/delay.h> | |
ad62e1e6 | 42 | #include <linux/ktime.h> |
80b8286a PP |
43 | #include <linux/rwsem.h> |
44 | #include <linux/wait.h> | |
337aadff AC |
45 | |
46 | #include <acpi/cppc_acpi.h> | |
80b8286a | 47 | |
8482ef8c PP |
48 | struct cppc_pcc_data { |
49 | struct mbox_chan *pcc_channel; | |
50 | void __iomem *pcc_comm_addr; | |
51 | int pcc_subspace_idx; | |
52 | bool pcc_channel_acquired; | |
53 | ktime_t deadline; | |
54 | unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; | |
80b8286a | 55 | |
8482ef8c | 56 | bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ |
139aee73 | 57 | bool platform_owns_pcc; /* Ownership of PCC subspace */ |
8482ef8c | 58 | unsigned int pcc_write_cnt; /* Running count of PCC write commands */ |
80b8286a | 59 | |
8482ef8c PP |
60 | /* |
61 | * Lock to provide controlled access to the PCC channel. | |
62 | * | |
63 | * For performance critical usecases(currently cppc_set_perf) | |
64 | * We need to take read_lock and check if channel belongs to OSPM | |
65 | * before reading or writing to PCC subspace | |
66 | * We need to take write_lock before transferring the channel | |
67 | * ownership to the platform via a Doorbell | |
68 | * This allows us to batch a number of CPPC requests if they happen | |
69 | * to originate in about the same time | |
70 | * | |
71 | * For non-performance critical usecases(init) | |
72 | * Take write_lock for all purposes which gives exclusive access | |
73 | */ | |
74 | struct rw_semaphore pcc_lock; | |
75 | ||
76 | /* Wait queue for CPUs whose requests were batched */ | |
77 | wait_queue_head_t pcc_write_wait_q; | |
78 | }; | |
80b8286a | 79 | |
8482ef8c PP |
80 | /* Structure to represent the single PCC channel */ |
81 | static struct cppc_pcc_data pcc_data = { | |
82 | .pcc_subspace_idx = -1, | |
139aee73 | 83 | .platform_owns_pcc = true, |
8482ef8c | 84 | }; |
337aadff AC |
85 | |
86 | /* | |
87 | * The cpc_desc structure contains the ACPI register details | |
88 | * as described in the per CPU _CPC tables. The details | |
89 | * include the type of register (e.g. PCC, System IO, FFH etc.) | |
90 | * and destination addresses which lets us READ/WRITE CPU performance | |
91 | * information using the appropriate I/O methods. | |
92 | */ | |
93 | static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); | |
94 | ||
77e3d86f | 95 | /* pcc mapped address + header size + offset within PCC subspace */ |
8482ef8c | 96 | #define GET_PCC_VADDR(offs) (pcc_data.pcc_comm_addr + 0x8 + (offs)) |
77e3d86f | 97 | |
80b8286a PP |
98 | /* Check if a CPC regsiter is in PCC */ |
99 | #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ | |
100 | (cpc)->cpc_entry.reg.space_id == \ | |
101 | ACPI_ADR_SPACE_PLATFORM_COMM) | |
102 | ||
158c998e AC |
103 | /* Evalutes to True if reg is a NULL register descriptor */ |
104 | #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ | |
105 | (reg)->address == 0 && \ | |
106 | (reg)->bit_width == 0 && \ | |
107 | (reg)->bit_offset == 0 && \ | |
108 | (reg)->access_width == 0) | |
109 | ||
110 | /* Evalutes to True if an optional cpc field is supported */ | |
111 | #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ | |
112 | !!(cpc)->cpc_entry.int_value : \ | |
113 | !IS_NULL_REG(&(cpc)->cpc_entry.reg)) | |
337aadff AC |
114 | /* |
115 | * Arbitrary Retries in case the remote processor is slow to respond | |
ad62e1e6 AC |
116 | * to PCC commands. Keeping it high enough to cover emulators where |
117 | * the processors run painfully slow. | |
337aadff AC |
118 | */ |
119 | #define NUM_RETRIES 500 | |
120 | ||
158c998e AC |
121 | struct cppc_attr { |
122 | struct attribute attr; | |
123 | ssize_t (*show)(struct kobject *kobj, | |
124 | struct attribute *attr, char *buf); | |
125 | ssize_t (*store)(struct kobject *kobj, | |
126 | struct attribute *attr, const char *c, ssize_t count); | |
127 | }; | |
128 | ||
129 | #define define_one_cppc_ro(_name) \ | |
130 | static struct cppc_attr _name = \ | |
131 | __ATTR(_name, 0444, show_##_name, NULL) | |
132 | ||
133 | #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) | |
134 | ||
135 | static ssize_t show_feedback_ctrs(struct kobject *kobj, | |
136 | struct attribute *attr, char *buf) | |
137 | { | |
138 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
139 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
140 | ||
141 | cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); | |
142 | ||
143 | return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", | |
144 | fb_ctrs.reference, fb_ctrs.delivered); | |
145 | } | |
146 | define_one_cppc_ro(feedback_ctrs); | |
147 | ||
148 | static ssize_t show_reference_perf(struct kobject *kobj, | |
149 | struct attribute *attr, char *buf) | |
150 | { | |
151 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
152 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
153 | ||
154 | cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); | |
155 | ||
156 | return scnprintf(buf, PAGE_SIZE, "%llu\n", | |
157 | fb_ctrs.reference_perf); | |
158 | } | |
159 | define_one_cppc_ro(reference_perf); | |
160 | ||
161 | static ssize_t show_wraparound_time(struct kobject *kobj, | |
162 | struct attribute *attr, char *buf) | |
163 | { | |
164 | struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); | |
165 | struct cppc_perf_fb_ctrs fb_ctrs = {0}; | |
166 | ||
167 | cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); | |
168 | ||
169 | return scnprintf(buf, PAGE_SIZE, "%llu\n", fb_ctrs.ctr_wrap_time); | |
170 | ||
171 | } | |
172 | define_one_cppc_ro(wraparound_time); | |
173 | ||
174 | static struct attribute *cppc_attrs[] = { | |
175 | &feedback_ctrs.attr, | |
176 | &reference_perf.attr, | |
177 | &wraparound_time.attr, | |
178 | NULL | |
179 | }; | |
180 | ||
181 | static struct kobj_type cppc_ktype = { | |
182 | .sysfs_ops = &kobj_sysfs_ops, | |
183 | .default_attrs = cppc_attrs, | |
184 | }; | |
185 | ||
139aee73 | 186 | static int check_pcc_chan(bool chk_err_bit) |
ad62e1e6 | 187 | { |
139aee73 | 188 | int ret = -EIO, status = 0; |
8482ef8c PP |
189 | struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_data.pcc_comm_addr; |
190 | ktime_t next_deadline = ktime_add(ktime_get(), pcc_data.deadline); | |
ad62e1e6 | 191 | |
139aee73 PP |
192 | if (!pcc_data.platform_owns_pcc) |
193 | return 0; | |
194 | ||
ad62e1e6 AC |
195 | /* Retry in case the remote processor was too slow to catch up. */ |
196 | while (!ktime_after(ktime_get(), next_deadline)) { | |
f387e5b9 PP |
197 | /* |
198 | * Per spec, prior to boot the PCC space wil be initialized by | |
199 | * platform and should have set the command completion bit when | |
200 | * PCC can be used by OSPM | |
201 | */ | |
139aee73 PP |
202 | status = readw_relaxed(&generic_comm_base->status); |
203 | if (status & PCC_CMD_COMPLETE_MASK) { | |
ad62e1e6 | 204 | ret = 0; |
139aee73 PP |
205 | if (chk_err_bit && (status & PCC_ERROR_MASK)) |
206 | ret = -EIO; | |
ad62e1e6 AC |
207 | break; |
208 | } | |
209 | /* | |
210 | * Reducing the bus traffic in case this loop takes longer than | |
211 | * a few retries. | |
212 | */ | |
213 | udelay(3); | |
214 | } | |
215 | ||
139aee73 PP |
216 | if (likely(!ret)) |
217 | pcc_data.platform_owns_pcc = false; | |
218 | else | |
219 | pr_err("PCC check channel failed. Status=%x\n", status); | |
220 | ||
ad62e1e6 AC |
221 | return ret; |
222 | } | |
223 | ||
80b8286a PP |
224 | /* |
225 | * This function transfers the ownership of the PCC to the platform | |
226 | * So it must be called while holding write_lock(pcc_lock) | |
227 | */ | |
337aadff AC |
228 | static int send_pcc_cmd(u16 cmd) |
229 | { | |
80b8286a | 230 | int ret = -EIO, i; |
337aadff | 231 | struct acpi_pcct_shared_memory *generic_comm_base = |
8482ef8c | 232 | (struct acpi_pcct_shared_memory *) pcc_data.pcc_comm_addr; |
f387e5b9 PP |
233 | static ktime_t last_cmd_cmpl_time, last_mpar_reset; |
234 | static int mpar_count; | |
235 | unsigned int time_delta; | |
337aadff | 236 | |
ad62e1e6 AC |
237 | /* |
238 | * For CMD_WRITE we know for a fact the caller should have checked | |
239 | * the channel before writing to PCC space | |
240 | */ | |
241 | if (cmd == CMD_READ) { | |
80b8286a PP |
242 | /* |
243 | * If there are pending cpc_writes, then we stole the channel | |
244 | * before write completion, so first send a WRITE command to | |
245 | * platform | |
246 | */ | |
8482ef8c | 247 | if (pcc_data.pending_pcc_write_cmd) |
80b8286a PP |
248 | send_pcc_cmd(CMD_WRITE); |
249 | ||
139aee73 | 250 | ret = check_pcc_chan(false); |
ad62e1e6 | 251 | if (ret) |
80b8286a PP |
252 | goto end; |
253 | } else /* CMD_WRITE */ | |
8482ef8c | 254 | pcc_data.pending_pcc_write_cmd = FALSE; |
337aadff | 255 | |
f387e5b9 PP |
256 | /* |
257 | * Handle the Minimum Request Turnaround Time(MRTT) | |
258 | * "The minimum amount of time that OSPM must wait after the completion | |
259 | * of a command before issuing the next command, in microseconds" | |
260 | */ | |
8482ef8c | 261 | if (pcc_data.pcc_mrtt) { |
f387e5b9 | 262 | time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time); |
8482ef8c PP |
263 | if (pcc_data.pcc_mrtt > time_delta) |
264 | udelay(pcc_data.pcc_mrtt - time_delta); | |
f387e5b9 PP |
265 | } |
266 | ||
267 | /* | |
268 | * Handle the non-zero Maximum Periodic Access Rate(MPAR) | |
269 | * "The maximum number of periodic requests that the subspace channel can | |
270 | * support, reported in commands per minute. 0 indicates no limitation." | |
271 | * | |
272 | * This parameter should be ideally zero or large enough so that it can | |
273 | * handle maximum number of requests that all the cores in the system can | |
274 | * collectively generate. If it is not, we will follow the spec and just | |
275 | * not send the request to the platform after hitting the MPAR limit in | |
276 | * any 60s window | |
277 | */ | |
8482ef8c | 278 | if (pcc_data.pcc_mpar) { |
f387e5b9 PP |
279 | if (mpar_count == 0) { |
280 | time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset); | |
281 | if (time_delta < 60 * MSEC_PER_SEC) { | |
282 | pr_debug("PCC cmd not sent due to MPAR limit"); | |
80b8286a PP |
283 | ret = -EIO; |
284 | goto end; | |
f387e5b9 PP |
285 | } |
286 | last_mpar_reset = ktime_get(); | |
8482ef8c | 287 | mpar_count = pcc_data.pcc_mpar; |
f387e5b9 PP |
288 | } |
289 | mpar_count--; | |
290 | } | |
291 | ||
337aadff | 292 | /* Write to the shared comm region. */ |
beee23ae | 293 | writew_relaxed(cmd, &generic_comm_base->command); |
337aadff AC |
294 | |
295 | /* Flip CMD COMPLETE bit */ | |
beee23ae | 296 | writew_relaxed(0, &generic_comm_base->status); |
337aadff | 297 | |
139aee73 PP |
298 | pcc_data.platform_owns_pcc = true; |
299 | ||
337aadff | 300 | /* Ring doorbell */ |
8482ef8c | 301 | ret = mbox_send_message(pcc_data.pcc_channel, &cmd); |
ad62e1e6 | 302 | if (ret < 0) { |
337aadff | 303 | pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n", |
ad62e1e6 | 304 | cmd, ret); |
80b8286a | 305 | goto end; |
337aadff AC |
306 | } |
307 | ||
139aee73 PP |
308 | /* wait for completion and check for PCC errro bit */ |
309 | ret = check_pcc_chan(true); | |
310 | ||
311 | if (pcc_data.pcc_mrtt) | |
312 | last_cmd_cmpl_time = ktime_get(); | |
337aadff | 313 | |
8482ef8c | 314 | mbox_client_txdone(pcc_data.pcc_channel, ret); |
80b8286a PP |
315 | |
316 | end: | |
317 | if (cmd == CMD_WRITE) { | |
318 | if (unlikely(ret)) { | |
319 | for_each_possible_cpu(i) { | |
320 | struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); | |
321 | if (!desc) | |
322 | continue; | |
323 | ||
8482ef8c | 324 | if (desc->write_cmd_id == pcc_data.pcc_write_cnt) |
80b8286a PP |
325 | desc->write_cmd_status = ret; |
326 | } | |
327 | } | |
8482ef8c PP |
328 | pcc_data.pcc_write_cnt++; |
329 | wake_up_all(&pcc_data.pcc_write_wait_q); | |
80b8286a PP |
330 | } |
331 | ||
ad62e1e6 | 332 | return ret; |
337aadff AC |
333 | } |
334 | ||
335 | static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) | |
336 | { | |
ad62e1e6 | 337 | if (ret < 0) |
337aadff AC |
338 | pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", |
339 | *(u16 *)msg, ret); | |
340 | else | |
341 | pr_debug("TX completed. CMD sent:%x, ret:%d\n", | |
342 | *(u16 *)msg, ret); | |
343 | } | |
344 | ||
345 | struct mbox_client cppc_mbox_cl = { | |
346 | .tx_done = cppc_chan_tx_done, | |
347 | .knows_txdone = true, | |
348 | }; | |
349 | ||
350 | static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) | |
351 | { | |
352 | int result = -EFAULT; | |
353 | acpi_status status = AE_OK; | |
354 | struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; | |
355 | struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; | |
356 | struct acpi_buffer state = {0, NULL}; | |
357 | union acpi_object *psd = NULL; | |
358 | struct acpi_psd_package *pdomain; | |
359 | ||
360 | status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer, | |
361 | ACPI_TYPE_PACKAGE); | |
362 | if (ACPI_FAILURE(status)) | |
363 | return -ENODEV; | |
364 | ||
365 | psd = buffer.pointer; | |
366 | if (!psd || psd->package.count != 1) { | |
367 | pr_debug("Invalid _PSD data\n"); | |
368 | goto end; | |
369 | } | |
370 | ||
371 | pdomain = &(cpc_ptr->domain_info); | |
372 | ||
373 | state.length = sizeof(struct acpi_psd_package); | |
374 | state.pointer = pdomain; | |
375 | ||
376 | status = acpi_extract_package(&(psd->package.elements[0]), | |
377 | &format, &state); | |
378 | if (ACPI_FAILURE(status)) { | |
379 | pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); | |
380 | goto end; | |
381 | } | |
382 | ||
383 | if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { | |
384 | pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); | |
385 | goto end; | |
386 | } | |
387 | ||
388 | if (pdomain->revision != ACPI_PSD_REV0_REVISION) { | |
389 | pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); | |
390 | goto end; | |
391 | } | |
392 | ||
393 | if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && | |
394 | pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && | |
395 | pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { | |
396 | pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); | |
397 | goto end; | |
398 | } | |
399 | ||
400 | result = 0; | |
401 | end: | |
402 | kfree(buffer.pointer); | |
403 | return result; | |
404 | } | |
405 | ||
406 | /** | |
407 | * acpi_get_psd_map - Map the CPUs in a common freq domain. | |
408 | * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info. | |
409 | * | |
410 | * Return: 0 for success or negative value for err. | |
411 | */ | |
412 | int acpi_get_psd_map(struct cpudata **all_cpu_data) | |
413 | { | |
414 | int count_target; | |
415 | int retval = 0; | |
416 | unsigned int i, j; | |
417 | cpumask_var_t covered_cpus; | |
418 | struct cpudata *pr, *match_pr; | |
419 | struct acpi_psd_package *pdomain; | |
420 | struct acpi_psd_package *match_pdomain; | |
421 | struct cpc_desc *cpc_ptr, *match_cpc_ptr; | |
422 | ||
423 | if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) | |
424 | return -ENOMEM; | |
425 | ||
426 | /* | |
427 | * Now that we have _PSD data from all CPUs, lets setup P-state | |
428 | * domain info. | |
429 | */ | |
430 | for_each_possible_cpu(i) { | |
431 | pr = all_cpu_data[i]; | |
432 | if (!pr) | |
433 | continue; | |
434 | ||
435 | if (cpumask_test_cpu(i, covered_cpus)) | |
436 | continue; | |
437 | ||
438 | cpc_ptr = per_cpu(cpc_desc_ptr, i); | |
8343c40d HT |
439 | if (!cpc_ptr) { |
440 | retval = -EFAULT; | |
441 | goto err_ret; | |
442 | } | |
337aadff AC |
443 | |
444 | pdomain = &(cpc_ptr->domain_info); | |
445 | cpumask_set_cpu(i, pr->shared_cpu_map); | |
446 | cpumask_set_cpu(i, covered_cpus); | |
447 | if (pdomain->num_processors <= 1) | |
448 | continue; | |
449 | ||
450 | /* Validate the Domain info */ | |
451 | count_target = pdomain->num_processors; | |
452 | if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) | |
453 | pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
454 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) | |
455 | pr->shared_type = CPUFREQ_SHARED_TYPE_HW; | |
456 | else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) | |
457 | pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
458 | ||
459 | for_each_possible_cpu(j) { | |
460 | if (i == j) | |
461 | continue; | |
462 | ||
463 | match_cpc_ptr = per_cpu(cpc_desc_ptr, j); | |
8343c40d HT |
464 | if (!match_cpc_ptr) { |
465 | retval = -EFAULT; | |
466 | goto err_ret; | |
467 | } | |
337aadff AC |
468 | |
469 | match_pdomain = &(match_cpc_ptr->domain_info); | |
470 | if (match_pdomain->domain != pdomain->domain) | |
471 | continue; | |
472 | ||
473 | /* Here i and j are in the same domain */ | |
474 | if (match_pdomain->num_processors != count_target) { | |
475 | retval = -EFAULT; | |
476 | goto err_ret; | |
477 | } | |
478 | ||
479 | if (pdomain->coord_type != match_pdomain->coord_type) { | |
480 | retval = -EFAULT; | |
481 | goto err_ret; | |
482 | } | |
483 | ||
484 | cpumask_set_cpu(j, covered_cpus); | |
485 | cpumask_set_cpu(j, pr->shared_cpu_map); | |
486 | } | |
487 | ||
488 | for_each_possible_cpu(j) { | |
489 | if (i == j) | |
490 | continue; | |
491 | ||
492 | match_pr = all_cpu_data[j]; | |
493 | if (!match_pr) | |
494 | continue; | |
495 | ||
496 | match_cpc_ptr = per_cpu(cpc_desc_ptr, j); | |
8343c40d HT |
497 | if (!match_cpc_ptr) { |
498 | retval = -EFAULT; | |
499 | goto err_ret; | |
500 | } | |
337aadff AC |
501 | |
502 | match_pdomain = &(match_cpc_ptr->domain_info); | |
503 | if (match_pdomain->domain != pdomain->domain) | |
504 | continue; | |
505 | ||
506 | match_pr->shared_type = pr->shared_type; | |
507 | cpumask_copy(match_pr->shared_cpu_map, | |
508 | pr->shared_cpu_map); | |
509 | } | |
510 | } | |
511 | ||
512 | err_ret: | |
513 | for_each_possible_cpu(i) { | |
514 | pr = all_cpu_data[i]; | |
515 | if (!pr) | |
516 | continue; | |
517 | ||
518 | /* Assume no coordination on any error parsing domain info */ | |
519 | if (retval) { | |
520 | cpumask_clear(pr->shared_cpu_map); | |
521 | cpumask_set_cpu(i, pr->shared_cpu_map); | |
522 | pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
523 | } | |
524 | } | |
525 | ||
526 | free_cpumask_var(covered_cpus); | |
527 | return retval; | |
528 | } | |
529 | EXPORT_SYMBOL_GPL(acpi_get_psd_map); | |
530 | ||
32c0b2f6 | 531 | static int register_pcc_channel(int pcc_subspace_idx) |
337aadff | 532 | { |
d29d6735 | 533 | struct acpi_pcct_hw_reduced *cppc_ss; |
ad62e1e6 | 534 | u64 usecs_lat; |
337aadff AC |
535 | |
536 | if (pcc_subspace_idx >= 0) { | |
8482ef8c | 537 | pcc_data.pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl, |
337aadff AC |
538 | pcc_subspace_idx); |
539 | ||
8482ef8c | 540 | if (IS_ERR(pcc_data.pcc_channel)) { |
337aadff AC |
541 | pr_err("Failed to find PCC communication channel\n"); |
542 | return -ENODEV; | |
543 | } | |
544 | ||
545 | /* | |
546 | * The PCC mailbox controller driver should | |
547 | * have parsed the PCCT (global table of all | |
548 | * PCC channels) and stored pointers to the | |
549 | * subspace communication region in con_priv. | |
550 | */ | |
8482ef8c | 551 | cppc_ss = (pcc_data.pcc_channel)->con_priv; |
337aadff AC |
552 | |
553 | if (!cppc_ss) { | |
554 | pr_err("No PCC subspace found for CPPC\n"); | |
555 | return -ENODEV; | |
556 | } | |
557 | ||
ad62e1e6 AC |
558 | /* |
559 | * cppc_ss->latency is just a Nominal value. In reality | |
560 | * the remote processor could be much slower to reply. | |
561 | * So add an arbitrary amount of wait on top of Nominal. | |
562 | */ | |
563 | usecs_lat = NUM_RETRIES * cppc_ss->latency; | |
8482ef8c PP |
564 | pcc_data.deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC); |
565 | pcc_data.pcc_mrtt = cppc_ss->min_turnaround_time; | |
566 | pcc_data.pcc_mpar = cppc_ss->max_access_rate; | |
567 | pcc_data.pcc_nominal = cppc_ss->latency; | |
337aadff | 568 | |
8482ef8c PP |
569 | pcc_data.pcc_comm_addr = acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length); |
570 | if (!pcc_data.pcc_comm_addr) { | |
337aadff AC |
571 | pr_err("Failed to ioremap PCC comm region mem\n"); |
572 | return -ENOMEM; | |
573 | } | |
574 | ||
575 | /* Set flag so that we dont come here for each CPU. */ | |
8482ef8c | 576 | pcc_data.pcc_channel_acquired = true; |
337aadff AC |
577 | } |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
a6cbcdd5 SP |
582 | /** |
583 | * cpc_ffh_supported() - check if FFH reading supported | |
584 | * | |
585 | * Check if the architecture has support for functional fixed hardware | |
586 | * read/write capability. | |
587 | * | |
588 | * Return: true for supported, false for not supported | |
589 | */ | |
590 | bool __weak cpc_ffh_supported(void) | |
591 | { | |
592 | return false; | |
593 | } | |
594 | ||
337aadff AC |
595 | /* |
596 | * An example CPC table looks like the following. | |
597 | * | |
598 | * Name(_CPC, Package() | |
599 | * { | |
600 | * 17, | |
601 | * NumEntries | |
602 | * 1, | |
603 | * // Revision | |
604 | * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, | |
605 | * // Highest Performance | |
606 | * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, | |
607 | * // Nominal Performance | |
608 | * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, | |
609 | * // Lowest Nonlinear Performance | |
610 | * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, | |
611 | * // Lowest Performance | |
612 | * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, | |
613 | * // Guaranteed Performance Register | |
614 | * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, | |
615 | * // Desired Performance Register | |
616 | * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, | |
617 | * .. | |
618 | * .. | |
619 | * .. | |
620 | * | |
621 | * } | |
622 | * Each Register() encodes how to access that specific register. | |
623 | * e.g. a sample PCC entry has the following encoding: | |
624 | * | |
625 | * Register ( | |
626 | * PCC, | |
627 | * AddressSpaceKeyword | |
628 | * 8, | |
629 | * //RegisterBitWidth | |
630 | * 8, | |
631 | * //RegisterBitOffset | |
632 | * 0x30, | |
633 | * //RegisterAddress | |
634 | * 9 | |
635 | * //AccessSize (subspace ID) | |
636 | * 0 | |
637 | * ) | |
638 | * } | |
639 | */ | |
640 | ||
641 | /** | |
642 | * acpi_cppc_processor_probe - Search for per CPU _CPC objects. | |
643 | * @pr: Ptr to acpi_processor containing this CPUs logical Id. | |
644 | * | |
645 | * Return: 0 for success or negative value for err. | |
646 | */ | |
647 | int acpi_cppc_processor_probe(struct acpi_processor *pr) | |
648 | { | |
649 | struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; | |
650 | union acpi_object *out_obj, *cpc_obj; | |
651 | struct cpc_desc *cpc_ptr; | |
652 | struct cpc_reg *gas_t; | |
158c998e | 653 | struct device *cpu_dev; |
337aadff AC |
654 | acpi_handle handle = pr->handle; |
655 | unsigned int num_ent, i, cpc_rev; | |
656 | acpi_status status; | |
657 | int ret = -EFAULT; | |
658 | ||
659 | /* Parse the ACPI _CPC table for this cpu. */ | |
660 | status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, | |
661 | ACPI_TYPE_PACKAGE); | |
662 | if (ACPI_FAILURE(status)) { | |
663 | ret = -ENODEV; | |
664 | goto out_buf_free; | |
665 | } | |
666 | ||
667 | out_obj = (union acpi_object *) output.pointer; | |
668 | ||
669 | cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); | |
670 | if (!cpc_ptr) { | |
671 | ret = -ENOMEM; | |
672 | goto out_buf_free; | |
673 | } | |
674 | ||
675 | /* First entry is NumEntries. */ | |
676 | cpc_obj = &out_obj->package.elements[0]; | |
677 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
678 | num_ent = cpc_obj->integer.value; | |
679 | } else { | |
680 | pr_debug("Unexpected entry type(%d) for NumEntries\n", | |
681 | cpc_obj->type); | |
682 | goto out_free; | |
683 | } | |
684 | ||
685 | /* Only support CPPCv2. Bail otherwise. */ | |
686 | if (num_ent != CPPC_NUM_ENT) { | |
687 | pr_debug("Firmware exports %d entries. Expected: %d\n", | |
688 | num_ent, CPPC_NUM_ENT); | |
689 | goto out_free; | |
690 | } | |
691 | ||
5bbb86aa AC |
692 | cpc_ptr->num_entries = num_ent; |
693 | ||
337aadff AC |
694 | /* Second entry should be revision. */ |
695 | cpc_obj = &out_obj->package.elements[1]; | |
696 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
697 | cpc_rev = cpc_obj->integer.value; | |
698 | } else { | |
699 | pr_debug("Unexpected entry type(%d) for Revision\n", | |
700 | cpc_obj->type); | |
701 | goto out_free; | |
702 | } | |
703 | ||
704 | if (cpc_rev != CPPC_REV) { | |
705 | pr_debug("Firmware exports revision:%d. Expected:%d\n", | |
706 | cpc_rev, CPPC_REV); | |
707 | goto out_free; | |
708 | } | |
709 | ||
710 | /* Iterate through remaining entries in _CPC */ | |
711 | for (i = 2; i < num_ent; i++) { | |
712 | cpc_obj = &out_obj->package.elements[i]; | |
713 | ||
714 | if (cpc_obj->type == ACPI_TYPE_INTEGER) { | |
715 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; | |
716 | cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; | |
717 | } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { | |
718 | gas_t = (struct cpc_reg *) | |
719 | cpc_obj->buffer.pointer; | |
720 | ||
721 | /* | |
722 | * The PCC Subspace index is encoded inside | |
723 | * the CPC table entries. The same PCC index | |
724 | * will be used for all the PCC entries, | |
725 | * so extract it only once. | |
726 | */ | |
727 | if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { | |
8482ef8c PP |
728 | if (pcc_data.pcc_subspace_idx < 0) |
729 | pcc_data.pcc_subspace_idx = gas_t->access_width; | |
730 | else if (pcc_data.pcc_subspace_idx != gas_t->access_width) { | |
337aadff AC |
731 | pr_debug("Mismatched PCC ids.\n"); |
732 | goto out_free; | |
733 | } | |
5bbb86aa AC |
734 | } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
735 | if (gas_t->address) { | |
736 | void __iomem *addr; | |
737 | ||
738 | addr = ioremap(gas_t->address, gas_t->bit_width/8); | |
739 | if (!addr) | |
740 | goto out_free; | |
741 | cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; | |
742 | } | |
743 | } else { | |
a6cbcdd5 SP |
744 | if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { |
745 | /* Support only PCC ,SYS MEM and FFH type regs */ | |
746 | pr_debug("Unsupported register type: %d\n", gas_t->space_id); | |
747 | goto out_free; | |
748 | } | |
337aadff AC |
749 | } |
750 | ||
751 | cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; | |
752 | memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); | |
753 | } else { | |
754 | pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); | |
755 | goto out_free; | |
756 | } | |
757 | } | |
758 | /* Store CPU Logical ID */ | |
759 | cpc_ptr->cpu_id = pr->id; | |
760 | ||
337aadff AC |
761 | /* Parse PSD data for this CPU */ |
762 | ret = acpi_get_psd(cpc_ptr, handle); | |
763 | if (ret) | |
764 | goto out_free; | |
765 | ||
766 | /* Register PCC channel once for all CPUs. */ | |
8482ef8c PP |
767 | if (!pcc_data.pcc_channel_acquired) { |
768 | ret = register_pcc_channel(pcc_data.pcc_subspace_idx); | |
337aadff AC |
769 | if (ret) |
770 | goto out_free; | |
8482ef8c PP |
771 | |
772 | init_rwsem(&pcc_data.pcc_lock); | |
773 | init_waitqueue_head(&pcc_data.pcc_write_wait_q); | |
337aadff AC |
774 | } |
775 | ||
2324d154 HT |
776 | /* Plug PSD data into this CPUs CPC descriptor. */ |
777 | per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; | |
778 | ||
337aadff AC |
779 | /* Everything looks okay */ |
780 | pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); | |
781 | ||
158c998e AC |
782 | /* Add per logical CPU nodes for reading its feedback counters. */ |
783 | cpu_dev = get_cpu_device(pr->id); | |
784 | if (!cpu_dev) | |
785 | goto out_free; | |
786 | ||
787 | ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, | |
788 | "acpi_cppc"); | |
789 | if (ret) | |
790 | goto out_free; | |
791 | ||
337aadff AC |
792 | kfree(output.pointer); |
793 | return 0; | |
794 | ||
795 | out_free: | |
5bbb86aa AC |
796 | /* Free all the mapped sys mem areas for this CPU */ |
797 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
798 | void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
799 | ||
800 | if (addr) | |
801 | iounmap(addr); | |
802 | } | |
337aadff AC |
803 | kfree(cpc_ptr); |
804 | ||
805 | out_buf_free: | |
806 | kfree(output.pointer); | |
807 | return ret; | |
808 | } | |
809 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); | |
810 | ||
811 | /** | |
812 | * acpi_cppc_processor_exit - Cleanup CPC structs. | |
813 | * @pr: Ptr to acpi_processor containing this CPUs logical Id. | |
814 | * | |
815 | * Return: Void | |
816 | */ | |
817 | void acpi_cppc_processor_exit(struct acpi_processor *pr) | |
818 | { | |
819 | struct cpc_desc *cpc_ptr; | |
5bbb86aa AC |
820 | unsigned int i; |
821 | void __iomem *addr; | |
158c998e | 822 | |
337aadff | 823 | cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); |
5bbb86aa AC |
824 | |
825 | /* Free all the mapped sys mem areas for this CPU */ | |
826 | for (i = 2; i < cpc_ptr->num_entries; i++) { | |
827 | addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; | |
828 | if (addr) | |
829 | iounmap(addr); | |
830 | } | |
831 | ||
158c998e | 832 | kobject_put(&cpc_ptr->kobj); |
337aadff AC |
833 | kfree(cpc_ptr); |
834 | } | |
835 | EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); | |
836 | ||
a6cbcdd5 SP |
837 | /** |
838 | * cpc_read_ffh() - Read FFH register | |
839 | * @cpunum: cpu number to read | |
840 | * @reg: cppc register information | |
841 | * @val: place holder for return value | |
842 | * | |
843 | * Read bit_width bits from a specified address and bit_offset | |
844 | * | |
845 | * Return: 0 for success and error code | |
846 | */ | |
847 | int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | |
848 | { | |
849 | return -ENOTSUPP; | |
850 | } | |
851 | ||
852 | /** | |
853 | * cpc_write_ffh() - Write FFH register | |
854 | * @cpunum: cpu number to write | |
855 | * @reg: cppc register information | |
856 | * @val: value to write | |
857 | * | |
858 | * Write value of bit_width bits to a specified address and bit_offset | |
859 | * | |
860 | * Return: 0 for success and error code | |
861 | */ | |
862 | int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | |
863 | { | |
864 | return -ENOTSUPP; | |
865 | } | |
866 | ||
77e3d86f PP |
867 | /* |
868 | * Since cpc_read and cpc_write are called while holding pcc_lock, it should be | |
869 | * as fast as possible. We have already mapped the PCC subspace during init, so | |
870 | * we can directly write to it. | |
871 | */ | |
337aadff | 872 | |
a6cbcdd5 | 873 | static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) |
337aadff | 874 | { |
77e3d86f | 875 | int ret_val = 0; |
5bbb86aa AC |
876 | void __iomem *vaddr = 0; |
877 | struct cpc_reg *reg = ®_res->cpc_entry.reg; | |
878 | ||
879 | if (reg_res->type == ACPI_TYPE_INTEGER) { | |
880 | *val = reg_res->cpc_entry.int_value; | |
881 | return ret_val; | |
882 | } | |
77e3d86f PP |
883 | |
884 | *val = 0; | |
5bbb86aa AC |
885 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) |
886 | vaddr = GET_PCC_VADDR(reg->address); | |
887 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) | |
888 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
889 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
890 | return cpc_read_ffh(cpu, reg, val); | |
5bbb86aa AC |
891 | else |
892 | return acpi_os_read_memory((acpi_physical_address)reg->address, | |
893 | val, reg->bit_width); | |
337aadff | 894 | |
5bbb86aa | 895 | switch (reg->bit_width) { |
77e3d86f | 896 | case 8: |
beee23ae | 897 | *val = readb_relaxed(vaddr); |
77e3d86f PP |
898 | break; |
899 | case 16: | |
beee23ae | 900 | *val = readw_relaxed(vaddr); |
77e3d86f PP |
901 | break; |
902 | case 32: | |
beee23ae | 903 | *val = readl_relaxed(vaddr); |
77e3d86f PP |
904 | break; |
905 | case 64: | |
beee23ae | 906 | *val = readq_relaxed(vaddr); |
77e3d86f PP |
907 | break; |
908 | default: | |
909 | pr_debug("Error: Cannot read %u bit width from PCC\n", | |
5bbb86aa | 910 | reg->bit_width); |
77e3d86f | 911 | ret_val = -EFAULT; |
5bbb86aa AC |
912 | } |
913 | ||
77e3d86f | 914 | return ret_val; |
337aadff AC |
915 | } |
916 | ||
a6cbcdd5 | 917 | static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) |
337aadff | 918 | { |
77e3d86f | 919 | int ret_val = 0; |
5bbb86aa AC |
920 | void __iomem *vaddr = 0; |
921 | struct cpc_reg *reg = ®_res->cpc_entry.reg; | |
77e3d86f | 922 | |
5bbb86aa AC |
923 | if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) |
924 | vaddr = GET_PCC_VADDR(reg->address); | |
925 | else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) | |
926 | vaddr = reg_res->sys_mem_vaddr; | |
a6cbcdd5 SP |
927 | else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) |
928 | return cpc_write_ffh(cpu, reg, val); | |
5bbb86aa AC |
929 | else |
930 | return acpi_os_write_memory((acpi_physical_address)reg->address, | |
931 | val, reg->bit_width); | |
337aadff | 932 | |
5bbb86aa | 933 | switch (reg->bit_width) { |
77e3d86f | 934 | case 8: |
beee23ae | 935 | writeb_relaxed(val, vaddr); |
77e3d86f PP |
936 | break; |
937 | case 16: | |
beee23ae | 938 | writew_relaxed(val, vaddr); |
77e3d86f PP |
939 | break; |
940 | case 32: | |
beee23ae | 941 | writel_relaxed(val, vaddr); |
77e3d86f PP |
942 | break; |
943 | case 64: | |
beee23ae | 944 | writeq_relaxed(val, vaddr); |
77e3d86f PP |
945 | break; |
946 | default: | |
947 | pr_debug("Error: Cannot write %u bit width to PCC\n", | |
5bbb86aa | 948 | reg->bit_width); |
77e3d86f PP |
949 | ret_val = -EFAULT; |
950 | break; | |
5bbb86aa AC |
951 | } |
952 | ||
77e3d86f | 953 | return ret_val; |
337aadff AC |
954 | } |
955 | ||
956 | /** | |
957 | * cppc_get_perf_caps - Get a CPUs performance capabilities. | |
958 | * @cpunum: CPU from which to get capabilities info. | |
959 | * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h | |
960 | * | |
961 | * Return: 0 for success with perf_caps populated else -ERRNO. | |
962 | */ | |
963 | int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) | |
964 | { | |
965 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
966 | struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf, | |
967 | *nom_perf; | |
158c998e | 968 | u64 high, low, nom; |
850d64a4 | 969 | int ret = 0, regs_in_pcc = 0; |
337aadff AC |
970 | |
971 | if (!cpc_desc) { | |
972 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); | |
973 | return -ENODEV; | |
974 | } | |
975 | ||
976 | highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; | |
977 | lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; | |
978 | ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF]; | |
979 | nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
980 | ||
337aadff | 981 | /* Are any of the regs PCC ?*/ |
80b8286a PP |
982 | if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || |
983 | CPC_IN_PCC(ref_perf) || CPC_IN_PCC(nom_perf)) { | |
850d64a4 | 984 | regs_in_pcc = 1; |
8482ef8c | 985 | down_write(&pcc_data.pcc_lock); |
337aadff | 986 | /* Ring doorbell once to update PCC subspace */ |
ad62e1e6 | 987 | if (send_pcc_cmd(CMD_READ) < 0) { |
337aadff AC |
988 | ret = -EIO; |
989 | goto out_err; | |
990 | } | |
991 | } | |
992 | ||
a6cbcdd5 | 993 | cpc_read(cpunum, highest_reg, &high); |
337aadff AC |
994 | perf_caps->highest_perf = high; |
995 | ||
a6cbcdd5 | 996 | cpc_read(cpunum, lowest_reg, &low); |
337aadff AC |
997 | perf_caps->lowest_perf = low; |
998 | ||
a6cbcdd5 | 999 | cpc_read(cpunum, nom_perf, &nom); |
337aadff AC |
1000 | perf_caps->nominal_perf = nom; |
1001 | ||
337aadff AC |
1002 | if (!high || !low || !nom) |
1003 | ret = -EFAULT; | |
1004 | ||
1005 | out_err: | |
850d64a4 | 1006 | if (regs_in_pcc) |
8482ef8c | 1007 | up_write(&pcc_data.pcc_lock); |
337aadff AC |
1008 | return ret; |
1009 | } | |
1010 | EXPORT_SYMBOL_GPL(cppc_get_perf_caps); | |
1011 | ||
1012 | /** | |
1013 | * cppc_get_perf_ctrs - Read a CPUs performance feedback counters. | |
1014 | * @cpunum: CPU from which to read counters. | |
1015 | * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h | |
1016 | * | |
1017 | * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. | |
1018 | */ | |
1019 | int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) | |
1020 | { | |
1021 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); | |
158c998e AC |
1022 | struct cpc_register_resource *delivered_reg, *reference_reg, |
1023 | *ref_perf_reg, *ctr_wrap_reg; | |
1024 | u64 delivered, reference, ref_perf, ctr_wrap_time; | |
850d64a4 | 1025 | int ret = 0, regs_in_pcc = 0; |
337aadff AC |
1026 | |
1027 | if (!cpc_desc) { | |
1028 | pr_debug("No CPC descriptor for CPU:%d\n", cpunum); | |
1029 | return -ENODEV; | |
1030 | } | |
1031 | ||
1032 | delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; | |
1033 | reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; | |
158c998e AC |
1034 | ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; |
1035 | ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; | |
1036 | ||
1037 | /* | |
1038 | * If refernce perf register is not supported then we should | |
1039 | * use the nominal perf value | |
1040 | */ | |
1041 | if (!CPC_SUPPORTED(ref_perf_reg)) | |
1042 | ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; | |
337aadff | 1043 | |
337aadff | 1044 | /* Are any of the regs PCC ?*/ |
158c998e AC |
1045 | if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || |
1046 | CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { | |
8482ef8c | 1047 | down_write(&pcc_data.pcc_lock); |
850d64a4 | 1048 | regs_in_pcc = 1; |
337aadff | 1049 | /* Ring doorbell once to update PCC subspace */ |
ad62e1e6 | 1050 | if (send_pcc_cmd(CMD_READ) < 0) { |
337aadff AC |
1051 | ret = -EIO; |
1052 | goto out_err; | |
1053 | } | |
1054 | } | |
1055 | ||
a6cbcdd5 SP |
1056 | cpc_read(cpunum, delivered_reg, &delivered); |
1057 | cpc_read(cpunum, reference_reg, &reference); | |
1058 | cpc_read(cpunum, ref_perf_reg, &ref_perf); | |
158c998e AC |
1059 | |
1060 | /* | |
1061 | * Per spec, if ctr_wrap_time optional register is unsupported, then the | |
1062 | * performance counters are assumed to never wrap during the lifetime of | |
1063 | * platform | |
1064 | */ | |
1065 | ctr_wrap_time = (u64)(~((u64)0)); | |
1066 | if (CPC_SUPPORTED(ctr_wrap_reg)) | |
a6cbcdd5 | 1067 | cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); |
337aadff | 1068 | |
158c998e | 1069 | if (!delivered || !reference || !ref_perf) { |
337aadff AC |
1070 | ret = -EFAULT; |
1071 | goto out_err; | |
1072 | } | |
1073 | ||
1074 | perf_fb_ctrs->delivered = delivered; | |
1075 | perf_fb_ctrs->reference = reference; | |
158c998e AC |
1076 | perf_fb_ctrs->reference_perf = ref_perf; |
1077 | perf_fb_ctrs->ctr_wrap_time = ctr_wrap_time; | |
337aadff | 1078 | out_err: |
850d64a4 | 1079 | if (regs_in_pcc) |
8482ef8c | 1080 | up_write(&pcc_data.pcc_lock); |
337aadff AC |
1081 | return ret; |
1082 | } | |
1083 | EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); | |
1084 | ||
1085 | /** | |
1086 | * cppc_set_perf - Set a CPUs performance controls. | |
1087 | * @cpu: CPU for which to set performance controls. | |
1088 | * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h | |
1089 | * | |
1090 | * Return: 0 for success, -ERRNO otherwise. | |
1091 | */ | |
1092 | int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) | |
1093 | { | |
1094 | struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); | |
1095 | struct cpc_register_resource *desired_reg; | |
1096 | int ret = 0; | |
1097 | ||
1098 | if (!cpc_desc) { | |
1099 | pr_debug("No CPC descriptor for CPU:%d\n", cpu); | |
1100 | return -ENODEV; | |
1101 | } | |
1102 | ||
1103 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1104 | ||
80b8286a PP |
1105 | /* |
1106 | * This is Phase-I where we want to write to CPC registers | |
1107 | * -> We want all CPUs to be able to execute this phase in parallel | |
1108 | * | |
1109 | * Since read_lock can be acquired by multiple CPUs simultaneously we | |
1110 | * achieve that goal here | |
1111 | */ | |
1112 | if (CPC_IN_PCC(desired_reg)) { | |
8482ef8c | 1113 | down_read(&pcc_data.pcc_lock); /* BEGIN Phase-I */ |
139aee73 PP |
1114 | if (pcc_data.platform_owns_pcc) { |
1115 | ret = check_pcc_chan(false); | |
80b8286a | 1116 | if (ret) { |
8482ef8c | 1117 | up_read(&pcc_data.pcc_lock); |
80b8286a PP |
1118 | return ret; |
1119 | } | |
80b8286a | 1120 | } |
139aee73 PP |
1121 | /* |
1122 | * Update the pending_write to make sure a PCC CMD_READ will not | |
1123 | * arrive and steal the channel during the switch to write lock | |
1124 | */ | |
1125 | pcc_data.pending_pcc_write_cmd = true; | |
8482ef8c | 1126 | cpc_desc->write_cmd_id = pcc_data.pcc_write_cnt; |
80b8286a | 1127 | cpc_desc->write_cmd_status = 0; |
ad62e1e6 AC |
1128 | } |
1129 | ||
337aadff AC |
1130 | /* |
1131 | * Skip writing MIN/MAX until Linux knows how to come up with | |
1132 | * useful values. | |
1133 | */ | |
a6cbcdd5 | 1134 | cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); |
337aadff | 1135 | |
80b8286a | 1136 | if (CPC_IN_PCC(desired_reg)) |
8482ef8c | 1137 | up_read(&pcc_data.pcc_lock); /* END Phase-I */ |
80b8286a PP |
1138 | /* |
1139 | * This is Phase-II where we transfer the ownership of PCC to Platform | |
1140 | * | |
1141 | * Short Summary: Basically if we think of a group of cppc_set_perf | |
1142 | * requests that happened in short overlapping interval. The last CPU to | |
1143 | * come out of Phase-I will enter Phase-II and ring the doorbell. | |
1144 | * | |
1145 | * We have the following requirements for Phase-II: | |
1146 | * 1. We want to execute Phase-II only when there are no CPUs | |
1147 | * currently executing in Phase-I | |
1148 | * 2. Once we start Phase-II we want to avoid all other CPUs from | |
1149 | * entering Phase-I. | |
1150 | * 3. We want only one CPU among all those who went through Phase-I | |
1151 | * to run phase-II | |
1152 | * | |
1153 | * If write_trylock fails to get the lock and doesn't transfer the | |
1154 | * PCC ownership to the platform, then one of the following will be TRUE | |
1155 | * 1. There is at-least one CPU in Phase-I which will later execute | |
1156 | * write_trylock, so the CPUs in Phase-I will be responsible for | |
1157 | * executing the Phase-II. | |
1158 | * 2. Some other CPU has beaten this CPU to successfully execute the | |
1159 | * write_trylock and has already acquired the write_lock. We know for a | |
1160 | * fact it(other CPU acquiring the write_lock) couldn't have happened | |
1161 | * before this CPU's Phase-I as we held the read_lock. | |
1162 | * 3. Some other CPU executing pcc CMD_READ has stolen the | |
1163 | * down_write, in which case, send_pcc_cmd will check for pending | |
1164 | * CMD_WRITE commands by checking the pending_pcc_write_cmd. | |
1165 | * So this CPU can be certain that its request will be delivered | |
1166 | * So in all cases, this CPU knows that its request will be delivered | |
1167 | * by another CPU and can return | |
1168 | * | |
1169 | * After getting the down_write we still need to check for | |
1170 | * pending_pcc_write_cmd to take care of the following scenario | |
1171 | * The thread running this code could be scheduled out between | |
1172 | * Phase-I and Phase-II. Before it is scheduled back on, another CPU | |
1173 | * could have delivered the request to Platform by triggering the | |
1174 | * doorbell and transferred the ownership of PCC to platform. So this | |
1175 | * avoids triggering an unnecessary doorbell and more importantly before | |
1176 | * triggering the doorbell it makes sure that the PCC channel ownership | |
1177 | * is still with OSPM. | |
1178 | * pending_pcc_write_cmd can also be cleared by a different CPU, if | |
1179 | * there was a pcc CMD_READ waiting on down_write and it steals the lock | |
1180 | * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this | |
1181 | * case during a CMD_READ and if there are pending writes it delivers | |
1182 | * the write command before servicing the read command | |
1183 | */ | |
1184 | if (CPC_IN_PCC(desired_reg)) { | |
8482ef8c | 1185 | if (down_write_trylock(&pcc_data.pcc_lock)) { /* BEGIN Phase-II */ |
80b8286a | 1186 | /* Update only if there are pending write commands */ |
8482ef8c | 1187 | if (pcc_data.pending_pcc_write_cmd) |
80b8286a | 1188 | send_pcc_cmd(CMD_WRITE); |
8482ef8c | 1189 | up_write(&pcc_data.pcc_lock); /* END Phase-II */ |
80b8286a PP |
1190 | } else |
1191 | /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ | |
8482ef8c PP |
1192 | wait_event(pcc_data.pcc_write_wait_q, |
1193 | cpc_desc->write_cmd_id != pcc_data.pcc_write_cnt); | |
80b8286a PP |
1194 | |
1195 | /* send_pcc_cmd updates the status in case of failure */ | |
1196 | ret = cpc_desc->write_cmd_status; | |
337aadff | 1197 | } |
337aadff AC |
1198 | return ret; |
1199 | } | |
1200 | EXPORT_SYMBOL_GPL(cppc_set_perf); | |
be8b88d7 PP |
1201 | |
1202 | /** | |
1203 | * cppc_get_transition_latency - returns frequency transition latency in ns | |
1204 | * | |
1205 | * ACPI CPPC does not explicitly specifiy how a platform can specify the | |
1206 | * transition latency for perfromance change requests. The closest we have | |
1207 | * is the timing information from the PCCT tables which provides the info | |
1208 | * on the number and frequency of PCC commands the platform can handle. | |
1209 | */ | |
1210 | unsigned int cppc_get_transition_latency(int cpu_num) | |
1211 | { | |
1212 | /* | |
1213 | * Expected transition latency is based on the PCCT timing values | |
1214 | * Below are definition from ACPI spec: | |
1215 | * pcc_nominal- Expected latency to process a command, in microseconds | |
1216 | * pcc_mpar - The maximum number of periodic requests that the subspace | |
1217 | * channel can support, reported in commands per minute. 0 | |
1218 | * indicates no limitation. | |
1219 | * pcc_mrtt - The minimum amount of time that OSPM must wait after the | |
1220 | * completion of a command before issuing the next command, | |
1221 | * in microseconds. | |
1222 | */ | |
1223 | unsigned int latency_ns = 0; | |
1224 | struct cpc_desc *cpc_desc; | |
1225 | struct cpc_register_resource *desired_reg; | |
1226 | ||
1227 | cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); | |
1228 | if (!cpc_desc) | |
1229 | return CPUFREQ_ETERNAL; | |
1230 | ||
1231 | desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; | |
1232 | if (!CPC_IN_PCC(desired_reg)) | |
1233 | return CPUFREQ_ETERNAL; | |
1234 | ||
8482ef8c PP |
1235 | if (pcc_data.pcc_mpar) |
1236 | latency_ns = 60 * (1000 * 1000 * 1000 / pcc_data.pcc_mpar); | |
be8b88d7 | 1237 | |
8482ef8c PP |
1238 | latency_ns = max(latency_ns, pcc_data.pcc_nominal * 1000); |
1239 | latency_ns = max(latency_ns, pcc_data.pcc_mrtt * 1000); | |
be8b88d7 PP |
1240 | |
1241 | return latency_ns; | |
1242 | } | |
1243 | EXPORT_SYMBOL_GPL(cppc_get_transition_latency); |