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b94d5230
DW		 1/*
2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13#include <linux/list_sort.h>
14#include <linux/libnvdimm.h>
15#include <linux/module.h>
047fc8a1 16#include <linux/mutex.h>
62232e45 17#include <linux/ndctl.h>
b94d5230
DW		 18#include <linux/list.h>
19#include <linux/acpi.h>
eaf96153 20#include <linux/sort.h>
c2ad2954 21#include <linux/pmem.h>
047fc8a1 22#include <linux/io.h>
b94d5230
DW		 23#include "nfit.h"
24
047fc8a1
RZ		 25/*
26 * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is
27 * irrelevant.
28 */
29#include <asm-generic/io-64-nonatomic-hi-lo.h>
30
4d88a97a
DW		 31static bool force_enable_dimms;
32module_param(force_enable_dimms, bool, S_IRUGO|S_IWUSR);
33MODULE_PARM_DESC(force_enable_dimms, "Ignore _STA (ACPI DIMM device) status");
34
b94d5230
DW		 35static u8 nfit_uuid[NFIT_UUID_MAX][16];
36
6bc75619 37const u8 *to_nfit_uuid(enum nfit_uuids id)
b94d5230
DW		 38{
39 return nfit_uuid[id];
40}
6bc75619 41EXPORT_SYMBOL(to_nfit_uuid);
b94d5230 42
62232e45
DW		 43static struct acpi_nfit_desc *to_acpi_nfit_desc(
44 struct nvdimm_bus_descriptor *nd_desc)
45{
46 return container_of(nd_desc, struct acpi_nfit_desc, nd_desc);
47}
48
49static struct acpi_device *to_acpi_dev(struct acpi_nfit_desc *acpi_desc)
50{
51 struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
52
53 /*
54 * If provider == 'ACPI.NFIT' we can assume 'dev' is a struct
55 * acpi_device.
56 */
57 if (!nd_desc->provider_name
58 || strcmp(nd_desc->provider_name, "ACPI.NFIT") != 0)
59 return NULL;
60
61 return to_acpi_device(acpi_desc->dev);
62}
63
b94d5230
DW		 64static int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc,
65 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
66 unsigned int buf_len)
67{
62232e45
DW		 68 struct acpi_nfit_desc *acpi_desc = to_acpi_nfit_desc(nd_desc);
69 const struct nd_cmd_desc *desc = NULL;
70 union acpi_object in_obj, in_buf, *out_obj;
71 struct device *dev = acpi_desc->dev;
72 const char *cmd_name, *dimm_name;
73 unsigned long dsm_mask;
74 acpi_handle handle;
75 const u8 *uuid;
76 u32 offset;
77 int rc, i;
78
79 if (nvdimm) {
80 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
81 struct acpi_device *adev = nfit_mem->adev;
82
83 if (!adev)
84 return -ENOTTY;
047fc8a1 85 dimm_name = nvdimm_name(nvdimm);
62232e45
DW		 86 cmd_name = nvdimm_cmd_name(cmd);
87 dsm_mask = nfit_mem->dsm_mask;
88 desc = nd_cmd_dimm_desc(cmd);
89 uuid = to_nfit_uuid(NFIT_DEV_DIMM);
90 handle = adev->handle;
91 } else {
92 struct acpi_device *adev = to_acpi_dev(acpi_desc);
93
94 cmd_name = nvdimm_bus_cmd_name(cmd);
95 dsm_mask = nd_desc->dsm_mask;
96 desc = nd_cmd_bus_desc(cmd);
97 uuid = to_nfit_uuid(NFIT_DEV_BUS);
98 handle = adev->handle;
99 dimm_name = "bus";
100 }
101
102 if (!desc || (cmd && (desc->out_num + desc->in_num == 0)))
103 return -ENOTTY;
104
105 if (!test_bit(cmd, &dsm_mask))
106 return -ENOTTY;
107
108 in_obj.type = ACPI_TYPE_PACKAGE;
109 in_obj.package.count = 1;
110 in_obj.package.elements = &in_buf;
111 in_buf.type = ACPI_TYPE_BUFFER;
112 in_buf.buffer.pointer = buf;
113 in_buf.buffer.length = 0;
114
115 /* libnvdimm has already validated the input envelope */
116 for (i = 0; i < desc->in_num; i++)
117 in_buf.buffer.length += nd_cmd_in_size(nvdimm, cmd, desc,
118 i, buf);
119
120 if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) {
121 dev_dbg(dev, "%s:%s cmd: %s input length: %d\n", __func__,
122 dimm_name, cmd_name, in_buf.buffer.length);
123 print_hex_dump_debug(cmd_name, DUMP_PREFIX_OFFSET, 4,
124 4, in_buf.buffer.pointer, min_t(u32, 128,
125 in_buf.buffer.length), true);
126 }
127
128 out_obj = acpi_evaluate_dsm(handle, uuid, 1, cmd, &in_obj);
129 if (!out_obj) {
130 dev_dbg(dev, "%s:%s _DSM failed cmd: %s\n", __func__, dimm_name,
131 cmd_name);
132 return -EINVAL;
133 }
134
135 if (out_obj->package.type != ACPI_TYPE_BUFFER) {
136 dev_dbg(dev, "%s:%s unexpected output object type cmd: %s type: %d\n",
137 __func__, dimm_name, cmd_name, out_obj->type);
138 rc = -EINVAL;
139 goto out;
140 }
141
142 if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) {
143 dev_dbg(dev, "%s:%s cmd: %s output length: %d\n", __func__,
144 dimm_name, cmd_name, out_obj->buffer.length);
145 print_hex_dump_debug(cmd_name, DUMP_PREFIX_OFFSET, 4,
146 4, out_obj->buffer.pointer, min_t(u32, 128,
147 out_obj->buffer.length), true);
148 }
149
150 for (i = 0, offset = 0; i < desc->out_num; i++) {
151 u32 out_size = nd_cmd_out_size(nvdimm, cmd, desc, i, buf,
152 (u32 *) out_obj->buffer.pointer);
153
154 if (offset + out_size > out_obj->buffer.length) {
155 dev_dbg(dev, "%s:%s output object underflow cmd: %s field: %d\n",
156 __func__, dimm_name, cmd_name, i);
157 break;
158 }
159
160 if (in_buf.buffer.length + offset + out_size > buf_len) {
161 dev_dbg(dev, "%s:%s output overrun cmd: %s field: %d\n",
162 __func__, dimm_name, cmd_name, i);
163 rc = -ENXIO;
164 goto out;
165 }
166 memcpy(buf + in_buf.buffer.length + offset,
167 out_obj->buffer.pointer + offset, out_size);
168 offset += out_size;
169 }
170 if (offset + in_buf.buffer.length < buf_len) {
171 if (i >= 1) {
172 /*
173 * status valid, return the number of bytes left
174 * unfilled in the output buffer
175 */
176 rc = buf_len - offset - in_buf.buffer.length;
177 } else {
178 dev_err(dev, "%s:%s underrun cmd: %s buf_len: %d out_len: %d\n",
179 __func__, dimm_name, cmd_name, buf_len,
180 offset);
181 rc = -ENXIO;
182 }
183 } else
184 rc = 0;
185
186 out:
187 ACPI_FREE(out_obj);
188
189 return rc;
b94d5230
DW		 190}
191
192static const char *spa_type_name(u16 type)
193{
194 static const char *to_name[] = {
195 [NFIT_SPA_VOLATILE] = "volatile",
196 [NFIT_SPA_PM] = "pmem",
197 [NFIT_SPA_DCR] = "dimm-control-region",
198 [NFIT_SPA_BDW] = "block-data-window",
199 [NFIT_SPA_VDISK] = "volatile-disk",
200 [NFIT_SPA_VCD] = "volatile-cd",
201 [NFIT_SPA_PDISK] = "persistent-disk",
202 [NFIT_SPA_PCD] = "persistent-cd",
203
204 };
205
206 if (type > NFIT_SPA_PCD)
207 return "unknown";
208
209 return to_name[type];
210}
211
212static int nfit_spa_type(struct acpi_nfit_system_address *spa)
213{
214 int i;
215
216 for (i = 0; i < NFIT_UUID_MAX; i++)
217 if (memcmp(to_nfit_uuid(i), spa->range_guid, 16) == 0)
218 return i;
219 return -1;
220}
221
222static bool add_spa(struct acpi_nfit_desc *acpi_desc,
223 struct acpi_nfit_system_address *spa)
224{
225 struct device *dev = acpi_desc->dev;
226 struct nfit_spa *nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa),
227 GFP_KERNEL);
228
229 if (!nfit_spa)
230 return false;
231 INIT_LIST_HEAD(&nfit_spa->list);
232 nfit_spa->spa = spa;
233 list_add_tail(&nfit_spa->list, &acpi_desc->spas);
234 dev_dbg(dev, "%s: spa index: %d type: %s\n", __func__,
235 spa->range_index,
236 spa_type_name(nfit_spa_type(spa)));
237 return true;
238}
239
240static bool add_memdev(struct acpi_nfit_desc *acpi_desc,
241 struct acpi_nfit_memory_map *memdev)
242{
243 struct device *dev = acpi_desc->dev;
244 struct nfit_memdev *nfit_memdev = devm_kzalloc(dev,
245 sizeof(*nfit_memdev), GFP_KERNEL);
246
247 if (!nfit_memdev)
248 return false;
249 INIT_LIST_HEAD(&nfit_memdev->list);
250 nfit_memdev->memdev = memdev;
251 list_add_tail(&nfit_memdev->list, &acpi_desc->memdevs);
252 dev_dbg(dev, "%s: memdev handle: %#x spa: %d dcr: %d\n",
253 __func__, memdev->device_handle, memdev->range_index,
254 memdev->region_index);
255 return true;
256}
257
258static bool add_dcr(struct acpi_nfit_desc *acpi_desc,
259 struct acpi_nfit_control_region *dcr)
260{
261 struct device *dev = acpi_desc->dev;
262 struct nfit_dcr *nfit_dcr = devm_kzalloc(dev, sizeof(*nfit_dcr),
263 GFP_KERNEL);
264
265 if (!nfit_dcr)
266 return false;
267 INIT_LIST_HEAD(&nfit_dcr->list);
268 nfit_dcr->dcr = dcr;
269 list_add_tail(&nfit_dcr->list, &acpi_desc->dcrs);
270 dev_dbg(dev, "%s: dcr index: %d windows: %d\n", __func__,
271 dcr->region_index, dcr->windows);
272 return true;
273}
274
275static bool add_bdw(struct acpi_nfit_desc *acpi_desc,
276 struct acpi_nfit_data_region *bdw)
277{
278 struct device *dev = acpi_desc->dev;
279 struct nfit_bdw *nfit_bdw = devm_kzalloc(dev, sizeof(*nfit_bdw),
280 GFP_KERNEL);
281
282 if (!nfit_bdw)
283 return false;
284 INIT_LIST_HEAD(&nfit_bdw->list);
285 nfit_bdw->bdw = bdw;
286 list_add_tail(&nfit_bdw->list, &acpi_desc->bdws);
287 dev_dbg(dev, "%s: bdw dcr: %d windows: %d\n", __func__,
288 bdw->region_index, bdw->windows);
289 return true;
290}
291
047fc8a1
RZ		 292static bool add_idt(struct acpi_nfit_desc *acpi_desc,
293 struct acpi_nfit_interleave *idt)
294{
295 struct device *dev = acpi_desc->dev;
296 struct nfit_idt *nfit_idt = devm_kzalloc(dev, sizeof(*nfit_idt),
297 GFP_KERNEL);
298
299 if (!nfit_idt)
300 return false;
301 INIT_LIST_HEAD(&nfit_idt->list);
302 nfit_idt->idt = idt;
303 list_add_tail(&nfit_idt->list, &acpi_desc->idts);
304 dev_dbg(dev, "%s: idt index: %d num_lines: %d\n", __func__,
305 idt->interleave_index, idt->line_count);
306 return true;
307}
308
c2ad2954
RZ		 309static bool add_flush(struct acpi_nfit_desc *acpi_desc,
310 struct acpi_nfit_flush_address *flush)
311{
312 struct device *dev = acpi_desc->dev;
313 struct nfit_flush *nfit_flush = devm_kzalloc(dev, sizeof(*nfit_flush),
314 GFP_KERNEL);
315
316 if (!nfit_flush)
317 return false;
318 INIT_LIST_HEAD(&nfit_flush->list);
319 nfit_flush->flush = flush;
320 list_add_tail(&nfit_flush->list, &acpi_desc->flushes);
321 dev_dbg(dev, "%s: nfit_flush handle: %d hint_count: %d\n", __func__,
322 flush->device_handle, flush->hint_count);
323 return true;
324}
325
b94d5230
DW		 326static void *add_table(struct acpi_nfit_desc *acpi_desc, void *table,
327 const void *end)
328{
329 struct device *dev = acpi_desc->dev;
330 struct acpi_nfit_header *hdr;
331 void *err = ERR_PTR(-ENOMEM);
332
333 if (table >= end)
334 return NULL;
335
336 hdr = table;
337 switch (hdr->type) {
338 case ACPI_NFIT_TYPE_SYSTEM_ADDRESS:
339 if (!add_spa(acpi_desc, table))
340 return err;
341 break;
342 case ACPI_NFIT_TYPE_MEMORY_MAP:
343 if (!add_memdev(acpi_desc, table))
344 return err;
345 break;
346 case ACPI_NFIT_TYPE_CONTROL_REGION:
347 if (!add_dcr(acpi_desc, table))
348 return err;
349 break;
350 case ACPI_NFIT_TYPE_DATA_REGION:
351 if (!add_bdw(acpi_desc, table))
352 return err;
353 break;
b94d5230 354 case ACPI_NFIT_TYPE_INTERLEAVE:
047fc8a1
RZ		 355 if (!add_idt(acpi_desc, table))
356 return err;
b94d5230
DW		 357 break;
358 case ACPI_NFIT_TYPE_FLUSH_ADDRESS:
c2ad2954
RZ		 359 if (!add_flush(acpi_desc, table))
360 return err;
b94d5230
DW		 361 break;
362 case ACPI_NFIT_TYPE_SMBIOS:
363 dev_dbg(dev, "%s: smbios\n", __func__);
364 break;
365 default:
366 dev_err(dev, "unknown table '%d' parsing nfit\n", hdr->type);
367 break;
368 }
369
370 return table + hdr->length;
371}
372
373static void nfit_mem_find_spa_bdw(struct acpi_nfit_desc *acpi_desc,
374 struct nfit_mem *nfit_mem)
375{
376 u32 device_handle = __to_nfit_memdev(nfit_mem)->device_handle;
377 u16 dcr = nfit_mem->dcr->region_index;
378 struct nfit_spa *nfit_spa;
379
380 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
381 u16 range_index = nfit_spa->spa->range_index;
382 int type = nfit_spa_type(nfit_spa->spa);
383 struct nfit_memdev *nfit_memdev;
384
385 if (type != NFIT_SPA_BDW)
386 continue;
387
388 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
389 if (nfit_memdev->memdev->range_index != range_index)
390 continue;
391 if (nfit_memdev->memdev->device_handle != device_handle)
392 continue;
393 if (nfit_memdev->memdev->region_index != dcr)
394 continue;
395
396 nfit_mem->spa_bdw = nfit_spa->spa;
397 return;
398 }
399 }
400
401 dev_dbg(acpi_desc->dev, "SPA-BDW not found for SPA-DCR %d\n",
402 nfit_mem->spa_dcr->range_index);
403 nfit_mem->bdw = NULL;
404}
405
406static int nfit_mem_add(struct acpi_nfit_desc *acpi_desc,
407 struct nfit_mem *nfit_mem, struct acpi_nfit_system_address *spa)
408{
409 u16 dcr = __to_nfit_memdev(nfit_mem)->region_index;
047fc8a1 410 struct nfit_memdev *nfit_memdev;
c2ad2954 411 struct nfit_flush *nfit_flush;
b94d5230
DW		 412 struct nfit_dcr *nfit_dcr;
413 struct nfit_bdw *nfit_bdw;
047fc8a1
RZ		 414 struct nfit_idt *nfit_idt;
415 u16 idt_idx, range_index;
b94d5230
DW		 416
417 list_for_each_entry(nfit_dcr, &acpi_desc->dcrs, list) {
418 if (nfit_dcr->dcr->region_index != dcr)
419 continue;
420 nfit_mem->dcr = nfit_dcr->dcr;
421 break;
422 }
423
424 if (!nfit_mem->dcr) {
425 dev_dbg(acpi_desc->dev, "SPA %d missing:%s%s\n",
426 spa->range_index, __to_nfit_memdev(nfit_mem)
427 ? "" : " MEMDEV", nfit_mem->dcr ? "" : " DCR");
428 return -ENODEV;
429 }
430
431 /*
432 * We've found enough to create an nvdimm, optionally
433 * find an associated BDW
434 */
435 list_add(&nfit_mem->list, &acpi_desc->dimms);
436
437 list_for_each_entry(nfit_bdw, &acpi_desc->bdws, list) {
438 if (nfit_bdw->bdw->region_index != dcr)
439 continue;
440 nfit_mem->bdw = nfit_bdw->bdw;
441 break;
442 }
443
444 if (!nfit_mem->bdw)
445 return 0;
446
447 nfit_mem_find_spa_bdw(acpi_desc, nfit_mem);
047fc8a1
RZ		 448
449 if (!nfit_mem->spa_bdw)
450 return 0;
451
452 range_index = nfit_mem->spa_bdw->range_index;
453 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
454 if (nfit_memdev->memdev->range_index != range_index ||
455 nfit_memdev->memdev->region_index != dcr)
456 continue;
457 nfit_mem->memdev_bdw = nfit_memdev->memdev;
458 idt_idx = nfit_memdev->memdev->interleave_index;
459 list_for_each_entry(nfit_idt, &acpi_desc->idts, list) {
460 if (nfit_idt->idt->interleave_index != idt_idx)
461 continue;
462 nfit_mem->idt_bdw = nfit_idt->idt;
463 break;
464 }
c2ad2954
RZ		 465
466 list_for_each_entry(nfit_flush, &acpi_desc->flushes, list) {
467 if (nfit_flush->flush->device_handle !=
468 nfit_memdev->memdev->device_handle)
469 continue;
470 nfit_mem->nfit_flush = nfit_flush;
471 break;
472 }
047fc8a1
RZ		 473 break;
474 }
475
b94d5230
DW		 476 return 0;
477}
478
479static int nfit_mem_dcr_init(struct acpi_nfit_desc *acpi_desc,
480 struct acpi_nfit_system_address *spa)
481{
482 struct nfit_mem *nfit_mem, *found;
483 struct nfit_memdev *nfit_memdev;
484 int type = nfit_spa_type(spa);
485 u16 dcr;
486
487 switch (type) {
488 case NFIT_SPA_DCR:
489 case NFIT_SPA_PM:
490 break;
491 default:
492 return 0;
493 }
494
495 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
496 int rc;
497
498 if (nfit_memdev->memdev->range_index != spa->range_index)
499 continue;
500 found = NULL;
501 dcr = nfit_memdev->memdev->region_index;
502 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list)
503 if (__to_nfit_memdev(nfit_mem)->region_index == dcr) {
504 found = nfit_mem;
505 break;
506 }
507
508 if (found)
509 nfit_mem = found;
510 else {
511 nfit_mem = devm_kzalloc(acpi_desc->dev,
512 sizeof(*nfit_mem), GFP_KERNEL);
513 if (!nfit_mem)
514 return -ENOMEM;
515 INIT_LIST_HEAD(&nfit_mem->list);
516 }
517
518 if (type == NFIT_SPA_DCR) {
047fc8a1
RZ		 519 struct nfit_idt *nfit_idt;
520 u16 idt_idx;
521
b94d5230
DW		 522 /* multiple dimms may share a SPA when interleaved */
523 nfit_mem->spa_dcr = spa;
524 nfit_mem->memdev_dcr = nfit_memdev->memdev;
047fc8a1
RZ		 525 idt_idx = nfit_memdev->memdev->interleave_index;
526 list_for_each_entry(nfit_idt, &acpi_desc->idts, list) {
527 if (nfit_idt->idt->interleave_index != idt_idx)
528 continue;
529 nfit_mem->idt_dcr = nfit_idt->idt;
530 break;
531 }
b94d5230
DW		 532 } else {
533 /*
534 * A single dimm may belong to multiple SPA-PM
535 * ranges, record at least one in addition to
536 * any SPA-DCR range.
537 */
538 nfit_mem->memdev_pmem = nfit_memdev->memdev;
539 }
540
541 if (found)
542 continue;
543
544 rc = nfit_mem_add(acpi_desc, nfit_mem, spa);
545 if (rc)
546 return rc;
547 }
548
549 return 0;
550}
551
552static int nfit_mem_cmp(void *priv, struct list_head *_a, struct list_head *_b)
553{
554 struct nfit_mem *a = container_of(_a, typeof(*a), list);
555 struct nfit_mem *b = container_of(_b, typeof(*b), list);
556 u32 handleA, handleB;
557
558 handleA = __to_nfit_memdev(a)->device_handle;
559 handleB = __to_nfit_memdev(b)->device_handle;
560 if (handleA < handleB)
561 return -1;
562 else if (handleA > handleB)
563 return 1;
564 return 0;
565}
566
567static int nfit_mem_init(struct acpi_nfit_desc *acpi_desc)
568{
569 struct nfit_spa *nfit_spa;
570
571 /*
572 * For each SPA-DCR or SPA-PMEM address range find its
573 * corresponding MEMDEV(s). From each MEMDEV find the
574 * corresponding DCR. Then, if we're operating on a SPA-DCR,
575 * try to find a SPA-BDW and a corresponding BDW that references
576 * the DCR. Throw it all into an nfit_mem object. Note, that
577 * BDWs are optional.
578 */
579 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
580 int rc;
581
582 rc = nfit_mem_dcr_init(acpi_desc, nfit_spa->spa);
583 if (rc)
584 return rc;
585 }
586
587 list_sort(NULL, &acpi_desc->dimms, nfit_mem_cmp);
588
589 return 0;
590}
591
45def22c
DW		 592static ssize_t revision_show(struct device *dev,
593 struct device_attribute *attr, char *buf)
594{
595 struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
596 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
597 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
598
599 return sprintf(buf, "%d\n", acpi_desc->nfit->header.revision);
600}
601static DEVICE_ATTR_RO(revision);
602
603static struct attribute *acpi_nfit_attributes[] = {
604 &dev_attr_revision.attr,
605 NULL,
606};
607
608static struct attribute_group acpi_nfit_attribute_group = {
609 .name = "nfit",
610 .attrs = acpi_nfit_attributes,
611};
612
6bc75619 613const struct attribute_group *acpi_nfit_attribute_groups[] = {
45def22c
DW		 614 &nvdimm_bus_attribute_group,
615 &acpi_nfit_attribute_group,
616 NULL,
617};
6bc75619 618EXPORT_SYMBOL_GPL(acpi_nfit_attribute_groups);
45def22c 619
e6dfb2de
DW		 620static struct acpi_nfit_memory_map *to_nfit_memdev(struct device *dev)
621{
622 struct nvdimm *nvdimm = to_nvdimm(dev);
623 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
624
625 return __to_nfit_memdev(nfit_mem);
626}
627
628static struct acpi_nfit_control_region *to_nfit_dcr(struct device *dev)
629{
630 struct nvdimm *nvdimm = to_nvdimm(dev);
631 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
632
633 return nfit_mem->dcr;
634}
635
636static ssize_t handle_show(struct device *dev,
637 struct device_attribute *attr, char *buf)
638{
639 struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
640
641 return sprintf(buf, "%#x\n", memdev->device_handle);
642}
643static DEVICE_ATTR_RO(handle);
644
645static ssize_t phys_id_show(struct device *dev,
646 struct device_attribute *attr, char *buf)
647{
648 struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
649
650 return sprintf(buf, "%#x\n", memdev->physical_id);
651}
652static DEVICE_ATTR_RO(phys_id);
653
654static ssize_t vendor_show(struct device *dev,
655 struct device_attribute *attr, char *buf)
656{
657 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
658
659 return sprintf(buf, "%#x\n", dcr->vendor_id);
660}
661static DEVICE_ATTR_RO(vendor);
662
663static ssize_t rev_id_show(struct device *dev,
664 struct device_attribute *attr, char *buf)
665{
666 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
667
668 return sprintf(buf, "%#x\n", dcr->revision_id);
669}
670static DEVICE_ATTR_RO(rev_id);
671
672static ssize_t device_show(struct device *dev,
673 struct device_attribute *attr, char *buf)
674{
675 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
676
677 return sprintf(buf, "%#x\n", dcr->device_id);
678}
679static DEVICE_ATTR_RO(device);
680
681static ssize_t format_show(struct device *dev,
682 struct device_attribute *attr, char *buf)
683{
684 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
685
686 return sprintf(buf, "%#x\n", dcr->code);
687}
688static DEVICE_ATTR_RO(format);
689
690static ssize_t serial_show(struct device *dev,
691 struct device_attribute *attr, char *buf)
692{
693 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
694
695 return sprintf(buf, "%#x\n", dcr->serial_number);
696}
697static DEVICE_ATTR_RO(serial);
698
58138820
DW		 699static ssize_t flags_show(struct device *dev,
700 struct device_attribute *attr, char *buf)
701{
702 u16 flags = to_nfit_memdev(dev)->flags;
703
704 return sprintf(buf, "%s%s%s%s%s\n",
705 flags & ACPI_NFIT_MEM_SAVE_FAILED ? "save " : "",
706 flags & ACPI_NFIT_MEM_RESTORE_FAILED ? "restore " : "",
707 flags & ACPI_NFIT_MEM_FLUSH_FAILED ? "flush " : "",
708 flags & ACPI_NFIT_MEM_ARMED ? "arm " : "",
709 flags & ACPI_NFIT_MEM_HEALTH_OBSERVED ? "smart " : "");
710}
711static DEVICE_ATTR_RO(flags);
712
e6dfb2de
DW		 713static struct attribute *acpi_nfit_dimm_attributes[] = {
714 &dev_attr_handle.attr,
715 &dev_attr_phys_id.attr,
716 &dev_attr_vendor.attr,
717 &dev_attr_device.attr,
718 &dev_attr_format.attr,
719 &dev_attr_serial.attr,
720 &dev_attr_rev_id.attr,
58138820 721 &dev_attr_flags.attr,
e6dfb2de
DW		 722 NULL,
723};
724
725static umode_t acpi_nfit_dimm_attr_visible(struct kobject *kobj,
726 struct attribute *a, int n)
727{
728 struct device *dev = container_of(kobj, struct device, kobj);
729
730 if (to_nfit_dcr(dev))
731 return a->mode;
732 else
733 return 0;
734}
735
736static struct attribute_group acpi_nfit_dimm_attribute_group = {
737 .name = "nfit",
738 .attrs = acpi_nfit_dimm_attributes,
739 .is_visible = acpi_nfit_dimm_attr_visible,
740};
741
742static const struct attribute_group *acpi_nfit_dimm_attribute_groups[] = {
62232e45 743 &nvdimm_attribute_group,
4d88a97a 744 &nd_device_attribute_group,
e6dfb2de
DW		 745 &acpi_nfit_dimm_attribute_group,
746 NULL,
747};
748
749static struct nvdimm *acpi_nfit_dimm_by_handle(struct acpi_nfit_desc *acpi_desc,
750 u32 device_handle)
751{
752 struct nfit_mem *nfit_mem;
753
754 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list)
755 if (__to_nfit_memdev(nfit_mem)->device_handle == device_handle)
756 return nfit_mem->nvdimm;
757
758 return NULL;
759}
760
62232e45
DW		 761static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc,
762 struct nfit_mem *nfit_mem, u32 device_handle)
763{
764 struct acpi_device *adev, *adev_dimm;
765 struct device *dev = acpi_desc->dev;
766 const u8 *uuid = to_nfit_uuid(NFIT_DEV_DIMM);
60e95f43 767 int i;
62232e45
DW		 768
769 nfit_mem->dsm_mask = acpi_desc->dimm_dsm_force_en;
770 adev = to_acpi_dev(acpi_desc);
771 if (!adev)
772 return 0;
773
774 adev_dimm = acpi_find_child_device(adev, device_handle, false);
775 nfit_mem->adev = adev_dimm;
776 if (!adev_dimm) {
777 dev_err(dev, "no ACPI.NFIT device with _ADR %#x, disabling...\n",
778 device_handle);
4d88a97a 779 return force_enable_dimms ? 0 : -ENODEV;
62232e45
DW		 780 }
781
62232e45
DW		 782 for (i = ND_CMD_SMART; i <= ND_CMD_VENDOR; i++)
783 if (acpi_check_dsm(adev_dimm->handle, uuid, 1, 1ULL << i))
784 set_bit(i, &nfit_mem->dsm_mask);
785
60e95f43 786 return 0;
62232e45
DW		 787}
788
e6dfb2de
DW		 789static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
790{
791 struct nfit_mem *nfit_mem;
4d88a97a 792 int dimm_count = 0;
e6dfb2de
DW		 793
794 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
795 struct nvdimm *nvdimm;
796 unsigned long flags = 0;
797 u32 device_handle;
58138820 798 u16 mem_flags;
62232e45 799 int rc;
e6dfb2de
DW		 800
801 device_handle = __to_nfit_memdev(nfit_mem)->device_handle;
802 nvdimm = acpi_nfit_dimm_by_handle(acpi_desc, device_handle);
803 if (nvdimm) {
804 /*
805 * If for some reason we find multiple DCRs the
806 * first one wins
807 */
808 dev_err(acpi_desc->dev, "duplicate DCR detected: %s\n",
809 nvdimm_name(nvdimm));
810 continue;
811 }
812
813 if (nfit_mem->bdw && nfit_mem->memdev_pmem)
814 flags |= NDD_ALIASING;
815
58138820
DW		 816 mem_flags = __to_nfit_memdev(nfit_mem)->flags;
817 if (mem_flags & ACPI_NFIT_MEM_ARMED)
818 flags |= NDD_UNARMED;
819
62232e45
DW		 820 rc = acpi_nfit_add_dimm(acpi_desc, nfit_mem, device_handle);
821 if (rc)
822 continue;
823
e6dfb2de 824 nvdimm = nvdimm_create(acpi_desc->nvdimm_bus, nfit_mem,
62232e45
DW		 825 acpi_nfit_dimm_attribute_groups,
826 flags, &nfit_mem->dsm_mask);
e6dfb2de
DW		 827 if (!nvdimm)
828 return -ENOMEM;
829
830 nfit_mem->nvdimm = nvdimm;
4d88a97a 831 dimm_count++;
58138820
DW		 832
833 if ((mem_flags & ACPI_NFIT_MEM_FAILED_MASK) == 0)
834 continue;
835
836 dev_info(acpi_desc->dev, "%s: failed: %s%s%s%s\n",
837 nvdimm_name(nvdimm),
838 mem_flags & ACPI_NFIT_MEM_SAVE_FAILED ? "save " : "",
839 mem_flags & ACPI_NFIT_MEM_RESTORE_FAILED ? "restore " : "",
840 mem_flags & ACPI_NFIT_MEM_FLUSH_FAILED ? "flush " : "",
841 mem_flags & ACPI_NFIT_MEM_ARMED ? "arm " : "");
842
e6dfb2de
DW		 843 }
844
4d88a97a 845 return nvdimm_bus_check_dimm_count(acpi_desc->nvdimm_bus, dimm_count);
e6dfb2de
DW		 846}
847
62232e45
DW		 848static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc)
849{
850 struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
851 const u8 *uuid = to_nfit_uuid(NFIT_DEV_BUS);
852 struct acpi_device *adev;
853 int i;
854
39c686b8 855 nd_desc->dsm_mask = acpi_desc->bus_dsm_force_en;
62232e45
DW		 856 adev = to_acpi_dev(acpi_desc);
857 if (!adev)
858 return;
859
860 for (i = ND_CMD_ARS_CAP; i <= ND_CMD_ARS_STATUS; i++)
861 if (acpi_check_dsm(adev->handle, uuid, 1, 1ULL << i))
862 set_bit(i, &nd_desc->dsm_mask);
863}
864
1f7df6f8
DW		 865static ssize_t range_index_show(struct device *dev,
866 struct device_attribute *attr, char *buf)
867{
868 struct nd_region *nd_region = to_nd_region(dev);
869 struct nfit_spa *nfit_spa = nd_region_provider_data(nd_region);
870
871 return sprintf(buf, "%d\n", nfit_spa->spa->range_index);
872}
873static DEVICE_ATTR_RO(range_index);
874
875static struct attribute *acpi_nfit_region_attributes[] = {
876 &dev_attr_range_index.attr,
877 NULL,
878};
879
880static struct attribute_group acpi_nfit_region_attribute_group = {
881 .name = "nfit",
882 .attrs = acpi_nfit_region_attributes,
883};
884
885static const struct attribute_group *acpi_nfit_region_attribute_groups[] = {
886 &nd_region_attribute_group,
887 &nd_mapping_attribute_group,
3d88002e 888 &nd_device_attribute_group,
74ae66c3 889 &nd_numa_attribute_group,
1f7df6f8
DW		 890 &acpi_nfit_region_attribute_group,
891 NULL,
892};
893
eaf96153
DW		 894/* enough info to uniquely specify an interleave set */
895struct nfit_set_info {
896 struct nfit_set_info_map {
897 u64 region_offset;
898 u32 serial_number;
899 u32 pad;
900 } mapping[0];
901};
902
903static size_t sizeof_nfit_set_info(int num_mappings)
904{
905 return sizeof(struct nfit_set_info)
906 + num_mappings * sizeof(struct nfit_set_info_map);
907}
908
909static int cmp_map(const void *m0, const void *m1)
910{
911 const struct nfit_set_info_map *map0 = m0;
912 const struct nfit_set_info_map *map1 = m1;
913
914 return memcmp(&map0->region_offset, &map1->region_offset,
915 sizeof(u64));
916}
917
918/* Retrieve the nth entry referencing this spa */
919static struct acpi_nfit_memory_map *memdev_from_spa(
920 struct acpi_nfit_desc *acpi_desc, u16 range_index, int n)
921{
922 struct nfit_memdev *nfit_memdev;
923
924 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list)
925 if (nfit_memdev->memdev->range_index == range_index)
926 if (n-- == 0)
927 return nfit_memdev->memdev;
928 return NULL;
929}
930
931static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,
932 struct nd_region_desc *ndr_desc,
933 struct acpi_nfit_system_address *spa)
934{
935 int i, spa_type = nfit_spa_type(spa);
936 struct device *dev = acpi_desc->dev;
937 struct nd_interleave_set *nd_set;
938 u16 nr = ndr_desc->num_mappings;
939 struct nfit_set_info *info;
940
941 if (spa_type == NFIT_SPA_PM || spa_type == NFIT_SPA_VOLATILE)
942 /* pass */;
943 else
944 return 0;
945
946 nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);
947 if (!nd_set)
948 return -ENOMEM;
949
950 info = devm_kzalloc(dev, sizeof_nfit_set_info(nr), GFP_KERNEL);
951 if (!info)
952 return -ENOMEM;
953 for (i = 0; i < nr; i++) {
954 struct nd_mapping *nd_mapping = &ndr_desc->nd_mapping[i];
955 struct nfit_set_info_map *map = &info->mapping[i];
956 struct nvdimm *nvdimm = nd_mapping->nvdimm;
957 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
958 struct acpi_nfit_memory_map *memdev = memdev_from_spa(acpi_desc,
959 spa->range_index, i);
960
961 if (!memdev || !nfit_mem->dcr) {
962 dev_err(dev, "%s: failed to find DCR\n", __func__);
963 return -ENODEV;
964 }
965
966 map->region_offset = memdev->region_offset;
967 map->serial_number = nfit_mem->dcr->serial_number;
968 }
969
970 sort(&info->mapping[0], nr, sizeof(struct nfit_set_info_map),
971 cmp_map, NULL);
972 nd_set->cookie = nd_fletcher64(info, sizeof_nfit_set_info(nr), 0);
973 ndr_desc->nd_set = nd_set;
974 devm_kfree(dev, info);
975
976 return 0;
977}
978
047fc8a1
RZ		 979static u64 to_interleave_offset(u64 offset, struct nfit_blk_mmio *mmio)
980{
981 struct acpi_nfit_interleave *idt = mmio->idt;
982 u32 sub_line_offset, line_index, line_offset;
983 u64 line_no, table_skip_count, table_offset;
984
985 line_no = div_u64_rem(offset, mmio->line_size, &sub_line_offset);
986 table_skip_count = div_u64_rem(line_no, mmio->num_lines, &line_index);
987 line_offset = idt->line_offset[line_index]
988 * mmio->line_size;
989 table_offset = table_skip_count * mmio->table_size;
990
991 return mmio->base_offset + line_offset + table_offset + sub_line_offset;
992}
993
c2ad2954
RZ		 994static void wmb_blk(struct nfit_blk *nfit_blk)
995{
996
997 if (nfit_blk->nvdimm_flush) {
998 /*
999 * The first wmb() is needed to 'sfence' all previous writes
1000 * such that they are architecturally visible for the platform
1001 * buffer flush. Note that we've already arranged for pmem
1002 * writes to avoid the cache via arch_memcpy_to_pmem(). The
1003 * final wmb() ensures ordering for the NVDIMM flush write.
1004 */
1005 wmb();
1006 writeq(1, nfit_blk->nvdimm_flush);
1007 wmb();
1008 } else
1009 wmb_pmem();
1010}
1011
047fc8a1
RZ		 1012static u64 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw)
1013{
1014 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
1015 u64 offset = nfit_blk->stat_offset + mmio->size * bw;
1016
1017 if (mmio->num_lines)
1018 offset = to_interleave_offset(offset, mmio);
1019
67a3e8fe 1020 return readq(mmio->addr.base + offset);
047fc8a1
RZ		 1021}
1022
1023static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
1024 resource_size_t dpa, unsigned int len, unsigned int write)
1025{
1026 u64 cmd, offset;
1027 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
1028
1029 enum {
1030 BCW_OFFSET_MASK = (1ULL << 48)-1,
1031 BCW_LEN_SHIFT = 48,
1032 BCW_LEN_MASK = (1ULL << 8) - 1,
1033 BCW_CMD_SHIFT = 56,
1034 };
1035
1036 cmd = (dpa >> L1_CACHE_SHIFT) & BCW_OFFSET_MASK;
1037 len = len >> L1_CACHE_SHIFT;
1038 cmd |= ((u64) len & BCW_LEN_MASK) << BCW_LEN_SHIFT;
1039 cmd |= ((u64) write) << BCW_CMD_SHIFT;
1040
1041 offset = nfit_blk->cmd_offset + mmio->size * bw;
1042 if (mmio->num_lines)
1043 offset = to_interleave_offset(offset, mmio);
1044
67a3e8fe 1045 writeq(cmd, mmio->addr.base + offset);
c2ad2954 1046 wmb_blk(nfit_blk);
f0f2c072
RZ		 1047
1048 if (nfit_blk->dimm_flags & ND_BLK_DCR_LATCH)
67a3e8fe 1049 readq(mmio->addr.base + offset);
047fc8a1
RZ		 1050}
1051
1052static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
1053 resource_size_t dpa, void *iobuf, size_t len, int rw,
1054 unsigned int lane)
1055{
1056 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1057 unsigned int copied = 0;
1058 u64 base_offset;
1059 int rc;
1060
1061 base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES
1062 + lane * mmio->size;
047fc8a1
RZ		 1063 write_blk_ctl(nfit_blk, lane, dpa, len, rw);
1064 while (len) {
1065 unsigned int c;
1066 u64 offset;
1067
1068 if (mmio->num_lines) {
1069 u32 line_offset;
1070
1071 offset = to_interleave_offset(base_offset + copied,
1072 mmio);
1073 div_u64_rem(offset, mmio->line_size, &line_offset);
1074 c = min_t(size_t, len, mmio->line_size - line_offset);
1075 } else {
1076 offset = base_offset + nfit_blk->bdw_offset;
1077 c = len;
1078 }
1079
1080 if (rw)
67a3e8fe 1081 memcpy_to_pmem(mmio->addr.aperture + offset,
c2ad2954 1082 iobuf + copied, c);
67a3e8fe
RZ		 1083 else {
1084 if (nfit_blk->dimm_flags & ND_BLK_READ_FLUSH)
1085 mmio_flush_range((void __force *)
1086 mmio->addr.aperture + offset, c);
1087
c2ad2954 1088 memcpy_from_pmem(iobuf + copied,
67a3e8fe
RZ		 1089 mmio->addr.aperture + offset, c);
1090 }
047fc8a1
RZ		 1091
1092 copied += c;
1093 len -= c;
1094 }
c2ad2954
RZ		 1095
1096 if (rw)
1097 wmb_blk(nfit_blk);
1098
047fc8a1
RZ		 1099 rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0;
1100 return rc;
1101}
1102
1103static int acpi_nfit_blk_region_do_io(struct nd_blk_region *ndbr,
1104 resource_size_t dpa, void *iobuf, u64 len, int rw)
1105{
1106 struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr);
1107 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1108 struct nd_region *nd_region = nfit_blk->nd_region;
1109 unsigned int lane, copied = 0;
1110 int rc = 0;
1111
1112 lane = nd_region_acquire_lane(nd_region);
1113 while (len) {
1114 u64 c = min(len, mmio->size);
1115
1116 rc = acpi_nfit_blk_single_io(nfit_blk, dpa + copied,
1117 iobuf + copied, c, rw, lane);
1118 if (rc)
1119 break;
1120
1121 copied += c;
1122 len -= c;
1123 }
1124 nd_region_release_lane(nd_region, lane);
1125
1126 return rc;
1127}
1128
1129static void nfit_spa_mapping_release(struct kref *kref)
1130{
1131 struct nfit_spa_mapping *spa_map = to_spa_map(kref);
1132 struct acpi_nfit_system_address *spa = spa_map->spa;
1133 struct acpi_nfit_desc *acpi_desc = spa_map->acpi_desc;
1134
1135 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1136 dev_dbg(acpi_desc->dev, "%s: SPA%d\n", __func__, spa->range_index);
67a3e8fe
RZ		 1137 if (spa_map->type == SPA_MAP_APERTURE)
1138 memunmap((void __force *)spa_map->addr.aperture);
1139 else
1140 iounmap(spa_map->addr.base);
047fc8a1
RZ		 1141 release_mem_region(spa->address, spa->length);
1142 list_del(&spa_map->list);
1143 kfree(spa_map);
1144}
1145
1146static struct nfit_spa_mapping *find_spa_mapping(
1147 struct acpi_nfit_desc *acpi_desc,
1148 struct acpi_nfit_system_address *spa)
1149{
1150 struct nfit_spa_mapping *spa_map;
1151
1152 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1153 list_for_each_entry(spa_map, &acpi_desc->spa_maps, list)
1154 if (spa_map->spa == spa)
1155 return spa_map;
1156
1157 return NULL;
1158}
1159
1160static void nfit_spa_unmap(struct acpi_nfit_desc *acpi_desc,
1161 struct acpi_nfit_system_address *spa)
1162{
1163 struct nfit_spa_mapping *spa_map;
1164
1165 mutex_lock(&acpi_desc->spa_map_mutex);
1166 spa_map = find_spa_mapping(acpi_desc, spa);
1167
1168 if (spa_map)
1169 kref_put(&spa_map->kref, nfit_spa_mapping_release);
1170 mutex_unlock(&acpi_desc->spa_map_mutex);
1171}
1172
1173static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
c2ad2954 1174 struct acpi_nfit_system_address *spa, enum spa_map_type type)
047fc8a1
RZ		 1175{
1176 resource_size_t start = spa->address;
1177 resource_size_t n = spa->length;
1178 struct nfit_spa_mapping *spa_map;
1179 struct resource *res;
1180
1181 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1182
1183 spa_map = find_spa_mapping(acpi_desc, spa);
1184 if (spa_map) {
1185 kref_get(&spa_map->kref);
67a3e8fe 1186 return spa_map->addr.base;
047fc8a1
RZ		 1187 }
1188
1189 spa_map = kzalloc(sizeof(*spa_map), GFP_KERNEL);
1190 if (!spa_map)
1191 return NULL;
1192
1193 INIT_LIST_HEAD(&spa_map->list);
1194 spa_map->spa = spa;
1195 kref_init(&spa_map->kref);
1196 spa_map->acpi_desc = acpi_desc;
1197
1198 res = request_mem_region(start, n, dev_name(acpi_desc->dev));
1199 if (!res)
1200 goto err_mem;
1201
67a3e8fe
RZ		 1202 spa_map->type = type;
1203 if (type == SPA_MAP_APERTURE)
1204 spa_map->addr.aperture = (void __pmem *)memremap(start, n,
1205 ARCH_MEMREMAP_PMEM);
1206 else
1207 spa_map->addr.base = ioremap_nocache(start, n);
1208
c2ad2954 1209
67a3e8fe 1210 if (!spa_map->addr.base)
047fc8a1
RZ		 1211 goto err_map;
1212
1213 list_add_tail(&spa_map->list, &acpi_desc->spa_maps);
67a3e8fe 1214 return spa_map->addr.base;
047fc8a1
RZ		 1215
1216 err_map:
1217 release_mem_region(start, n);
1218 err_mem:
1219 kfree(spa_map);
1220 return NULL;
1221}
1222
1223/**
1224 * nfit_spa_map - interleave-aware managed-mappings of acpi_nfit_system_address ranges
1225 * @nvdimm_bus: NFIT-bus that provided the spa table entry
1226 * @nfit_spa: spa table to map
c2ad2954 1227 * @type: aperture or control region
047fc8a1
RZ		 1228 *
1229 * In the case where block-data-window apertures and
1230 * dimm-control-regions are interleaved they will end up sharing a
1231 * single request_mem_region() + ioremap() for the address range. In
1232 * the style of devm nfit_spa_map() mappings are automatically dropped
1233 * when all region devices referencing the same mapping are disabled /
1234 * unbound.
1235 */
1236static void __iomem *nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
c2ad2954 1237 struct acpi_nfit_system_address *spa, enum spa_map_type type)
047fc8a1
RZ		 1238{
1239 void __iomem *iomem;
1240
1241 mutex_lock(&acpi_desc->spa_map_mutex);
c2ad2954 1242 iomem = __nfit_spa_map(acpi_desc, spa, type);
047fc8a1
RZ		 1243 mutex_unlock(&acpi_desc->spa_map_mutex);
1244
1245 return iomem;
1246}
1247
1248static int nfit_blk_init_interleave(struct nfit_blk_mmio *mmio,
1249 struct acpi_nfit_interleave *idt, u16 interleave_ways)
1250{
1251 if (idt) {
1252 mmio->num_lines = idt->line_count;
1253 mmio->line_size = idt->line_size;
1254 if (interleave_ways == 0)
1255 return -ENXIO;
1256 mmio->table_size = mmio->num_lines * interleave_ways
1257 * mmio->line_size;
1258 }
1259
1260 return 0;
1261}
1262
f0f2c072
RZ		 1263static int acpi_nfit_blk_get_flags(struct nvdimm_bus_descriptor *nd_desc,
1264 struct nvdimm *nvdimm, struct nfit_blk *nfit_blk)
1265{
1266 struct nd_cmd_dimm_flags flags;
1267 int rc;
1268
1269 memset(&flags, 0, sizeof(flags));
1270 rc = nd_desc->ndctl(nd_desc, nvdimm, ND_CMD_DIMM_FLAGS, &flags,
1271 sizeof(flags));
1272
1273 if (rc >= 0 && flags.status == 0)
1274 nfit_blk->dimm_flags = flags.flags;
1275 else if (rc == -ENOTTY) {
1276 /* fall back to a conservative default */
67a3e8fe 1277 nfit_blk->dimm_flags = ND_BLK_DCR_LATCH | ND_BLK_READ_FLUSH;
f0f2c072
RZ		 1278 rc = 0;
1279 } else
1280 rc = -ENXIO;
1281
1282 return rc;
1283}
1284
047fc8a1
RZ		 1285static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
1286 struct device *dev)
1287{
1288 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
1289 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1290 struct nd_blk_region *ndbr = to_nd_blk_region(dev);
c2ad2954 1291 struct nfit_flush *nfit_flush;
047fc8a1
RZ		 1292 struct nfit_blk_mmio *mmio;
1293 struct nfit_blk *nfit_blk;
1294 struct nfit_mem *nfit_mem;
1295 struct nvdimm *nvdimm;
1296 int rc;
1297
1298 nvdimm = nd_blk_region_to_dimm(ndbr);
1299 nfit_mem = nvdimm_provider_data(nvdimm);
1300 if (!nfit_mem || !nfit_mem->dcr || !nfit_mem->bdw) {
1301 dev_dbg(dev, "%s: missing%s%s%s\n", __func__,
1302 nfit_mem ? "" : " nfit_mem",
193ccca4
DW		 1303 (nfit_mem && nfit_mem->dcr) ? "" : " dcr",
1304 (nfit_mem && nfit_mem->bdw) ? "" : " bdw");
047fc8a1
RZ		 1305 return -ENXIO;
1306 }
1307
1308 nfit_blk = devm_kzalloc(dev, sizeof(*nfit_blk), GFP_KERNEL);
1309 if (!nfit_blk)
1310 return -ENOMEM;
1311 nd_blk_region_set_provider_data(ndbr, nfit_blk);
1312 nfit_blk->nd_region = to_nd_region(dev);
1313
1314 /* map block aperture memory */
1315 nfit_blk->bdw_offset = nfit_mem->bdw->offset;
1316 mmio = &nfit_blk->mmio[BDW];
67a3e8fe 1317 mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw,
c2ad2954 1318 SPA_MAP_APERTURE);
67a3e8fe 1319 if (!mmio->addr.base) {
047fc8a1
RZ		 1320 dev_dbg(dev, "%s: %s failed to map bdw\n", __func__,
1321 nvdimm_name(nvdimm));
1322 return -ENOMEM;
1323 }
1324 mmio->size = nfit_mem->bdw->size;
1325 mmio->base_offset = nfit_mem->memdev_bdw->region_offset;
1326 mmio->idt = nfit_mem->idt_bdw;
1327 mmio->spa = nfit_mem->spa_bdw;
1328 rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_bdw,
1329 nfit_mem->memdev_bdw->interleave_ways);
1330 if (rc) {
1331 dev_dbg(dev, "%s: %s failed to init bdw interleave\n",
1332 __func__, nvdimm_name(nvdimm));
1333 return rc;
1334 }
1335
1336 /* map block control memory */
1337 nfit_blk->cmd_offset = nfit_mem->dcr->command_offset;
1338 nfit_blk->stat_offset = nfit_mem->dcr->status_offset;
1339 mmio = &nfit_blk->mmio[DCR];
67a3e8fe 1340 mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr,
c2ad2954 1341 SPA_MAP_CONTROL);
67a3e8fe 1342 if (!mmio->addr.base) {
047fc8a1
RZ		 1343 dev_dbg(dev, "%s: %s failed to map dcr\n", __func__,
1344 nvdimm_name(nvdimm));
1345 return -ENOMEM;
1346 }
1347 mmio->size = nfit_mem->dcr->window_size;
1348 mmio->base_offset = nfit_mem->memdev_dcr->region_offset;
1349 mmio->idt = nfit_mem->idt_dcr;
1350 mmio->spa = nfit_mem->spa_dcr;
1351 rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_dcr,
1352 nfit_mem->memdev_dcr->interleave_ways);
1353 if (rc) {
1354 dev_dbg(dev, "%s: %s failed to init dcr interleave\n",
1355 __func__, nvdimm_name(nvdimm));
1356 return rc;
1357 }
1358
f0f2c072
RZ		 1359 rc = acpi_nfit_blk_get_flags(nd_desc, nvdimm, nfit_blk);
1360 if (rc < 0) {
1361 dev_dbg(dev, "%s: %s failed get DIMM flags\n",
1362 __func__, nvdimm_name(nvdimm));
1363 return rc;
1364 }
1365
c2ad2954
RZ		 1366 nfit_flush = nfit_mem->nfit_flush;
1367 if (nfit_flush && nfit_flush->flush->hint_count != 0) {
1368 nfit_blk->nvdimm_flush = devm_ioremap_nocache(dev,
1369 nfit_flush->flush->hint_address[0], 8);
1370 if (!nfit_blk->nvdimm_flush)
1371 return -ENOMEM;
1372 }
1373
1374 if (!arch_has_pmem_api() && !nfit_blk->nvdimm_flush)
1375 dev_warn(dev, "unable to guarantee persistence of writes\n");
1376
047fc8a1
RZ		 1377 if (mmio->line_size == 0)
1378 return 0;
1379
1380 if ((u32) nfit_blk->cmd_offset % mmio->line_size
1381 + 8 > mmio->line_size) {
1382 dev_dbg(dev, "cmd_offset crosses interleave boundary\n");
1383 return -ENXIO;
1384 } else if ((u32) nfit_blk->stat_offset % mmio->line_size
1385 + 8 > mmio->line_size) {
1386 dev_dbg(dev, "stat_offset crosses interleave boundary\n");
1387 return -ENXIO;
1388 }
1389
1390 return 0;
1391}
1392
1393static void acpi_nfit_blk_region_disable(struct nvdimm_bus *nvdimm_bus,
1394 struct device *dev)
1395{
1396 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
1397 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1398 struct nd_blk_region *ndbr = to_nd_blk_region(dev);
1399 struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr);
1400 int i;
1401
1402 if (!nfit_blk)
1403 return; /* never enabled */
1404
1405 /* auto-free BLK spa mappings */
1406 for (i = 0; i < 2; i++) {
1407 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[i];
1408
67a3e8fe 1409 if (mmio->addr.base)
047fc8a1
RZ		 1410 nfit_spa_unmap(acpi_desc, mmio->spa);
1411 }
1412 nd_blk_region_set_provider_data(ndbr, NULL);
1413 /* devm will free nfit_blk */
1414}
1415
1f7df6f8
DW		 1416static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc,
1417 struct nd_mapping *nd_mapping, struct nd_region_desc *ndr_desc,
1418 struct acpi_nfit_memory_map *memdev,
1419 struct acpi_nfit_system_address *spa)
1420{
1421 struct nvdimm *nvdimm = acpi_nfit_dimm_by_handle(acpi_desc,
1422 memdev->device_handle);
047fc8a1 1423 struct nd_blk_region_desc *ndbr_desc;
1f7df6f8
DW		 1424 struct nfit_mem *nfit_mem;
1425 int blk_valid = 0;
1426
1427 if (!nvdimm) {
1428 dev_err(acpi_desc->dev, "spa%d dimm: %#x not found\n",
1429 spa->range_index, memdev->device_handle);
1430 return -ENODEV;
1431 }
1432
1433 nd_mapping->nvdimm = nvdimm;
1434 switch (nfit_spa_type(spa)) {
1435 case NFIT_SPA_PM:
1436 case NFIT_SPA_VOLATILE:
1437 nd_mapping->start = memdev->address;
1438 nd_mapping->size = memdev->region_size;
1439 break;
1440 case NFIT_SPA_DCR:
1441 nfit_mem = nvdimm_provider_data(nvdimm);
1442 if (!nfit_mem || !nfit_mem->bdw) {
1443 dev_dbg(acpi_desc->dev, "spa%d %s missing bdw\n",
1444 spa->range_index, nvdimm_name(nvdimm));
1445 } else {
1446 nd_mapping->size = nfit_mem->bdw->capacity;
1447 nd_mapping->start = nfit_mem->bdw->start_address;
5212e11f 1448 ndr_desc->num_lanes = nfit_mem->bdw->windows;
1f7df6f8
DW		 1449 blk_valid = 1;
1450 }
1451
1452 ndr_desc->nd_mapping = nd_mapping;
1453 ndr_desc->num_mappings = blk_valid;
047fc8a1
RZ		 1454 ndbr_desc = to_blk_region_desc(ndr_desc);
1455 ndbr_desc->enable = acpi_nfit_blk_region_enable;
1456 ndbr_desc->disable = acpi_nfit_blk_region_disable;
6bc75619 1457 ndbr_desc->do_io = acpi_desc->blk_do_io;
1f7df6f8
DW		 1458 if (!nvdimm_blk_region_create(acpi_desc->nvdimm_bus, ndr_desc))
1459 return -ENOMEM;
1460 break;
1461 }
1462
1463 return 0;
1464}
1465
1466static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
1467 struct nfit_spa *nfit_spa)
1468{
1469 static struct nd_mapping nd_mappings[ND_MAX_MAPPINGS];
1470 struct acpi_nfit_system_address *spa = nfit_spa->spa;
047fc8a1
RZ		 1471 struct nd_blk_region_desc ndbr_desc;
1472 struct nd_region_desc *ndr_desc;
1f7df6f8 1473 struct nfit_memdev *nfit_memdev;
1f7df6f8
DW		 1474 struct nvdimm_bus *nvdimm_bus;
1475 struct resource res;
eaf96153 1476 int count = 0, rc;
1f7df6f8
DW		 1477
1478 if (spa->range_index == 0) {
1479 dev_dbg(acpi_desc->dev, "%s: detected invalid spa index\n",
1480 __func__);
1481 return 0;
1482 }
1483
1484 memset(&res, 0, sizeof(res));
1485 memset(&nd_mappings, 0, sizeof(nd_mappings));
047fc8a1 1486 memset(&ndbr_desc, 0, sizeof(ndbr_desc));
1f7df6f8
DW		 1487 res.start = spa->address;
1488 res.end = res.start + spa->length - 1;
047fc8a1
RZ		 1489 ndr_desc = &ndbr_desc.ndr_desc;
1490 ndr_desc->res = &res;
1491 ndr_desc->provider_data = nfit_spa;
1492 ndr_desc->attr_groups = acpi_nfit_region_attribute_groups;
41d7a6d6
TK		 1493 if (spa->flags & ACPI_NFIT_PROXIMITY_VALID)
1494 ndr_desc->numa_node = acpi_map_pxm_to_online_node(
1495 spa->proximity_domain);
1496 else
1497 ndr_desc->numa_node = NUMA_NO_NODE;
1498
1f7df6f8
DW		 1499 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
1500 struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev;
1501 struct nd_mapping *nd_mapping;
1f7df6f8
DW		 1502
1503 if (memdev->range_index != spa->range_index)
1504 continue;
1505 if (count >= ND_MAX_MAPPINGS) {
1506 dev_err(acpi_desc->dev, "spa%d exceeds max mappings %d\n",
1507 spa->range_index, ND_MAX_MAPPINGS);
1508 return -ENXIO;
1509 }
1510 nd_mapping = &nd_mappings[count++];
047fc8a1 1511 rc = acpi_nfit_init_mapping(acpi_desc, nd_mapping, ndr_desc,
1f7df6f8
DW		 1512 memdev, spa);
1513 if (rc)
1514 return rc;
1515 }
1516
047fc8a1
RZ		 1517 ndr_desc->nd_mapping = nd_mappings;
1518 ndr_desc->num_mappings = count;
1519 rc = acpi_nfit_init_interleave_set(acpi_desc, ndr_desc, spa);
eaf96153
DW		 1520 if (rc)
1521 return rc;
1522
1f7df6f8
DW		 1523 nvdimm_bus = acpi_desc->nvdimm_bus;
1524 if (nfit_spa_type(spa) == NFIT_SPA_PM) {
047fc8a1 1525 if (!nvdimm_pmem_region_create(nvdimm_bus, ndr_desc))
1f7df6f8
DW		 1526 return -ENOMEM;
1527 } else if (nfit_spa_type(spa) == NFIT_SPA_VOLATILE) {
047fc8a1 1528 if (!nvdimm_volatile_region_create(nvdimm_bus, ndr_desc))
1f7df6f8
DW		 1529 return -ENOMEM;
1530 }
1531 return 0;
1532}
1533
1534static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
1535{
1536 struct nfit_spa *nfit_spa;
1537
1538 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
1539 int rc = acpi_nfit_register_region(acpi_desc, nfit_spa);
1540
1541 if (rc)
1542 return rc;
1543 }
1544 return 0;
1545}
1546
6bc75619 1547int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, acpi_size sz)
b94d5230
DW		 1548{
1549 struct device *dev = acpi_desc->dev;
1550 const void *end;
1551 u8 *data;
1f7df6f8 1552 int rc;
b94d5230 1553
047fc8a1 1554 INIT_LIST_HEAD(&acpi_desc->spa_maps);
b94d5230
DW		 1555 INIT_LIST_HEAD(&acpi_desc->spas);
1556 INIT_LIST_HEAD(&acpi_desc->dcrs);
1557 INIT_LIST_HEAD(&acpi_desc->bdws);
047fc8a1 1558 INIT_LIST_HEAD(&acpi_desc->idts);
c2ad2954 1559 INIT_LIST_HEAD(&acpi_desc->flushes);
b94d5230
DW		 1560 INIT_LIST_HEAD(&acpi_desc->memdevs);
1561 INIT_LIST_HEAD(&acpi_desc->dimms);
047fc8a1 1562 mutex_init(&acpi_desc->spa_map_mutex);
b94d5230
DW		 1563
1564 data = (u8 *) acpi_desc->nfit;
1565 end = data + sz;
1566 data += sizeof(struct acpi_table_nfit);
1567 while (!IS_ERR_OR_NULL(data))
1568 data = add_table(acpi_desc, data, end);
1569
1570 if (IS_ERR(data)) {
1571 dev_dbg(dev, "%s: nfit table parsing error: %ld\n", __func__,
1572 PTR_ERR(data));
1573 return PTR_ERR(data);
1574 }
1575
1576 if (nfit_mem_init(acpi_desc) != 0)
1577 return -ENOMEM;
1578
62232e45
DW		 1579 acpi_nfit_init_dsms(acpi_desc);
1580
1f7df6f8
DW		 1581 rc = acpi_nfit_register_dimms(acpi_desc);
1582 if (rc)
1583 return rc;
1584
1585 return acpi_nfit_register_regions(acpi_desc);
b94d5230 1586}
6bc75619 1587EXPORT_SYMBOL_GPL(acpi_nfit_init);
b94d5230
DW		 1588
1589static int acpi_nfit_add(struct acpi_device *adev)
1590{
1591 struct nvdimm_bus_descriptor *nd_desc;
1592 struct acpi_nfit_desc *acpi_desc;
1593 struct device *dev = &adev->dev;
1594 struct acpi_table_header *tbl;
1595 acpi_status status = AE_OK;
1596 acpi_size sz;
1597 int rc;
1598
1599 status = acpi_get_table_with_size("NFIT", 0, &tbl, &sz);
1600 if (ACPI_FAILURE(status)) {
1601 dev_err(dev, "failed to find NFIT\n");
1602 return -ENXIO;
1603 }
1604
1605 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
1606 if (!acpi_desc)
1607 return -ENOMEM;
1608
1609 dev_set_drvdata(dev, acpi_desc);
1610 acpi_desc->dev = dev;
1611 acpi_desc->nfit = (struct acpi_table_nfit *) tbl;
6bc75619 1612 acpi_desc->blk_do_io = acpi_nfit_blk_region_do_io;
b94d5230
DW		 1613 nd_desc = &acpi_desc->nd_desc;
1614 nd_desc->provider_name = "ACPI.NFIT";
1615 nd_desc->ndctl = acpi_nfit_ctl;
45def22c 1616 nd_desc->attr_groups = acpi_nfit_attribute_groups;
b94d5230
DW		 1617
1618 acpi_desc->nvdimm_bus = nvdimm_bus_register(dev, nd_desc);
1619 if (!acpi_desc->nvdimm_bus)
1620 return -ENXIO;
1621
1622 rc = acpi_nfit_init(acpi_desc, sz);
1623 if (rc) {
1624 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1625 return rc;
1626 }
1627 return 0;
1628}
1629
1630static int acpi_nfit_remove(struct acpi_device *adev)
1631{
1632 struct acpi_nfit_desc *acpi_desc = dev_get_drvdata(&adev->dev);
1633
1634 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1635 return 0;
1636}
1637
1638static const struct acpi_device_id acpi_nfit_ids[] = {
1639 { "ACPI0012", 0 },
1640 { "", 0 },
1641};
1642MODULE_DEVICE_TABLE(acpi, acpi_nfit_ids);
1643
1644static struct acpi_driver acpi_nfit_driver = {
1645 .name = KBUILD_MODNAME,
1646 .ids = acpi_nfit_ids,
1647 .ops = {
1648 .add = acpi_nfit_add,
1649 .remove = acpi_nfit_remove,
1650 },
1651};
1652
1653static __init int nfit_init(void)
1654{
1655 BUILD_BUG_ON(sizeof(struct acpi_table_nfit) != 40);
1656 BUILD_BUG_ON(sizeof(struct acpi_nfit_system_address) != 56);
1657 BUILD_BUG_ON(sizeof(struct acpi_nfit_memory_map) != 48);
1658 BUILD_BUG_ON(sizeof(struct acpi_nfit_interleave) != 20);
1659 BUILD_BUG_ON(sizeof(struct acpi_nfit_smbios) != 9);
1660 BUILD_BUG_ON(sizeof(struct acpi_nfit_control_region) != 80);
1661 BUILD_BUG_ON(sizeof(struct acpi_nfit_data_region) != 40);
1662
1663 acpi_str_to_uuid(UUID_VOLATILE_MEMORY, nfit_uuid[NFIT_SPA_VOLATILE]);
1664 acpi_str_to_uuid(UUID_PERSISTENT_MEMORY, nfit_uuid[NFIT_SPA_PM]);
1665 acpi_str_to_uuid(UUID_CONTROL_REGION, nfit_uuid[NFIT_SPA_DCR]);
1666 acpi_str_to_uuid(UUID_DATA_REGION, nfit_uuid[NFIT_SPA_BDW]);
1667 acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_VDISK]);
1668 acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_CD, nfit_uuid[NFIT_SPA_VCD]);
1669 acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_PDISK]);
1670 acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_CD, nfit_uuid[NFIT_SPA_PCD]);
1671 acpi_str_to_uuid(UUID_NFIT_BUS, nfit_uuid[NFIT_DEV_BUS]);
1672 acpi_str_to_uuid(UUID_NFIT_DIMM, nfit_uuid[NFIT_DEV_DIMM]);
1673
1674 return acpi_bus_register_driver(&acpi_nfit_driver);
1675}
1676
1677static __exit void nfit_exit(void)
1678{
1679 acpi_bus_unregister_driver(&acpi_nfit_driver);
1680}
1681
1682module_init(nfit_init);
1683module_exit(nfit_exit);
1684MODULE_LICENSE("GPL v2");
1685MODULE_AUTHOR("Intel Corporation");
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