[mirror_ubuntu-artful-kernel.git] / drivers / acpi / pci_mcfg.c

/*
 * Copyright (C) 2016 Broadcom
 *	Author: Jayachandran C <jchandra@broadcom.com>
 * Copyright (C) 2016 Semihalf
 * 	Author: Tomasz Nowicki <tn@semihalf.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation (the "GPL").
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License version 2 (GPLv2) for more details.
 *
 * You should have received a copy of the GNU General Public License
 * version 2 (GPLv2) along with this source code.
 */

#define pr_fmt(fmt) "ACPI: " fmt

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>

/* Structure to hold entries from the MCFG table */
struct mcfg_entry {
	struct list_head	list;
	phys_addr_t		addr;
	u16			segment;
	u8			bus_start;
	u8			bus_end;
};

#ifdef CONFIG_PCI_QUIRKS
struct mcfg_fixup {
	char oem_id[ACPI_OEM_ID_SIZE + 1];
	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
	u32 oem_revision;
	u16 segment;
	struct resource bus_range;
	struct pci_ecam_ops *ops;
	struct resource cfgres;
};

#define MCFG_BUS_RANGE(start, end)	DEFINE_RES_NAMED((start),	\
						((end) - (start) + 1),	\
						NULL, IORESOURCE_BUS)
#define MCFG_BUS_ANY			MCFG_BUS_RANGE(0x0, 0xff)

static struct mcfg_fixup mcfg_quirks[] = {
/*	{ OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */

#define QCOM_ECAM32(seg) \
	{ "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
	QCOM_ECAM32(0),
	QCOM_ECAM32(1),
	QCOM_ECAM32(2),
	QCOM_ECAM32(3),
	QCOM_ECAM32(4),
	QCOM_ECAM32(5),
	QCOM_ECAM32(6),
	QCOM_ECAM32(7),

#define HISI_QUAD_DOM(table_id, seg, ops) \
	{ "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
	{ "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
	{ "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
	{ "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
	HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),
	HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),
	HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),
	HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),
	HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),
	HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),

#define THUNDER_PEM_RES(addr, node) \
	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
#define THUNDER_PEM_QUIRK(rev, node) \
	{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \
	{ "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \
	{ "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \
	{ "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \
	{ "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) },  \
	{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY,	    \
	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
	/* SoC pass2.x */
	THUNDER_PEM_QUIRK(1, 0),
	THUNDER_PEM_QUIRK(1, 1),

#define THUNDER_ECAM_QUIRK(rev, seg)					\
	{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,			\
	&pci_thunder_ecam_ops }
	/* SoC pass1.x */
	THUNDER_PEM_QUIRK(2, 0),	/* off-chip devices */
	THUNDER_PEM_QUIRK(2, 1),	/* off-chip devices */
	THUNDER_ECAM_QUIRK(2,  0),
	THUNDER_ECAM_QUIRK(2,  1),
	THUNDER_ECAM_QUIRK(2,  2),
	THUNDER_ECAM_QUIRK(2,  3),
	THUNDER_ECAM_QUIRK(2, 10),
	THUNDER_ECAM_QUIRK(2, 11),
	THUNDER_ECAM_QUIRK(2, 12),
	THUNDER_ECAM_QUIRK(2, 13),

#define XGENE_V1_ECAM_MCFG(rev, seg) \
	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
		&xgene_v1_pcie_ecam_ops }
#define XGENE_V2_ECAM_MCFG(rev, seg) \
	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
		&xgene_v2_pcie_ecam_ops }
	/* X-Gene SoC with v1 PCIe controller */
	XGENE_V1_ECAM_MCFG(1, 0),
	XGENE_V1_ECAM_MCFG(1, 1),
	XGENE_V1_ECAM_MCFG(1, 2),
	XGENE_V1_ECAM_MCFG(1, 3),
	XGENE_V1_ECAM_MCFG(1, 4),
	XGENE_V1_ECAM_MCFG(2, 0),
	XGENE_V1_ECAM_MCFG(2, 1),
	XGENE_V1_ECAM_MCFG(2, 2),
	XGENE_V1_ECAM_MCFG(2, 3),
	XGENE_V1_ECAM_MCFG(2, 4),
	/* X-Gene SoC with v2.1 PCIe controller */
	XGENE_V2_ECAM_MCFG(3, 0),
	XGENE_V2_ECAM_MCFG(3, 1),
	/* X-Gene SoC with v2.2 PCIe controller */
	XGENE_V2_ECAM_MCFG(4, 0),
	XGENE_V2_ECAM_MCFG(4, 1),
	XGENE_V2_ECAM_MCFG(4, 2),
};

static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
static u32 mcfg_oem_revision;

static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
				  struct resource *bus_range)
{
	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
	    !memcmp(f->oem_table_id, mcfg_oem_table_id,
	            ACPI_OEM_TABLE_ID_SIZE) &&
	    f->oem_revision == mcfg_oem_revision &&
	    f->segment == segment &&
	    resource_contains(&f->bus_range, bus_range))
		return 1;

	return 0;
}
#endif

static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
				  struct resource *cfgres,
				  struct pci_ecam_ops **ecam_ops)
{
#ifdef CONFIG_PCI_QUIRKS
	u16 segment = root->segment;
	struct resource *bus_range = &root->secondary;
	struct mcfg_fixup *f;
	int i;

	for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
		if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
			if (f->cfgres.start)
				*cfgres = f->cfgres;
			if (f->ops)
				*ecam_ops =  f->ops;
			dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
				 cfgres, bus_range, *ecam_ops);
			return;
		}
	}
#endif
}

/* List to save MCFG entries */
static LIST_HEAD(pci_mcfg_list);

int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
		    struct pci_ecam_ops **ecam_ops)
{
	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
	struct resource *bus_res = &root->secondary;
	u16 seg = root->segment;
	struct mcfg_entry *e;
	struct resource res;

	/* Use address from _CBA if present, otherwise lookup MCFG */
	if (root->mcfg_addr)
		goto skip_lookup;

	/*
	 * We expect the range in bus_res in the coverage of MCFG bus range.
	 */
	list_for_each_entry(e, &pci_mcfg_list, list) {
		if (e->segment == seg && e->bus_start <= bus_res->start &&
		    e->bus_end >= bus_res->end) {
			root->mcfg_addr = e->addr;
		}

	}

skip_lookup:
	memset(&res, 0, sizeof(res));
	if (root->mcfg_addr) {
		res.start = root->mcfg_addr + (bus_res->start << 20);
		res.end = res.start + (resource_size(bus_res) << 20) - 1;
		res.flags = IORESOURCE_MEM;
	}

	/*
	 * Allow quirks to override default ECAM ops and CFG resource
	 * range.  This may even fabricate a CFG resource range in case
	 * MCFG does not have it.  Invalid CFG start address means MCFG
	 * firmware bug or we need another quirk in array.
	 */
	pci_mcfg_apply_quirks(root, &res, &ops);
	if (!res.start)
		return -ENXIO;

	*cfgres = res;
	*ecam_ops = ops;
	return 0;
}

static __init int pci_mcfg_parse(struct acpi_table_header *header)
{
	struct acpi_table_mcfg *mcfg;
	struct acpi_mcfg_allocation *mptr;
	struct mcfg_entry *e, *arr;
	int i, n;

	if (header->length < sizeof(struct acpi_table_mcfg))
		return -EINVAL;

	n = (header->length - sizeof(struct acpi_table_mcfg)) /
					sizeof(struct acpi_mcfg_allocation);
	mcfg = (struct acpi_table_mcfg *)header;
	mptr = (struct acpi_mcfg_allocation *) &mcfg[1];

	arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
	if (!arr)
		return -ENOMEM;

	for (i = 0, e = arr; i < n; i++, mptr++, e++) {
		e->segment = mptr->pci_segment;
		e->addr =  mptr->address;
		e->bus_start = mptr->start_bus_number;
		e->bus_end = mptr->end_bus_number;
		list_add(&e->list, &pci_mcfg_list);
	}

#ifdef CONFIG_PCI_QUIRKS
	/* Save MCFG IDs and revision for quirks matching */
	memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
	memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
	mcfg_oem_revision = header->oem_revision;
#endif

	pr_info("MCFG table detected, %d entries\n", n);
	return 0;
}

/* Interface called by ACPI - parse and save MCFG table */
void __init pci_mmcfg_late_init(void)
{
	int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
	if (err)
		pr_err("Failed to parse MCFG (%d)\n", err);
}
Commit	Line	Data
935c760e TN	1	/*
	2	* Copyright (C) 2016 Broadcom
	3	* Author: Jayachandran C <jchandra@broadcom.com>
	4	* Copyright (C) 2016 Semihalf
	5	* Author: Tomasz Nowicki <tn@semihalf.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License, version 2, as
	9	* published by the Free Software Foundation (the "GPL").
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License version 2 (GPLv2) for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* version 2 (GPLv2) along with this source code.
	18	*/
	19
	20	#define pr_fmt(fmt) "ACPI: " fmt
	21
	22	#include <linux/kernel.h>
	23	#include <linux/pci.h>
	24	#include <linux/pci-acpi.h>
13983eb8	25	#include <linux/pci-ecam.h>
935c760e TN	26
	27	/* Structure to hold entries from the MCFG table */
	28	struct mcfg_entry {
	29	struct list_head list;
	30	phys_addr_t addr;
	31	u16 segment;
	32	u8 bus_start;
	33	u8 bus_end;
	34	};
	35
5b69b85b TN	36	#ifdef CONFIG_PCI_QUIRKS
	37	struct mcfg_fixup {
	38	char oem_id[ACPI_OEM_ID_SIZE + 1];
	39	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
	40	u32 oem_revision;
	41	u16 segment;
	42	struct resource bus_range;
	43	struct pci_ecam_ops *ops;
	44	struct resource cfgres;
	45	};
	46
	47	#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
	48	((end) - (start) + 1), \
	49	NULL, IORESOURCE_BUS)
	50	#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
	51
	52	static struct mcfg_fixup mcfg_quirks[] = {
	53	/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
2ca5b8dd CC	54
	55	#define QCOM_ECAM32(seg) \
	56	{ "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
	57	QCOM_ECAM32(0),
	58	QCOM_ECAM32(1),
	59	QCOM_ECAM32(2),
	60	QCOM_ECAM32(3),
	61	QCOM_ECAM32(4),
	62	QCOM_ECAM32(5),
	63	QCOM_ECAM32(6),
	64	QCOM_ECAM32(7),
5f00f1a0 DL	65
	66	#define HISI_QUAD_DOM(table_id, seg, ops) \
	67	{ "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
	68	{ "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
	69	{ "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
	70	{ "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
	71	HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
	72	HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
	73	HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
	74	HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
	75	HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
	76	HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
44f22bd9 TN	77
	78	#define THUNDER_PEM_RES(addr, node) \
	79	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
	80	#define THUNDER_PEM_QUIRK(rev, node) \
	81	{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
	82	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
	83	{ "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
	84	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
	85	{ "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
	86	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
	87	{ "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
	88	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
	89	{ "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
	90	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
	91	{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
	92	&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
	93	/* SoC pass2.x */
	94	THUNDER_PEM_QUIRK(1, 0),
	95	THUNDER_PEM_QUIRK(1, 1),
648d93fc TN	96
	97	#define THUNDER_ECAM_QUIRK(rev, seg) \
	98	{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
	99	&pci_thunder_ecam_ops }
	100	/* SoC pass1.x */
	101	THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
	102	THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
	103	THUNDER_ECAM_QUIRK(2, 0),
	104	THUNDER_ECAM_QUIRK(2, 1),
	105	THUNDER_ECAM_QUIRK(2, 2),
	106	THUNDER_ECAM_QUIRK(2, 3),
	107	THUNDER_ECAM_QUIRK(2, 10),
	108	THUNDER_ECAM_QUIRK(2, 11),
	109	THUNDER_ECAM_QUIRK(2, 12),
	110	THUNDER_ECAM_QUIRK(2, 13),
c5d46039 DD	111
	112	#define XGENE_V1_ECAM_MCFG(rev, seg) \
	113	{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
	114	&xgene_v1_pcie_ecam_ops }
	115	#define XGENE_V2_ECAM_MCFG(rev, seg) \
	116	{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
	117	&xgene_v2_pcie_ecam_ops }
	118	/* X-Gene SoC with v1 PCIe controller */
	119	XGENE_V1_ECAM_MCFG(1, 0),
	120	XGENE_V1_ECAM_MCFG(1, 1),
	121	XGENE_V1_ECAM_MCFG(1, 2),
	122	XGENE_V1_ECAM_MCFG(1, 3),
	123	XGENE_V1_ECAM_MCFG(1, 4),
	124	XGENE_V1_ECAM_MCFG(2, 0),
	125	XGENE_V1_ECAM_MCFG(2, 1),
	126	XGENE_V1_ECAM_MCFG(2, 2),
	127	XGENE_V1_ECAM_MCFG(2, 3),
	128	XGENE_V1_ECAM_MCFG(2, 4),
	129	/* X-Gene SoC with v2.1 PCIe controller */
	130	XGENE_V2_ECAM_MCFG(3, 0),
	131	XGENE_V2_ECAM_MCFG(3, 1),
	132	/* X-Gene SoC with v2.2 PCIe controller */
	133	XGENE_V2_ECAM_MCFG(4, 0),
	134	XGENE_V2_ECAM_MCFG(4, 1),
	135	XGENE_V2_ECAM_MCFG(4, 2),
5b69b85b TN	136	};
	137
	138	static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
	139	static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
	140	static u32 mcfg_oem_revision;
	141
	142	static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
	143	struct resource *bus_range)
	144	{
	145	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
	146	!memcmp(f->oem_table_id, mcfg_oem_table_id,
	147	ACPI_OEM_TABLE_ID_SIZE) &&
	148	f->oem_revision == mcfg_oem_revision &&
	149	f->segment == segment &&
	150	resource_contains(&f->bus_range, bus_range))
	151	return 1;
	152
	153	return 0;
	154	}
	155	#endif
	156
	157	static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
	158	struct resource *cfgres,
	159	struct pci_ecam_ops **ecam_ops)
	160	{
	161	#ifdef CONFIG_PCI_QUIRKS
	162	u16 segment = root->segment;
	163	struct resource *bus_range = &root->secondary;
	164	struct mcfg_fixup *f;
	165	int i;
	166
	167	for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
	168	if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
	169	if (f->cfgres.start)
	170	*cfgres = f->cfgres;
	171	if (f->ops)
	172	*ecam_ops = f->ops;
	173	dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
	174	cfgres, bus_range, *ecam_ops);
	175	return;
	176	}
	177	}
	178	#endif
	179	}
	180
935c760e TN	181	/* List to save MCFG entries */
	182	static LIST_HEAD(pci_mcfg_list);
	183
13983eb8 TN	184	int pci_mcfg_lookup(struct acpi_pci_root root, struct resource cfgres,
13983eb8 TN	185	struct pci_ecam_ops **ecam_ops)
935c760e	186	{
13983eb8 TN	187	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
	188	struct resource *bus_res = &root->secondary;
	189	u16 seg = root->segment;
935c760e	190	struct mcfg_entry *e;
13983eb8 TN	191	struct resource res;
	192
	193	/* Use address from _CBA if present, otherwise lookup MCFG */
	194	if (root->mcfg_addr)
	195	goto skip_lookup;
935c760e TN	196
935c760e TN	197	/*
53762ba8	198	* We expect the range in bus_res in the coverage of MCFG bus range.
935c760e TN	199	*/
935c760e TN	200	list_for_each_entry(e, &pci_mcfg_list, list) {
53762ba8	201	if (e->segment == seg && e->bus_start <= bus_res->start &&
13983eb8 TN	202	e->bus_end >= bus_res->end) {
	203	root->mcfg_addr = e->addr;
	204	}
	205
935c760e TN	206	}
935c760e TN	207
13983eb8 TN	208	skip_lookup:
13983eb8 TN	209	memset(&res, 0, sizeof(res));
5b69b85b TN	210	if (root->mcfg_addr) {
	211	res.start = root->mcfg_addr + (bus_res->start << 20);
	212	res.end = res.start + (resource_size(bus_res) << 20) - 1;
	213	res.flags = IORESOURCE_MEM;
	214	}
	215
	216	/*
	217	* Allow quirks to override default ECAM ops and CFG resource
	218	* range. This may even fabricate a CFG resource range in case
	219	* MCFG does not have it. Invalid CFG start address means MCFG
	220	* firmware bug or we need another quirk in array.
	221	*/
	222	pci_mcfg_apply_quirks(root, &res, &ops);
	223	if (!res.start)
	224	return -ENXIO;
	225
13983eb8 TN	226	*cfgres = res;
13983eb8 TN	227	*ecam_ops = ops;
935c760e TN	228	return 0;
	229	}
	230
	231	static __init int pci_mcfg_parse(struct acpi_table_header *header)
	232	{
	233	struct acpi_table_mcfg *mcfg;
	234	struct acpi_mcfg_allocation *mptr;
	235	struct mcfg_entry e, arr;
	236	int i, n;
	237
	238	if (header->length < sizeof(struct acpi_table_mcfg))
	239	return -EINVAL;
	240
	241	n = (header->length - sizeof(struct acpi_table_mcfg)) /
	242	sizeof(struct acpi_mcfg_allocation);
	243	mcfg = (struct acpi_table_mcfg *)header;
	244	mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
	245
	246	arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
	247	if (!arr)
	248	return -ENOMEM;
	249
	250	for (i = 0, e = arr; i < n; i++, mptr++, e++) {
	251	e->segment = mptr->pci_segment;
	252	e->addr = mptr->address;
	253	e->bus_start = mptr->start_bus_number;
	254	e->bus_end = mptr->end_bus_number;
	255	list_add(&e->list, &pci_mcfg_list);
	256	}
	257
5b69b85b TN	258	#ifdef CONFIG_PCI_QUIRKS
	259	/* Save MCFG IDs and revision for quirks matching */
	260	memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
	261	memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
	262	mcfg_oem_revision = header->oem_revision;
	263	#endif
	264
935c760e TN	265	pr_info("MCFG table detected, %d entries\n", n);
	266	return 0;
	267	}
	268
	269	/* Interface called by ACPI - parse and save MCFG table */
	270	void __init pci_mmcfg_late_init(void)
	271	{
	272	int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
	273	if (err)
	274	pr_err("Failed to parse MCFG (%d)\n", err);
	275	}