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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
1da177e4 | 31 | #include <linux/module.h> |
1da177e4 LT |
32 | #include <linux/acpi.h> |
33 | #include <linux/dmi.h> | |
e2668fb5 | 34 | #include <linux/sched.h> /* need_resched() */ |
e9e2cdb4 | 35 | #include <linux/clockchips.h> |
4f86d3a8 | 36 | #include <linux/cpuidle.h> |
0a3b15ac | 37 | #include <linux/syscore_ops.h> |
1da177e4 | 38 | |
3434933b TG |
39 | /* |
40 | * Include the apic definitions for x86 to have the APIC timer related defines | |
41 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
42 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
43 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
44 | */ | |
45 | #ifdef CONFIG_X86 | |
46 | #include <asm/apic.h> | |
47 | #endif | |
48 | ||
1da177e4 LT |
49 | #include <acpi/acpi_bus.h> |
50 | #include <acpi/processor.h> | |
51 | ||
a192a958 LB |
52 | #define PREFIX "ACPI: " |
53 | ||
1da177e4 | 54 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 55 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 56 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 57 | |
4f86d3a8 LB |
58 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
59 | module_param(max_cstate, uint, 0000); | |
b6835052 | 60 | static unsigned int nocst __read_mostly; |
1da177e4 | 61 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
62 | static int bm_check_disable __read_mostly; |
63 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 64 | |
25de5718 | 65 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 66 | module_param(latency_factor, uint, 0644); |
1da177e4 | 67 | |
3d339dcb DL |
68 | static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); |
69 | ||
6240a10d AS |
70 | static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], |
71 | acpi_cstate); | |
ac3ebafa | 72 | |
d1896049 TR |
73 | static int disabled_by_idle_boot_param(void) |
74 | { | |
75 | return boot_option_idle_override == IDLE_POLL || | |
d1896049 TR |
76 | boot_option_idle_override == IDLE_HALT; |
77 | } | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
81 | * For now disable this. Probably a bug somewhere else. | |
82 | * | |
83 | * To skip this limit, boot/load with a large max_cstate limit. | |
84 | */ | |
1855256c | 85 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
86 | { |
87 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
88 | return 0; | |
89 | ||
3d35600a | 90 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
91 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
92 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 93 | |
3d35600a | 94 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
95 | |
96 | return 0; | |
97 | } | |
98 | ||
fe7bf106 | 99 | static struct dmi_system_id processor_power_dmi_table[] = { |
876c184b TR |
100 | { set_max_cstate, "Clevo 5600D", { |
101 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
102 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 103 | (void *)2}, |
370d5cd8 AV |
104 | { set_max_cstate, "Pavilion zv5000", { |
105 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
106 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
107 | (void *)1}, | |
108 | { set_max_cstate, "Asus L8400B", { | |
109 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
110 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
111 | (void *)1}, | |
1da177e4 LT |
112 | {}, |
113 | }; | |
114 | ||
4f86d3a8 | 115 | |
2e906655 | 116 | /* |
117 | * Callers should disable interrupts before the call and enable | |
118 | * interrupts after return. | |
119 | */ | |
ddc081a1 VP |
120 | static void acpi_safe_halt(void) |
121 | { | |
ea811747 | 122 | if (!tif_need_resched()) { |
ddc081a1 | 123 | safe_halt(); |
71e93d15 VP |
124 | local_irq_disable(); |
125 | } | |
ddc081a1 VP |
126 | } |
127 | ||
169a0abb TG |
128 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
129 | ||
130 | /* | |
131 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
132 | * This seems to be a common problem on AMD boxen, but other vendors |
133 | * are affected too. We pick the most conservative approach: we assume | |
134 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 135 | */ |
7e275cc4 | 136 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
137 | struct acpi_processor_cx *cx) |
138 | { | |
139 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 140 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 141 | |
db954b58 VP |
142 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
143 | return; | |
144 | ||
02c68a02 | 145 | if (amd_e400_c1e_detected) |
87ad57ba SL |
146 | type = ACPI_STATE_C1; |
147 | ||
169a0abb TG |
148 | /* |
149 | * Check, if one of the previous states already marked the lapic | |
150 | * unstable | |
151 | */ | |
152 | if (pwr->timer_broadcast_on_state < state) | |
153 | return; | |
154 | ||
e585bef8 | 155 | if (cx->type >= type) |
296d93cd | 156 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
157 | } |
158 | ||
918aae42 | 159 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 160 | { |
f833bab8 | 161 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
162 | unsigned long reason; |
163 | ||
164 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
165 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
166 | ||
167 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
168 | } |
169 | ||
918aae42 HS |
170 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
171 | { | |
172 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
173 | (void *)pr, 1); | |
174 | } | |
175 | ||
e9e2cdb4 | 176 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 177 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
178 | struct acpi_processor_cx *cx, |
179 | int broadcast) | |
180 | { | |
e9e2cdb4 TG |
181 | int state = cx - pr->power.states; |
182 | ||
183 | if (state >= pr->power.timer_broadcast_on_state) { | |
184 | unsigned long reason; | |
185 | ||
186 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
187 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
188 | clockevents_notify(reason, &pr->id); | |
189 | } | |
169a0abb TG |
190 | } |
191 | ||
192 | #else | |
193 | ||
7e275cc4 | 194 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 195 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
196 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
197 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
198 | struct acpi_processor_cx *cx, |
199 | int broadcast) | |
200 | { | |
201 | } | |
169a0abb TG |
202 | |
203 | #endif | |
204 | ||
0a3b15ac | 205 | #ifdef CONFIG_PM_SLEEP |
815ab0fd LB |
206 | static u32 saved_bm_rld; |
207 | ||
95d45d4c | 208 | static int acpi_processor_suspend(void) |
815ab0fd LB |
209 | { |
210 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
0a3b15ac | 211 | return 0; |
815ab0fd | 212 | } |
0a3b15ac | 213 | |
95d45d4c | 214 | static void acpi_processor_resume(void) |
815ab0fd LB |
215 | { |
216 | u32 resumed_bm_rld; | |
217 | ||
218 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
0a3b15ac RW |
219 | if (resumed_bm_rld == saved_bm_rld) |
220 | return; | |
815ab0fd | 221 | |
0a3b15ac | 222 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); |
815ab0fd | 223 | } |
b04e7bdb | 224 | |
0a3b15ac RW |
225 | static struct syscore_ops acpi_processor_syscore_ops = { |
226 | .suspend = acpi_processor_suspend, | |
227 | .resume = acpi_processor_resume, | |
228 | }; | |
229 | ||
230 | void acpi_processor_syscore_init(void) | |
b04e7bdb | 231 | { |
0a3b15ac | 232 | register_syscore_ops(&acpi_processor_syscore_ops); |
b04e7bdb TG |
233 | } |
234 | ||
0a3b15ac | 235 | void acpi_processor_syscore_exit(void) |
b04e7bdb | 236 | { |
0a3b15ac | 237 | unregister_syscore_ops(&acpi_processor_syscore_ops); |
b04e7bdb | 238 | } |
0a3b15ac | 239 | #endif /* CONFIG_PM_SLEEP */ |
b04e7bdb | 240 | |
592913ec | 241 | #if defined(CONFIG_X86) |
520daf72 | 242 | static void tsc_check_state(int state) |
ddb25f9a AK |
243 | { |
244 | switch (boot_cpu_data.x86_vendor) { | |
245 | case X86_VENDOR_AMD: | |
40fb1715 | 246 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
247 | /* |
248 | * AMD Fam10h TSC will tick in all | |
249 | * C/P/S0/S1 states when this bit is set. | |
250 | */ | |
40fb1715 | 251 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 252 | return; |
40fb1715 | 253 | |
ddb25f9a | 254 | /*FALL THROUGH*/ |
ddb25f9a | 255 | default: |
520daf72 LB |
256 | /* TSC could halt in idle, so notify users */ |
257 | if (state > ACPI_STATE_C1) | |
258 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
259 | } |
260 | } | |
520daf72 LB |
261 | #else |
262 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
263 | #endif |
264 | ||
4be44fcd | 265 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 266 | { |
1da177e4 | 267 | |
1da177e4 | 268 | if (!pr->pblk) |
d550d98d | 269 | return -ENODEV; |
1da177e4 | 270 | |
1da177e4 | 271 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
272 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
273 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
274 | ||
4c033552 VP |
275 | #ifndef CONFIG_HOTPLUG_CPU |
276 | /* | |
277 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 278 | * an SMP system. |
4c033552 | 279 | */ |
ad71860a | 280 | if ((num_online_cpus() > 1) && |
cee324b1 | 281 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 282 | return -ENODEV; |
4c033552 VP |
283 | #endif |
284 | ||
1da177e4 LT |
285 | /* determine C2 and C3 address from pblk */ |
286 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
287 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
288 | ||
289 | /* determine latencies from FADT */ | |
ba494bee BM |
290 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; |
291 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; | |
1da177e4 | 292 | |
5d76b6f6 LB |
293 | /* |
294 | * FADT specified C2 latency must be less than or equal to | |
295 | * 100 microseconds. | |
296 | */ | |
ba494bee | 297 | if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { |
5d76b6f6 | 298 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 299 | "C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency)); |
5d76b6f6 LB |
300 | /* invalidate C2 */ |
301 | pr->power.states[ACPI_STATE_C2].address = 0; | |
302 | } | |
303 | ||
a6d72c18 LB |
304 | /* |
305 | * FADT supplied C3 latency must be less than or equal to | |
306 | * 1000 microseconds. | |
307 | */ | |
ba494bee | 308 | if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { |
a6d72c18 | 309 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
ba494bee | 310 | "C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency)); |
a6d72c18 LB |
311 | /* invalidate C3 */ |
312 | pr->power.states[ACPI_STATE_C3].address = 0; | |
313 | } | |
314 | ||
1da177e4 LT |
315 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
316 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
317 | pr->power.states[ACPI_STATE_C2].address, | |
318 | pr->power.states[ACPI_STATE_C3].address)); | |
319 | ||
d550d98d | 320 | return 0; |
1da177e4 LT |
321 | } |
322 | ||
991528d7 | 323 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 324 | { |
991528d7 VP |
325 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
326 | /* set the first C-State to C1 */ | |
327 | /* all processors need to support C1 */ | |
328 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
329 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 330 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
331 | } |
332 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 333 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 334 | return 0; |
acf05f4b VP |
335 | } |
336 | ||
4be44fcd | 337 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 338 | { |
4be44fcd | 339 | acpi_status status = 0; |
439913ff | 340 | u64 count; |
cf824788 | 341 | int current_count; |
4be44fcd LB |
342 | int i; |
343 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
344 | union acpi_object *cst; | |
1da177e4 | 345 | |
1da177e4 | 346 | |
1da177e4 | 347 | if (nocst) |
d550d98d | 348 | return -ENODEV; |
1da177e4 | 349 | |
991528d7 | 350 | current_count = 0; |
1da177e4 LT |
351 | |
352 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
353 | if (ACPI_FAILURE(status)) { | |
354 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 355 | return -ENODEV; |
4be44fcd | 356 | } |
1da177e4 | 357 | |
50dd0969 | 358 | cst = buffer.pointer; |
1da177e4 LT |
359 | |
360 | /* There must be at least 2 elements */ | |
361 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 362 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
363 | status = -EFAULT; |
364 | goto end; | |
365 | } | |
366 | ||
367 | count = cst->package.elements[0].integer.value; | |
368 | ||
369 | /* Validate number of power states. */ | |
370 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 371 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
372 | status = -EFAULT; |
373 | goto end; | |
374 | } | |
375 | ||
1da177e4 LT |
376 | /* Tell driver that at least _CST is supported. */ |
377 | pr->flags.has_cst = 1; | |
378 | ||
379 | for (i = 1; i <= count; i++) { | |
380 | union acpi_object *element; | |
381 | union acpi_object *obj; | |
382 | struct acpi_power_register *reg; | |
383 | struct acpi_processor_cx cx; | |
384 | ||
385 | memset(&cx, 0, sizeof(cx)); | |
386 | ||
50dd0969 | 387 | element = &(cst->package.elements[i]); |
1da177e4 LT |
388 | if (element->type != ACPI_TYPE_PACKAGE) |
389 | continue; | |
390 | ||
391 | if (element->package.count != 4) | |
392 | continue; | |
393 | ||
50dd0969 | 394 | obj = &(element->package.elements[0]); |
1da177e4 LT |
395 | |
396 | if (obj->type != ACPI_TYPE_BUFFER) | |
397 | continue; | |
398 | ||
4be44fcd | 399 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
400 | |
401 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 402 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
403 | continue; |
404 | ||
1da177e4 | 405 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 406 | obj = &(element->package.elements[1]); |
1da177e4 LT |
407 | if (obj->type != ACPI_TYPE_INTEGER) |
408 | continue; | |
409 | ||
410 | cx.type = obj->integer.value; | |
991528d7 VP |
411 | /* |
412 | * Some buggy BIOSes won't list C1 in _CST - | |
413 | * Let acpi_processor_get_power_info_default() handle them later | |
414 | */ | |
415 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
416 | current_count++; | |
417 | ||
418 | cx.address = reg->address; | |
419 | cx.index = current_count + 1; | |
420 | ||
bc71bec9 | 421 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
422 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
423 | if (acpi_processor_ffh_cstate_probe | |
424 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 425 | cx.entry_method = ACPI_CSTATE_FFH; |
426 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
427 | /* |
428 | * C1 is a special case where FIXED_HARDWARE | |
429 | * can be handled in non-MWAIT way as well. | |
430 | * In that case, save this _CST entry info. | |
991528d7 VP |
431 | * Otherwise, ignore this info and continue. |
432 | */ | |
bc71bec9 | 433 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 434 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 435 | } else { |
991528d7 VP |
436 | continue; |
437 | } | |
da5e09a1 | 438 | if (cx.type == ACPI_STATE_C1 && |
d1896049 | 439 | (boot_option_idle_override == IDLE_NOMWAIT)) { |
c1e3b377 ZY |
440 | /* |
441 | * In most cases the C1 space_id obtained from | |
442 | * _CST object is FIXED_HARDWARE access mode. | |
443 | * But when the option of idle=halt is added, | |
444 | * the entry_method type should be changed from | |
445 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
446 | * When the option of idle=nomwait is added, |
447 | * the C1 entry_method type should be | |
448 | * CSTATE_HALT. | |
c1e3b377 ZY |
449 | */ |
450 | cx.entry_method = ACPI_CSTATE_HALT; | |
451 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
452 | } | |
4fcb2fcd VP |
453 | } else { |
454 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
455 | cx.address); | |
991528d7 | 456 | } |
1da177e4 | 457 | |
0fda6b40 VP |
458 | if (cx.type == ACPI_STATE_C1) { |
459 | cx.valid = 1; | |
460 | } | |
4fcb2fcd | 461 | |
50dd0969 | 462 | obj = &(element->package.elements[2]); |
1da177e4 LT |
463 | if (obj->type != ACPI_TYPE_INTEGER) |
464 | continue; | |
465 | ||
466 | cx.latency = obj->integer.value; | |
467 | ||
50dd0969 | 468 | obj = &(element->package.elements[3]); |
1da177e4 LT |
469 | if (obj->type != ACPI_TYPE_INTEGER) |
470 | continue; | |
471 | ||
cf824788 JM |
472 | current_count++; |
473 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
474 | ||
475 | /* | |
476 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
477 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
478 | */ | |
479 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
480 | printk(KERN_WARNING | |
481 | "Limiting number of power states to max (%d)\n", | |
482 | ACPI_PROCESSOR_MAX_POWER); | |
483 | printk(KERN_WARNING | |
484 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
485 | break; | |
486 | } | |
1da177e4 LT |
487 | } |
488 | ||
4be44fcd | 489 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 490 | current_count)); |
1da177e4 LT |
491 | |
492 | /* Validate number of power states discovered */ | |
cf824788 | 493 | if (current_count < 2) |
6d93c648 | 494 | status = -EFAULT; |
1da177e4 | 495 | |
4be44fcd | 496 | end: |
02438d87 | 497 | kfree(buffer.pointer); |
1da177e4 | 498 | |
d550d98d | 499 | return status; |
1da177e4 LT |
500 | } |
501 | ||
4be44fcd LB |
502 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
503 | struct acpi_processor_cx *cx) | |
1da177e4 | 504 | { |
ee1ca48f PV |
505 | static int bm_check_flag = -1; |
506 | static int bm_control_flag = -1; | |
02df8b93 | 507 | |
1da177e4 LT |
508 | |
509 | if (!cx->address) | |
d550d98d | 510 | return; |
1da177e4 | 511 | |
1da177e4 LT |
512 | /* |
513 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
514 | * DMA transfers are used by any ISA device to avoid livelock. | |
515 | * Note that we could disable Type-F DMA (as recommended by | |
516 | * the erratum), but this is known to disrupt certain ISA | |
517 | * devices thus we take the conservative approach. | |
518 | */ | |
519 | else if (errata.piix4.fdma) { | |
520 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 521 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 522 | return; |
1da177e4 LT |
523 | } |
524 | ||
02df8b93 | 525 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 526 | if (bm_check_flag == -1) { |
02df8b93 VP |
527 | /* Determine whether bm_check is needed based on CPU */ |
528 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
529 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 530 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
531 | } else { |
532 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 533 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
534 | } |
535 | ||
536 | if (pr->flags.bm_check) { | |
02df8b93 | 537 | if (!pr->flags.bm_control) { |
ed3110ef VP |
538 | if (pr->flags.has_cst != 1) { |
539 | /* bus mastering control is necessary */ | |
540 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
541 | "C3 support requires BM control\n")); | |
542 | return; | |
543 | } else { | |
544 | /* Here we enter C3 without bus mastering */ | |
545 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
546 | "C3 support without BM control\n")); | |
547 | } | |
02df8b93 VP |
548 | } |
549 | } else { | |
02df8b93 VP |
550 | /* |
551 | * WBINVD should be set in fadt, for C3 state to be | |
552 | * supported on when bm_check is not required. | |
553 | */ | |
cee324b1 | 554 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 555 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
556 | "Cache invalidation should work properly" |
557 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 558 | return; |
02df8b93 | 559 | } |
02df8b93 VP |
560 | } |
561 | ||
1da177e4 LT |
562 | /* |
563 | * Otherwise we've met all of our C3 requirements. | |
564 | * Normalize the C3 latency to expidite policy. Enable | |
565 | * checking of bus mastering status (bm_check) so we can | |
566 | * use this in our C3 policy | |
567 | */ | |
568 | cx->valid = 1; | |
4f86d3a8 | 569 | |
31878dd8 LB |
570 | /* |
571 | * On older chipsets, BM_RLD needs to be set | |
572 | * in order for Bus Master activity to wake the | |
573 | * system from C3. Newer chipsets handle DMA | |
574 | * during C3 automatically and BM_RLD is a NOP. | |
575 | * In either case, the proper way to | |
576 | * handle BM_RLD is to set it and leave it set. | |
577 | */ | |
50ffba1b | 578 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 579 | |
d550d98d | 580 | return; |
1da177e4 LT |
581 | } |
582 | ||
1da177e4 LT |
583 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
584 | { | |
585 | unsigned int i; | |
586 | unsigned int working = 0; | |
6eb0a0fd | 587 | |
169a0abb | 588 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 589 | |
a0bf284b | 590 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
591 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
592 | ||
593 | switch (cx->type) { | |
594 | case ACPI_STATE_C1: | |
595 | cx->valid = 1; | |
596 | break; | |
597 | ||
598 | case ACPI_STATE_C2: | |
d22edd29 LB |
599 | if (!cx->address) |
600 | break; | |
601 | cx->valid = 1; | |
1da177e4 LT |
602 | break; |
603 | ||
604 | case ACPI_STATE_C3: | |
605 | acpi_processor_power_verify_c3(pr, cx); | |
606 | break; | |
607 | } | |
7e275cc4 LB |
608 | if (!cx->valid) |
609 | continue; | |
1da177e4 | 610 | |
7e275cc4 LB |
611 | lapic_timer_check_state(i, pr, cx); |
612 | tsc_check_state(cx->type); | |
613 | working++; | |
1da177e4 | 614 | } |
bd663347 | 615 | |
918aae42 | 616 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
617 | |
618 | return (working); | |
619 | } | |
620 | ||
4be44fcd | 621 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
622 | { |
623 | unsigned int i; | |
624 | int result; | |
625 | ||
1da177e4 LT |
626 | |
627 | /* NOTE: the idle thread may not be running while calling | |
628 | * this function */ | |
629 | ||
991528d7 VP |
630 | /* Zero initialize all the C-states info. */ |
631 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
632 | ||
1da177e4 | 633 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 634 | if (result == -ENODEV) |
c5a114f1 | 635 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 636 | |
991528d7 VP |
637 | if (result) |
638 | return result; | |
639 | ||
640 | acpi_processor_get_power_info_default(pr); | |
641 | ||
cf824788 | 642 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 643 | |
1da177e4 LT |
644 | /* |
645 | * if one state of type C2 or C3 is available, mark this | |
646 | * CPU as being "idle manageable" | |
647 | */ | |
648 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 649 | if (pr->power.states[i].valid) { |
1da177e4 | 650 | pr->power.count = i; |
2203d6ed LT |
651 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
652 | pr->flags.power = 1; | |
acf05f4b | 653 | } |
1da177e4 LT |
654 | } |
655 | ||
d550d98d | 656 | return 0; |
1da177e4 LT |
657 | } |
658 | ||
4f86d3a8 LB |
659 | /** |
660 | * acpi_idle_bm_check - checks if bus master activity was detected | |
661 | */ | |
662 | static int acpi_idle_bm_check(void) | |
663 | { | |
664 | u32 bm_status = 0; | |
665 | ||
d3e7e99f LB |
666 | if (bm_check_disable) |
667 | return 0; | |
668 | ||
50ffba1b | 669 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 670 | if (bm_status) |
50ffba1b | 671 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
672 | /* |
673 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
674 | * the true state of bus mastering activity; forcing us to | |
675 | * manually check the BMIDEA bit of each IDE channel. | |
676 | */ | |
677 | else if (errata.piix4.bmisx) { | |
678 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
679 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
680 | bm_status = 1; | |
681 | } | |
682 | return bm_status; | |
683 | } | |
684 | ||
4f86d3a8 LB |
685 | /** |
686 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
687 | * @cx: cstate data | |
bc71bec9 | 688 | * |
689 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
690 | */ |
691 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
692 | { | |
dcf30997 SR |
693 | /* Don't trace irqs off for idle */ |
694 | stop_critical_timings(); | |
bc71bec9 | 695 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
696 | /* Call into architectural FFH based C-state */ |
697 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 698 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
699 | acpi_safe_halt(); | |
4f86d3a8 | 700 | } else { |
4f86d3a8 LB |
701 | /* IO port based C-state */ |
702 | inb(cx->address); | |
703 | /* Dummy wait op - must do something useless after P_LVL2 read | |
704 | because chipsets cannot guarantee that STPCLK# signal | |
705 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 706 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 707 | } |
dcf30997 | 708 | start_critical_timings(); |
4f86d3a8 LB |
709 | } |
710 | ||
711 | /** | |
712 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
713 | * @dev: the target CPU | |
46bcfad7 | 714 | * @drv: cpuidle driver containing cpuidle state info |
e978aa7d | 715 | * @index: index of target state |
4f86d3a8 LB |
716 | * |
717 | * This is equivalent to the HALT instruction. | |
718 | */ | |
719 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
46bcfad7 | 720 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
721 | { |
722 | struct acpi_processor *pr; | |
6240a10d | 723 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
9b12e18c | 724 | |
4a6f4fe8 | 725 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
726 | |
727 | if (unlikely(!pr)) | |
e978aa7d | 728 | return -EINVAL; |
4f86d3a8 | 729 | |
ea811747 PZ |
730 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
731 | if (current_set_polling_and_test()) | |
732 | return -EINVAL; | |
733 | } | |
734 | ||
7e275cc4 | 735 | lapic_timer_state_broadcast(pr, cx, 1); |
bc71bec9 | 736 | acpi_idle_do_entry(cx); |
e978aa7d | 737 | |
7e275cc4 | 738 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 739 | |
e978aa7d | 740 | return index; |
4f86d3a8 LB |
741 | } |
742 | ||
1a022e3f BO |
743 | |
744 | /** | |
745 | * acpi_idle_play_dead - enters an ACPI state for long-term idle (i.e. off-lining) | |
746 | * @dev: the target CPU | |
747 | * @index: the index of suggested state | |
748 | */ | |
749 | static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) | |
750 | { | |
6240a10d | 751 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
1a022e3f BO |
752 | |
753 | ACPI_FLUSH_CPU_CACHE(); | |
754 | ||
755 | while (1) { | |
756 | ||
757 | if (cx->entry_method == ACPI_CSTATE_HALT) | |
54f70077 | 758 | safe_halt(); |
1a022e3f BO |
759 | else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) { |
760 | inb(cx->address); | |
761 | /* See comment in acpi_idle_do_entry() */ | |
762 | inl(acpi_gbl_FADT.xpm_timer_block.address); | |
763 | } else | |
764 | return -ENODEV; | |
765 | } | |
766 | ||
767 | /* Never reached */ | |
768 | return 0; | |
769 | } | |
770 | ||
4f86d3a8 LB |
771 | /** |
772 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
773 | * @dev: the target CPU | |
46bcfad7 | 774 | * @drv: cpuidle driver with cpuidle state information |
e978aa7d | 775 | * @index: the index of suggested state |
4f86d3a8 LB |
776 | */ |
777 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
46bcfad7 | 778 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
779 | { |
780 | struct acpi_processor *pr; | |
6240a10d | 781 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
50629118 | 782 | |
4a6f4fe8 | 783 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
784 | |
785 | if (unlikely(!pr)) | |
e978aa7d | 786 | return -EINVAL; |
e196441b | 787 | |
ea811747 PZ |
788 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
789 | if (current_set_polling_and_test()) | |
e978aa7d | 790 | return -EINVAL; |
4f86d3a8 LB |
791 | } |
792 | ||
e17bcb43 TG |
793 | /* |
794 | * Must be done before busmaster disable as we might need to | |
795 | * access HPET ! | |
796 | */ | |
7e275cc4 | 797 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 798 | |
4f86d3a8 LB |
799 | if (cx->type == ACPI_STATE_C3) |
800 | ACPI_FLUSH_CPU_CACHE(); | |
801 | ||
50629118 VP |
802 | /* Tell the scheduler that we are going deep-idle: */ |
803 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 804 | acpi_idle_do_entry(cx); |
4f86d3a8 | 805 | |
a474a515 | 806 | sched_clock_idle_wakeup_event(0); |
e978aa7d | 807 | |
7e275cc4 | 808 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 809 | return index; |
4f86d3a8 LB |
810 | } |
811 | ||
812 | static int c3_cpu_count; | |
e12f65f7 | 813 | static DEFINE_RAW_SPINLOCK(c3_lock); |
4f86d3a8 LB |
814 | |
815 | /** | |
816 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
817 | * @dev: the target CPU | |
46bcfad7 | 818 | * @drv: cpuidle driver containing state data |
e978aa7d | 819 | * @index: the index of suggested state |
4f86d3a8 LB |
820 | * |
821 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
822 | */ | |
823 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
46bcfad7 | 824 | struct cpuidle_driver *drv, int index) |
4f86d3a8 LB |
825 | { |
826 | struct acpi_processor *pr; | |
6240a10d | 827 | struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); |
50629118 | 828 | |
4a6f4fe8 | 829 | pr = __this_cpu_read(processors); |
4f86d3a8 LB |
830 | |
831 | if (unlikely(!pr)) | |
e978aa7d | 832 | return -EINVAL; |
4f86d3a8 | 833 | |
718be4aa | 834 | if (!cx->bm_sts_skip && acpi_idle_bm_check()) { |
46bcfad7 DD |
835 | if (drv->safe_state_index >= 0) { |
836 | return drv->states[drv->safe_state_index].enter(dev, | |
837 | drv, drv->safe_state_index); | |
ddc081a1 | 838 | } else { |
8651f97b | 839 | acpi_safe_halt(); |
75cc5235 | 840 | return -EBUSY; |
ddc081a1 VP |
841 | } |
842 | } | |
843 | ||
ea811747 PZ |
844 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
845 | if (current_set_polling_and_test()) | |
e978aa7d | 846 | return -EINVAL; |
4f86d3a8 LB |
847 | } |
848 | ||
996520c1 VP |
849 | acpi_unlazy_tlb(smp_processor_id()); |
850 | ||
50629118 VP |
851 | /* Tell the scheduler that we are going deep-idle: */ |
852 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
853 | /* |
854 | * Must be done before busmaster disable as we might need to | |
855 | * access HPET ! | |
856 | */ | |
7e275cc4 | 857 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 858 | |
ddc081a1 VP |
859 | /* |
860 | * disable bus master | |
861 | * bm_check implies we need ARB_DIS | |
862 | * !bm_check implies we need cache flush | |
863 | * bm_control implies whether we can do ARB_DIS | |
864 | * | |
865 | * That leaves a case where bm_check is set and bm_control is | |
866 | * not set. In that case we cannot do much, we enter C3 | |
867 | * without doing anything. | |
868 | */ | |
869 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 870 | raw_spin_lock(&c3_lock); |
4f86d3a8 LB |
871 | c3_cpu_count++; |
872 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
873 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 874 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
e12f65f7 | 875 | raw_spin_unlock(&c3_lock); |
ddc081a1 VP |
876 | } else if (!pr->flags.bm_check) { |
877 | ACPI_FLUSH_CPU_CACHE(); | |
878 | } | |
4f86d3a8 | 879 | |
ddc081a1 | 880 | acpi_idle_do_entry(cx); |
4f86d3a8 | 881 | |
ddc081a1 VP |
882 | /* Re-enable bus master arbitration */ |
883 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
e12f65f7 | 884 | raw_spin_lock(&c3_lock); |
50ffba1b | 885 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 | 886 | c3_cpu_count--; |
e12f65f7 | 887 | raw_spin_unlock(&c3_lock); |
4f86d3a8 | 888 | } |
e978aa7d | 889 | |
a474a515 | 890 | sched_clock_idle_wakeup_event(0); |
4f86d3a8 | 891 | |
7e275cc4 | 892 | lapic_timer_state_broadcast(pr, cx, 0); |
e978aa7d | 893 | return index; |
4f86d3a8 LB |
894 | } |
895 | ||
896 | struct cpuidle_driver acpi_idle_driver = { | |
897 | .name = "acpi_idle", | |
898 | .owner = THIS_MODULE, | |
899 | }; | |
900 | ||
901 | /** | |
46bcfad7 DD |
902 | * acpi_processor_setup_cpuidle_cx - prepares and configures CPUIDLE |
903 | * device i.e. per-cpu data | |
904 | * | |
4f86d3a8 | 905 | * @pr: the ACPI processor |
6ef0f086 | 906 | * @dev : the cpuidle device |
4f86d3a8 | 907 | */ |
6ef0f086 DL |
908 | static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, |
909 | struct cpuidle_device *dev) | |
4f86d3a8 | 910 | { |
9a0b8415 | 911 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 | 912 | struct acpi_processor_cx *cx; |
4f86d3a8 LB |
913 | |
914 | if (!pr->flags.power_setup_done) | |
915 | return -EINVAL; | |
916 | ||
917 | if (pr->flags.power == 0) { | |
918 | return -EINVAL; | |
919 | } | |
920 | ||
b88a634a KRW |
921 | if (!dev) |
922 | return -EINVAL; | |
923 | ||
dcb84f33 | 924 | dev->cpu = pr->id; |
4fcb2fcd | 925 | |
615dfd93 LB |
926 | if (max_cstate == 0) |
927 | max_cstate = 1; | |
928 | ||
4f86d3a8 LB |
929 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
930 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
931 | |
932 | if (!cx->valid) | |
933 | continue; | |
934 | ||
935 | #ifdef CONFIG_HOTPLUG_CPU | |
936 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
937 | !pr->flags.has_cst && | |
938 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
939 | continue; | |
1fec74a9 | 940 | #endif |
6240a10d | 941 | per_cpu(acpi_cstate[count], dev->cpu) = cx; |
4f86d3a8 | 942 | |
46bcfad7 DD |
943 | count++; |
944 | if (count == CPUIDLE_STATE_MAX) | |
945 | break; | |
946 | } | |
947 | ||
948 | dev->state_count = count; | |
949 | ||
950 | if (!count) | |
951 | return -EINVAL; | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /** | |
957 | * acpi_processor_setup_cpuidle states- prepares and configures cpuidle | |
958 | * global state data i.e. idle routines | |
959 | * | |
960 | * @pr: the ACPI processor | |
961 | */ | |
962 | static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr) | |
963 | { | |
964 | int i, count = CPUIDLE_DRIVER_STATE_START; | |
965 | struct acpi_processor_cx *cx; | |
966 | struct cpuidle_state *state; | |
967 | struct cpuidle_driver *drv = &acpi_idle_driver; | |
968 | ||
969 | if (!pr->flags.power_setup_done) | |
970 | return -EINVAL; | |
971 | ||
972 | if (pr->flags.power == 0) | |
973 | return -EINVAL; | |
974 | ||
975 | drv->safe_state_index = -1; | |
4fcb2fcd | 976 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
46bcfad7 DD |
977 | drv->states[i].name[0] = '\0'; |
978 | drv->states[i].desc[0] = '\0'; | |
4fcb2fcd VP |
979 | } |
980 | ||
615dfd93 LB |
981 | if (max_cstate == 0) |
982 | max_cstate = 1; | |
983 | ||
4f86d3a8 LB |
984 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
985 | cx = &pr->power.states[i]; | |
4f86d3a8 LB |
986 | |
987 | if (!cx->valid) | |
988 | continue; | |
989 | ||
990 | #ifdef CONFIG_HOTPLUG_CPU | |
991 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
992 | !pr->flags.has_cst && | |
993 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
994 | continue; | |
1fec74a9 | 995 | #endif |
4f86d3a8 | 996 | |
46bcfad7 | 997 | state = &drv->states[count]; |
4f86d3a8 | 998 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); |
4fcb2fcd | 999 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1000 | state->exit_latency = cx->latency; |
4963f620 | 1001 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1002 | |
1003 | state->flags = 0; | |
1004 | switch (cx->type) { | |
1005 | case ACPI_STATE_C1: | |
8e92b660 VP |
1006 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1007 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1008 | ||
4f86d3a8 | 1009 | state->enter = acpi_idle_enter_c1; |
1a022e3f | 1010 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1011 | drv->safe_state_index = count; |
4f86d3a8 LB |
1012 | break; |
1013 | ||
1014 | case ACPI_STATE_C2: | |
4f86d3a8 LB |
1015 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1016 | state->enter = acpi_idle_enter_simple; | |
1a022e3f | 1017 | state->enter_dead = acpi_idle_play_dead; |
46bcfad7 | 1018 | drv->safe_state_index = count; |
4f86d3a8 LB |
1019 | break; |
1020 | ||
1021 | case ACPI_STATE_C3: | |
4f86d3a8 | 1022 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
4f86d3a8 LB |
1023 | state->enter = pr->flags.bm_check ? |
1024 | acpi_idle_enter_bm : | |
1025 | acpi_idle_enter_simple; | |
1026 | break; | |
1027 | } | |
1028 | ||
1029 | count++; | |
9a0b8415 | 1030 | if (count == CPUIDLE_STATE_MAX) |
1031 | break; | |
4f86d3a8 LB |
1032 | } |
1033 | ||
46bcfad7 | 1034 | drv->state_count = count; |
4f86d3a8 LB |
1035 | |
1036 | if (!count) | |
1037 | return -EINVAL; | |
1038 | ||
4f86d3a8 LB |
1039 | return 0; |
1040 | } | |
1041 | ||
46bcfad7 | 1042 | int acpi_processor_hotplug(struct acpi_processor *pr) |
4f86d3a8 | 1043 | { |
dcb84f33 | 1044 | int ret = 0; |
e8b1b59d | 1045 | struct cpuidle_device *dev; |
4f86d3a8 | 1046 | |
d1896049 | 1047 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1048 | return 0; |
1049 | ||
bf9b59f2 | 1050 | if (nocst) |
4f86d3a8 | 1051 | return -ENODEV; |
4f86d3a8 LB |
1052 | |
1053 | if (!pr->flags.power_setup_done) | |
1054 | return -ENODEV; | |
1055 | ||
e8b1b59d | 1056 | dev = per_cpu(acpi_cpuidle_device, pr->id); |
4f86d3a8 | 1057 | cpuidle_pause_and_lock(); |
3d339dcb | 1058 | cpuidle_disable_device(dev); |
4f86d3a8 | 1059 | acpi_processor_get_power_info(pr); |
dcb84f33 | 1060 | if (pr->flags.power) { |
6ef0f086 | 1061 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 1062 | ret = cpuidle_enable_device(dev); |
dcb84f33 | 1063 | } |
4f86d3a8 LB |
1064 | cpuidle_resume_and_unlock(); |
1065 | ||
1066 | return ret; | |
1067 | } | |
1068 | ||
46bcfad7 DD |
1069 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) |
1070 | { | |
1071 | int cpu; | |
1072 | struct acpi_processor *_pr; | |
3d339dcb | 1073 | struct cpuidle_device *dev; |
46bcfad7 DD |
1074 | |
1075 | if (disabled_by_idle_boot_param()) | |
1076 | return 0; | |
1077 | ||
46bcfad7 DD |
1078 | if (nocst) |
1079 | return -ENODEV; | |
1080 | ||
1081 | if (!pr->flags.power_setup_done) | |
1082 | return -ENODEV; | |
1083 | ||
1084 | /* | |
1085 | * FIXME: Design the ACPI notification to make it once per | |
1086 | * system instead of once per-cpu. This condition is a hack | |
1087 | * to make the code that updates C-States be called once. | |
1088 | */ | |
1089 | ||
9505626d | 1090 | if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) { |
46bcfad7 DD |
1091 | |
1092 | cpuidle_pause_and_lock(); | |
1093 | /* Protect against cpu-hotplug */ | |
1094 | get_online_cpus(); | |
1095 | ||
1096 | /* Disable all cpuidle devices */ | |
1097 | for_each_online_cpu(cpu) { | |
1098 | _pr = per_cpu(processors, cpu); | |
1099 | if (!_pr || !_pr->flags.power_setup_done) | |
1100 | continue; | |
3d339dcb DL |
1101 | dev = per_cpu(acpi_cpuidle_device, cpu); |
1102 | cpuidle_disable_device(dev); | |
46bcfad7 DD |
1103 | } |
1104 | ||
1105 | /* Populate Updated C-state information */ | |
f427e5f1 | 1106 | acpi_processor_get_power_info(pr); |
46bcfad7 DD |
1107 | acpi_processor_setup_cpuidle_states(pr); |
1108 | ||
1109 | /* Enable all cpuidle devices */ | |
1110 | for_each_online_cpu(cpu) { | |
1111 | _pr = per_cpu(processors, cpu); | |
1112 | if (!_pr || !_pr->flags.power_setup_done) | |
1113 | continue; | |
1114 | acpi_processor_get_power_info(_pr); | |
1115 | if (_pr->flags.power) { | |
3d339dcb | 1116 | dev = per_cpu(acpi_cpuidle_device, cpu); |
6ef0f086 | 1117 | acpi_processor_setup_cpuidle_cx(_pr, dev); |
3d339dcb | 1118 | cpuidle_enable_device(dev); |
46bcfad7 DD |
1119 | } |
1120 | } | |
1121 | put_online_cpus(); | |
1122 | cpuidle_resume_and_unlock(); | |
1123 | } | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | static int acpi_processor_registered; | |
1129 | ||
fe7bf106 | 1130 | int acpi_processor_power_init(struct acpi_processor *pr) |
1da177e4 | 1131 | { |
4be44fcd | 1132 | acpi_status status = 0; |
46bcfad7 | 1133 | int retval; |
3d339dcb | 1134 | struct cpuidle_device *dev; |
b6835052 | 1135 | static int first_run; |
1da177e4 | 1136 | |
d1896049 | 1137 | if (disabled_by_idle_boot_param()) |
36a91358 | 1138 | return 0; |
1da177e4 LT |
1139 | |
1140 | if (!first_run) { | |
1141 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1142 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1143 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1144 | printk(KERN_NOTICE |
1145 | "ACPI: processor limited to max C-state %d\n", | |
1146 | max_cstate); | |
1da177e4 LT |
1147 | first_run++; |
1148 | } | |
1149 | ||
cee324b1 | 1150 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1151 | status = |
cee324b1 | 1152 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1153 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1154 | ACPI_EXCEPTION((AE_INFO, status, |
1155 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1156 | } |
1157 | } | |
1158 | ||
1159 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1160 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1161 | |
1162 | /* | |
1163 | * Install the idle handler if processor power management is supported. | |
1164 | * Note that we use previously set idle handler will be used on | |
1165 | * platforms that only support C1. | |
1166 | */ | |
36a91358 | 1167 | if (pr->flags.power) { |
46bcfad7 DD |
1168 | /* Register acpi_idle_driver if not already registered */ |
1169 | if (!acpi_processor_registered) { | |
1170 | acpi_processor_setup_cpuidle_states(pr); | |
1171 | retval = cpuidle_register_driver(&acpi_idle_driver); | |
1172 | if (retval) | |
1173 | return retval; | |
1174 | printk(KERN_DEBUG "ACPI: %s registered with cpuidle\n", | |
1175 | acpi_idle_driver.name); | |
1176 | } | |
3d339dcb DL |
1177 | |
1178 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1179 | if (!dev) | |
1180 | return -ENOMEM; | |
1181 | per_cpu(acpi_cpuidle_device, pr->id) = dev; | |
1182 | ||
6ef0f086 | 1183 | acpi_processor_setup_cpuidle_cx(pr, dev); |
3d339dcb | 1184 | |
46bcfad7 DD |
1185 | /* Register per-cpu cpuidle_device. Cpuidle driver |
1186 | * must already be registered before registering device | |
1187 | */ | |
3d339dcb | 1188 | retval = cpuidle_register_device(dev); |
46bcfad7 DD |
1189 | if (retval) { |
1190 | if (acpi_processor_registered == 0) | |
1191 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1192 | return retval; | |
1193 | } | |
1194 | acpi_processor_registered++; | |
1da177e4 | 1195 | } |
d550d98d | 1196 | return 0; |
1da177e4 LT |
1197 | } |
1198 | ||
38a991b6 | 1199 | int acpi_processor_power_exit(struct acpi_processor *pr) |
1da177e4 | 1200 | { |
3d339dcb DL |
1201 | struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id); |
1202 | ||
d1896049 | 1203 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1204 | return 0; |
1205 | ||
46bcfad7 | 1206 | if (pr->flags.power) { |
3d339dcb | 1207 | cpuidle_unregister_device(dev); |
46bcfad7 DD |
1208 | acpi_processor_registered--; |
1209 | if (acpi_processor_registered == 0) | |
1210 | cpuidle_unregister_driver(&acpi_idle_driver); | |
1211 | } | |
1da177e4 | 1212 | |
46bcfad7 | 1213 | pr->flags.power_setup_done = 0; |
d550d98d | 1214 | return 0; |
1da177e4 | 1215 | } |