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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
60 | ||
61 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
62 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 63 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 64 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 65 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 | 66 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 | 68 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
69 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ |
70 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 71 | static void (*pm_idle_save) (void) __read_mostly; |
4f86d3a8 LB |
72 | #else |
73 | #define C2_OVERHEAD 1 /* 1us */ | |
74 | #define C3_OVERHEAD 1 /* 1us */ | |
75 | #endif | |
76 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) | |
1da177e4 | 77 | |
4f86d3a8 | 78 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
5b3f0e6c | 79 | #ifdef CONFIG_CPU_IDLE |
4f86d3a8 | 80 | module_param(max_cstate, uint, 0000); |
5b3f0e6c VP |
81 | #else |
82 | module_param(max_cstate, uint, 0644); | |
83 | #endif | |
b6835052 | 84 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
85 | module_param(nocst, uint, 0000); |
86 | ||
4f86d3a8 | 87 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
88 | /* |
89 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
90 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
91 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
92 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
93 | * reduce history for more aggressive entry into C3 | |
94 | */ | |
b6835052 | 95 | static unsigned int bm_history __read_mostly = |
4be44fcd | 96 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 97 | module_param(bm_history, uint, 0644); |
4f86d3a8 LB |
98 | |
99 | static int acpi_processor_set_power_policy(struct acpi_processor *pr); | |
100 | ||
101 | #endif | |
1da177e4 LT |
102 | |
103 | /* | |
104 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
105 | * For now disable this. Probably a bug somewhere else. | |
106 | * | |
107 | * To skip this limit, boot/load with a large max_cstate limit. | |
108 | */ | |
1855256c | 109 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
110 | { |
111 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
112 | return 0; | |
113 | ||
3d35600a | 114 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
115 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
116 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 117 | |
3d35600a | 118 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
7ded5689 AR |
123 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
124 | callers to only run once -AK */ | |
125 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
126 | { set_max_cstate, "IBM ThinkPad R40e", { |
127 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
128 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
129 | { set_max_cstate, "IBM ThinkPad R40e", { |
130 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
131 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
132 | { set_max_cstate, "IBM ThinkPad R40e", { | |
133 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
134 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
135 | { set_max_cstate, "IBM ThinkPad R40e", { | |
136 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
137 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
138 | { set_max_cstate, "IBM ThinkPad R40e", { | |
139 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
140 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
141 | { set_max_cstate, "IBM ThinkPad R40e", { | |
142 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
143 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
144 | { set_max_cstate, "IBM ThinkPad R40e", { | |
145 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
146 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
147 | { set_max_cstate, "IBM ThinkPad R40e", { | |
148 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
149 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
150 | { set_max_cstate, "IBM ThinkPad R40e", { | |
151 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
152 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
153 | { set_max_cstate, "IBM ThinkPad R40e", { | |
154 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
155 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
156 | { set_max_cstate, "IBM ThinkPad R40e", { | |
157 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
158 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
159 | { set_max_cstate, "IBM ThinkPad R40e", { | |
160 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
161 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
162 | { set_max_cstate, "IBM ThinkPad R40e", { | |
163 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
164 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
165 | { set_max_cstate, "IBM ThinkPad R40e", { | |
166 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
167 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
168 | { set_max_cstate, "IBM ThinkPad R40e", { | |
169 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
170 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
171 | { set_max_cstate, "IBM ThinkPad R40e", { | |
172 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
173 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
174 | { set_max_cstate, "Medion 41700", { | |
175 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
176 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
177 | { set_max_cstate, "Clevo 5600D", { | |
178 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
179 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 180 | (void *)2}, |
1da177e4 LT |
181 | {}, |
182 | }; | |
183 | ||
4be44fcd | 184 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
185 | { |
186 | if (t2 >= t1) | |
187 | return (t2 - t1); | |
cee324b1 | 188 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
189 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
190 | else | |
191 | return ((0xFFFFFFFF - t1) + t2); | |
192 | } | |
193 | ||
4f86d3a8 LB |
194 | static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) |
195 | { | |
196 | if (t2 >= t1) | |
197 | return PM_TIMER_TICKS_TO_US(t2 - t1); | |
198 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) | |
199 | return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); | |
200 | else | |
201 | return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); | |
202 | } | |
203 | ||
2e906655 | 204 | /* |
205 | * Callers should disable interrupts before the call and enable | |
206 | * interrupts after return. | |
207 | */ | |
ddc081a1 VP |
208 | static void acpi_safe_halt(void) |
209 | { | |
210 | current_thread_info()->status &= ~TS_POLLING; | |
211 | /* | |
212 | * TS_POLLING-cleared state must be visible before we | |
213 | * test NEED_RESCHED: | |
214 | */ | |
215 | smp_mb(); | |
216 | if (!need_resched()) | |
217 | safe_halt(); | |
218 | current_thread_info()->status |= TS_POLLING; | |
219 | } | |
220 | ||
4f86d3a8 LB |
221 | #ifndef CONFIG_CPU_IDLE |
222 | ||
1da177e4 | 223 | static void |
4be44fcd LB |
224 | acpi_processor_power_activate(struct acpi_processor *pr, |
225 | struct acpi_processor_cx *new) | |
1da177e4 | 226 | { |
4be44fcd | 227 | struct acpi_processor_cx *old; |
1da177e4 LT |
228 | |
229 | if (!pr || !new) | |
230 | return; | |
231 | ||
232 | old = pr->power.state; | |
233 | ||
234 | if (old) | |
235 | old->promotion.count = 0; | |
4be44fcd | 236 | new->demotion.count = 0; |
1da177e4 LT |
237 | |
238 | /* Cleanup from old state. */ | |
239 | if (old) { | |
240 | switch (old->type) { | |
241 | case ACPI_STATE_C3: | |
242 | /* Disable bus master reload */ | |
02df8b93 | 243 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 244 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
245 | break; |
246 | } | |
247 | } | |
248 | ||
249 | /* Prepare to use new state. */ | |
250 | switch (new->type) { | |
251 | case ACPI_STATE_C3: | |
252 | /* Enable bus master reload */ | |
02df8b93 | 253 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 254 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
255 | break; |
256 | } | |
257 | ||
258 | pr->power.state = new; | |
259 | ||
260 | return; | |
261 | } | |
262 | ||
4be44fcd | 263 | static atomic_t c3_cpu_count; |
1da177e4 | 264 | |
991528d7 VP |
265 | /* Common C-state entry for C2, C3, .. */ |
266 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
267 | { | |
268 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
269 | /* Call into architectural FFH based C-state */ | |
270 | acpi_processor_ffh_cstate_enter(cstate); | |
271 | } else { | |
272 | int unused; | |
273 | /* IO port based C-state */ | |
274 | inb(cstate->address); | |
275 | /* Dummy wait op - must do something useless after P_LVL2 read | |
276 | because chipsets cannot guarantee that STPCLK# signal | |
277 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 278 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
279 | } |
280 | } | |
4f86d3a8 | 281 | #endif /* !CONFIG_CPU_IDLE */ |
991528d7 | 282 | |
169a0abb TG |
283 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
284 | ||
285 | /* | |
286 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
287 | * This seems to be a common problem on AMD boxen, but other vendors |
288 | * are affected too. We pick the most conservative approach: we assume | |
289 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
290 | */ |
291 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
292 | struct acpi_processor_cx *cx) | |
293 | { | |
294 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 295 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
296 | |
297 | /* | |
298 | * Check, if one of the previous states already marked the lapic | |
299 | * unstable | |
300 | */ | |
301 | if (pwr->timer_broadcast_on_state < state) | |
302 | return; | |
303 | ||
e585bef8 | 304 | if (cx->type >= type) |
296d93cd | 305 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
306 | } |
307 | ||
308 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
309 | { | |
e9e2cdb4 TG |
310 | unsigned long reason; |
311 | ||
312 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
313 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
314 | ||
315 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
316 | } |
317 | ||
318 | /* Power(C) State timer broadcast control */ | |
319 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
320 | struct acpi_processor_cx *cx, | |
321 | int broadcast) | |
322 | { | |
e9e2cdb4 TG |
323 | int state = cx - pr->power.states; |
324 | ||
325 | if (state >= pr->power.timer_broadcast_on_state) { | |
326 | unsigned long reason; | |
327 | ||
328 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
329 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
330 | clockevents_notify(reason, &pr->id); | |
331 | } | |
169a0abb TG |
332 | } |
333 | ||
334 | #else | |
335 | ||
336 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
337 | struct acpi_processor_cx *cstate) { } | |
338 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
339 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
340 | struct acpi_processor_cx *cx, | |
341 | int broadcast) | |
342 | { | |
343 | } | |
169a0abb TG |
344 | |
345 | #endif | |
346 | ||
b04e7bdb TG |
347 | /* |
348 | * Suspend / resume control | |
349 | */ | |
350 | static int acpi_idle_suspend; | |
351 | ||
352 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
353 | { | |
354 | acpi_idle_suspend = 1; | |
355 | return 0; | |
356 | } | |
357 | ||
358 | int acpi_processor_resume(struct acpi_device * device) | |
359 | { | |
360 | acpi_idle_suspend = 0; | |
361 | return 0; | |
362 | } | |
363 | ||
ddb25f9a AK |
364 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
365 | static int tsc_halts_in_c(int state) | |
366 | { | |
367 | switch (boot_cpu_data.x86_vendor) { | |
368 | case X86_VENDOR_AMD: | |
369 | /* | |
370 | * AMD Fam10h TSC will tick in all | |
371 | * C/P/S0/S1 states when this bit is set. | |
372 | */ | |
373 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
374 | return 0; | |
375 | /*FALL THROUGH*/ | |
376 | case X86_VENDOR_INTEL: | |
377 | /* Several cases known where TSC halts in C2 too */ | |
378 | default: | |
379 | return state > ACPI_STATE_C1; | |
380 | } | |
381 | } | |
382 | #endif | |
383 | ||
4f86d3a8 | 384 | #ifndef CONFIG_CPU_IDLE |
4be44fcd | 385 | static void acpi_processor_idle(void) |
1da177e4 | 386 | { |
4be44fcd | 387 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
388 | struct acpi_processor_cx *cx = NULL; |
389 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
390 | int sleep_ticks = 0; |
391 | u32 t1, t2 = 0; | |
1da177e4 | 392 | |
1da177e4 LT |
393 | /* |
394 | * Interrupts must be disabled during bus mastering calculations and | |
395 | * for C2/C3 transitions. | |
396 | */ | |
397 | local_irq_disable(); | |
398 | ||
d5a3d32a VP |
399 | pr = processors[smp_processor_id()]; |
400 | if (!pr) { | |
401 | local_irq_enable(); | |
402 | return; | |
403 | } | |
404 | ||
1da177e4 LT |
405 | /* |
406 | * Check whether we truly need to go idle, or should | |
407 | * reschedule: | |
408 | */ | |
409 | if (unlikely(need_resched())) { | |
410 | local_irq_enable(); | |
411 | return; | |
412 | } | |
413 | ||
414 | cx = pr->power.state; | |
b04e7bdb | 415 | if (!cx || acpi_idle_suspend) { |
64c7c8f8 NP |
416 | if (pm_idle_save) |
417 | pm_idle_save(); | |
418 | else | |
419 | acpi_safe_halt(); | |
2e906655 | 420 | |
421 | local_irq_enable(); | |
64c7c8f8 NP |
422 | return; |
423 | } | |
1da177e4 LT |
424 | |
425 | /* | |
426 | * Check BM Activity | |
427 | * ----------------- | |
428 | * Check for bus mastering activity (if required), record, and check | |
429 | * for demotion. | |
430 | */ | |
431 | if (pr->flags.bm_check) { | |
4be44fcd LB |
432 | u32 bm_status = 0; |
433 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 434 | |
c5ab81ca DB |
435 | if (diff > 31) |
436 | diff = 31; | |
1da177e4 | 437 | |
c5ab81ca | 438 | pr->power.bm_activity <<= diff; |
1da177e4 | 439 | |
d8c71b6d | 440 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 441 | if (bm_status) { |
c5ab81ca | 442 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 443 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
444 | } |
445 | /* | |
446 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
447 | * the true state of bus mastering activity; forcing us to | |
448 | * manually check the BMIDEA bit of each IDE channel. | |
449 | */ | |
450 | else if (errata.piix4.bmisx) { | |
451 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 452 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 453 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
454 | } |
455 | ||
456 | pr->power.bm_check_timestamp = jiffies; | |
457 | ||
458 | /* | |
c4a001b1 | 459 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
460 | * to avoid a faulty transition. Note that the processor |
461 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 462 | * function) but should upon the next. |
1da177e4 LT |
463 | * |
464 | * TBD: A better policy might be to fallback to the demotion | |
465 | * state (use it for this quantum only) istead of | |
466 | * demoting -- and rely on duration as our sole demotion | |
467 | * qualification. This may, however, introduce DMA | |
468 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
469 | */ | |
c4a001b1 DB |
470 | if ((pr->power.bm_activity & 0x1) && |
471 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
472 | local_irq_enable(); |
473 | next_state = cx->demotion.state; | |
474 | goto end; | |
475 | } | |
476 | } | |
477 | ||
4c033552 VP |
478 | #ifdef CONFIG_HOTPLUG_CPU |
479 | /* | |
480 | * Check for P_LVL2_UP flag before entering C2 and above on | |
481 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
482 | * detection phase, to work cleanly with logical CPU hotplug. | |
483 | */ | |
4f86d3a8 | 484 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
cee324b1 | 485 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 486 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 487 | #endif |
1e483969 | 488 | |
1da177e4 LT |
489 | /* |
490 | * Sleep: | |
491 | * ------ | |
492 | * Invoke the current Cx state to put the processor to sleep. | |
493 | */ | |
2a298a35 | 494 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 495 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
496 | /* |
497 | * TS_POLLING-cleared state must be visible before we | |
498 | * test NEED_RESCHED: | |
499 | */ | |
500 | smp_mb(); | |
2a298a35 | 501 | if (need_resched()) { |
495ab9c0 | 502 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 503 | local_irq_enable(); |
2a298a35 NP |
504 | return; |
505 | } | |
506 | } | |
507 | ||
1da177e4 LT |
508 | switch (cx->type) { |
509 | ||
510 | case ACPI_STATE_C1: | |
511 | /* | |
512 | * Invoke C1. | |
513 | * Use the appropriate idle routine, the one that would | |
514 | * be used without acpi C-states. | |
515 | */ | |
516 | if (pm_idle_save) | |
517 | pm_idle_save(); | |
518 | else | |
64c7c8f8 NP |
519 | acpi_safe_halt(); |
520 | ||
1da177e4 | 521 | /* |
4be44fcd | 522 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
523 | * go to an ISR rather than here. Need to instrument |
524 | * base interrupt handler. | |
2aa44d05 IM |
525 | * |
526 | * Note: the TSC better not stop in C1, sched_clock() will | |
527 | * skew otherwise. | |
1da177e4 LT |
528 | */ |
529 | sleep_ticks = 0xFFFFFFFF; | |
2e906655 | 530 | local_irq_enable(); |
1da177e4 LT |
531 | break; |
532 | ||
533 | case ACPI_STATE_C2: | |
534 | /* Get start time (ticks) */ | |
cee324b1 | 535 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
2aa44d05 IM |
536 | /* Tell the scheduler that we are going deep-idle: */ |
537 | sched_clock_idle_sleep_event(); | |
1da177e4 | 538 | /* Invoke C2 */ |
e9e2cdb4 | 539 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 540 | acpi_cstate_enter(cx); |
1da177e4 | 541 | /* Get end time (ticks) */ |
cee324b1 | 542 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 543 | |
0aa366f3 | 544 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 545 | /* TSC halts in C2, so notify users */ |
ddb25f9a AK |
546 | if (tsc_halts_in_c(ACPI_STATE_C2)) |
547 | mark_tsc_unstable("possible TSC halt in C2"); | |
539eb11e | 548 | #endif |
2aa44d05 IM |
549 | /* Compute time (ticks) that we were actually asleep */ |
550 | sleep_ticks = ticks_elapsed(t1, t2); | |
551 | ||
552 | /* Tell the scheduler how much we idled: */ | |
553 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
554 | ||
1da177e4 LT |
555 | /* Re-enable interrupts */ |
556 | local_irq_enable(); | |
2aa44d05 IM |
557 | /* Do not account our idle-switching overhead: */ |
558 | sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; | |
559 | ||
495ab9c0 | 560 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 561 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
562 | break; |
563 | ||
564 | case ACPI_STATE_C3: | |
bde6f5f5 | 565 | acpi_unlazy_tlb(smp_processor_id()); |
e17bcb43 TG |
566 | /* |
567 | * Must be done before busmaster disable as we might | |
568 | * need to access HPET ! | |
569 | */ | |
570 | acpi_state_timer_broadcast(pr, cx, 1); | |
18eab855 VP |
571 | /* |
572 | * disable bus master | |
573 | * bm_check implies we need ARB_DIS | |
574 | * !bm_check implies we need cache flush | |
575 | * bm_control implies whether we can do ARB_DIS | |
576 | * | |
577 | * That leaves a case where bm_check is set and bm_control is | |
578 | * not set. In that case we cannot do much, we enter C3 | |
579 | * without doing anything. | |
580 | */ | |
581 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 582 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 583 | num_online_cpus()) { |
02df8b93 VP |
584 | /* |
585 | * All CPUs are trying to go to C3 | |
586 | * Disable bus master arbitration | |
587 | */ | |
d8c71b6d | 588 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 589 | } |
18eab855 | 590 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
591 | /* SMP with no shared cache... Invalidate cache */ |
592 | ACPI_FLUSH_CPU_CACHE(); | |
593 | } | |
4be44fcd | 594 | |
1da177e4 | 595 | /* Get start time (ticks) */ |
cee324b1 | 596 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 597 | /* Invoke C3 */ |
2aa44d05 IM |
598 | /* Tell the scheduler that we are going deep-idle: */ |
599 | sched_clock_idle_sleep_event(); | |
991528d7 | 600 | acpi_cstate_enter(cx); |
1da177e4 | 601 | /* Get end time (ticks) */ |
cee324b1 | 602 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 603 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
604 | /* Enable bus master arbitration */ |
605 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 606 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
607 | } |
608 | ||
0aa366f3 | 609 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 610 | /* TSC halts in C3, so notify users */ |
ddb25f9a AK |
611 | if (tsc_halts_in_c(ACPI_STATE_C3)) |
612 | mark_tsc_unstable("TSC halts in C3"); | |
539eb11e | 613 | #endif |
2aa44d05 IM |
614 | /* Compute time (ticks) that we were actually asleep */ |
615 | sleep_ticks = ticks_elapsed(t1, t2); | |
616 | /* Tell the scheduler how much we idled: */ | |
617 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
618 | ||
1da177e4 LT |
619 | /* Re-enable interrupts */ |
620 | local_irq_enable(); | |
2aa44d05 IM |
621 | /* Do not account our idle-switching overhead: */ |
622 | sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; | |
623 | ||
495ab9c0 | 624 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 625 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
626 | break; |
627 | ||
628 | default: | |
629 | local_irq_enable(); | |
630 | return; | |
631 | } | |
a3c6598f DB |
632 | cx->usage++; |
633 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
634 | cx->time += sleep_ticks; | |
1da177e4 LT |
635 | |
636 | next_state = pr->power.state; | |
637 | ||
1e483969 DSL |
638 | #ifdef CONFIG_HOTPLUG_CPU |
639 | /* Don't do promotion/demotion */ | |
640 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 641 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
642 | next_state = cx; |
643 | goto end; | |
644 | } | |
645 | #endif | |
646 | ||
1da177e4 LT |
647 | /* |
648 | * Promotion? | |
649 | * ---------- | |
650 | * Track the number of longs (time asleep is greater than threshold) | |
651 | * and promote when the count threshold is reached. Note that bus | |
652 | * mastering activity may prevent promotions. | |
653 | * Do not promote above max_cstate. | |
654 | */ | |
655 | if (cx->promotion.state && | |
656 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e | 657 | if (sleep_ticks > cx->promotion.threshold.ticks && |
f011e2e2 MG |
658 | cx->promotion.state->latency <= |
659 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { | |
1da177e4 | 660 | cx->promotion.count++; |
4be44fcd LB |
661 | cx->demotion.count = 0; |
662 | if (cx->promotion.count >= | |
663 | cx->promotion.threshold.count) { | |
1da177e4 | 664 | if (pr->flags.bm_check) { |
4be44fcd LB |
665 | if (! |
666 | (pr->power.bm_activity & cx-> | |
667 | promotion.threshold.bm)) { | |
668 | next_state = | |
669 | cx->promotion.state; | |
1da177e4 LT |
670 | goto end; |
671 | } | |
4be44fcd | 672 | } else { |
1da177e4 LT |
673 | next_state = cx->promotion.state; |
674 | goto end; | |
675 | } | |
676 | } | |
677 | } | |
678 | } | |
679 | ||
680 | /* | |
681 | * Demotion? | |
682 | * --------- | |
683 | * Track the number of shorts (time asleep is less than time threshold) | |
684 | * and demote when the usage threshold is reached. | |
685 | */ | |
686 | if (cx->demotion.state) { | |
687 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
688 | cx->demotion.count++; | |
689 | cx->promotion.count = 0; | |
690 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
691 | next_state = cx->demotion.state; | |
692 | goto end; | |
693 | } | |
694 | } | |
695 | } | |
696 | ||
4be44fcd | 697 | end: |
1da177e4 LT |
698 | /* |
699 | * Demote if current state exceeds max_cstate | |
5c87579e | 700 | * or if the latency of the current state is unacceptable |
1da177e4 | 701 | */ |
5c87579e | 702 | if ((pr->power.state - pr->power.states) > max_cstate || |
f011e2e2 MG |
703 | pr->power.state->latency > |
704 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { | |
1da177e4 LT |
705 | if (cx->demotion.state) |
706 | next_state = cx->demotion.state; | |
707 | } | |
708 | ||
709 | /* | |
710 | * New Cx State? | |
711 | * ------------- | |
712 | * If we're going to start using a new Cx state we must clean up | |
713 | * from the previous and prepare to use the new. | |
714 | */ | |
715 | if (next_state != pr->power.state) | |
716 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
717 | } |
718 | ||
4be44fcd | 719 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
720 | { |
721 | unsigned int i; | |
722 | unsigned int state_is_set = 0; | |
723 | struct acpi_processor_cx *lower = NULL; | |
724 | struct acpi_processor_cx *higher = NULL; | |
725 | struct acpi_processor_cx *cx; | |
726 | ||
1da177e4 LT |
727 | |
728 | if (!pr) | |
d550d98d | 729 | return -EINVAL; |
1da177e4 LT |
730 | |
731 | /* | |
732 | * This function sets the default Cx state policy (OS idle handler). | |
733 | * Our scheme is to promote quickly to C2 but more conservatively | |
734 | * to C3. We're favoring C2 for its characteristics of low latency | |
735 | * (quick response), good power savings, and ability to allow bus | |
736 | * mastering activity. Note that the Cx state policy is completely | |
737 | * customizable and can be altered dynamically. | |
738 | */ | |
739 | ||
740 | /* startup state */ | |
4be44fcd | 741 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
742 | cx = &pr->power.states[i]; |
743 | if (!cx->valid) | |
744 | continue; | |
745 | ||
746 | if (!state_is_set) | |
747 | pr->power.state = cx; | |
748 | state_is_set++; | |
749 | break; | |
4be44fcd | 750 | } |
1da177e4 LT |
751 | |
752 | if (!state_is_set) | |
d550d98d | 753 | return -ENODEV; |
1da177e4 LT |
754 | |
755 | /* demotion */ | |
4be44fcd | 756 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
757 | cx = &pr->power.states[i]; |
758 | if (!cx->valid) | |
759 | continue; | |
760 | ||
761 | if (lower) { | |
762 | cx->demotion.state = lower; | |
763 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
764 | cx->demotion.threshold.count = 1; | |
765 | if (cx->type == ACPI_STATE_C3) | |
766 | cx->demotion.threshold.bm = bm_history; | |
767 | } | |
768 | ||
769 | lower = cx; | |
770 | } | |
771 | ||
772 | /* promotion */ | |
773 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
774 | cx = &pr->power.states[i]; | |
775 | if (!cx->valid) | |
776 | continue; | |
777 | ||
778 | if (higher) { | |
4be44fcd | 779 | cx->promotion.state = higher; |
1da177e4 LT |
780 | cx->promotion.threshold.ticks = cx->latency_ticks; |
781 | if (cx->type >= ACPI_STATE_C2) | |
782 | cx->promotion.threshold.count = 4; | |
783 | else | |
784 | cx->promotion.threshold.count = 10; | |
785 | if (higher->type == ACPI_STATE_C3) | |
786 | cx->promotion.threshold.bm = bm_history; | |
787 | } | |
788 | ||
789 | higher = cx; | |
790 | } | |
791 | ||
d550d98d | 792 | return 0; |
1da177e4 | 793 | } |
4f86d3a8 | 794 | #endif /* !CONFIG_CPU_IDLE */ |
1da177e4 | 795 | |
4be44fcd | 796 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 797 | { |
1da177e4 LT |
798 | |
799 | if (!pr) | |
d550d98d | 800 | return -EINVAL; |
1da177e4 LT |
801 | |
802 | if (!pr->pblk) | |
d550d98d | 803 | return -ENODEV; |
1da177e4 | 804 | |
1da177e4 | 805 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
806 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
807 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
808 | ||
4c033552 VP |
809 | #ifndef CONFIG_HOTPLUG_CPU |
810 | /* | |
811 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 812 | * an SMP system. |
4c033552 | 813 | */ |
ad71860a | 814 | if ((num_online_cpus() > 1) && |
cee324b1 | 815 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 816 | return -ENODEV; |
4c033552 VP |
817 | #endif |
818 | ||
1da177e4 LT |
819 | /* determine C2 and C3 address from pblk */ |
820 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
821 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
822 | ||
823 | /* determine latencies from FADT */ | |
cee324b1 AS |
824 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
825 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
826 | |
827 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
828 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
829 | pr->power.states[ACPI_STATE_C2].address, | |
830 | pr->power.states[ACPI_STATE_C3].address)); | |
831 | ||
d550d98d | 832 | return 0; |
1da177e4 LT |
833 | } |
834 | ||
991528d7 | 835 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 836 | { |
991528d7 VP |
837 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
838 | /* set the first C-State to C1 */ | |
839 | /* all processors need to support C1 */ | |
840 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
841 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
842 | } | |
843 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 844 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 845 | return 0; |
acf05f4b VP |
846 | } |
847 | ||
4be44fcd | 848 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 849 | { |
4be44fcd LB |
850 | acpi_status status = 0; |
851 | acpi_integer count; | |
cf824788 | 852 | int current_count; |
4be44fcd LB |
853 | int i; |
854 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
855 | union acpi_object *cst; | |
1da177e4 | 856 | |
1da177e4 | 857 | |
1da177e4 | 858 | if (nocst) |
d550d98d | 859 | return -ENODEV; |
1da177e4 | 860 | |
991528d7 | 861 | current_count = 0; |
1da177e4 LT |
862 | |
863 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
864 | if (ACPI_FAILURE(status)) { | |
865 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 866 | return -ENODEV; |
4be44fcd | 867 | } |
1da177e4 | 868 | |
50dd0969 | 869 | cst = buffer.pointer; |
1da177e4 LT |
870 | |
871 | /* There must be at least 2 elements */ | |
872 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 873 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
874 | status = -EFAULT; |
875 | goto end; | |
876 | } | |
877 | ||
878 | count = cst->package.elements[0].integer.value; | |
879 | ||
880 | /* Validate number of power states. */ | |
881 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 882 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
883 | status = -EFAULT; |
884 | goto end; | |
885 | } | |
886 | ||
1da177e4 LT |
887 | /* Tell driver that at least _CST is supported. */ |
888 | pr->flags.has_cst = 1; | |
889 | ||
890 | for (i = 1; i <= count; i++) { | |
891 | union acpi_object *element; | |
892 | union acpi_object *obj; | |
893 | struct acpi_power_register *reg; | |
894 | struct acpi_processor_cx cx; | |
895 | ||
896 | memset(&cx, 0, sizeof(cx)); | |
897 | ||
50dd0969 | 898 | element = &(cst->package.elements[i]); |
1da177e4 LT |
899 | if (element->type != ACPI_TYPE_PACKAGE) |
900 | continue; | |
901 | ||
902 | if (element->package.count != 4) | |
903 | continue; | |
904 | ||
50dd0969 | 905 | obj = &(element->package.elements[0]); |
1da177e4 LT |
906 | |
907 | if (obj->type != ACPI_TYPE_BUFFER) | |
908 | continue; | |
909 | ||
4be44fcd | 910 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
911 | |
912 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 913 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
914 | continue; |
915 | ||
1da177e4 | 916 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 917 | obj = &(element->package.elements[1]); |
1da177e4 LT |
918 | if (obj->type != ACPI_TYPE_INTEGER) |
919 | continue; | |
920 | ||
921 | cx.type = obj->integer.value; | |
991528d7 VP |
922 | /* |
923 | * Some buggy BIOSes won't list C1 in _CST - | |
924 | * Let acpi_processor_get_power_info_default() handle them later | |
925 | */ | |
926 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
927 | current_count++; | |
928 | ||
929 | cx.address = reg->address; | |
930 | cx.index = current_count + 1; | |
931 | ||
932 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
933 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
934 | if (acpi_processor_ffh_cstate_probe | |
935 | (pr->id, &cx, reg) == 0) { | |
936 | cx.space_id = ACPI_CSTATE_FFH; | |
937 | } else if (cx.type != ACPI_STATE_C1) { | |
938 | /* | |
939 | * C1 is a special case where FIXED_HARDWARE | |
940 | * can be handled in non-MWAIT way as well. | |
941 | * In that case, save this _CST entry info. | |
942 | * That is, we retain space_id of SYSTEM_IO for | |
943 | * halt based C1. | |
944 | * Otherwise, ignore this info and continue. | |
945 | */ | |
946 | continue; | |
947 | } | |
948 | } | |
1da177e4 | 949 | |
50dd0969 | 950 | obj = &(element->package.elements[2]); |
1da177e4 LT |
951 | if (obj->type != ACPI_TYPE_INTEGER) |
952 | continue; | |
953 | ||
954 | cx.latency = obj->integer.value; | |
955 | ||
50dd0969 | 956 | obj = &(element->package.elements[3]); |
1da177e4 LT |
957 | if (obj->type != ACPI_TYPE_INTEGER) |
958 | continue; | |
959 | ||
960 | cx.power = obj->integer.value; | |
961 | ||
cf824788 JM |
962 | current_count++; |
963 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
964 | ||
965 | /* | |
966 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
967 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
968 | */ | |
969 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
970 | printk(KERN_WARNING | |
971 | "Limiting number of power states to max (%d)\n", | |
972 | ACPI_PROCESSOR_MAX_POWER); | |
973 | printk(KERN_WARNING | |
974 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
975 | break; | |
976 | } | |
1da177e4 LT |
977 | } |
978 | ||
4be44fcd | 979 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 980 | current_count)); |
1da177e4 LT |
981 | |
982 | /* Validate number of power states discovered */ | |
cf824788 | 983 | if (current_count < 2) |
6d93c648 | 984 | status = -EFAULT; |
1da177e4 | 985 | |
4be44fcd | 986 | end: |
02438d87 | 987 | kfree(buffer.pointer); |
1da177e4 | 988 | |
d550d98d | 989 | return status; |
1da177e4 LT |
990 | } |
991 | ||
1da177e4 LT |
992 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
993 | { | |
1da177e4 LT |
994 | |
995 | if (!cx->address) | |
d550d98d | 996 | return; |
1da177e4 LT |
997 | |
998 | /* | |
999 | * C2 latency must be less than or equal to 100 | |
1000 | * microseconds. | |
1001 | */ | |
1002 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
1003 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1004 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1005 | return; |
1da177e4 LT |
1006 | } |
1007 | ||
1da177e4 LT |
1008 | /* |
1009 | * Otherwise we've met all of our C2 requirements. | |
1010 | * Normalize the C2 latency to expidite policy | |
1011 | */ | |
1012 | cx->valid = 1; | |
4f86d3a8 LB |
1013 | |
1014 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1015 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1016 | #else |
1017 | cx->latency_ticks = cx->latency; | |
1018 | #endif | |
1da177e4 | 1019 | |
d550d98d | 1020 | return; |
1da177e4 LT |
1021 | } |
1022 | ||
4be44fcd LB |
1023 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
1024 | struct acpi_processor_cx *cx) | |
1da177e4 | 1025 | { |
02df8b93 VP |
1026 | static int bm_check_flag; |
1027 | ||
1da177e4 LT |
1028 | |
1029 | if (!cx->address) | |
d550d98d | 1030 | return; |
1da177e4 LT |
1031 | |
1032 | /* | |
1033 | * C3 latency must be less than or equal to 1000 | |
1034 | * microseconds. | |
1035 | */ | |
1036 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
1037 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1038 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1039 | return; |
1da177e4 LT |
1040 | } |
1041 | ||
1da177e4 LT |
1042 | /* |
1043 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
1044 | * DMA transfers are used by any ISA device to avoid livelock. | |
1045 | * Note that we could disable Type-F DMA (as recommended by | |
1046 | * the erratum), but this is known to disrupt certain ISA | |
1047 | * devices thus we take the conservative approach. | |
1048 | */ | |
1049 | else if (errata.piix4.fdma) { | |
1050 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1051 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 1052 | return; |
1da177e4 LT |
1053 | } |
1054 | ||
02df8b93 VP |
1055 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
1056 | if (!bm_check_flag) { | |
1057 | /* Determine whether bm_check is needed based on CPU */ | |
1058 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
1059 | bm_check_flag = pr->flags.bm_check; | |
1060 | } else { | |
1061 | pr->flags.bm_check = bm_check_flag; | |
1062 | } | |
1063 | ||
1064 | if (pr->flags.bm_check) { | |
02df8b93 | 1065 | if (!pr->flags.bm_control) { |
ed3110ef VP |
1066 | if (pr->flags.has_cst != 1) { |
1067 | /* bus mastering control is necessary */ | |
1068 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1069 | "C3 support requires BM control\n")); | |
1070 | return; | |
1071 | } else { | |
1072 | /* Here we enter C3 without bus mastering */ | |
1073 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1074 | "C3 support without BM control\n")); | |
1075 | } | |
02df8b93 VP |
1076 | } |
1077 | } else { | |
02df8b93 VP |
1078 | /* |
1079 | * WBINVD should be set in fadt, for C3 state to be | |
1080 | * supported on when bm_check is not required. | |
1081 | */ | |
cee324b1 | 1082 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 1083 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1084 | "Cache invalidation should work properly" |
1085 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1086 | return; |
02df8b93 | 1087 | } |
d8c71b6d | 1088 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1089 | } |
1090 | ||
1da177e4 LT |
1091 | /* |
1092 | * Otherwise we've met all of our C3 requirements. | |
1093 | * Normalize the C3 latency to expidite policy. Enable | |
1094 | * checking of bus mastering status (bm_check) so we can | |
1095 | * use this in our C3 policy | |
1096 | */ | |
1097 | cx->valid = 1; | |
4f86d3a8 LB |
1098 | |
1099 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1100 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1101 | #else |
1102 | cx->latency_ticks = cx->latency; | |
1103 | #endif | |
1da177e4 | 1104 | |
d550d98d | 1105 | return; |
1da177e4 LT |
1106 | } |
1107 | ||
1da177e4 LT |
1108 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1109 | { | |
1110 | unsigned int i; | |
1111 | unsigned int working = 0; | |
6eb0a0fd | 1112 | |
169a0abb | 1113 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1114 | |
4be44fcd | 1115 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1116 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1117 | ||
1118 | switch (cx->type) { | |
1119 | case ACPI_STATE_C1: | |
1120 | cx->valid = 1; | |
1121 | break; | |
1122 | ||
1123 | case ACPI_STATE_C2: | |
1124 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1125 | if (cx->valid) |
169a0abb | 1126 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1127 | break; |
1128 | ||
1129 | case ACPI_STATE_C3: | |
1130 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1131 | if (cx->valid) |
169a0abb | 1132 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1133 | break; |
1134 | } | |
1135 | ||
1136 | if (cx->valid) | |
1137 | working++; | |
1138 | } | |
bd663347 | 1139 | |
169a0abb | 1140 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1141 | |
1142 | return (working); | |
1143 | } | |
1144 | ||
4be44fcd | 1145 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1146 | { |
1147 | unsigned int i; | |
1148 | int result; | |
1149 | ||
1da177e4 LT |
1150 | |
1151 | /* NOTE: the idle thread may not be running while calling | |
1152 | * this function */ | |
1153 | ||
991528d7 VP |
1154 | /* Zero initialize all the C-states info. */ |
1155 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1156 | ||
1da177e4 | 1157 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1158 | if (result == -ENODEV) |
c5a114f1 | 1159 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1160 | |
991528d7 VP |
1161 | if (result) |
1162 | return result; | |
1163 | ||
1164 | acpi_processor_get_power_info_default(pr); | |
1165 | ||
cf824788 | 1166 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 1167 | |
4f86d3a8 | 1168 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1169 | /* |
1170 | * Set Default Policy | |
1171 | * ------------------ | |
1172 | * Now that we know which states are supported, set the default | |
1173 | * policy. Note that this policy can be changed dynamically | |
1174 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1175 | * not on AC). | |
1176 | */ | |
1177 | result = acpi_processor_set_power_policy(pr); | |
1178 | if (result) | |
d550d98d | 1179 | return result; |
4f86d3a8 | 1180 | #endif |
1da177e4 LT |
1181 | |
1182 | /* | |
1183 | * if one state of type C2 or C3 is available, mark this | |
1184 | * CPU as being "idle manageable" | |
1185 | */ | |
1186 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1187 | if (pr->power.states[i].valid) { |
1da177e4 | 1188 | pr->power.count = i; |
2203d6ed LT |
1189 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1190 | pr->flags.power = 1; | |
acf05f4b | 1191 | } |
1da177e4 LT |
1192 | } |
1193 | ||
d550d98d | 1194 | return 0; |
1da177e4 LT |
1195 | } |
1196 | ||
1da177e4 LT |
1197 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
1198 | { | |
50dd0969 | 1199 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1200 | unsigned int i; |
1da177e4 | 1201 | |
1da177e4 LT |
1202 | |
1203 | if (!pr) | |
1204 | goto end; | |
1205 | ||
1206 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1207 | "max_cstate: C%d\n" |
5c87579e AV |
1208 | "bus master activity: %08x\n" |
1209 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1210 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e | 1211 | max_cstate, (unsigned)pr->power.bm_activity, |
f011e2e2 | 1212 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
1213 | |
1214 | seq_puts(seq, "states:\n"); | |
1215 | ||
1216 | for (i = 1; i <= pr->power.count; i++) { | |
1217 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1218 | (&pr->power.states[i] == |
1219 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1220 | |
1221 | if (!pr->power.states[i].valid) { | |
1222 | seq_puts(seq, "<not supported>\n"); | |
1223 | continue; | |
1224 | } | |
1225 | ||
1226 | switch (pr->power.states[i].type) { | |
1227 | case ACPI_STATE_C1: | |
1228 | seq_printf(seq, "type[C1] "); | |
1229 | break; | |
1230 | case ACPI_STATE_C2: | |
1231 | seq_printf(seq, "type[C2] "); | |
1232 | break; | |
1233 | case ACPI_STATE_C3: | |
1234 | seq_printf(seq, "type[C3] "); | |
1235 | break; | |
1236 | default: | |
1237 | seq_printf(seq, "type[--] "); | |
1238 | break; | |
1239 | } | |
1240 | ||
1241 | if (pr->power.states[i].promotion.state) | |
1242 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1243 | (pr->power.states[i].promotion.state - |
1244 | pr->power.states)); | |
1da177e4 LT |
1245 | else |
1246 | seq_puts(seq, "promotion[--] "); | |
1247 | ||
1248 | if (pr->power.states[i].demotion.state) | |
1249 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1250 | (pr->power.states[i].demotion.state - |
1251 | pr->power.states)); | |
1da177e4 LT |
1252 | else |
1253 | seq_puts(seq, "demotion[--] "); | |
1254 | ||
a3c6598f | 1255 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1256 | pr->power.states[i].latency, |
a3c6598f | 1257 | pr->power.states[i].usage, |
b0b7eaaf | 1258 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1259 | } |
1260 | ||
4be44fcd | 1261 | end: |
d550d98d | 1262 | return 0; |
1da177e4 LT |
1263 | } |
1264 | ||
1265 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1266 | { | |
1267 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1268 | PDE(inode)->data); |
1da177e4 LT |
1269 | } |
1270 | ||
d7508032 | 1271 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1272 | .open = acpi_processor_power_open_fs, |
1273 | .read = seq_read, | |
1274 | .llseek = seq_lseek, | |
1275 | .release = single_release, | |
1da177e4 LT |
1276 | }; |
1277 | ||
4f86d3a8 LB |
1278 | #ifndef CONFIG_CPU_IDLE |
1279 | ||
1280 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1281 | { | |
1282 | int result = 0; | |
1283 | ||
1284 | ||
1285 | if (!pr) | |
1286 | return -EINVAL; | |
1287 | ||
1288 | if (nocst) { | |
1289 | return -ENODEV; | |
1290 | } | |
1291 | ||
1292 | if (!pr->flags.power_setup_done) | |
1293 | return -ENODEV; | |
1294 | ||
1295 | /* Fall back to the default idle loop */ | |
1296 | pm_idle = pm_idle_save; | |
1297 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ | |
1298 | ||
1299 | pr->flags.power = 0; | |
1300 | result = acpi_processor_get_power_info(pr); | |
1301 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1302 | pm_idle = acpi_processor_idle; | |
1303 | ||
1304 | return result; | |
1305 | } | |
1306 | ||
1fec74a9 | 1307 | #ifdef CONFIG_SMP |
5c87579e AV |
1308 | static void smp_callback(void *v) |
1309 | { | |
1310 | /* we already woke the CPU up, nothing more to do */ | |
1311 | } | |
1312 | ||
1313 | /* | |
1314 | * This function gets called when a part of the kernel has a new latency | |
1315 | * requirement. This means we need to get all processors out of their C-state, | |
1316 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1317 | * wakes them all right up. | |
1318 | */ | |
1319 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1320 | unsigned long l, void *v) | |
1321 | { | |
1322 | smp_call_function(smp_callback, NULL, 0, 1); | |
1323 | return NOTIFY_OK; | |
1324 | } | |
1325 | ||
1326 | static struct notifier_block acpi_processor_latency_notifier = { | |
1327 | .notifier_call = acpi_processor_latency_notify, | |
1328 | }; | |
4f86d3a8 LB |
1329 | |
1330 | #endif | |
1331 | ||
1332 | #else /* CONFIG_CPU_IDLE */ | |
1333 | ||
1334 | /** | |
1335 | * acpi_idle_bm_check - checks if bus master activity was detected | |
1336 | */ | |
1337 | static int acpi_idle_bm_check(void) | |
1338 | { | |
1339 | u32 bm_status = 0; | |
1340 | ||
1341 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | |
1342 | if (bm_status) | |
1343 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | |
1344 | /* | |
1345 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
1346 | * the true state of bus mastering activity; forcing us to | |
1347 | * manually check the BMIDEA bit of each IDE channel. | |
1348 | */ | |
1349 | else if (errata.piix4.bmisx) { | |
1350 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
1351 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
1352 | bm_status = 1; | |
1353 | } | |
1354 | return bm_status; | |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state | |
1359 | * @pr: the processor | |
1360 | * @target: the new target state | |
1361 | */ | |
1362 | static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, | |
1363 | struct acpi_processor_cx *target) | |
1364 | { | |
1365 | if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { | |
1366 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); | |
1367 | pr->flags.bm_rld_set = 0; | |
1368 | } | |
1369 | ||
1370 | if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { | |
1371 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); | |
1372 | pr->flags.bm_rld_set = 1; | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | /** | |
1377 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
1378 | * @cx: cstate data | |
1379 | */ | |
1380 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
1381 | { | |
1382 | if (cx->space_id == ACPI_CSTATE_FFH) { | |
1383 | /* Call into architectural FFH based C-state */ | |
1384 | acpi_processor_ffh_cstate_enter(cx); | |
1385 | } else { | |
1386 | int unused; | |
1387 | /* IO port based C-state */ | |
1388 | inb(cx->address); | |
1389 | /* Dummy wait op - must do something useless after P_LVL2 read | |
1390 | because chipsets cannot guarantee that STPCLK# signal | |
1391 | gets asserted in time to freeze execution properly. */ | |
1392 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1393 | } | |
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
1398 | * @dev: the target CPU | |
1399 | * @state: the state data | |
1400 | * | |
1401 | * This is equivalent to the HALT instruction. | |
1402 | */ | |
1403 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
1404 | struct cpuidle_state *state) | |
1405 | { | |
1406 | struct acpi_processor *pr; | |
1407 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1408 | pr = processors[smp_processor_id()]; | |
1409 | ||
1410 | if (unlikely(!pr)) | |
1411 | return 0; | |
1412 | ||
2e906655 | 1413 | local_irq_disable(); |
4f86d3a8 LB |
1414 | if (pr->flags.bm_check) |
1415 | acpi_idle_update_bm_rld(pr, cx); | |
1416 | ||
ddc081a1 | 1417 | acpi_safe_halt(); |
4f86d3a8 | 1418 | |
2e906655 | 1419 | local_irq_enable(); |
4f86d3a8 LB |
1420 | cx->usage++; |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | /** | |
1426 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
1427 | * @dev: the target CPU | |
1428 | * @state: the state data | |
1429 | */ | |
1430 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
1431 | struct cpuidle_state *state) | |
1432 | { | |
1433 | struct acpi_processor *pr; | |
1434 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1435 | u32 t1, t2; | |
50629118 VP |
1436 | int sleep_ticks = 0; |
1437 | ||
4f86d3a8 LB |
1438 | pr = processors[smp_processor_id()]; |
1439 | ||
1440 | if (unlikely(!pr)) | |
1441 | return 0; | |
1442 | ||
e196441b LB |
1443 | if (acpi_idle_suspend) |
1444 | return(acpi_idle_enter_c1(dev, state)); | |
1445 | ||
4f86d3a8 LB |
1446 | local_irq_disable(); |
1447 | current_thread_info()->status &= ~TS_POLLING; | |
1448 | /* | |
1449 | * TS_POLLING-cleared state must be visible before we test | |
1450 | * NEED_RESCHED: | |
1451 | */ | |
1452 | smp_mb(); | |
1453 | ||
1454 | if (unlikely(need_resched())) { | |
1455 | current_thread_info()->status |= TS_POLLING; | |
1456 | local_irq_enable(); | |
1457 | return 0; | |
1458 | } | |
1459 | ||
bde6f5f5 | 1460 | acpi_unlazy_tlb(smp_processor_id()); |
e17bcb43 TG |
1461 | /* |
1462 | * Must be done before busmaster disable as we might need to | |
1463 | * access HPET ! | |
1464 | */ | |
1465 | acpi_state_timer_broadcast(pr, cx, 1); | |
1466 | ||
1467 | if (pr->flags.bm_check) | |
1468 | acpi_idle_update_bm_rld(pr, cx); | |
1469 | ||
4f86d3a8 LB |
1470 | if (cx->type == ACPI_STATE_C3) |
1471 | ACPI_FLUSH_CPU_CACHE(); | |
1472 | ||
1473 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
50629118 VP |
1474 | /* Tell the scheduler that we are going deep-idle: */ |
1475 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1476 | acpi_idle_do_entry(cx); |
1477 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1478 | ||
1479 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1480 | /* TSC could halt in idle, so notify users */ | |
ddb25f9a AK |
1481 | if (tsc_halts_in_c(cx->type)) |
1482 | mark_tsc_unstable("TSC halts in idle");; | |
4f86d3a8 | 1483 | #endif |
50629118 VP |
1484 | sleep_ticks = ticks_elapsed(t1, t2); |
1485 | ||
1486 | /* Tell the scheduler how much we idled: */ | |
1487 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1488 | |
1489 | local_irq_enable(); | |
1490 | current_thread_info()->status |= TS_POLLING; | |
1491 | ||
1492 | cx->usage++; | |
1493 | ||
1494 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1495 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1496 | return ticks_elapsed_in_us(t1, t2); |
1497 | } | |
1498 | ||
1499 | static int c3_cpu_count; | |
1500 | static DEFINE_SPINLOCK(c3_lock); | |
1501 | ||
1502 | /** | |
1503 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
1504 | * @dev: the target CPU | |
1505 | * @state: the state data | |
1506 | * | |
1507 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
1508 | */ | |
1509 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
1510 | struct cpuidle_state *state) | |
1511 | { | |
1512 | struct acpi_processor *pr; | |
1513 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1514 | u32 t1, t2; | |
50629118 VP |
1515 | int sleep_ticks = 0; |
1516 | ||
4f86d3a8 LB |
1517 | pr = processors[smp_processor_id()]; |
1518 | ||
1519 | if (unlikely(!pr)) | |
1520 | return 0; | |
1521 | ||
e196441b LB |
1522 | if (acpi_idle_suspend) |
1523 | return(acpi_idle_enter_c1(dev, state)); | |
1524 | ||
ddc081a1 VP |
1525 | if (acpi_idle_bm_check()) { |
1526 | if (dev->safe_state) { | |
1527 | return dev->safe_state->enter(dev, dev->safe_state); | |
1528 | } else { | |
2e906655 | 1529 | local_irq_disable(); |
ddc081a1 | 1530 | acpi_safe_halt(); |
2e906655 | 1531 | local_irq_enable(); |
ddc081a1 VP |
1532 | return 0; |
1533 | } | |
1534 | } | |
1535 | ||
4f86d3a8 LB |
1536 | local_irq_disable(); |
1537 | current_thread_info()->status &= ~TS_POLLING; | |
1538 | /* | |
1539 | * TS_POLLING-cleared state must be visible before we test | |
1540 | * NEED_RESCHED: | |
1541 | */ | |
1542 | smp_mb(); | |
1543 | ||
1544 | if (unlikely(need_resched())) { | |
1545 | current_thread_info()->status |= TS_POLLING; | |
1546 | local_irq_enable(); | |
1547 | return 0; | |
1548 | } | |
1549 | ||
50629118 VP |
1550 | /* Tell the scheduler that we are going deep-idle: */ |
1551 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1552 | /* |
1553 | * Must be done before busmaster disable as we might need to | |
1554 | * access HPET ! | |
1555 | */ | |
1556 | acpi_state_timer_broadcast(pr, cx, 1); | |
1557 | ||
ddc081a1 | 1558 | acpi_idle_update_bm_rld(pr, cx); |
4f86d3a8 | 1559 | |
ddc081a1 VP |
1560 | /* |
1561 | * disable bus master | |
1562 | * bm_check implies we need ARB_DIS | |
1563 | * !bm_check implies we need cache flush | |
1564 | * bm_control implies whether we can do ARB_DIS | |
1565 | * | |
1566 | * That leaves a case where bm_check is set and bm_control is | |
1567 | * not set. In that case we cannot do much, we enter C3 | |
1568 | * without doing anything. | |
1569 | */ | |
1570 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1571 | spin_lock(&c3_lock); |
1572 | c3_cpu_count++; | |
1573 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1574 | if (c3_cpu_count == num_online_cpus()) | |
1575 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); | |
1576 | spin_unlock(&c3_lock); | |
ddc081a1 VP |
1577 | } else if (!pr->flags.bm_check) { |
1578 | ACPI_FLUSH_CPU_CACHE(); | |
1579 | } | |
4f86d3a8 | 1580 | |
ddc081a1 VP |
1581 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1582 | acpi_idle_do_entry(cx); | |
1583 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
4f86d3a8 | 1584 | |
ddc081a1 VP |
1585 | /* Re-enable bus master arbitration */ |
1586 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1587 | spin_lock(&c3_lock); |
ddc081a1 | 1588 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1589 | c3_cpu_count--; |
1590 | spin_unlock(&c3_lock); | |
1591 | } | |
1592 | ||
1593 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1594 | /* TSC could halt in idle, so notify users */ | |
ddb25f9a AK |
1595 | if (tsc_halts_in_c(ACPI_STATE_C3)) |
1596 | mark_tsc_unstable("TSC halts in idle"); | |
4f86d3a8 | 1597 | #endif |
50629118 VP |
1598 | sleep_ticks = ticks_elapsed(t1, t2); |
1599 | /* Tell the scheduler how much we idled: */ | |
1600 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1601 | |
1602 | local_irq_enable(); | |
1603 | current_thread_info()->status |= TS_POLLING; | |
1604 | ||
1605 | cx->usage++; | |
1606 | ||
1607 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1608 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1609 | return ticks_elapsed_in_us(t1, t2); |
1610 | } | |
1611 | ||
1612 | struct cpuidle_driver acpi_idle_driver = { | |
1613 | .name = "acpi_idle", | |
1614 | .owner = THIS_MODULE, | |
1615 | }; | |
1616 | ||
1617 | /** | |
1618 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1619 | * @pr: the ACPI processor | |
1620 | */ | |
1621 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1622 | { | |
1623 | int i, count = 0; | |
1624 | struct acpi_processor_cx *cx; | |
1625 | struct cpuidle_state *state; | |
1626 | struct cpuidle_device *dev = &pr->power.dev; | |
1627 | ||
1628 | if (!pr->flags.power_setup_done) | |
1629 | return -EINVAL; | |
1630 | ||
1631 | if (pr->flags.power == 0) { | |
1632 | return -EINVAL; | |
1633 | } | |
1634 | ||
1635 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { | |
1636 | cx = &pr->power.states[i]; | |
1637 | state = &dev->states[count]; | |
1638 | ||
1639 | if (!cx->valid) | |
1640 | continue; | |
1641 | ||
1642 | #ifdef CONFIG_HOTPLUG_CPU | |
1643 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1644 | !pr->flags.has_cst && | |
1645 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1646 | continue; | |
1fec74a9 | 1647 | #endif |
4f86d3a8 LB |
1648 | cpuidle_set_statedata(state, cx); |
1649 | ||
1650 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
1651 | state->exit_latency = cx->latency; | |
1652 | state->target_residency = cx->latency * 6; | |
1653 | state->power_usage = cx->power; | |
1654 | ||
1655 | state->flags = 0; | |
1656 | switch (cx->type) { | |
1657 | case ACPI_STATE_C1: | |
1658 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
1659 | state->enter = acpi_idle_enter_c1; | |
ddc081a1 | 1660 | dev->safe_state = state; |
4f86d3a8 LB |
1661 | break; |
1662 | ||
1663 | case ACPI_STATE_C2: | |
1664 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1665 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1666 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1667 | dev->safe_state = state; |
4f86d3a8 LB |
1668 | break; |
1669 | ||
1670 | case ACPI_STATE_C3: | |
1671 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1672 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1673 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1674 | state->enter = pr->flags.bm_check ? | |
1675 | acpi_idle_enter_bm : | |
1676 | acpi_idle_enter_simple; | |
1677 | break; | |
1678 | } | |
1679 | ||
1680 | count++; | |
1681 | } | |
1682 | ||
1683 | dev->state_count = count; | |
1684 | ||
1685 | if (!count) | |
1686 | return -EINVAL; | |
1687 | ||
4f86d3a8 LB |
1688 | return 0; |
1689 | } | |
1690 | ||
1691 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1692 | { | |
1693 | int ret; | |
1694 | ||
1695 | if (!pr) | |
1696 | return -EINVAL; | |
1697 | ||
1698 | if (nocst) { | |
1699 | return -ENODEV; | |
1700 | } | |
1701 | ||
1702 | if (!pr->flags.power_setup_done) | |
1703 | return -ENODEV; | |
1704 | ||
1705 | cpuidle_pause_and_lock(); | |
1706 | cpuidle_disable_device(&pr->power.dev); | |
1707 | acpi_processor_get_power_info(pr); | |
1708 | acpi_processor_setup_cpuidle(pr); | |
1709 | ret = cpuidle_enable_device(&pr->power.dev); | |
1710 | cpuidle_resume_and_unlock(); | |
1711 | ||
1712 | return ret; | |
1713 | } | |
1714 | ||
1715 | #endif /* CONFIG_CPU_IDLE */ | |
5c87579e | 1716 | |
7af8b660 | 1717 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1718 | struct acpi_device *device) |
1da177e4 | 1719 | { |
4be44fcd | 1720 | acpi_status status = 0; |
b6835052 | 1721 | static int first_run; |
4be44fcd | 1722 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1723 | unsigned int i; |
1724 | ||
1da177e4 LT |
1725 | |
1726 | if (!first_run) { | |
1727 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1728 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1729 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1730 | printk(KERN_NOTICE |
1731 | "ACPI: processor limited to max C-state %d\n", | |
1732 | max_cstate); | |
1da177e4 | 1733 | first_run++; |
f011e2e2 MG |
1734 | #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP) |
1735 | pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY, | |
1736 | &acpi_processor_latency_notifier); | |
1fec74a9 | 1737 | #endif |
1da177e4 LT |
1738 | } |
1739 | ||
02df8b93 | 1740 | if (!pr) |
d550d98d | 1741 | return -EINVAL; |
02df8b93 | 1742 | |
cee324b1 | 1743 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1744 | status = |
cee324b1 | 1745 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1746 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1747 | ACPI_EXCEPTION((AE_INFO, status, |
1748 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1749 | } |
1750 | } | |
1751 | ||
1752 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1753 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1754 | |
1755 | /* | |
1756 | * Install the idle handler if processor power management is supported. | |
1757 | * Note that we use previously set idle handler will be used on | |
1758 | * platforms that only support C1. | |
1759 | */ | |
1760 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
4f86d3a8 LB |
1761 | #ifdef CONFIG_CPU_IDLE |
1762 | acpi_processor_setup_cpuidle(pr); | |
1763 | pr->power.dev.cpu = pr->id; | |
1764 | if (cpuidle_register_device(&pr->power.dev)) | |
1765 | return -EIO; | |
1766 | #endif | |
1767 | ||
1da177e4 LT |
1768 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1769 | for (i = 1; i <= pr->power.count; i++) | |
1770 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1771 | printk(" C%d[C%d]", i, |
1772 | pr->power.states[i].type); | |
1da177e4 LT |
1773 | printk(")\n"); |
1774 | ||
4f86d3a8 | 1775 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1776 | if (pr->id == 0) { |
1777 | pm_idle_save = pm_idle; | |
1778 | pm_idle = acpi_processor_idle; | |
1779 | } | |
4f86d3a8 | 1780 | #endif |
1da177e4 LT |
1781 | } |
1782 | ||
1783 | /* 'power' [R] */ | |
1784 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1785 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1786 | if (!entry) |
a6fc6720 | 1787 | return -EIO; |
1da177e4 LT |
1788 | else { |
1789 | entry->proc_fops = &acpi_processor_power_fops; | |
1790 | entry->data = acpi_driver_data(device); | |
1791 | entry->owner = THIS_MODULE; | |
1792 | } | |
1793 | ||
d550d98d | 1794 | return 0; |
1da177e4 LT |
1795 | } |
1796 | ||
4be44fcd LB |
1797 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1798 | struct acpi_device *device) | |
1da177e4 | 1799 | { |
4f86d3a8 LB |
1800 | #ifdef CONFIG_CPU_IDLE |
1801 | if ((pr->flags.power) && (!boot_option_idle_override)) | |
1802 | cpuidle_unregister_device(&pr->power.dev); | |
1803 | #endif | |
1da177e4 LT |
1804 | pr->flags.power_setup_done = 0; |
1805 | ||
1806 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1807 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1808 | acpi_device_dir(device)); | |
1da177e4 | 1809 | |
4f86d3a8 LB |
1810 | #ifndef CONFIG_CPU_IDLE |
1811 | ||
1da177e4 LT |
1812 | /* Unregister the idle handler when processor #0 is removed. */ |
1813 | if (pr->id == 0) { | |
1814 | pm_idle = pm_idle_save; | |
1815 | ||
1816 | /* | |
1817 | * We are about to unload the current idle thread pm callback | |
1818 | * (pm_idle), Wait for all processors to update cached/local | |
1819 | * copies of pm_idle before proceeding. | |
1820 | */ | |
1821 | cpu_idle_wait(); | |
1fec74a9 | 1822 | #ifdef CONFIG_SMP |
f011e2e2 MG |
1823 | pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY, |
1824 | &acpi_processor_latency_notifier); | |
1fec74a9 | 1825 | #endif |
1da177e4 | 1826 | } |
4f86d3a8 | 1827 | #endif |
1da177e4 | 1828 | |
d550d98d | 1829 | return 0; |
1da177e4 | 1830 | } |