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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
1da177e4 LT |
36 | #include <linux/acpi.h> |
37 | #include <linux/dmi.h> | |
38 | #include <linux/moduleparam.h> | |
4e57b681 | 39 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 40 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 41 | #include <linux/clockchips.h> |
4f86d3a8 | 42 | #include <linux/cpuidle.h> |
ba84be23 | 43 | #include <linux/irqflags.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
c1e3b377 | 60 | #include <asm/processor.h> |
1da177e4 | 61 | |
a192a958 LB |
62 | #define PREFIX "ACPI: " |
63 | ||
1da177e4 | 64 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 65 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 66 | ACPI_MODULE_NAME("processor_idle"); |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
68 | #define C2_OVERHEAD 1 /* 1us */ |
69 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 70 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 71 | |
4f86d3a8 LB |
72 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
73 | module_param(max_cstate, uint, 0000); | |
b6835052 | 74 | static unsigned int nocst __read_mostly; |
1da177e4 | 75 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
76 | static int bm_check_disable __read_mostly; |
77 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 78 | |
25de5718 | 79 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 80 | module_param(latency_factor, uint, 0644); |
1da177e4 | 81 | |
d1896049 TR |
82 | static int disabled_by_idle_boot_param(void) |
83 | { | |
84 | return boot_option_idle_override == IDLE_POLL || | |
85 | boot_option_idle_override == IDLE_FORCE_MWAIT || | |
86 | boot_option_idle_override == IDLE_HALT; | |
87 | } | |
88 | ||
1da177e4 LT |
89 | /* |
90 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
91 | * For now disable this. Probably a bug somewhere else. | |
92 | * | |
93 | * To skip this limit, boot/load with a large max_cstate limit. | |
94 | */ | |
1855256c | 95 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
96 | { |
97 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
98 | return 0; | |
99 | ||
3d35600a | 100 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
101 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
102 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 103 | |
3d35600a | 104 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
105 | |
106 | return 0; | |
107 | } | |
108 | ||
7ded5689 AR |
109 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
110 | callers to only run once -AK */ | |
111 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
112 | { set_max_cstate, "Clevo 5600D", { |
113 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
114 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 115 | (void *)2}, |
370d5cd8 AV |
116 | { set_max_cstate, "Pavilion zv5000", { |
117 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
118 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
119 | (void *)1}, | |
120 | { set_max_cstate, "Asus L8400B", { | |
121 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
122 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
123 | (void *)1}, | |
1da177e4 LT |
124 | {}, |
125 | }; | |
126 | ||
4f86d3a8 | 127 | |
2e906655 | 128 | /* |
129 | * Callers should disable interrupts before the call and enable | |
130 | * interrupts after return. | |
131 | */ | |
ddc081a1 VP |
132 | static void acpi_safe_halt(void) |
133 | { | |
134 | current_thread_info()->status &= ~TS_POLLING; | |
135 | /* | |
136 | * TS_POLLING-cleared state must be visible before we | |
137 | * test NEED_RESCHED: | |
138 | */ | |
139 | smp_mb(); | |
71e93d15 | 140 | if (!need_resched()) { |
ddc081a1 | 141 | safe_halt(); |
71e93d15 VP |
142 | local_irq_disable(); |
143 | } | |
ddc081a1 VP |
144 | current_thread_info()->status |= TS_POLLING; |
145 | } | |
146 | ||
169a0abb TG |
147 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
148 | ||
149 | /* | |
150 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
151 | * This seems to be a common problem on AMD boxen, but other vendors |
152 | * are affected too. We pick the most conservative approach: we assume | |
153 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 154 | */ |
7e275cc4 | 155 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
156 | struct acpi_processor_cx *cx) |
157 | { | |
158 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 159 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 160 | |
db954b58 VP |
161 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
162 | return; | |
163 | ||
02c68a02 | 164 | if (amd_e400_c1e_detected) |
87ad57ba SL |
165 | type = ACPI_STATE_C1; |
166 | ||
169a0abb TG |
167 | /* |
168 | * Check, if one of the previous states already marked the lapic | |
169 | * unstable | |
170 | */ | |
171 | if (pwr->timer_broadcast_on_state < state) | |
172 | return; | |
173 | ||
e585bef8 | 174 | if (cx->type >= type) |
296d93cd | 175 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
176 | } |
177 | ||
918aae42 | 178 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 179 | { |
f833bab8 | 180 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
181 | unsigned long reason; |
182 | ||
183 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
184 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
185 | ||
186 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
187 | } |
188 | ||
918aae42 HS |
189 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
190 | { | |
191 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
192 | (void *)pr, 1); | |
193 | } | |
194 | ||
e9e2cdb4 | 195 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 196 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
197 | struct acpi_processor_cx *cx, |
198 | int broadcast) | |
199 | { | |
e9e2cdb4 TG |
200 | int state = cx - pr->power.states; |
201 | ||
202 | if (state >= pr->power.timer_broadcast_on_state) { | |
203 | unsigned long reason; | |
204 | ||
205 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
206 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
207 | clockevents_notify(reason, &pr->id); | |
208 | } | |
169a0abb TG |
209 | } |
210 | ||
211 | #else | |
212 | ||
7e275cc4 | 213 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 214 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
215 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
216 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
217 | struct acpi_processor_cx *cx, |
218 | int broadcast) | |
219 | { | |
220 | } | |
169a0abb TG |
221 | |
222 | #endif | |
223 | ||
b04e7bdb TG |
224 | /* |
225 | * Suspend / resume control | |
226 | */ | |
227 | static int acpi_idle_suspend; | |
815ab0fd LB |
228 | static u32 saved_bm_rld; |
229 | ||
230 | static void acpi_idle_bm_rld_save(void) | |
231 | { | |
232 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
233 | } | |
234 | static void acpi_idle_bm_rld_restore(void) | |
235 | { | |
236 | u32 resumed_bm_rld; | |
237 | ||
238 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
239 | ||
240 | if (resumed_bm_rld != saved_bm_rld) | |
241 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
242 | } | |
b04e7bdb TG |
243 | |
244 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
245 | { | |
815ab0fd LB |
246 | if (acpi_idle_suspend == 1) |
247 | return 0; | |
248 | ||
249 | acpi_idle_bm_rld_save(); | |
b04e7bdb TG |
250 | acpi_idle_suspend = 1; |
251 | return 0; | |
252 | } | |
253 | ||
254 | int acpi_processor_resume(struct acpi_device * device) | |
255 | { | |
815ab0fd LB |
256 | if (acpi_idle_suspend == 0) |
257 | return 0; | |
258 | ||
259 | acpi_idle_bm_rld_restore(); | |
b04e7bdb TG |
260 | acpi_idle_suspend = 0; |
261 | return 0; | |
262 | } | |
263 | ||
592913ec | 264 | #if defined(CONFIG_X86) |
520daf72 | 265 | static void tsc_check_state(int state) |
ddb25f9a AK |
266 | { |
267 | switch (boot_cpu_data.x86_vendor) { | |
268 | case X86_VENDOR_AMD: | |
40fb1715 | 269 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
270 | /* |
271 | * AMD Fam10h TSC will tick in all | |
272 | * C/P/S0/S1 states when this bit is set. | |
273 | */ | |
40fb1715 | 274 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 275 | return; |
40fb1715 | 276 | |
ddb25f9a | 277 | /*FALL THROUGH*/ |
ddb25f9a | 278 | default: |
520daf72 LB |
279 | /* TSC could halt in idle, so notify users */ |
280 | if (state > ACPI_STATE_C1) | |
281 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
282 | } |
283 | } | |
520daf72 LB |
284 | #else |
285 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
286 | #endif |
287 | ||
4be44fcd | 288 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 289 | { |
1da177e4 LT |
290 | |
291 | if (!pr) | |
d550d98d | 292 | return -EINVAL; |
1da177e4 LT |
293 | |
294 | if (!pr->pblk) | |
d550d98d | 295 | return -ENODEV; |
1da177e4 | 296 | |
1da177e4 | 297 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
298 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
299 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
300 | ||
4c033552 VP |
301 | #ifndef CONFIG_HOTPLUG_CPU |
302 | /* | |
303 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 304 | * an SMP system. |
4c033552 | 305 | */ |
ad71860a | 306 | if ((num_online_cpus() > 1) && |
cee324b1 | 307 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 308 | return -ENODEV; |
4c033552 VP |
309 | #endif |
310 | ||
1da177e4 LT |
311 | /* determine C2 and C3 address from pblk */ |
312 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
313 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
314 | ||
315 | /* determine latencies from FADT */ | |
cee324b1 AS |
316 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
317 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 | 318 | |
5d76b6f6 LB |
319 | /* |
320 | * FADT specified C2 latency must be less than or equal to | |
321 | * 100 microseconds. | |
322 | */ | |
323 | if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
324 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
325 | "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); | |
326 | /* invalidate C2 */ | |
327 | pr->power.states[ACPI_STATE_C2].address = 0; | |
328 | } | |
329 | ||
a6d72c18 LB |
330 | /* |
331 | * FADT supplied C3 latency must be less than or equal to | |
332 | * 1000 microseconds. | |
333 | */ | |
334 | if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
335 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
336 | "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); | |
337 | /* invalidate C3 */ | |
338 | pr->power.states[ACPI_STATE_C3].address = 0; | |
339 | } | |
340 | ||
1da177e4 LT |
341 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
342 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
343 | pr->power.states[ACPI_STATE_C2].address, | |
344 | pr->power.states[ACPI_STATE_C3].address)); | |
345 | ||
d550d98d | 346 | return 0; |
1da177e4 LT |
347 | } |
348 | ||
991528d7 | 349 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 350 | { |
991528d7 VP |
351 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
352 | /* set the first C-State to C1 */ | |
353 | /* all processors need to support C1 */ | |
354 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
355 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 356 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
357 | } |
358 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 359 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 360 | return 0; |
acf05f4b VP |
361 | } |
362 | ||
4be44fcd | 363 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 364 | { |
4be44fcd | 365 | acpi_status status = 0; |
439913ff | 366 | u64 count; |
cf824788 | 367 | int current_count; |
4be44fcd LB |
368 | int i; |
369 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
370 | union acpi_object *cst; | |
1da177e4 | 371 | |
1da177e4 | 372 | |
1da177e4 | 373 | if (nocst) |
d550d98d | 374 | return -ENODEV; |
1da177e4 | 375 | |
991528d7 | 376 | current_count = 0; |
1da177e4 LT |
377 | |
378 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
379 | if (ACPI_FAILURE(status)) { | |
380 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 381 | return -ENODEV; |
4be44fcd | 382 | } |
1da177e4 | 383 | |
50dd0969 | 384 | cst = buffer.pointer; |
1da177e4 LT |
385 | |
386 | /* There must be at least 2 elements */ | |
387 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 388 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
389 | status = -EFAULT; |
390 | goto end; | |
391 | } | |
392 | ||
393 | count = cst->package.elements[0].integer.value; | |
394 | ||
395 | /* Validate number of power states. */ | |
396 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 397 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
398 | status = -EFAULT; |
399 | goto end; | |
400 | } | |
401 | ||
1da177e4 LT |
402 | /* Tell driver that at least _CST is supported. */ |
403 | pr->flags.has_cst = 1; | |
404 | ||
405 | for (i = 1; i <= count; i++) { | |
406 | union acpi_object *element; | |
407 | union acpi_object *obj; | |
408 | struct acpi_power_register *reg; | |
409 | struct acpi_processor_cx cx; | |
410 | ||
411 | memset(&cx, 0, sizeof(cx)); | |
412 | ||
50dd0969 | 413 | element = &(cst->package.elements[i]); |
1da177e4 LT |
414 | if (element->type != ACPI_TYPE_PACKAGE) |
415 | continue; | |
416 | ||
417 | if (element->package.count != 4) | |
418 | continue; | |
419 | ||
50dd0969 | 420 | obj = &(element->package.elements[0]); |
1da177e4 LT |
421 | |
422 | if (obj->type != ACPI_TYPE_BUFFER) | |
423 | continue; | |
424 | ||
4be44fcd | 425 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
426 | |
427 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 428 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
429 | continue; |
430 | ||
1da177e4 | 431 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 432 | obj = &(element->package.elements[1]); |
1da177e4 LT |
433 | if (obj->type != ACPI_TYPE_INTEGER) |
434 | continue; | |
435 | ||
436 | cx.type = obj->integer.value; | |
991528d7 VP |
437 | /* |
438 | * Some buggy BIOSes won't list C1 in _CST - | |
439 | * Let acpi_processor_get_power_info_default() handle them later | |
440 | */ | |
441 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
442 | current_count++; | |
443 | ||
444 | cx.address = reg->address; | |
445 | cx.index = current_count + 1; | |
446 | ||
bc71bec9 | 447 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
448 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
449 | if (acpi_processor_ffh_cstate_probe | |
450 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 451 | cx.entry_method = ACPI_CSTATE_FFH; |
452 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
453 | /* |
454 | * C1 is a special case where FIXED_HARDWARE | |
455 | * can be handled in non-MWAIT way as well. | |
456 | * In that case, save this _CST entry info. | |
991528d7 VP |
457 | * Otherwise, ignore this info and continue. |
458 | */ | |
bc71bec9 | 459 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 460 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 461 | } else { |
991528d7 VP |
462 | continue; |
463 | } | |
da5e09a1 | 464 | if (cx.type == ACPI_STATE_C1 && |
d1896049 | 465 | (boot_option_idle_override == IDLE_NOMWAIT)) { |
c1e3b377 ZY |
466 | /* |
467 | * In most cases the C1 space_id obtained from | |
468 | * _CST object is FIXED_HARDWARE access mode. | |
469 | * But when the option of idle=halt is added, | |
470 | * the entry_method type should be changed from | |
471 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
472 | * When the option of idle=nomwait is added, |
473 | * the C1 entry_method type should be | |
474 | * CSTATE_HALT. | |
c1e3b377 ZY |
475 | */ |
476 | cx.entry_method = ACPI_CSTATE_HALT; | |
477 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
478 | } | |
4fcb2fcd VP |
479 | } else { |
480 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
481 | cx.address); | |
991528d7 | 482 | } |
1da177e4 | 483 | |
0fda6b40 VP |
484 | if (cx.type == ACPI_STATE_C1) { |
485 | cx.valid = 1; | |
486 | } | |
4fcb2fcd | 487 | |
50dd0969 | 488 | obj = &(element->package.elements[2]); |
1da177e4 LT |
489 | if (obj->type != ACPI_TYPE_INTEGER) |
490 | continue; | |
491 | ||
492 | cx.latency = obj->integer.value; | |
493 | ||
50dd0969 | 494 | obj = &(element->package.elements[3]); |
1da177e4 LT |
495 | if (obj->type != ACPI_TYPE_INTEGER) |
496 | continue; | |
497 | ||
498 | cx.power = obj->integer.value; | |
499 | ||
cf824788 JM |
500 | current_count++; |
501 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
502 | ||
503 | /* | |
504 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
505 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
506 | */ | |
507 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
508 | printk(KERN_WARNING | |
509 | "Limiting number of power states to max (%d)\n", | |
510 | ACPI_PROCESSOR_MAX_POWER); | |
511 | printk(KERN_WARNING | |
512 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
513 | break; | |
514 | } | |
1da177e4 LT |
515 | } |
516 | ||
4be44fcd | 517 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 518 | current_count)); |
1da177e4 LT |
519 | |
520 | /* Validate number of power states discovered */ | |
cf824788 | 521 | if (current_count < 2) |
6d93c648 | 522 | status = -EFAULT; |
1da177e4 | 523 | |
4be44fcd | 524 | end: |
02438d87 | 525 | kfree(buffer.pointer); |
1da177e4 | 526 | |
d550d98d | 527 | return status; |
1da177e4 LT |
528 | } |
529 | ||
4be44fcd LB |
530 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
531 | struct acpi_processor_cx *cx) | |
1da177e4 | 532 | { |
ee1ca48f PV |
533 | static int bm_check_flag = -1; |
534 | static int bm_control_flag = -1; | |
02df8b93 | 535 | |
1da177e4 LT |
536 | |
537 | if (!cx->address) | |
d550d98d | 538 | return; |
1da177e4 | 539 | |
1da177e4 LT |
540 | /* |
541 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
542 | * DMA transfers are used by any ISA device to avoid livelock. | |
543 | * Note that we could disable Type-F DMA (as recommended by | |
544 | * the erratum), but this is known to disrupt certain ISA | |
545 | * devices thus we take the conservative approach. | |
546 | */ | |
547 | else if (errata.piix4.fdma) { | |
548 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 549 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 550 | return; |
1da177e4 LT |
551 | } |
552 | ||
02df8b93 | 553 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 554 | if (bm_check_flag == -1) { |
02df8b93 VP |
555 | /* Determine whether bm_check is needed based on CPU */ |
556 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
557 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 558 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
559 | } else { |
560 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 561 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
562 | } |
563 | ||
564 | if (pr->flags.bm_check) { | |
02df8b93 | 565 | if (!pr->flags.bm_control) { |
ed3110ef VP |
566 | if (pr->flags.has_cst != 1) { |
567 | /* bus mastering control is necessary */ | |
568 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
569 | "C3 support requires BM control\n")); | |
570 | return; | |
571 | } else { | |
572 | /* Here we enter C3 without bus mastering */ | |
573 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
574 | "C3 support without BM control\n")); | |
575 | } | |
02df8b93 VP |
576 | } |
577 | } else { | |
02df8b93 VP |
578 | /* |
579 | * WBINVD should be set in fadt, for C3 state to be | |
580 | * supported on when bm_check is not required. | |
581 | */ | |
cee324b1 | 582 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 583 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
584 | "Cache invalidation should work properly" |
585 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 586 | return; |
02df8b93 | 587 | } |
02df8b93 VP |
588 | } |
589 | ||
1da177e4 LT |
590 | /* |
591 | * Otherwise we've met all of our C3 requirements. | |
592 | * Normalize the C3 latency to expidite policy. Enable | |
593 | * checking of bus mastering status (bm_check) so we can | |
594 | * use this in our C3 policy | |
595 | */ | |
596 | cx->valid = 1; | |
4f86d3a8 | 597 | |
4f86d3a8 | 598 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
599 | /* |
600 | * On older chipsets, BM_RLD needs to be set | |
601 | * in order for Bus Master activity to wake the | |
602 | * system from C3. Newer chipsets handle DMA | |
603 | * during C3 automatically and BM_RLD is a NOP. | |
604 | * In either case, the proper way to | |
605 | * handle BM_RLD is to set it and leave it set. | |
606 | */ | |
50ffba1b | 607 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 608 | |
d550d98d | 609 | return; |
1da177e4 LT |
610 | } |
611 | ||
1da177e4 LT |
612 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
613 | { | |
614 | unsigned int i; | |
615 | unsigned int working = 0; | |
6eb0a0fd | 616 | |
169a0abb | 617 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 618 | |
a0bf284b | 619 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
620 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
621 | ||
622 | switch (cx->type) { | |
623 | case ACPI_STATE_C1: | |
624 | cx->valid = 1; | |
625 | break; | |
626 | ||
627 | case ACPI_STATE_C2: | |
d22edd29 LB |
628 | if (!cx->address) |
629 | break; | |
630 | cx->valid = 1; | |
631 | cx->latency_ticks = cx->latency; /* Normalize latency */ | |
1da177e4 LT |
632 | break; |
633 | ||
634 | case ACPI_STATE_C3: | |
635 | acpi_processor_power_verify_c3(pr, cx); | |
636 | break; | |
637 | } | |
7e275cc4 LB |
638 | if (!cx->valid) |
639 | continue; | |
1da177e4 | 640 | |
7e275cc4 LB |
641 | lapic_timer_check_state(i, pr, cx); |
642 | tsc_check_state(cx->type); | |
643 | working++; | |
1da177e4 | 644 | } |
bd663347 | 645 | |
918aae42 | 646 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
647 | |
648 | return (working); | |
649 | } | |
650 | ||
4be44fcd | 651 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
652 | { |
653 | unsigned int i; | |
654 | int result; | |
655 | ||
1da177e4 LT |
656 | |
657 | /* NOTE: the idle thread may not be running while calling | |
658 | * this function */ | |
659 | ||
991528d7 VP |
660 | /* Zero initialize all the C-states info. */ |
661 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
662 | ||
1da177e4 | 663 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 664 | if (result == -ENODEV) |
c5a114f1 | 665 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 666 | |
991528d7 VP |
667 | if (result) |
668 | return result; | |
669 | ||
670 | acpi_processor_get_power_info_default(pr); | |
671 | ||
cf824788 | 672 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 673 | |
1da177e4 LT |
674 | /* |
675 | * if one state of type C2 or C3 is available, mark this | |
676 | * CPU as being "idle manageable" | |
677 | */ | |
678 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 679 | if (pr->power.states[i].valid) { |
1da177e4 | 680 | pr->power.count = i; |
2203d6ed LT |
681 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
682 | pr->flags.power = 1; | |
acf05f4b | 683 | } |
1da177e4 LT |
684 | } |
685 | ||
d550d98d | 686 | return 0; |
1da177e4 LT |
687 | } |
688 | ||
4f86d3a8 LB |
689 | /** |
690 | * acpi_idle_bm_check - checks if bus master activity was detected | |
691 | */ | |
692 | static int acpi_idle_bm_check(void) | |
693 | { | |
694 | u32 bm_status = 0; | |
695 | ||
d3e7e99f LB |
696 | if (bm_check_disable) |
697 | return 0; | |
698 | ||
50ffba1b | 699 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 700 | if (bm_status) |
50ffba1b | 701 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
702 | /* |
703 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
704 | * the true state of bus mastering activity; forcing us to | |
705 | * manually check the BMIDEA bit of each IDE channel. | |
706 | */ | |
707 | else if (errata.piix4.bmisx) { | |
708 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
709 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
710 | bm_status = 1; | |
711 | } | |
712 | return bm_status; | |
713 | } | |
714 | ||
4f86d3a8 LB |
715 | /** |
716 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
717 | * @cx: cstate data | |
bc71bec9 | 718 | * |
719 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
720 | */ |
721 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
722 | { | |
dcf30997 SR |
723 | /* Don't trace irqs off for idle */ |
724 | stop_critical_timings(); | |
bc71bec9 | 725 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
726 | /* Call into architectural FFH based C-state */ |
727 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 728 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
729 | acpi_safe_halt(); | |
4f86d3a8 | 730 | } else { |
4f86d3a8 LB |
731 | /* IO port based C-state */ |
732 | inb(cx->address); | |
733 | /* Dummy wait op - must do something useless after P_LVL2 read | |
734 | because chipsets cannot guarantee that STPCLK# signal | |
735 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 736 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 737 | } |
dcf30997 | 738 | start_critical_timings(); |
4f86d3a8 LB |
739 | } |
740 | ||
741 | /** | |
742 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
743 | * @dev: the target CPU | |
e978aa7d | 744 | * @index: index of target state |
4f86d3a8 LB |
745 | * |
746 | * This is equivalent to the HALT instruction. | |
747 | */ | |
4202735e | 748 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, int index) |
4f86d3a8 | 749 | { |
ff69f2bb AS |
750 | ktime_t kt1, kt2; |
751 | s64 idle_time; | |
4f86d3a8 | 752 | struct acpi_processor *pr; |
4202735e DD |
753 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
754 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
9b12e18c | 755 | |
4a6f4fe8 | 756 | pr = __this_cpu_read(processors); |
e978aa7d | 757 | dev->last_residency = 0; |
4f86d3a8 LB |
758 | |
759 | if (unlikely(!pr)) | |
e978aa7d | 760 | return -EINVAL; |
4f86d3a8 | 761 | |
2e906655 | 762 | local_irq_disable(); |
b077fbad VP |
763 | |
764 | /* Do not access any ACPI IO ports in suspend path */ | |
765 | if (acpi_idle_suspend) { | |
b077fbad | 766 | local_irq_enable(); |
7d60e8ab | 767 | cpu_relax(); |
e978aa7d | 768 | return -EINVAL; |
b077fbad VP |
769 | } |
770 | ||
7e275cc4 | 771 | lapic_timer_state_broadcast(pr, cx, 1); |
ff69f2bb | 772 | kt1 = ktime_get_real(); |
bc71bec9 | 773 | acpi_idle_do_entry(cx); |
ff69f2bb AS |
774 | kt2 = ktime_get_real(); |
775 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 776 | |
e978aa7d DD |
777 | /* Update device last_residency*/ |
778 | dev->last_residency = (int)idle_time; | |
779 | ||
2e906655 | 780 | local_irq_enable(); |
4f86d3a8 | 781 | cx->usage++; |
7e275cc4 | 782 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 783 | |
e978aa7d | 784 | return index; |
4f86d3a8 LB |
785 | } |
786 | ||
787 | /** | |
788 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
789 | * @dev: the target CPU | |
e978aa7d | 790 | * @index: the index of suggested state |
4f86d3a8 | 791 | */ |
4202735e | 792 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, int index) |
4f86d3a8 LB |
793 | { |
794 | struct acpi_processor *pr; | |
4202735e DD |
795 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
796 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
ff69f2bb | 797 | ktime_t kt1, kt2; |
2da513f5 | 798 | s64 idle_time_ns; |
ff69f2bb | 799 | s64 idle_time; |
50629118 | 800 | |
4a6f4fe8 | 801 | pr = __this_cpu_read(processors); |
e978aa7d | 802 | dev->last_residency = 0; |
4f86d3a8 LB |
803 | |
804 | if (unlikely(!pr)) | |
e978aa7d | 805 | return -EINVAL; |
e196441b | 806 | |
4f86d3a8 | 807 | local_irq_disable(); |
02cf4f98 | 808 | |
e978aa7d DD |
809 | if (acpi_idle_suspend) { |
810 | local_irq_enable(); | |
811 | cpu_relax(); | |
812 | return -EINVAL; | |
813 | } | |
814 | ||
815 | ||
d306ebc2 PV |
816 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
817 | current_thread_info()->status &= ~TS_POLLING; | |
818 | /* | |
819 | * TS_POLLING-cleared state must be visible before we test | |
820 | * NEED_RESCHED: | |
821 | */ | |
822 | smp_mb(); | |
4f86d3a8 | 823 | |
02cf4f98 LB |
824 | if (unlikely(need_resched())) { |
825 | current_thread_info()->status |= TS_POLLING; | |
826 | local_irq_enable(); | |
e978aa7d | 827 | return -EINVAL; |
02cf4f98 | 828 | } |
4f86d3a8 LB |
829 | } |
830 | ||
e17bcb43 TG |
831 | /* |
832 | * Must be done before busmaster disable as we might need to | |
833 | * access HPET ! | |
834 | */ | |
7e275cc4 | 835 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 836 | |
4f86d3a8 LB |
837 | if (cx->type == ACPI_STATE_C3) |
838 | ACPI_FLUSH_CPU_CACHE(); | |
839 | ||
ff69f2bb | 840 | kt1 = ktime_get_real(); |
50629118 VP |
841 | /* Tell the scheduler that we are going deep-idle: */ |
842 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 843 | acpi_idle_do_entry(cx); |
ff69f2bb | 844 | kt2 = ktime_get_real(); |
2da513f5 VP |
845 | idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1)); |
846 | idle_time = idle_time_ns; | |
847 | do_div(idle_time, NSEC_PER_USEC); | |
4f86d3a8 | 848 | |
e978aa7d DD |
849 | /* Update device last_residency*/ |
850 | dev->last_residency = (int)idle_time; | |
851 | ||
50629118 | 852 | /* Tell the scheduler how much we idled: */ |
2da513f5 | 853 | sched_clock_idle_wakeup_event(idle_time_ns); |
4f86d3a8 LB |
854 | |
855 | local_irq_enable(); | |
02cf4f98 LB |
856 | if (cx->entry_method != ACPI_CSTATE_FFH) |
857 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 LB |
858 | |
859 | cx->usage++; | |
860 | ||
7e275cc4 | 861 | lapic_timer_state_broadcast(pr, cx, 0); |
bceefad5 | 862 | cx->time += idle_time; |
e978aa7d | 863 | return index; |
4f86d3a8 LB |
864 | } |
865 | ||
866 | static int c3_cpu_count; | |
867 | static DEFINE_SPINLOCK(c3_lock); | |
868 | ||
869 | /** | |
870 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
871 | * @dev: the target CPU | |
e978aa7d | 872 | * @index: the index of suggested state |
4f86d3a8 LB |
873 | * |
874 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
875 | */ | |
4202735e | 876 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, int index) |
4f86d3a8 LB |
877 | { |
878 | struct acpi_processor *pr; | |
4202735e DD |
879 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; |
880 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage); | |
ff69f2bb | 881 | ktime_t kt1, kt2; |
2da513f5 | 882 | s64 idle_time_ns; |
ff69f2bb | 883 | s64 idle_time; |
ff69f2bb | 884 | |
50629118 | 885 | |
4a6f4fe8 | 886 | pr = __this_cpu_read(processors); |
e978aa7d | 887 | dev->last_residency = 0; |
4f86d3a8 LB |
888 | |
889 | if (unlikely(!pr)) | |
e978aa7d | 890 | return -EINVAL; |
4f86d3a8 | 891 | |
e978aa7d DD |
892 | |
893 | if (acpi_idle_suspend) { | |
894 | cpu_relax(); | |
895 | return -EINVAL; | |
896 | } | |
e196441b | 897 | |
718be4aa | 898 | if (!cx->bm_sts_skip && acpi_idle_bm_check()) { |
e978aa7d DD |
899 | if (dev->safe_state_index >= 0) { |
900 | return dev->states[dev->safe_state_index].enter(dev, | |
901 | dev->safe_state_index); | |
ddc081a1 | 902 | } else { |
2e906655 | 903 | local_irq_disable(); |
ddc081a1 | 904 | acpi_safe_halt(); |
2e906655 | 905 | local_irq_enable(); |
e978aa7d | 906 | return -EINVAL; |
ddc081a1 VP |
907 | } |
908 | } | |
909 | ||
4f86d3a8 | 910 | local_irq_disable(); |
02cf4f98 | 911 | |
d306ebc2 PV |
912 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
913 | current_thread_info()->status &= ~TS_POLLING; | |
914 | /* | |
915 | * TS_POLLING-cleared state must be visible before we test | |
916 | * NEED_RESCHED: | |
917 | */ | |
918 | smp_mb(); | |
4f86d3a8 | 919 | |
02cf4f98 LB |
920 | if (unlikely(need_resched())) { |
921 | current_thread_info()->status |= TS_POLLING; | |
922 | local_irq_enable(); | |
e978aa7d | 923 | return -EINVAL; |
02cf4f98 | 924 | } |
4f86d3a8 LB |
925 | } |
926 | ||
996520c1 VP |
927 | acpi_unlazy_tlb(smp_processor_id()); |
928 | ||
50629118 VP |
929 | /* Tell the scheduler that we are going deep-idle: */ |
930 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
931 | /* |
932 | * Must be done before busmaster disable as we might need to | |
933 | * access HPET ! | |
934 | */ | |
7e275cc4 | 935 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 936 | |
f461ddea | 937 | kt1 = ktime_get_real(); |
ddc081a1 VP |
938 | /* |
939 | * disable bus master | |
940 | * bm_check implies we need ARB_DIS | |
941 | * !bm_check implies we need cache flush | |
942 | * bm_control implies whether we can do ARB_DIS | |
943 | * | |
944 | * That leaves a case where bm_check is set and bm_control is | |
945 | * not set. In that case we cannot do much, we enter C3 | |
946 | * without doing anything. | |
947 | */ | |
948 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
949 | spin_lock(&c3_lock); |
950 | c3_cpu_count++; | |
951 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
952 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 953 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 954 | spin_unlock(&c3_lock); |
ddc081a1 VP |
955 | } else if (!pr->flags.bm_check) { |
956 | ACPI_FLUSH_CPU_CACHE(); | |
957 | } | |
4f86d3a8 | 958 | |
ddc081a1 | 959 | acpi_idle_do_entry(cx); |
4f86d3a8 | 960 | |
ddc081a1 VP |
961 | /* Re-enable bus master arbitration */ |
962 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 963 | spin_lock(&c3_lock); |
50ffba1b | 964 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
965 | c3_cpu_count--; |
966 | spin_unlock(&c3_lock); | |
967 | } | |
f461ddea | 968 | kt2 = ktime_get_real(); |
157317ba | 969 | idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1)); |
2da513f5 VP |
970 | idle_time = idle_time_ns; |
971 | do_div(idle_time, NSEC_PER_USEC); | |
4f86d3a8 | 972 | |
e978aa7d DD |
973 | /* Update device last_residency*/ |
974 | dev->last_residency = (int)idle_time; | |
975 | ||
50629118 | 976 | /* Tell the scheduler how much we idled: */ |
2da513f5 | 977 | sched_clock_idle_wakeup_event(idle_time_ns); |
4f86d3a8 LB |
978 | |
979 | local_irq_enable(); | |
02cf4f98 LB |
980 | if (cx->entry_method != ACPI_CSTATE_FFH) |
981 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 LB |
982 | |
983 | cx->usage++; | |
984 | ||
7e275cc4 | 985 | lapic_timer_state_broadcast(pr, cx, 0); |
bceefad5 | 986 | cx->time += idle_time; |
e978aa7d | 987 | return index; |
4f86d3a8 LB |
988 | } |
989 | ||
990 | struct cpuidle_driver acpi_idle_driver = { | |
991 | .name = "acpi_idle", | |
992 | .owner = THIS_MODULE, | |
993 | }; | |
994 | ||
995 | /** | |
996 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
997 | * @pr: the ACPI processor | |
998 | */ | |
999 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1000 | { | |
9a0b8415 | 1001 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1002 | struct acpi_processor_cx *cx; |
1003 | struct cpuidle_state *state; | |
4202735e | 1004 | struct cpuidle_state_usage *state_usage; |
4f86d3a8 LB |
1005 | struct cpuidle_device *dev = &pr->power.dev; |
1006 | ||
1007 | if (!pr->flags.power_setup_done) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | if (pr->flags.power == 0) { | |
1011 | return -EINVAL; | |
1012 | } | |
1013 | ||
dcb84f33 | 1014 | dev->cpu = pr->id; |
e978aa7d | 1015 | dev->safe_state_index = -1; |
4fcb2fcd VP |
1016 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1017 | dev->states[i].name[0] = '\0'; | |
1018 | dev->states[i].desc[0] = '\0'; | |
1019 | } | |
1020 | ||
615dfd93 LB |
1021 | if (max_cstate == 0) |
1022 | max_cstate = 1; | |
1023 | ||
4f86d3a8 LB |
1024 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1025 | cx = &pr->power.states[i]; | |
1026 | state = &dev->states[count]; | |
4202735e | 1027 | state_usage = &dev->states_usage[count]; |
4f86d3a8 LB |
1028 | |
1029 | if (!cx->valid) | |
1030 | continue; | |
1031 | ||
1032 | #ifdef CONFIG_HOTPLUG_CPU | |
1033 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1034 | !pr->flags.has_cst && | |
1035 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1036 | continue; | |
1fec74a9 | 1037 | #endif |
4202735e | 1038 | cpuidle_set_statedata(state_usage, cx); |
4f86d3a8 LB |
1039 | |
1040 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1041 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1042 | state->exit_latency = cx->latency; |
4963f620 | 1043 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1044 | |
1045 | state->flags = 0; | |
1046 | switch (cx->type) { | |
1047 | case ACPI_STATE_C1: | |
8e92b660 VP |
1048 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1049 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1050 | ||
4f86d3a8 | 1051 | state->enter = acpi_idle_enter_c1; |
e978aa7d | 1052 | dev->safe_state_index = count; |
4f86d3a8 LB |
1053 | break; |
1054 | ||
1055 | case ACPI_STATE_C2: | |
4f86d3a8 LB |
1056 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
1057 | state->enter = acpi_idle_enter_simple; | |
e978aa7d | 1058 | dev->safe_state_index = count; |
4f86d3a8 LB |
1059 | break; |
1060 | ||
1061 | case ACPI_STATE_C3: | |
4f86d3a8 | 1062 | state->flags |= CPUIDLE_FLAG_TIME_VALID; |
4f86d3a8 LB |
1063 | state->enter = pr->flags.bm_check ? |
1064 | acpi_idle_enter_bm : | |
1065 | acpi_idle_enter_simple; | |
1066 | break; | |
1067 | } | |
1068 | ||
1069 | count++; | |
9a0b8415 | 1070 | if (count == CPUIDLE_STATE_MAX) |
1071 | break; | |
4f86d3a8 LB |
1072 | } |
1073 | ||
1074 | dev->state_count = count; | |
1075 | ||
1076 | if (!count) | |
1077 | return -EINVAL; | |
1078 | ||
4f86d3a8 LB |
1079 | return 0; |
1080 | } | |
1081 | ||
1082 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1083 | { | |
dcb84f33 | 1084 | int ret = 0; |
4f86d3a8 | 1085 | |
d1896049 | 1086 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1087 | return 0; |
1088 | ||
4f86d3a8 LB |
1089 | if (!pr) |
1090 | return -EINVAL; | |
1091 | ||
1092 | if (nocst) { | |
1093 | return -ENODEV; | |
1094 | } | |
1095 | ||
1096 | if (!pr->flags.power_setup_done) | |
1097 | return -ENODEV; | |
1098 | ||
1099 | cpuidle_pause_and_lock(); | |
1100 | cpuidle_disable_device(&pr->power.dev); | |
1101 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1102 | if (pr->flags.power) { |
1103 | acpi_processor_setup_cpuidle(pr); | |
1104 | ret = cpuidle_enable_device(&pr->power.dev); | |
1105 | } | |
4f86d3a8 LB |
1106 | cpuidle_resume_and_unlock(); |
1107 | ||
1108 | return ret; | |
1109 | } | |
1110 | ||
7af8b660 | 1111 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1112 | struct acpi_device *device) |
1da177e4 | 1113 | { |
4be44fcd | 1114 | acpi_status status = 0; |
b6835052 | 1115 | static int first_run; |
1da177e4 | 1116 | |
d1896049 | 1117 | if (disabled_by_idle_boot_param()) |
36a91358 | 1118 | return 0; |
1da177e4 LT |
1119 | |
1120 | if (!first_run) { | |
1121 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1122 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1123 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1124 | printk(KERN_NOTICE |
1125 | "ACPI: processor limited to max C-state %d\n", | |
1126 | max_cstate); | |
1da177e4 LT |
1127 | first_run++; |
1128 | } | |
1129 | ||
02df8b93 | 1130 | if (!pr) |
d550d98d | 1131 | return -EINVAL; |
02df8b93 | 1132 | |
cee324b1 | 1133 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1134 | status = |
cee324b1 | 1135 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1136 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1137 | ACPI_EXCEPTION((AE_INFO, status, |
1138 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1139 | } |
1140 | } | |
1141 | ||
1142 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1143 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1144 | |
1145 | /* | |
1146 | * Install the idle handler if processor power management is supported. | |
1147 | * Note that we use previously set idle handler will be used on | |
1148 | * platforms that only support C1. | |
1149 | */ | |
36a91358 | 1150 | if (pr->flags.power) { |
4f86d3a8 | 1151 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1152 | if (cpuidle_register_device(&pr->power.dev)) |
1153 | return -EIO; | |
1da177e4 | 1154 | } |
d550d98d | 1155 | return 0; |
1da177e4 LT |
1156 | } |
1157 | ||
4be44fcd LB |
1158 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1159 | struct acpi_device *device) | |
1da177e4 | 1160 | { |
d1896049 | 1161 | if (disabled_by_idle_boot_param()) |
36a91358 VP |
1162 | return 0; |
1163 | ||
dcb84f33 | 1164 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1165 | pr->flags.power_setup_done = 0; |
1166 | ||
d550d98d | 1167 | return 0; |
1da177e4 | 1168 | } |