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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
ba84be23 | 44 | #include <linux/irqflags.h> |
1da177e4 | 45 | |
3434933b TG |
46 | /* |
47 | * Include the apic definitions for x86 to have the APIC timer related defines | |
48 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
49 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
50 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
51 | */ | |
52 | #ifdef CONFIG_X86 | |
53 | #include <asm/apic.h> | |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include <asm/io.h> |
57 | #include <asm/uaccess.h> | |
58 | ||
59 | #include <acpi/acpi_bus.h> | |
60 | #include <acpi/processor.h> | |
c1e3b377 | 61 | #include <asm/processor.h> |
1da177e4 | 62 | |
a192a958 LB |
63 | #define PREFIX "ACPI: " |
64 | ||
1da177e4 | 65 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 66 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 67 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 68 | #define ACPI_PROCESSOR_FILE_POWER "power" |
2aa44d05 | 69 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
70 | #define C2_OVERHEAD 1 /* 1us */ |
71 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 72 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 73 | |
4f86d3a8 LB |
74 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
75 | module_param(max_cstate, uint, 0000); | |
b6835052 | 76 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
77 | module_param(nocst, uint, 0000); |
78 | ||
25de5718 | 79 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 80 | module_param(latency_factor, uint, 0644); |
1da177e4 | 81 | |
ff69f2bb | 82 | static s64 us_to_pm_timer_ticks(s64 t) |
83 | { | |
84 | return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); | |
85 | } | |
1da177e4 LT |
86 | /* |
87 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
88 | * For now disable this. Probably a bug somewhere else. | |
89 | * | |
90 | * To skip this limit, boot/load with a large max_cstate limit. | |
91 | */ | |
1855256c | 92 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
93 | { |
94 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
95 | return 0; | |
96 | ||
3d35600a | 97 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
98 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
99 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 100 | |
3d35600a | 101 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
102 | |
103 | return 0; | |
104 | } | |
105 | ||
7ded5689 AR |
106 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
107 | callers to only run once -AK */ | |
108 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
109 | { set_max_cstate, "Clevo 5600D", { |
110 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
111 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 112 | (void *)2}, |
370d5cd8 AV |
113 | { set_max_cstate, "Pavilion zv5000", { |
114 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
115 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
116 | (void *)1}, | |
117 | { set_max_cstate, "Asus L8400B", { | |
118 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
119 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
120 | (void *)1}, | |
1da177e4 LT |
121 | {}, |
122 | }; | |
123 | ||
4f86d3a8 | 124 | |
2e906655 | 125 | /* |
126 | * Callers should disable interrupts before the call and enable | |
127 | * interrupts after return. | |
128 | */ | |
ddc081a1 VP |
129 | static void acpi_safe_halt(void) |
130 | { | |
131 | current_thread_info()->status &= ~TS_POLLING; | |
132 | /* | |
133 | * TS_POLLING-cleared state must be visible before we | |
134 | * test NEED_RESCHED: | |
135 | */ | |
136 | smp_mb(); | |
71e93d15 | 137 | if (!need_resched()) { |
ddc081a1 | 138 | safe_halt(); |
71e93d15 VP |
139 | local_irq_disable(); |
140 | } | |
ddc081a1 VP |
141 | current_thread_info()->status |= TS_POLLING; |
142 | } | |
143 | ||
169a0abb TG |
144 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
145 | ||
146 | /* | |
147 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
148 | * This seems to be a common problem on AMD boxen, but other vendors |
149 | * are affected too. We pick the most conservative approach: we assume | |
150 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 151 | */ |
7e275cc4 | 152 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
153 | struct acpi_processor_cx *cx) |
154 | { | |
155 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 156 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 157 | |
db954b58 VP |
158 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
159 | return; | |
160 | ||
87ad57ba SL |
161 | if (boot_cpu_has(X86_FEATURE_AMDC1E)) |
162 | type = ACPI_STATE_C1; | |
163 | ||
169a0abb TG |
164 | /* |
165 | * Check, if one of the previous states already marked the lapic | |
166 | * unstable | |
167 | */ | |
168 | if (pwr->timer_broadcast_on_state < state) | |
169 | return; | |
170 | ||
e585bef8 | 171 | if (cx->type >= type) |
296d93cd | 172 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
173 | } |
174 | ||
918aae42 | 175 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 176 | { |
f833bab8 | 177 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
178 | unsigned long reason; |
179 | ||
180 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
181 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
182 | ||
183 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
184 | } |
185 | ||
918aae42 HS |
186 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
187 | { | |
188 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
189 | (void *)pr, 1); | |
190 | } | |
191 | ||
e9e2cdb4 | 192 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 193 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
194 | struct acpi_processor_cx *cx, |
195 | int broadcast) | |
196 | { | |
e9e2cdb4 TG |
197 | int state = cx - pr->power.states; |
198 | ||
199 | if (state >= pr->power.timer_broadcast_on_state) { | |
200 | unsigned long reason; | |
201 | ||
202 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
203 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
204 | clockevents_notify(reason, &pr->id); | |
205 | } | |
169a0abb TG |
206 | } |
207 | ||
208 | #else | |
209 | ||
7e275cc4 | 210 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 211 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
212 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
213 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
214 | struct acpi_processor_cx *cx, |
215 | int broadcast) | |
216 | { | |
217 | } | |
169a0abb TG |
218 | |
219 | #endif | |
220 | ||
b04e7bdb TG |
221 | /* |
222 | * Suspend / resume control | |
223 | */ | |
224 | static int acpi_idle_suspend; | |
815ab0fd LB |
225 | static u32 saved_bm_rld; |
226 | ||
227 | static void acpi_idle_bm_rld_save(void) | |
228 | { | |
229 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
230 | } | |
231 | static void acpi_idle_bm_rld_restore(void) | |
232 | { | |
233 | u32 resumed_bm_rld; | |
234 | ||
235 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
236 | ||
237 | if (resumed_bm_rld != saved_bm_rld) | |
238 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
239 | } | |
b04e7bdb TG |
240 | |
241 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
242 | { | |
815ab0fd LB |
243 | if (acpi_idle_suspend == 1) |
244 | return 0; | |
245 | ||
246 | acpi_idle_bm_rld_save(); | |
b04e7bdb TG |
247 | acpi_idle_suspend = 1; |
248 | return 0; | |
249 | } | |
250 | ||
251 | int acpi_processor_resume(struct acpi_device * device) | |
252 | { | |
815ab0fd LB |
253 | if (acpi_idle_suspend == 0) |
254 | return 0; | |
255 | ||
256 | acpi_idle_bm_rld_restore(); | |
b04e7bdb TG |
257 | acpi_idle_suspend = 0; |
258 | return 0; | |
259 | } | |
260 | ||
61331168 | 261 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
520daf72 | 262 | static void tsc_check_state(int state) |
ddb25f9a AK |
263 | { |
264 | switch (boot_cpu_data.x86_vendor) { | |
265 | case X86_VENDOR_AMD: | |
40fb1715 | 266 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
267 | /* |
268 | * AMD Fam10h TSC will tick in all | |
269 | * C/P/S0/S1 states when this bit is set. | |
270 | */ | |
40fb1715 | 271 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 272 | return; |
40fb1715 | 273 | |
ddb25f9a | 274 | /*FALL THROUGH*/ |
ddb25f9a | 275 | default: |
520daf72 LB |
276 | /* TSC could halt in idle, so notify users */ |
277 | if (state > ACPI_STATE_C1) | |
278 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
279 | } |
280 | } | |
520daf72 LB |
281 | #else |
282 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
283 | #endif |
284 | ||
4be44fcd | 285 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 286 | { |
1da177e4 LT |
287 | |
288 | if (!pr) | |
d550d98d | 289 | return -EINVAL; |
1da177e4 LT |
290 | |
291 | if (!pr->pblk) | |
d550d98d | 292 | return -ENODEV; |
1da177e4 | 293 | |
1da177e4 | 294 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
295 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
296 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
297 | ||
4c033552 VP |
298 | #ifndef CONFIG_HOTPLUG_CPU |
299 | /* | |
300 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 301 | * an SMP system. |
4c033552 | 302 | */ |
ad71860a | 303 | if ((num_online_cpus() > 1) && |
cee324b1 | 304 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 305 | return -ENODEV; |
4c033552 VP |
306 | #endif |
307 | ||
1da177e4 LT |
308 | /* determine C2 and C3 address from pblk */ |
309 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
310 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
311 | ||
312 | /* determine latencies from FADT */ | |
cee324b1 AS |
313 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
314 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 | 315 | |
5d76b6f6 LB |
316 | /* |
317 | * FADT specified C2 latency must be less than or equal to | |
318 | * 100 microseconds. | |
319 | */ | |
320 | if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
321 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
322 | "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); | |
323 | /* invalidate C2 */ | |
324 | pr->power.states[ACPI_STATE_C2].address = 0; | |
325 | } | |
326 | ||
a6d72c18 LB |
327 | /* |
328 | * FADT supplied C3 latency must be less than or equal to | |
329 | * 1000 microseconds. | |
330 | */ | |
331 | if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
332 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
333 | "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); | |
334 | /* invalidate C3 */ | |
335 | pr->power.states[ACPI_STATE_C3].address = 0; | |
336 | } | |
337 | ||
1da177e4 LT |
338 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
339 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
340 | pr->power.states[ACPI_STATE_C2].address, | |
341 | pr->power.states[ACPI_STATE_C3].address)); | |
342 | ||
d550d98d | 343 | return 0; |
1da177e4 LT |
344 | } |
345 | ||
991528d7 | 346 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 347 | { |
991528d7 VP |
348 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
349 | /* set the first C-State to C1 */ | |
350 | /* all processors need to support C1 */ | |
351 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
352 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 353 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
354 | } |
355 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 356 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 357 | return 0; |
acf05f4b VP |
358 | } |
359 | ||
4be44fcd | 360 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 361 | { |
4be44fcd LB |
362 | acpi_status status = 0; |
363 | acpi_integer count; | |
cf824788 | 364 | int current_count; |
4be44fcd LB |
365 | int i; |
366 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
367 | union acpi_object *cst; | |
1da177e4 | 368 | |
1da177e4 | 369 | |
1da177e4 | 370 | if (nocst) |
d550d98d | 371 | return -ENODEV; |
1da177e4 | 372 | |
991528d7 | 373 | current_count = 0; |
1da177e4 LT |
374 | |
375 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
376 | if (ACPI_FAILURE(status)) { | |
377 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 378 | return -ENODEV; |
4be44fcd | 379 | } |
1da177e4 | 380 | |
50dd0969 | 381 | cst = buffer.pointer; |
1da177e4 LT |
382 | |
383 | /* There must be at least 2 elements */ | |
384 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 385 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
386 | status = -EFAULT; |
387 | goto end; | |
388 | } | |
389 | ||
390 | count = cst->package.elements[0].integer.value; | |
391 | ||
392 | /* Validate number of power states. */ | |
393 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 394 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
395 | status = -EFAULT; |
396 | goto end; | |
397 | } | |
398 | ||
1da177e4 LT |
399 | /* Tell driver that at least _CST is supported. */ |
400 | pr->flags.has_cst = 1; | |
401 | ||
402 | for (i = 1; i <= count; i++) { | |
403 | union acpi_object *element; | |
404 | union acpi_object *obj; | |
405 | struct acpi_power_register *reg; | |
406 | struct acpi_processor_cx cx; | |
407 | ||
408 | memset(&cx, 0, sizeof(cx)); | |
409 | ||
50dd0969 | 410 | element = &(cst->package.elements[i]); |
1da177e4 LT |
411 | if (element->type != ACPI_TYPE_PACKAGE) |
412 | continue; | |
413 | ||
414 | if (element->package.count != 4) | |
415 | continue; | |
416 | ||
50dd0969 | 417 | obj = &(element->package.elements[0]); |
1da177e4 LT |
418 | |
419 | if (obj->type != ACPI_TYPE_BUFFER) | |
420 | continue; | |
421 | ||
4be44fcd | 422 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
423 | |
424 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 425 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
426 | continue; |
427 | ||
1da177e4 | 428 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 429 | obj = &(element->package.elements[1]); |
1da177e4 LT |
430 | if (obj->type != ACPI_TYPE_INTEGER) |
431 | continue; | |
432 | ||
433 | cx.type = obj->integer.value; | |
991528d7 VP |
434 | /* |
435 | * Some buggy BIOSes won't list C1 in _CST - | |
436 | * Let acpi_processor_get_power_info_default() handle them later | |
437 | */ | |
438 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
439 | current_count++; | |
440 | ||
441 | cx.address = reg->address; | |
442 | cx.index = current_count + 1; | |
443 | ||
bc71bec9 | 444 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
445 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
446 | if (acpi_processor_ffh_cstate_probe | |
447 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 448 | cx.entry_method = ACPI_CSTATE_FFH; |
449 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
450 | /* |
451 | * C1 is a special case where FIXED_HARDWARE | |
452 | * can be handled in non-MWAIT way as well. | |
453 | * In that case, save this _CST entry info. | |
991528d7 VP |
454 | * Otherwise, ignore this info and continue. |
455 | */ | |
bc71bec9 | 456 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 457 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 458 | } else { |
991528d7 VP |
459 | continue; |
460 | } | |
da5e09a1 ZY |
461 | if (cx.type == ACPI_STATE_C1 && |
462 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
463 | /* |
464 | * In most cases the C1 space_id obtained from | |
465 | * _CST object is FIXED_HARDWARE access mode. | |
466 | * But when the option of idle=halt is added, | |
467 | * the entry_method type should be changed from | |
468 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
469 | * When the option of idle=nomwait is added, |
470 | * the C1 entry_method type should be | |
471 | * CSTATE_HALT. | |
c1e3b377 ZY |
472 | */ |
473 | cx.entry_method = ACPI_CSTATE_HALT; | |
474 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
475 | } | |
4fcb2fcd VP |
476 | } else { |
477 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
478 | cx.address); | |
991528d7 | 479 | } |
1da177e4 | 480 | |
0fda6b40 VP |
481 | if (cx.type == ACPI_STATE_C1) { |
482 | cx.valid = 1; | |
483 | } | |
4fcb2fcd | 484 | |
50dd0969 | 485 | obj = &(element->package.elements[2]); |
1da177e4 LT |
486 | if (obj->type != ACPI_TYPE_INTEGER) |
487 | continue; | |
488 | ||
489 | cx.latency = obj->integer.value; | |
490 | ||
50dd0969 | 491 | obj = &(element->package.elements[3]); |
1da177e4 LT |
492 | if (obj->type != ACPI_TYPE_INTEGER) |
493 | continue; | |
494 | ||
495 | cx.power = obj->integer.value; | |
496 | ||
cf824788 JM |
497 | current_count++; |
498 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
499 | ||
500 | /* | |
501 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
502 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
503 | */ | |
504 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
505 | printk(KERN_WARNING | |
506 | "Limiting number of power states to max (%d)\n", | |
507 | ACPI_PROCESSOR_MAX_POWER); | |
508 | printk(KERN_WARNING | |
509 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
510 | break; | |
511 | } | |
1da177e4 LT |
512 | } |
513 | ||
4be44fcd | 514 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 515 | current_count)); |
1da177e4 LT |
516 | |
517 | /* Validate number of power states discovered */ | |
cf824788 | 518 | if (current_count < 2) |
6d93c648 | 519 | status = -EFAULT; |
1da177e4 | 520 | |
4be44fcd | 521 | end: |
02438d87 | 522 | kfree(buffer.pointer); |
1da177e4 | 523 | |
d550d98d | 524 | return status; |
1da177e4 LT |
525 | } |
526 | ||
4be44fcd LB |
527 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
528 | struct acpi_processor_cx *cx) | |
1da177e4 | 529 | { |
ee1ca48f PV |
530 | static int bm_check_flag = -1; |
531 | static int bm_control_flag = -1; | |
02df8b93 | 532 | |
1da177e4 LT |
533 | |
534 | if (!cx->address) | |
d550d98d | 535 | return; |
1da177e4 | 536 | |
1da177e4 LT |
537 | /* |
538 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
539 | * DMA transfers are used by any ISA device to avoid livelock. | |
540 | * Note that we could disable Type-F DMA (as recommended by | |
541 | * the erratum), but this is known to disrupt certain ISA | |
542 | * devices thus we take the conservative approach. | |
543 | */ | |
544 | else if (errata.piix4.fdma) { | |
545 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 546 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 547 | return; |
1da177e4 LT |
548 | } |
549 | ||
02df8b93 | 550 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 551 | if (bm_check_flag == -1) { |
02df8b93 VP |
552 | /* Determine whether bm_check is needed based on CPU */ |
553 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
554 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 555 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
556 | } else { |
557 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 558 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
559 | } |
560 | ||
561 | if (pr->flags.bm_check) { | |
02df8b93 | 562 | if (!pr->flags.bm_control) { |
ed3110ef VP |
563 | if (pr->flags.has_cst != 1) { |
564 | /* bus mastering control is necessary */ | |
565 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
566 | "C3 support requires BM control\n")); | |
567 | return; | |
568 | } else { | |
569 | /* Here we enter C3 without bus mastering */ | |
570 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
571 | "C3 support without BM control\n")); | |
572 | } | |
02df8b93 VP |
573 | } |
574 | } else { | |
02df8b93 VP |
575 | /* |
576 | * WBINVD should be set in fadt, for C3 state to be | |
577 | * supported on when bm_check is not required. | |
578 | */ | |
cee324b1 | 579 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 580 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
581 | "Cache invalidation should work properly" |
582 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 583 | return; |
02df8b93 | 584 | } |
02df8b93 VP |
585 | } |
586 | ||
1da177e4 LT |
587 | /* |
588 | * Otherwise we've met all of our C3 requirements. | |
589 | * Normalize the C3 latency to expidite policy. Enable | |
590 | * checking of bus mastering status (bm_check) so we can | |
591 | * use this in our C3 policy | |
592 | */ | |
593 | cx->valid = 1; | |
4f86d3a8 | 594 | |
4f86d3a8 | 595 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
596 | /* |
597 | * On older chipsets, BM_RLD needs to be set | |
598 | * in order for Bus Master activity to wake the | |
599 | * system from C3. Newer chipsets handle DMA | |
600 | * during C3 automatically and BM_RLD is a NOP. | |
601 | * In either case, the proper way to | |
602 | * handle BM_RLD is to set it and leave it set. | |
603 | */ | |
50ffba1b | 604 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 605 | |
d550d98d | 606 | return; |
1da177e4 LT |
607 | } |
608 | ||
1da177e4 LT |
609 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
610 | { | |
611 | unsigned int i; | |
612 | unsigned int working = 0; | |
6eb0a0fd | 613 | |
169a0abb | 614 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 615 | |
a0bf284b | 616 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
617 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
618 | ||
619 | switch (cx->type) { | |
620 | case ACPI_STATE_C1: | |
621 | cx->valid = 1; | |
622 | break; | |
623 | ||
624 | case ACPI_STATE_C2: | |
d22edd29 LB |
625 | if (!cx->address) |
626 | break; | |
627 | cx->valid = 1; | |
628 | cx->latency_ticks = cx->latency; /* Normalize latency */ | |
1da177e4 LT |
629 | break; |
630 | ||
631 | case ACPI_STATE_C3: | |
632 | acpi_processor_power_verify_c3(pr, cx); | |
633 | break; | |
634 | } | |
7e275cc4 LB |
635 | if (!cx->valid) |
636 | continue; | |
1da177e4 | 637 | |
7e275cc4 LB |
638 | lapic_timer_check_state(i, pr, cx); |
639 | tsc_check_state(cx->type); | |
640 | working++; | |
1da177e4 | 641 | } |
bd663347 | 642 | |
918aae42 | 643 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
644 | |
645 | return (working); | |
646 | } | |
647 | ||
4be44fcd | 648 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
649 | { |
650 | unsigned int i; | |
651 | int result; | |
652 | ||
1da177e4 LT |
653 | |
654 | /* NOTE: the idle thread may not be running while calling | |
655 | * this function */ | |
656 | ||
991528d7 VP |
657 | /* Zero initialize all the C-states info. */ |
658 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
659 | ||
1da177e4 | 660 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 661 | if (result == -ENODEV) |
c5a114f1 | 662 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 663 | |
991528d7 VP |
664 | if (result) |
665 | return result; | |
666 | ||
667 | acpi_processor_get_power_info_default(pr); | |
668 | ||
cf824788 | 669 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 670 | |
1da177e4 LT |
671 | /* |
672 | * if one state of type C2 or C3 is available, mark this | |
673 | * CPU as being "idle manageable" | |
674 | */ | |
675 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 676 | if (pr->power.states[i].valid) { |
1da177e4 | 677 | pr->power.count = i; |
2203d6ed LT |
678 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
679 | pr->flags.power = 1; | |
acf05f4b | 680 | } |
1da177e4 LT |
681 | } |
682 | ||
d550d98d | 683 | return 0; |
1da177e4 LT |
684 | } |
685 | ||
74cad4ee | 686 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 LT |
687 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
688 | { | |
50dd0969 | 689 | struct acpi_processor *pr = seq->private; |
4be44fcd | 690 | unsigned int i; |
1da177e4 | 691 | |
1da177e4 LT |
692 | |
693 | if (!pr) | |
694 | goto end; | |
695 | ||
696 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 697 | "max_cstate: C%d\n" |
5c87579e | 698 | "maximum allowed latency: %d usec\n", |
4be44fcd | 699 | pr->power.state ? pr->power.state - pr->power.states : 0, |
92614610 | 700 | max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
701 | |
702 | seq_puts(seq, "states:\n"); | |
703 | ||
704 | for (i = 1; i <= pr->power.count; i++) { | |
705 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
706 | (&pr->power.states[i] == |
707 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
708 | |
709 | if (!pr->power.states[i].valid) { | |
710 | seq_puts(seq, "<not supported>\n"); | |
711 | continue; | |
712 | } | |
713 | ||
714 | switch (pr->power.states[i].type) { | |
715 | case ACPI_STATE_C1: | |
716 | seq_printf(seq, "type[C1] "); | |
717 | break; | |
718 | case ACPI_STATE_C2: | |
719 | seq_printf(seq, "type[C2] "); | |
720 | break; | |
721 | case ACPI_STATE_C3: | |
722 | seq_printf(seq, "type[C3] "); | |
723 | break; | |
724 | default: | |
725 | seq_printf(seq, "type[--] "); | |
726 | break; | |
727 | } | |
728 | ||
729 | if (pr->power.states[i].promotion.state) | |
730 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
731 | (pr->power.states[i].promotion.state - |
732 | pr->power.states)); | |
1da177e4 LT |
733 | else |
734 | seq_puts(seq, "promotion[--] "); | |
735 | ||
736 | if (pr->power.states[i].demotion.state) | |
737 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
738 | (pr->power.states[i].demotion.state - |
739 | pr->power.states)); | |
1da177e4 LT |
740 | else |
741 | seq_puts(seq, "demotion[--] "); | |
742 | ||
a3c6598f | 743 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 744 | pr->power.states[i].latency, |
a3c6598f | 745 | pr->power.states[i].usage, |
b0b7eaaf | 746 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
747 | } |
748 | ||
4be44fcd | 749 | end: |
d550d98d | 750 | return 0; |
1da177e4 LT |
751 | } |
752 | ||
753 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
754 | { | |
755 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 756 | PDE(inode)->data); |
1da177e4 LT |
757 | } |
758 | ||
d7508032 | 759 | static const struct file_operations acpi_processor_power_fops = { |
cf7acfab | 760 | .owner = THIS_MODULE, |
4be44fcd LB |
761 | .open = acpi_processor_power_open_fs, |
762 | .read = seq_read, | |
763 | .llseek = seq_lseek, | |
764 | .release = single_release, | |
1da177e4 | 765 | }; |
74cad4ee | 766 | #endif |
4f86d3a8 LB |
767 | |
768 | /** | |
769 | * acpi_idle_bm_check - checks if bus master activity was detected | |
770 | */ | |
771 | static int acpi_idle_bm_check(void) | |
772 | { | |
773 | u32 bm_status = 0; | |
774 | ||
50ffba1b | 775 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 776 | if (bm_status) |
50ffba1b | 777 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
778 | /* |
779 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
780 | * the true state of bus mastering activity; forcing us to | |
781 | * manually check the BMIDEA bit of each IDE channel. | |
782 | */ | |
783 | else if (errata.piix4.bmisx) { | |
784 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
785 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
786 | bm_status = 1; | |
787 | } | |
788 | return bm_status; | |
789 | } | |
790 | ||
4f86d3a8 LB |
791 | /** |
792 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
793 | * @cx: cstate data | |
bc71bec9 | 794 | * |
795 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
796 | */ |
797 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
798 | { | |
dcf30997 SR |
799 | /* Don't trace irqs off for idle */ |
800 | stop_critical_timings(); | |
bc71bec9 | 801 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
802 | /* Call into architectural FFH based C-state */ |
803 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 804 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
805 | acpi_safe_halt(); | |
4f86d3a8 LB |
806 | } else { |
807 | int unused; | |
808 | /* IO port based C-state */ | |
809 | inb(cx->address); | |
810 | /* Dummy wait op - must do something useless after P_LVL2 read | |
811 | because chipsets cannot guarantee that STPCLK# signal | |
812 | gets asserted in time to freeze execution properly. */ | |
813 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
814 | } | |
dcf30997 | 815 | start_critical_timings(); |
4f86d3a8 LB |
816 | } |
817 | ||
818 | /** | |
819 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
820 | * @dev: the target CPU | |
821 | * @state: the state data | |
822 | * | |
823 | * This is equivalent to the HALT instruction. | |
824 | */ | |
825 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
826 | struct cpuidle_state *state) | |
827 | { | |
ff69f2bb | 828 | ktime_t kt1, kt2; |
829 | s64 idle_time; | |
4f86d3a8 LB |
830 | struct acpi_processor *pr; |
831 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 832 | |
706546d0 | 833 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
834 | |
835 | if (unlikely(!pr)) | |
836 | return 0; | |
837 | ||
2e906655 | 838 | local_irq_disable(); |
b077fbad VP |
839 | |
840 | /* Do not access any ACPI IO ports in suspend path */ | |
841 | if (acpi_idle_suspend) { | |
b077fbad | 842 | local_irq_enable(); |
7d60e8ab | 843 | cpu_relax(); |
b077fbad VP |
844 | return 0; |
845 | } | |
846 | ||
7e275cc4 | 847 | lapic_timer_state_broadcast(pr, cx, 1); |
ff69f2bb | 848 | kt1 = ktime_get_real(); |
bc71bec9 | 849 | acpi_idle_do_entry(cx); |
ff69f2bb | 850 | kt2 = ktime_get_real(); |
851 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 852 | |
2e906655 | 853 | local_irq_enable(); |
4f86d3a8 | 854 | cx->usage++; |
7e275cc4 | 855 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 856 | |
ff69f2bb | 857 | return idle_time; |
4f86d3a8 LB |
858 | } |
859 | ||
860 | /** | |
861 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
862 | * @dev: the target CPU | |
863 | * @state: the state data | |
864 | */ | |
865 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
866 | struct cpuidle_state *state) | |
867 | { | |
868 | struct acpi_processor *pr; | |
869 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 870 | ktime_t kt1, kt2; |
871 | s64 idle_time; | |
872 | s64 sleep_ticks = 0; | |
50629118 | 873 | |
706546d0 | 874 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
875 | |
876 | if (unlikely(!pr)) | |
877 | return 0; | |
878 | ||
e196441b LB |
879 | if (acpi_idle_suspend) |
880 | return(acpi_idle_enter_c1(dev, state)); | |
881 | ||
4f86d3a8 LB |
882 | local_irq_disable(); |
883 | current_thread_info()->status &= ~TS_POLLING; | |
884 | /* | |
885 | * TS_POLLING-cleared state must be visible before we test | |
886 | * NEED_RESCHED: | |
887 | */ | |
888 | smp_mb(); | |
889 | ||
890 | if (unlikely(need_resched())) { | |
891 | current_thread_info()->status |= TS_POLLING; | |
892 | local_irq_enable(); | |
893 | return 0; | |
894 | } | |
895 | ||
e17bcb43 TG |
896 | /* |
897 | * Must be done before busmaster disable as we might need to | |
898 | * access HPET ! | |
899 | */ | |
7e275cc4 | 900 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 901 | |
4f86d3a8 LB |
902 | if (cx->type == ACPI_STATE_C3) |
903 | ACPI_FLUSH_CPU_CACHE(); | |
904 | ||
ff69f2bb | 905 | kt1 = ktime_get_real(); |
50629118 VP |
906 | /* Tell the scheduler that we are going deep-idle: */ |
907 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 908 | acpi_idle_do_entry(cx); |
ff69f2bb | 909 | kt2 = ktime_get_real(); |
910 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 911 | |
ff69f2bb | 912 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
913 | |
914 | /* Tell the scheduler how much we idled: */ | |
915 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
916 | |
917 | local_irq_enable(); | |
918 | current_thread_info()->status |= TS_POLLING; | |
919 | ||
920 | cx->usage++; | |
921 | ||
7e275cc4 | 922 | lapic_timer_state_broadcast(pr, cx, 0); |
50629118 | 923 | cx->time += sleep_ticks; |
ff69f2bb | 924 | return idle_time; |
4f86d3a8 LB |
925 | } |
926 | ||
927 | static int c3_cpu_count; | |
928 | static DEFINE_SPINLOCK(c3_lock); | |
929 | ||
930 | /** | |
931 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
932 | * @dev: the target CPU | |
933 | * @state: the state data | |
934 | * | |
935 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
936 | */ | |
937 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
938 | struct cpuidle_state *state) | |
939 | { | |
940 | struct acpi_processor *pr; | |
941 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 942 | ktime_t kt1, kt2; |
943 | s64 idle_time; | |
944 | s64 sleep_ticks = 0; | |
945 | ||
50629118 | 946 | |
706546d0 | 947 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
948 | |
949 | if (unlikely(!pr)) | |
950 | return 0; | |
951 | ||
e196441b LB |
952 | if (acpi_idle_suspend) |
953 | return(acpi_idle_enter_c1(dev, state)); | |
954 | ||
ddc081a1 VP |
955 | if (acpi_idle_bm_check()) { |
956 | if (dev->safe_state) { | |
addbad46 | 957 | dev->last_state = dev->safe_state; |
ddc081a1 VP |
958 | return dev->safe_state->enter(dev, dev->safe_state); |
959 | } else { | |
2e906655 | 960 | local_irq_disable(); |
ddc081a1 | 961 | acpi_safe_halt(); |
2e906655 | 962 | local_irq_enable(); |
ddc081a1 VP |
963 | return 0; |
964 | } | |
965 | } | |
966 | ||
4f86d3a8 LB |
967 | local_irq_disable(); |
968 | current_thread_info()->status &= ~TS_POLLING; | |
969 | /* | |
970 | * TS_POLLING-cleared state must be visible before we test | |
971 | * NEED_RESCHED: | |
972 | */ | |
973 | smp_mb(); | |
974 | ||
975 | if (unlikely(need_resched())) { | |
976 | current_thread_info()->status |= TS_POLLING; | |
977 | local_irq_enable(); | |
978 | return 0; | |
979 | } | |
980 | ||
996520c1 VP |
981 | acpi_unlazy_tlb(smp_processor_id()); |
982 | ||
50629118 VP |
983 | /* Tell the scheduler that we are going deep-idle: */ |
984 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
985 | /* |
986 | * Must be done before busmaster disable as we might need to | |
987 | * access HPET ! | |
988 | */ | |
7e275cc4 | 989 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 990 | |
f461ddea | 991 | kt1 = ktime_get_real(); |
ddc081a1 VP |
992 | /* |
993 | * disable bus master | |
994 | * bm_check implies we need ARB_DIS | |
995 | * !bm_check implies we need cache flush | |
996 | * bm_control implies whether we can do ARB_DIS | |
997 | * | |
998 | * That leaves a case where bm_check is set and bm_control is | |
999 | * not set. In that case we cannot do much, we enter C3 | |
1000 | * without doing anything. | |
1001 | */ | |
1002 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1003 | spin_lock(&c3_lock); |
1004 | c3_cpu_count++; | |
1005 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1006 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 1007 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 1008 | spin_unlock(&c3_lock); |
ddc081a1 VP |
1009 | } else if (!pr->flags.bm_check) { |
1010 | ACPI_FLUSH_CPU_CACHE(); | |
1011 | } | |
4f86d3a8 | 1012 | |
ddc081a1 | 1013 | acpi_idle_do_entry(cx); |
4f86d3a8 | 1014 | |
ddc081a1 VP |
1015 | /* Re-enable bus master arbitration */ |
1016 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1017 | spin_lock(&c3_lock); |
50ffba1b | 1018 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1019 | c3_cpu_count--; |
1020 | spin_unlock(&c3_lock); | |
1021 | } | |
f461ddea LB |
1022 | kt2 = ktime_get_real(); |
1023 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 1024 | |
ff69f2bb | 1025 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
1026 | /* Tell the scheduler how much we idled: */ |
1027 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1028 | |
1029 | local_irq_enable(); | |
1030 | current_thread_info()->status |= TS_POLLING; | |
1031 | ||
1032 | cx->usage++; | |
1033 | ||
7e275cc4 | 1034 | lapic_timer_state_broadcast(pr, cx, 0); |
50629118 | 1035 | cx->time += sleep_ticks; |
ff69f2bb | 1036 | return idle_time; |
4f86d3a8 LB |
1037 | } |
1038 | ||
1039 | struct cpuidle_driver acpi_idle_driver = { | |
1040 | .name = "acpi_idle", | |
1041 | .owner = THIS_MODULE, | |
1042 | }; | |
1043 | ||
1044 | /** | |
1045 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1046 | * @pr: the ACPI processor | |
1047 | */ | |
1048 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1049 | { | |
9a0b8415 | 1050 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1051 | struct acpi_processor_cx *cx; |
1052 | struct cpuidle_state *state; | |
1053 | struct cpuidle_device *dev = &pr->power.dev; | |
1054 | ||
1055 | if (!pr->flags.power_setup_done) | |
1056 | return -EINVAL; | |
1057 | ||
1058 | if (pr->flags.power == 0) { | |
1059 | return -EINVAL; | |
1060 | } | |
1061 | ||
dcb84f33 | 1062 | dev->cpu = pr->id; |
4fcb2fcd VP |
1063 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1064 | dev->states[i].name[0] = '\0'; | |
1065 | dev->states[i].desc[0] = '\0'; | |
1066 | } | |
1067 | ||
615dfd93 LB |
1068 | if (max_cstate == 0) |
1069 | max_cstate = 1; | |
1070 | ||
4f86d3a8 LB |
1071 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1072 | cx = &pr->power.states[i]; | |
1073 | state = &dev->states[count]; | |
1074 | ||
1075 | if (!cx->valid) | |
1076 | continue; | |
1077 | ||
1078 | #ifdef CONFIG_HOTPLUG_CPU | |
1079 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1080 | !pr->flags.has_cst && | |
1081 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1082 | continue; | |
1fec74a9 | 1083 | #endif |
4f86d3a8 LB |
1084 | cpuidle_set_statedata(state, cx); |
1085 | ||
1086 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1087 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1088 | state->exit_latency = cx->latency; |
4963f620 | 1089 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1090 | state->power_usage = cx->power; |
1091 | ||
1092 | state->flags = 0; | |
1093 | switch (cx->type) { | |
1094 | case ACPI_STATE_C1: | |
1095 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1096 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1097 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1098 | ||
4f86d3a8 | 1099 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1100 | dev->safe_state = state; |
4f86d3a8 LB |
1101 | break; |
1102 | ||
1103 | case ACPI_STATE_C2: | |
1104 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1105 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1106 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1107 | dev->safe_state = state; |
4f86d3a8 LB |
1108 | break; |
1109 | ||
1110 | case ACPI_STATE_C3: | |
1111 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1112 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1113 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1114 | state->enter = pr->flags.bm_check ? | |
1115 | acpi_idle_enter_bm : | |
1116 | acpi_idle_enter_simple; | |
1117 | break; | |
1118 | } | |
1119 | ||
1120 | count++; | |
9a0b8415 | 1121 | if (count == CPUIDLE_STATE_MAX) |
1122 | break; | |
4f86d3a8 LB |
1123 | } |
1124 | ||
1125 | dev->state_count = count; | |
1126 | ||
1127 | if (!count) | |
1128 | return -EINVAL; | |
1129 | ||
4f86d3a8 LB |
1130 | return 0; |
1131 | } | |
1132 | ||
1133 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1134 | { | |
dcb84f33 | 1135 | int ret = 0; |
4f86d3a8 | 1136 | |
36a91358 VP |
1137 | if (boot_option_idle_override) |
1138 | return 0; | |
1139 | ||
4f86d3a8 LB |
1140 | if (!pr) |
1141 | return -EINVAL; | |
1142 | ||
1143 | if (nocst) { | |
1144 | return -ENODEV; | |
1145 | } | |
1146 | ||
1147 | if (!pr->flags.power_setup_done) | |
1148 | return -ENODEV; | |
1149 | ||
1150 | cpuidle_pause_and_lock(); | |
1151 | cpuidle_disable_device(&pr->power.dev); | |
1152 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1153 | if (pr->flags.power) { |
1154 | acpi_processor_setup_cpuidle(pr); | |
1155 | ret = cpuidle_enable_device(&pr->power.dev); | |
1156 | } | |
4f86d3a8 LB |
1157 | cpuidle_resume_and_unlock(); |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
7af8b660 | 1162 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1163 | struct acpi_device *device) |
1da177e4 | 1164 | { |
4be44fcd | 1165 | acpi_status status = 0; |
b6835052 | 1166 | static int first_run; |
b188e4ce | 1167 | #ifdef CONFIG_ACPI_PROCFS |
4be44fcd | 1168 | struct proc_dir_entry *entry = NULL; |
b188e4ce | 1169 | #endif |
1da177e4 | 1170 | |
36a91358 VP |
1171 | if (boot_option_idle_override) |
1172 | return 0; | |
1da177e4 LT |
1173 | |
1174 | if (!first_run) { | |
c1e3b377 ZY |
1175 | if (idle_halt) { |
1176 | /* | |
1177 | * When the boot option of "idle=halt" is added, halt | |
1178 | * is used for CPU IDLE. | |
1179 | * In such case C2/C3 is meaningless. So the max_cstate | |
1180 | * is set to one. | |
1181 | */ | |
1182 | max_cstate = 1; | |
1183 | } | |
1da177e4 | 1184 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1185 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1186 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1187 | printk(KERN_NOTICE |
1188 | "ACPI: processor limited to max C-state %d\n", | |
1189 | max_cstate); | |
1da177e4 LT |
1190 | first_run++; |
1191 | } | |
1192 | ||
02df8b93 | 1193 | if (!pr) |
d550d98d | 1194 | return -EINVAL; |
02df8b93 | 1195 | |
cee324b1 | 1196 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1197 | status = |
cee324b1 | 1198 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1199 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1200 | ACPI_EXCEPTION((AE_INFO, status, |
1201 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1202 | } |
1203 | } | |
1204 | ||
1205 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1206 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1207 | |
1208 | /* | |
1209 | * Install the idle handler if processor power management is supported. | |
1210 | * Note that we use previously set idle handler will be used on | |
1211 | * platforms that only support C1. | |
1212 | */ | |
36a91358 | 1213 | if (pr->flags.power) { |
4f86d3a8 | 1214 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1215 | if (cpuidle_register_device(&pr->power.dev)) |
1216 | return -EIO; | |
1da177e4 | 1217 | } |
74cad4ee | 1218 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 | 1219 | /* 'power' [R] */ |
cf7acfab DL |
1220 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1221 | S_IRUGO, acpi_device_dir(device), | |
1222 | &acpi_processor_power_fops, | |
1223 | acpi_driver_data(device)); | |
1da177e4 | 1224 | if (!entry) |
a6fc6720 | 1225 | return -EIO; |
74cad4ee | 1226 | #endif |
d550d98d | 1227 | return 0; |
1da177e4 LT |
1228 | } |
1229 | ||
4be44fcd LB |
1230 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1231 | struct acpi_device *device) | |
1da177e4 | 1232 | { |
36a91358 VP |
1233 | if (boot_option_idle_override) |
1234 | return 0; | |
1235 | ||
dcb84f33 | 1236 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1237 | pr->flags.power_setup_done = 0; |
1238 | ||
74cad4ee | 1239 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 | 1240 | if (acpi_device_dir(device)) |
4be44fcd LB |
1241 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1242 | acpi_device_dir(device)); | |
74cad4ee | 1243 | #endif |
1da177e4 | 1244 | |
d550d98d | 1245 | return 0; |
1da177e4 | 1246 | } |