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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
5c87579e | 41 | #include <linux/latency.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
60 | ||
61 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
62 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 63 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 64 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 65 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 | 66 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 | 68 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
69 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ |
70 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 71 | static void (*pm_idle_save) (void) __read_mostly; |
4f86d3a8 LB |
72 | #else |
73 | #define C2_OVERHEAD 1 /* 1us */ | |
74 | #define C3_OVERHEAD 1 /* 1us */ | |
75 | #endif | |
76 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) | |
1da177e4 | 77 | |
4f86d3a8 | 78 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
5b3f0e6c | 79 | #ifdef CONFIG_CPU_IDLE |
4f86d3a8 | 80 | module_param(max_cstate, uint, 0000); |
5b3f0e6c VP |
81 | #else |
82 | module_param(max_cstate, uint, 0644); | |
83 | #endif | |
b6835052 | 84 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
85 | module_param(nocst, uint, 0000); |
86 | ||
4f86d3a8 | 87 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
88 | /* |
89 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
90 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
91 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
92 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
93 | * reduce history for more aggressive entry into C3 | |
94 | */ | |
b6835052 | 95 | static unsigned int bm_history __read_mostly = |
4be44fcd | 96 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 97 | module_param(bm_history, uint, 0644); |
4f86d3a8 LB |
98 | |
99 | static int acpi_processor_set_power_policy(struct acpi_processor *pr); | |
100 | ||
101 | #endif | |
1da177e4 LT |
102 | |
103 | /* | |
104 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
105 | * For now disable this. Probably a bug somewhere else. | |
106 | * | |
107 | * To skip this limit, boot/load with a large max_cstate limit. | |
108 | */ | |
1855256c | 109 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
110 | { |
111 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
112 | return 0; | |
113 | ||
3d35600a | 114 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
115 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
116 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 117 | |
3d35600a | 118 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
7ded5689 AR |
123 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
124 | callers to only run once -AK */ | |
125 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
126 | { set_max_cstate, "IBM ThinkPad R40e", { |
127 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
128 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
129 | { set_max_cstate, "IBM ThinkPad R40e", { |
130 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
131 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
132 | { set_max_cstate, "IBM ThinkPad R40e", { | |
133 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
134 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
135 | { set_max_cstate, "IBM ThinkPad R40e", { | |
136 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
137 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
138 | { set_max_cstate, "IBM ThinkPad R40e", { | |
139 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
140 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
141 | { set_max_cstate, "IBM ThinkPad R40e", { | |
142 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
143 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
144 | { set_max_cstate, "IBM ThinkPad R40e", { | |
145 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
146 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
147 | { set_max_cstate, "IBM ThinkPad R40e", { | |
148 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
149 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
150 | { set_max_cstate, "IBM ThinkPad R40e", { | |
151 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
152 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
153 | { set_max_cstate, "IBM ThinkPad R40e", { | |
154 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
155 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
156 | { set_max_cstate, "IBM ThinkPad R40e", { | |
157 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
158 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
159 | { set_max_cstate, "IBM ThinkPad R40e", { | |
160 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
161 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
162 | { set_max_cstate, "IBM ThinkPad R40e", { | |
163 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
164 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
165 | { set_max_cstate, "IBM ThinkPad R40e", { | |
166 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
167 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
168 | { set_max_cstate, "IBM ThinkPad R40e", { | |
169 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
170 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
171 | { set_max_cstate, "IBM ThinkPad R40e", { | |
172 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
173 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
174 | { set_max_cstate, "Medion 41700", { | |
175 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
176 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
177 | { set_max_cstate, "Clevo 5600D", { | |
178 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
179 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 180 | (void *)2}, |
1da177e4 LT |
181 | {}, |
182 | }; | |
183 | ||
4be44fcd | 184 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
185 | { |
186 | if (t2 >= t1) | |
187 | return (t2 - t1); | |
cee324b1 | 188 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
189 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
190 | else | |
191 | return ((0xFFFFFFFF - t1) + t2); | |
192 | } | |
193 | ||
4f86d3a8 LB |
194 | static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) |
195 | { | |
196 | if (t2 >= t1) | |
197 | return PM_TIMER_TICKS_TO_US(t2 - t1); | |
198 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) | |
199 | return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); | |
200 | else | |
201 | return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); | |
202 | } | |
203 | ||
ddc081a1 VP |
204 | static void acpi_safe_halt(void) |
205 | { | |
206 | current_thread_info()->status &= ~TS_POLLING; | |
207 | /* | |
208 | * TS_POLLING-cleared state must be visible before we | |
209 | * test NEED_RESCHED: | |
210 | */ | |
211 | smp_mb(); | |
212 | if (!need_resched()) | |
213 | safe_halt(); | |
214 | current_thread_info()->status |= TS_POLLING; | |
215 | } | |
216 | ||
4f86d3a8 LB |
217 | #ifndef CONFIG_CPU_IDLE |
218 | ||
1da177e4 | 219 | static void |
4be44fcd LB |
220 | acpi_processor_power_activate(struct acpi_processor *pr, |
221 | struct acpi_processor_cx *new) | |
1da177e4 | 222 | { |
4be44fcd | 223 | struct acpi_processor_cx *old; |
1da177e4 LT |
224 | |
225 | if (!pr || !new) | |
226 | return; | |
227 | ||
228 | old = pr->power.state; | |
229 | ||
230 | if (old) | |
231 | old->promotion.count = 0; | |
4be44fcd | 232 | new->demotion.count = 0; |
1da177e4 LT |
233 | |
234 | /* Cleanup from old state. */ | |
235 | if (old) { | |
236 | switch (old->type) { | |
237 | case ACPI_STATE_C3: | |
238 | /* Disable bus master reload */ | |
02df8b93 | 239 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 240 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
241 | break; |
242 | } | |
243 | } | |
244 | ||
245 | /* Prepare to use new state. */ | |
246 | switch (new->type) { | |
247 | case ACPI_STATE_C3: | |
248 | /* Enable bus master reload */ | |
02df8b93 | 249 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 250 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
251 | break; |
252 | } | |
253 | ||
254 | pr->power.state = new; | |
255 | ||
256 | return; | |
257 | } | |
258 | ||
4be44fcd | 259 | static atomic_t c3_cpu_count; |
1da177e4 | 260 | |
991528d7 VP |
261 | /* Common C-state entry for C2, C3, .. */ |
262 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
263 | { | |
264 | if (cstate->space_id == ACPI_CSTATE_FFH) { | |
265 | /* Call into architectural FFH based C-state */ | |
266 | acpi_processor_ffh_cstate_enter(cstate); | |
267 | } else { | |
268 | int unused; | |
269 | /* IO port based C-state */ | |
270 | inb(cstate->address); | |
271 | /* Dummy wait op - must do something useless after P_LVL2 read | |
272 | because chipsets cannot guarantee that STPCLK# signal | |
273 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 274 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
275 | } |
276 | } | |
4f86d3a8 | 277 | #endif /* !CONFIG_CPU_IDLE */ |
991528d7 | 278 | |
169a0abb TG |
279 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
280 | ||
281 | /* | |
282 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
283 | * This seems to be a common problem on AMD boxen, but other vendors |
284 | * are affected too. We pick the most conservative approach: we assume | |
285 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
286 | */ |
287 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
288 | struct acpi_processor_cx *cx) | |
289 | { | |
290 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 291 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
292 | |
293 | /* | |
294 | * Check, if one of the previous states already marked the lapic | |
295 | * unstable | |
296 | */ | |
297 | if (pwr->timer_broadcast_on_state < state) | |
298 | return; | |
299 | ||
e585bef8 | 300 | if (cx->type >= type) |
296d93cd | 301 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
302 | } |
303 | ||
304 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
305 | { | |
e9e2cdb4 TG |
306 | unsigned long reason; |
307 | ||
308 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
309 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
310 | ||
311 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
312 | } |
313 | ||
314 | /* Power(C) State timer broadcast control */ | |
315 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
316 | struct acpi_processor_cx *cx, | |
317 | int broadcast) | |
318 | { | |
e9e2cdb4 TG |
319 | int state = cx - pr->power.states; |
320 | ||
321 | if (state >= pr->power.timer_broadcast_on_state) { | |
322 | unsigned long reason; | |
323 | ||
324 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
325 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
326 | clockevents_notify(reason, &pr->id); | |
327 | } | |
169a0abb TG |
328 | } |
329 | ||
330 | #else | |
331 | ||
332 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
333 | struct acpi_processor_cx *cstate) { } | |
334 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
335 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
336 | struct acpi_processor_cx *cx, | |
337 | int broadcast) | |
338 | { | |
339 | } | |
169a0abb TG |
340 | |
341 | #endif | |
342 | ||
b04e7bdb TG |
343 | /* |
344 | * Suspend / resume control | |
345 | */ | |
346 | static int acpi_idle_suspend; | |
347 | ||
348 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
349 | { | |
350 | acpi_idle_suspend = 1; | |
351 | return 0; | |
352 | } | |
353 | ||
354 | int acpi_processor_resume(struct acpi_device * device) | |
355 | { | |
356 | acpi_idle_suspend = 0; | |
357 | return 0; | |
358 | } | |
359 | ||
4f86d3a8 | 360 | #ifndef CONFIG_CPU_IDLE |
4be44fcd | 361 | static void acpi_processor_idle(void) |
1da177e4 | 362 | { |
4be44fcd | 363 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
364 | struct acpi_processor_cx *cx = NULL; |
365 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
366 | int sleep_ticks = 0; |
367 | u32 t1, t2 = 0; | |
1da177e4 | 368 | |
1da177e4 LT |
369 | /* |
370 | * Interrupts must be disabled during bus mastering calculations and | |
371 | * for C2/C3 transitions. | |
372 | */ | |
373 | local_irq_disable(); | |
374 | ||
d5a3d32a VP |
375 | pr = processors[smp_processor_id()]; |
376 | if (!pr) { | |
377 | local_irq_enable(); | |
378 | return; | |
379 | } | |
380 | ||
1da177e4 LT |
381 | /* |
382 | * Check whether we truly need to go idle, or should | |
383 | * reschedule: | |
384 | */ | |
385 | if (unlikely(need_resched())) { | |
386 | local_irq_enable(); | |
387 | return; | |
388 | } | |
389 | ||
390 | cx = pr->power.state; | |
b04e7bdb | 391 | if (!cx || acpi_idle_suspend) { |
64c7c8f8 NP |
392 | if (pm_idle_save) |
393 | pm_idle_save(); | |
394 | else | |
395 | acpi_safe_halt(); | |
396 | return; | |
397 | } | |
1da177e4 LT |
398 | |
399 | /* | |
400 | * Check BM Activity | |
401 | * ----------------- | |
402 | * Check for bus mastering activity (if required), record, and check | |
403 | * for demotion. | |
404 | */ | |
405 | if (pr->flags.bm_check) { | |
4be44fcd LB |
406 | u32 bm_status = 0; |
407 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 408 | |
c5ab81ca DB |
409 | if (diff > 31) |
410 | diff = 31; | |
1da177e4 | 411 | |
c5ab81ca | 412 | pr->power.bm_activity <<= diff; |
1da177e4 | 413 | |
d8c71b6d | 414 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 415 | if (bm_status) { |
c5ab81ca | 416 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 417 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
418 | } |
419 | /* | |
420 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
421 | * the true state of bus mastering activity; forcing us to | |
422 | * manually check the BMIDEA bit of each IDE channel. | |
423 | */ | |
424 | else if (errata.piix4.bmisx) { | |
425 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 426 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 427 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
428 | } |
429 | ||
430 | pr->power.bm_check_timestamp = jiffies; | |
431 | ||
432 | /* | |
c4a001b1 | 433 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
434 | * to avoid a faulty transition. Note that the processor |
435 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 436 | * function) but should upon the next. |
1da177e4 LT |
437 | * |
438 | * TBD: A better policy might be to fallback to the demotion | |
439 | * state (use it for this quantum only) istead of | |
440 | * demoting -- and rely on duration as our sole demotion | |
441 | * qualification. This may, however, introduce DMA | |
442 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
443 | */ | |
c4a001b1 DB |
444 | if ((pr->power.bm_activity & 0x1) && |
445 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
446 | local_irq_enable(); |
447 | next_state = cx->demotion.state; | |
448 | goto end; | |
449 | } | |
450 | } | |
451 | ||
4c033552 VP |
452 | #ifdef CONFIG_HOTPLUG_CPU |
453 | /* | |
454 | * Check for P_LVL2_UP flag before entering C2 and above on | |
455 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
456 | * detection phase, to work cleanly with logical CPU hotplug. | |
457 | */ | |
4f86d3a8 | 458 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
cee324b1 | 459 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 460 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 461 | #endif |
1e483969 | 462 | |
1da177e4 LT |
463 | /* |
464 | * Sleep: | |
465 | * ------ | |
466 | * Invoke the current Cx state to put the processor to sleep. | |
467 | */ | |
2a298a35 | 468 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 469 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
470 | /* |
471 | * TS_POLLING-cleared state must be visible before we | |
472 | * test NEED_RESCHED: | |
473 | */ | |
474 | smp_mb(); | |
2a298a35 | 475 | if (need_resched()) { |
495ab9c0 | 476 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 477 | local_irq_enable(); |
2a298a35 NP |
478 | return; |
479 | } | |
480 | } | |
481 | ||
1da177e4 LT |
482 | switch (cx->type) { |
483 | ||
484 | case ACPI_STATE_C1: | |
485 | /* | |
486 | * Invoke C1. | |
487 | * Use the appropriate idle routine, the one that would | |
488 | * be used without acpi C-states. | |
489 | */ | |
490 | if (pm_idle_save) | |
491 | pm_idle_save(); | |
492 | else | |
64c7c8f8 NP |
493 | acpi_safe_halt(); |
494 | ||
1da177e4 | 495 | /* |
4be44fcd | 496 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
497 | * go to an ISR rather than here. Need to instrument |
498 | * base interrupt handler. | |
2aa44d05 IM |
499 | * |
500 | * Note: the TSC better not stop in C1, sched_clock() will | |
501 | * skew otherwise. | |
1da177e4 LT |
502 | */ |
503 | sleep_ticks = 0xFFFFFFFF; | |
504 | break; | |
505 | ||
506 | case ACPI_STATE_C2: | |
507 | /* Get start time (ticks) */ | |
cee324b1 | 508 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
2aa44d05 IM |
509 | /* Tell the scheduler that we are going deep-idle: */ |
510 | sched_clock_idle_sleep_event(); | |
1da177e4 | 511 | /* Invoke C2 */ |
e9e2cdb4 | 512 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 513 | acpi_cstate_enter(cx); |
1da177e4 | 514 | /* Get end time (ticks) */ |
cee324b1 | 515 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 516 | |
0aa366f3 | 517 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 518 | /* TSC halts in C2, so notify users */ |
5a90cf20 | 519 | mark_tsc_unstable("possible TSC halt in C2"); |
539eb11e | 520 | #endif |
2aa44d05 IM |
521 | /* Compute time (ticks) that we were actually asleep */ |
522 | sleep_ticks = ticks_elapsed(t1, t2); | |
523 | ||
524 | /* Tell the scheduler how much we idled: */ | |
525 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
526 | ||
1da177e4 LT |
527 | /* Re-enable interrupts */ |
528 | local_irq_enable(); | |
2aa44d05 IM |
529 | /* Do not account our idle-switching overhead: */ |
530 | sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; | |
531 | ||
495ab9c0 | 532 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 533 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
534 | break; |
535 | ||
536 | case ACPI_STATE_C3: | |
bde6f5f5 | 537 | acpi_unlazy_tlb(smp_processor_id()); |
e17bcb43 TG |
538 | /* |
539 | * Must be done before busmaster disable as we might | |
540 | * need to access HPET ! | |
541 | */ | |
542 | acpi_state_timer_broadcast(pr, cx, 1); | |
18eab855 VP |
543 | /* |
544 | * disable bus master | |
545 | * bm_check implies we need ARB_DIS | |
546 | * !bm_check implies we need cache flush | |
547 | * bm_control implies whether we can do ARB_DIS | |
548 | * | |
549 | * That leaves a case where bm_check is set and bm_control is | |
550 | * not set. In that case we cannot do much, we enter C3 | |
551 | * without doing anything. | |
552 | */ | |
553 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 554 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 555 | num_online_cpus()) { |
02df8b93 VP |
556 | /* |
557 | * All CPUs are trying to go to C3 | |
558 | * Disable bus master arbitration | |
559 | */ | |
d8c71b6d | 560 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 561 | } |
18eab855 | 562 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
563 | /* SMP with no shared cache... Invalidate cache */ |
564 | ACPI_FLUSH_CPU_CACHE(); | |
565 | } | |
4be44fcd | 566 | |
1da177e4 | 567 | /* Get start time (ticks) */ |
cee324b1 | 568 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 569 | /* Invoke C3 */ |
2aa44d05 IM |
570 | /* Tell the scheduler that we are going deep-idle: */ |
571 | sched_clock_idle_sleep_event(); | |
991528d7 | 572 | acpi_cstate_enter(cx); |
1da177e4 | 573 | /* Get end time (ticks) */ |
cee324b1 | 574 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 575 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
576 | /* Enable bus master arbitration */ |
577 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 578 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
579 | } |
580 | ||
0aa366f3 | 581 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) |
539eb11e | 582 | /* TSC halts in C3, so notify users */ |
5a90cf20 | 583 | mark_tsc_unstable("TSC halts in C3"); |
539eb11e | 584 | #endif |
2aa44d05 IM |
585 | /* Compute time (ticks) that we were actually asleep */ |
586 | sleep_ticks = ticks_elapsed(t1, t2); | |
587 | /* Tell the scheduler how much we idled: */ | |
588 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
589 | ||
1da177e4 LT |
590 | /* Re-enable interrupts */ |
591 | local_irq_enable(); | |
2aa44d05 IM |
592 | /* Do not account our idle-switching overhead: */ |
593 | sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; | |
594 | ||
495ab9c0 | 595 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 596 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
597 | break; |
598 | ||
599 | default: | |
600 | local_irq_enable(); | |
601 | return; | |
602 | } | |
a3c6598f DB |
603 | cx->usage++; |
604 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
605 | cx->time += sleep_ticks; | |
1da177e4 LT |
606 | |
607 | next_state = pr->power.state; | |
608 | ||
1e483969 DSL |
609 | #ifdef CONFIG_HOTPLUG_CPU |
610 | /* Don't do promotion/demotion */ | |
611 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 612 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
613 | next_state = cx; |
614 | goto end; | |
615 | } | |
616 | #endif | |
617 | ||
1da177e4 LT |
618 | /* |
619 | * Promotion? | |
620 | * ---------- | |
621 | * Track the number of longs (time asleep is greater than threshold) | |
622 | * and promote when the count threshold is reached. Note that bus | |
623 | * mastering activity may prevent promotions. | |
624 | * Do not promote above max_cstate. | |
625 | */ | |
626 | if (cx->promotion.state && | |
627 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e AV |
628 | if (sleep_ticks > cx->promotion.threshold.ticks && |
629 | cx->promotion.state->latency <= system_latency_constraint()) { | |
1da177e4 | 630 | cx->promotion.count++; |
4be44fcd LB |
631 | cx->demotion.count = 0; |
632 | if (cx->promotion.count >= | |
633 | cx->promotion.threshold.count) { | |
1da177e4 | 634 | if (pr->flags.bm_check) { |
4be44fcd LB |
635 | if (! |
636 | (pr->power.bm_activity & cx-> | |
637 | promotion.threshold.bm)) { | |
638 | next_state = | |
639 | cx->promotion.state; | |
1da177e4 LT |
640 | goto end; |
641 | } | |
4be44fcd | 642 | } else { |
1da177e4 LT |
643 | next_state = cx->promotion.state; |
644 | goto end; | |
645 | } | |
646 | } | |
647 | } | |
648 | } | |
649 | ||
650 | /* | |
651 | * Demotion? | |
652 | * --------- | |
653 | * Track the number of shorts (time asleep is less than time threshold) | |
654 | * and demote when the usage threshold is reached. | |
655 | */ | |
656 | if (cx->demotion.state) { | |
657 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
658 | cx->demotion.count++; | |
659 | cx->promotion.count = 0; | |
660 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
661 | next_state = cx->demotion.state; | |
662 | goto end; | |
663 | } | |
664 | } | |
665 | } | |
666 | ||
4be44fcd | 667 | end: |
1da177e4 LT |
668 | /* |
669 | * Demote if current state exceeds max_cstate | |
5c87579e | 670 | * or if the latency of the current state is unacceptable |
1da177e4 | 671 | */ |
5c87579e AV |
672 | if ((pr->power.state - pr->power.states) > max_cstate || |
673 | pr->power.state->latency > system_latency_constraint()) { | |
1da177e4 LT |
674 | if (cx->demotion.state) |
675 | next_state = cx->demotion.state; | |
676 | } | |
677 | ||
678 | /* | |
679 | * New Cx State? | |
680 | * ------------- | |
681 | * If we're going to start using a new Cx state we must clean up | |
682 | * from the previous and prepare to use the new. | |
683 | */ | |
684 | if (next_state != pr->power.state) | |
685 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
686 | } |
687 | ||
4be44fcd | 688 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
689 | { |
690 | unsigned int i; | |
691 | unsigned int state_is_set = 0; | |
692 | struct acpi_processor_cx *lower = NULL; | |
693 | struct acpi_processor_cx *higher = NULL; | |
694 | struct acpi_processor_cx *cx; | |
695 | ||
1da177e4 LT |
696 | |
697 | if (!pr) | |
d550d98d | 698 | return -EINVAL; |
1da177e4 LT |
699 | |
700 | /* | |
701 | * This function sets the default Cx state policy (OS idle handler). | |
702 | * Our scheme is to promote quickly to C2 but more conservatively | |
703 | * to C3. We're favoring C2 for its characteristics of low latency | |
704 | * (quick response), good power savings, and ability to allow bus | |
705 | * mastering activity. Note that the Cx state policy is completely | |
706 | * customizable and can be altered dynamically. | |
707 | */ | |
708 | ||
709 | /* startup state */ | |
4be44fcd | 710 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
711 | cx = &pr->power.states[i]; |
712 | if (!cx->valid) | |
713 | continue; | |
714 | ||
715 | if (!state_is_set) | |
716 | pr->power.state = cx; | |
717 | state_is_set++; | |
718 | break; | |
4be44fcd | 719 | } |
1da177e4 LT |
720 | |
721 | if (!state_is_set) | |
d550d98d | 722 | return -ENODEV; |
1da177e4 LT |
723 | |
724 | /* demotion */ | |
4be44fcd | 725 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
726 | cx = &pr->power.states[i]; |
727 | if (!cx->valid) | |
728 | continue; | |
729 | ||
730 | if (lower) { | |
731 | cx->demotion.state = lower; | |
732 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
733 | cx->demotion.threshold.count = 1; | |
734 | if (cx->type == ACPI_STATE_C3) | |
735 | cx->demotion.threshold.bm = bm_history; | |
736 | } | |
737 | ||
738 | lower = cx; | |
739 | } | |
740 | ||
741 | /* promotion */ | |
742 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
743 | cx = &pr->power.states[i]; | |
744 | if (!cx->valid) | |
745 | continue; | |
746 | ||
747 | if (higher) { | |
4be44fcd | 748 | cx->promotion.state = higher; |
1da177e4 LT |
749 | cx->promotion.threshold.ticks = cx->latency_ticks; |
750 | if (cx->type >= ACPI_STATE_C2) | |
751 | cx->promotion.threshold.count = 4; | |
752 | else | |
753 | cx->promotion.threshold.count = 10; | |
754 | if (higher->type == ACPI_STATE_C3) | |
755 | cx->promotion.threshold.bm = bm_history; | |
756 | } | |
757 | ||
758 | higher = cx; | |
759 | } | |
760 | ||
d550d98d | 761 | return 0; |
1da177e4 | 762 | } |
4f86d3a8 | 763 | #endif /* !CONFIG_CPU_IDLE */ |
1da177e4 | 764 | |
4be44fcd | 765 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 766 | { |
1da177e4 LT |
767 | |
768 | if (!pr) | |
d550d98d | 769 | return -EINVAL; |
1da177e4 LT |
770 | |
771 | if (!pr->pblk) | |
d550d98d | 772 | return -ENODEV; |
1da177e4 | 773 | |
1da177e4 | 774 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
775 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
776 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
777 | ||
4c033552 VP |
778 | #ifndef CONFIG_HOTPLUG_CPU |
779 | /* | |
780 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 781 | * an SMP system. |
4c033552 | 782 | */ |
ad71860a | 783 | if ((num_online_cpus() > 1) && |
cee324b1 | 784 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 785 | return -ENODEV; |
4c033552 VP |
786 | #endif |
787 | ||
1da177e4 LT |
788 | /* determine C2 and C3 address from pblk */ |
789 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
790 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
791 | ||
792 | /* determine latencies from FADT */ | |
cee324b1 AS |
793 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
794 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
795 | |
796 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
797 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
798 | pr->power.states[ACPI_STATE_C2].address, | |
799 | pr->power.states[ACPI_STATE_C3].address)); | |
800 | ||
d550d98d | 801 | return 0; |
1da177e4 LT |
802 | } |
803 | ||
991528d7 | 804 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 805 | { |
991528d7 VP |
806 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
807 | /* set the first C-State to C1 */ | |
808 | /* all processors need to support C1 */ | |
809 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
810 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
811 | } | |
812 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 813 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 814 | return 0; |
acf05f4b VP |
815 | } |
816 | ||
4be44fcd | 817 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 818 | { |
4be44fcd LB |
819 | acpi_status status = 0; |
820 | acpi_integer count; | |
cf824788 | 821 | int current_count; |
4be44fcd LB |
822 | int i; |
823 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
824 | union acpi_object *cst; | |
1da177e4 | 825 | |
1da177e4 | 826 | |
1da177e4 | 827 | if (nocst) |
d550d98d | 828 | return -ENODEV; |
1da177e4 | 829 | |
991528d7 | 830 | current_count = 0; |
1da177e4 LT |
831 | |
832 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
833 | if (ACPI_FAILURE(status)) { | |
834 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 835 | return -ENODEV; |
4be44fcd | 836 | } |
1da177e4 | 837 | |
50dd0969 | 838 | cst = buffer.pointer; |
1da177e4 LT |
839 | |
840 | /* There must be at least 2 elements */ | |
841 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 842 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
843 | status = -EFAULT; |
844 | goto end; | |
845 | } | |
846 | ||
847 | count = cst->package.elements[0].integer.value; | |
848 | ||
849 | /* Validate number of power states. */ | |
850 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 851 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
852 | status = -EFAULT; |
853 | goto end; | |
854 | } | |
855 | ||
1da177e4 LT |
856 | /* Tell driver that at least _CST is supported. */ |
857 | pr->flags.has_cst = 1; | |
858 | ||
859 | for (i = 1; i <= count; i++) { | |
860 | union acpi_object *element; | |
861 | union acpi_object *obj; | |
862 | struct acpi_power_register *reg; | |
863 | struct acpi_processor_cx cx; | |
864 | ||
865 | memset(&cx, 0, sizeof(cx)); | |
866 | ||
50dd0969 | 867 | element = &(cst->package.elements[i]); |
1da177e4 LT |
868 | if (element->type != ACPI_TYPE_PACKAGE) |
869 | continue; | |
870 | ||
871 | if (element->package.count != 4) | |
872 | continue; | |
873 | ||
50dd0969 | 874 | obj = &(element->package.elements[0]); |
1da177e4 LT |
875 | |
876 | if (obj->type != ACPI_TYPE_BUFFER) | |
877 | continue; | |
878 | ||
4be44fcd | 879 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
880 | |
881 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 882 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
883 | continue; |
884 | ||
1da177e4 | 885 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 886 | obj = &(element->package.elements[1]); |
1da177e4 LT |
887 | if (obj->type != ACPI_TYPE_INTEGER) |
888 | continue; | |
889 | ||
890 | cx.type = obj->integer.value; | |
991528d7 VP |
891 | /* |
892 | * Some buggy BIOSes won't list C1 in _CST - | |
893 | * Let acpi_processor_get_power_info_default() handle them later | |
894 | */ | |
895 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
896 | current_count++; | |
897 | ||
898 | cx.address = reg->address; | |
899 | cx.index = current_count + 1; | |
900 | ||
901 | cx.space_id = ACPI_CSTATE_SYSTEMIO; | |
902 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { | |
903 | if (acpi_processor_ffh_cstate_probe | |
904 | (pr->id, &cx, reg) == 0) { | |
905 | cx.space_id = ACPI_CSTATE_FFH; | |
906 | } else if (cx.type != ACPI_STATE_C1) { | |
907 | /* | |
908 | * C1 is a special case where FIXED_HARDWARE | |
909 | * can be handled in non-MWAIT way as well. | |
910 | * In that case, save this _CST entry info. | |
911 | * That is, we retain space_id of SYSTEM_IO for | |
912 | * halt based C1. | |
913 | * Otherwise, ignore this info and continue. | |
914 | */ | |
915 | continue; | |
916 | } | |
917 | } | |
1da177e4 | 918 | |
50dd0969 | 919 | obj = &(element->package.elements[2]); |
1da177e4 LT |
920 | if (obj->type != ACPI_TYPE_INTEGER) |
921 | continue; | |
922 | ||
923 | cx.latency = obj->integer.value; | |
924 | ||
50dd0969 | 925 | obj = &(element->package.elements[3]); |
1da177e4 LT |
926 | if (obj->type != ACPI_TYPE_INTEGER) |
927 | continue; | |
928 | ||
929 | cx.power = obj->integer.value; | |
930 | ||
cf824788 JM |
931 | current_count++; |
932 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
933 | ||
934 | /* | |
935 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
936 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
937 | */ | |
938 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
939 | printk(KERN_WARNING | |
940 | "Limiting number of power states to max (%d)\n", | |
941 | ACPI_PROCESSOR_MAX_POWER); | |
942 | printk(KERN_WARNING | |
943 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
944 | break; | |
945 | } | |
1da177e4 LT |
946 | } |
947 | ||
4be44fcd | 948 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 949 | current_count)); |
1da177e4 LT |
950 | |
951 | /* Validate number of power states discovered */ | |
cf824788 | 952 | if (current_count < 2) |
6d93c648 | 953 | status = -EFAULT; |
1da177e4 | 954 | |
4be44fcd | 955 | end: |
02438d87 | 956 | kfree(buffer.pointer); |
1da177e4 | 957 | |
d550d98d | 958 | return status; |
1da177e4 LT |
959 | } |
960 | ||
1da177e4 LT |
961 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
962 | { | |
1da177e4 LT |
963 | |
964 | if (!cx->address) | |
d550d98d | 965 | return; |
1da177e4 LT |
966 | |
967 | /* | |
968 | * C2 latency must be less than or equal to 100 | |
969 | * microseconds. | |
970 | */ | |
971 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
972 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 973 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 974 | return; |
1da177e4 LT |
975 | } |
976 | ||
1da177e4 LT |
977 | /* |
978 | * Otherwise we've met all of our C2 requirements. | |
979 | * Normalize the C2 latency to expidite policy | |
980 | */ | |
981 | cx->valid = 1; | |
4f86d3a8 LB |
982 | |
983 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 984 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
985 | #else |
986 | cx->latency_ticks = cx->latency; | |
987 | #endif | |
1da177e4 | 988 | |
d550d98d | 989 | return; |
1da177e4 LT |
990 | } |
991 | ||
4be44fcd LB |
992 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
993 | struct acpi_processor_cx *cx) | |
1da177e4 | 994 | { |
02df8b93 VP |
995 | static int bm_check_flag; |
996 | ||
1da177e4 LT |
997 | |
998 | if (!cx->address) | |
d550d98d | 999 | return; |
1da177e4 LT |
1000 | |
1001 | /* | |
1002 | * C3 latency must be less than or equal to 1000 | |
1003 | * microseconds. | |
1004 | */ | |
1005 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
1006 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1007 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1008 | return; |
1da177e4 LT |
1009 | } |
1010 | ||
1da177e4 LT |
1011 | /* |
1012 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
1013 | * DMA transfers are used by any ISA device to avoid livelock. | |
1014 | * Note that we could disable Type-F DMA (as recommended by | |
1015 | * the erratum), but this is known to disrupt certain ISA | |
1016 | * devices thus we take the conservative approach. | |
1017 | */ | |
1018 | else if (errata.piix4.fdma) { | |
1019 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1020 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 1021 | return; |
1da177e4 LT |
1022 | } |
1023 | ||
02df8b93 VP |
1024 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
1025 | if (!bm_check_flag) { | |
1026 | /* Determine whether bm_check is needed based on CPU */ | |
1027 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
1028 | bm_check_flag = pr->flags.bm_check; | |
1029 | } else { | |
1030 | pr->flags.bm_check = bm_check_flag; | |
1031 | } | |
1032 | ||
1033 | if (pr->flags.bm_check) { | |
02df8b93 | 1034 | if (!pr->flags.bm_control) { |
ed3110ef VP |
1035 | if (pr->flags.has_cst != 1) { |
1036 | /* bus mastering control is necessary */ | |
1037 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1038 | "C3 support requires BM control\n")); | |
1039 | return; | |
1040 | } else { | |
1041 | /* Here we enter C3 without bus mastering */ | |
1042 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1043 | "C3 support without BM control\n")); | |
1044 | } | |
02df8b93 VP |
1045 | } |
1046 | } else { | |
02df8b93 VP |
1047 | /* |
1048 | * WBINVD should be set in fadt, for C3 state to be | |
1049 | * supported on when bm_check is not required. | |
1050 | */ | |
cee324b1 | 1051 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 1052 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1053 | "Cache invalidation should work properly" |
1054 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1055 | return; |
02df8b93 | 1056 | } |
d8c71b6d | 1057 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1058 | } |
1059 | ||
1da177e4 LT |
1060 | /* |
1061 | * Otherwise we've met all of our C3 requirements. | |
1062 | * Normalize the C3 latency to expidite policy. Enable | |
1063 | * checking of bus mastering status (bm_check) so we can | |
1064 | * use this in our C3 policy | |
1065 | */ | |
1066 | cx->valid = 1; | |
4f86d3a8 LB |
1067 | |
1068 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1069 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1070 | #else |
1071 | cx->latency_ticks = cx->latency; | |
1072 | #endif | |
1da177e4 | 1073 | |
d550d98d | 1074 | return; |
1da177e4 LT |
1075 | } |
1076 | ||
1da177e4 LT |
1077 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1078 | { | |
1079 | unsigned int i; | |
1080 | unsigned int working = 0; | |
6eb0a0fd | 1081 | |
169a0abb | 1082 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1083 | |
4be44fcd | 1084 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1085 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1086 | ||
1087 | switch (cx->type) { | |
1088 | case ACPI_STATE_C1: | |
1089 | cx->valid = 1; | |
1090 | break; | |
1091 | ||
1092 | case ACPI_STATE_C2: | |
1093 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1094 | if (cx->valid) |
169a0abb | 1095 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1096 | break; |
1097 | ||
1098 | case ACPI_STATE_C3: | |
1099 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1100 | if (cx->valid) |
169a0abb | 1101 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1102 | break; |
1103 | } | |
1104 | ||
1105 | if (cx->valid) | |
1106 | working++; | |
1107 | } | |
bd663347 | 1108 | |
169a0abb | 1109 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1110 | |
1111 | return (working); | |
1112 | } | |
1113 | ||
4be44fcd | 1114 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1115 | { |
1116 | unsigned int i; | |
1117 | int result; | |
1118 | ||
1da177e4 LT |
1119 | |
1120 | /* NOTE: the idle thread may not be running while calling | |
1121 | * this function */ | |
1122 | ||
991528d7 VP |
1123 | /* Zero initialize all the C-states info. */ |
1124 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1125 | ||
1da177e4 | 1126 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1127 | if (result == -ENODEV) |
c5a114f1 | 1128 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1129 | |
991528d7 VP |
1130 | if (result) |
1131 | return result; | |
1132 | ||
1133 | acpi_processor_get_power_info_default(pr); | |
1134 | ||
cf824788 | 1135 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 1136 | |
4f86d3a8 | 1137 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1138 | /* |
1139 | * Set Default Policy | |
1140 | * ------------------ | |
1141 | * Now that we know which states are supported, set the default | |
1142 | * policy. Note that this policy can be changed dynamically | |
1143 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1144 | * not on AC). | |
1145 | */ | |
1146 | result = acpi_processor_set_power_policy(pr); | |
1147 | if (result) | |
d550d98d | 1148 | return result; |
4f86d3a8 | 1149 | #endif |
1da177e4 LT |
1150 | |
1151 | /* | |
1152 | * if one state of type C2 or C3 is available, mark this | |
1153 | * CPU as being "idle manageable" | |
1154 | */ | |
1155 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1156 | if (pr->power.states[i].valid) { |
1da177e4 | 1157 | pr->power.count = i; |
2203d6ed LT |
1158 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1159 | pr->flags.power = 1; | |
acf05f4b | 1160 | } |
1da177e4 LT |
1161 | } |
1162 | ||
d550d98d | 1163 | return 0; |
1da177e4 LT |
1164 | } |
1165 | ||
1da177e4 LT |
1166 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
1167 | { | |
50dd0969 | 1168 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1169 | unsigned int i; |
1da177e4 | 1170 | |
1da177e4 LT |
1171 | |
1172 | if (!pr) | |
1173 | goto end; | |
1174 | ||
1175 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1176 | "max_cstate: C%d\n" |
5c87579e AV |
1177 | "bus master activity: %08x\n" |
1178 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1179 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e AV |
1180 | max_cstate, (unsigned)pr->power.bm_activity, |
1181 | system_latency_constraint()); | |
1da177e4 LT |
1182 | |
1183 | seq_puts(seq, "states:\n"); | |
1184 | ||
1185 | for (i = 1; i <= pr->power.count; i++) { | |
1186 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1187 | (&pr->power.states[i] == |
1188 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1189 | |
1190 | if (!pr->power.states[i].valid) { | |
1191 | seq_puts(seq, "<not supported>\n"); | |
1192 | continue; | |
1193 | } | |
1194 | ||
1195 | switch (pr->power.states[i].type) { | |
1196 | case ACPI_STATE_C1: | |
1197 | seq_printf(seq, "type[C1] "); | |
1198 | break; | |
1199 | case ACPI_STATE_C2: | |
1200 | seq_printf(seq, "type[C2] "); | |
1201 | break; | |
1202 | case ACPI_STATE_C3: | |
1203 | seq_printf(seq, "type[C3] "); | |
1204 | break; | |
1205 | default: | |
1206 | seq_printf(seq, "type[--] "); | |
1207 | break; | |
1208 | } | |
1209 | ||
1210 | if (pr->power.states[i].promotion.state) | |
1211 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1212 | (pr->power.states[i].promotion.state - |
1213 | pr->power.states)); | |
1da177e4 LT |
1214 | else |
1215 | seq_puts(seq, "promotion[--] "); | |
1216 | ||
1217 | if (pr->power.states[i].demotion.state) | |
1218 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1219 | (pr->power.states[i].demotion.state - |
1220 | pr->power.states)); | |
1da177e4 LT |
1221 | else |
1222 | seq_puts(seq, "demotion[--] "); | |
1223 | ||
a3c6598f | 1224 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1225 | pr->power.states[i].latency, |
a3c6598f | 1226 | pr->power.states[i].usage, |
b0b7eaaf | 1227 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1228 | } |
1229 | ||
4be44fcd | 1230 | end: |
d550d98d | 1231 | return 0; |
1da177e4 LT |
1232 | } |
1233 | ||
1234 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1235 | { | |
1236 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1237 | PDE(inode)->data); |
1da177e4 LT |
1238 | } |
1239 | ||
d7508032 | 1240 | static const struct file_operations acpi_processor_power_fops = { |
4be44fcd LB |
1241 | .open = acpi_processor_power_open_fs, |
1242 | .read = seq_read, | |
1243 | .llseek = seq_lseek, | |
1244 | .release = single_release, | |
1da177e4 LT |
1245 | }; |
1246 | ||
4f86d3a8 LB |
1247 | #ifndef CONFIG_CPU_IDLE |
1248 | ||
1249 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1250 | { | |
1251 | int result = 0; | |
1252 | ||
1253 | ||
1254 | if (!pr) | |
1255 | return -EINVAL; | |
1256 | ||
1257 | if (nocst) { | |
1258 | return -ENODEV; | |
1259 | } | |
1260 | ||
1261 | if (!pr->flags.power_setup_done) | |
1262 | return -ENODEV; | |
1263 | ||
1264 | /* Fall back to the default idle loop */ | |
1265 | pm_idle = pm_idle_save; | |
1266 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ | |
1267 | ||
1268 | pr->flags.power = 0; | |
1269 | result = acpi_processor_get_power_info(pr); | |
1270 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1271 | pm_idle = acpi_processor_idle; | |
1272 | ||
1273 | return result; | |
1274 | } | |
1275 | ||
1fec74a9 | 1276 | #ifdef CONFIG_SMP |
5c87579e AV |
1277 | static void smp_callback(void *v) |
1278 | { | |
1279 | /* we already woke the CPU up, nothing more to do */ | |
1280 | } | |
1281 | ||
1282 | /* | |
1283 | * This function gets called when a part of the kernel has a new latency | |
1284 | * requirement. This means we need to get all processors out of their C-state, | |
1285 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1286 | * wakes them all right up. | |
1287 | */ | |
1288 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1289 | unsigned long l, void *v) | |
1290 | { | |
1291 | smp_call_function(smp_callback, NULL, 0, 1); | |
1292 | return NOTIFY_OK; | |
1293 | } | |
1294 | ||
1295 | static struct notifier_block acpi_processor_latency_notifier = { | |
1296 | .notifier_call = acpi_processor_latency_notify, | |
1297 | }; | |
4f86d3a8 LB |
1298 | |
1299 | #endif | |
1300 | ||
1301 | #else /* CONFIG_CPU_IDLE */ | |
1302 | ||
1303 | /** | |
1304 | * acpi_idle_bm_check - checks if bus master activity was detected | |
1305 | */ | |
1306 | static int acpi_idle_bm_check(void) | |
1307 | { | |
1308 | u32 bm_status = 0; | |
1309 | ||
1310 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | |
1311 | if (bm_status) | |
1312 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | |
1313 | /* | |
1314 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
1315 | * the true state of bus mastering activity; forcing us to | |
1316 | * manually check the BMIDEA bit of each IDE channel. | |
1317 | */ | |
1318 | else if (errata.piix4.bmisx) { | |
1319 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
1320 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
1321 | bm_status = 1; | |
1322 | } | |
1323 | return bm_status; | |
1324 | } | |
1325 | ||
1326 | /** | |
1327 | * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state | |
1328 | * @pr: the processor | |
1329 | * @target: the new target state | |
1330 | */ | |
1331 | static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, | |
1332 | struct acpi_processor_cx *target) | |
1333 | { | |
1334 | if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { | |
1335 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); | |
1336 | pr->flags.bm_rld_set = 0; | |
1337 | } | |
1338 | ||
1339 | if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { | |
1340 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); | |
1341 | pr->flags.bm_rld_set = 1; | |
1342 | } | |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
1347 | * @cx: cstate data | |
1348 | */ | |
1349 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
1350 | { | |
1351 | if (cx->space_id == ACPI_CSTATE_FFH) { | |
1352 | /* Call into architectural FFH based C-state */ | |
1353 | acpi_processor_ffh_cstate_enter(cx); | |
1354 | } else { | |
1355 | int unused; | |
1356 | /* IO port based C-state */ | |
1357 | inb(cx->address); | |
1358 | /* Dummy wait op - must do something useless after P_LVL2 read | |
1359 | because chipsets cannot guarantee that STPCLK# signal | |
1360 | gets asserted in time to freeze execution properly. */ | |
1361 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | /** | |
1366 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
1367 | * @dev: the target CPU | |
1368 | * @state: the state data | |
1369 | * | |
1370 | * This is equivalent to the HALT instruction. | |
1371 | */ | |
1372 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
1373 | struct cpuidle_state *state) | |
1374 | { | |
1375 | struct acpi_processor *pr; | |
1376 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1377 | pr = processors[smp_processor_id()]; | |
1378 | ||
1379 | if (unlikely(!pr)) | |
1380 | return 0; | |
1381 | ||
1382 | if (pr->flags.bm_check) | |
1383 | acpi_idle_update_bm_rld(pr, cx); | |
1384 | ||
ddc081a1 | 1385 | acpi_safe_halt(); |
4f86d3a8 LB |
1386 | |
1387 | cx->usage++; | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | /** | |
1393 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
1394 | * @dev: the target CPU | |
1395 | * @state: the state data | |
1396 | */ | |
1397 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
1398 | struct cpuidle_state *state) | |
1399 | { | |
1400 | struct acpi_processor *pr; | |
1401 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1402 | u32 t1, t2; | |
50629118 VP |
1403 | int sleep_ticks = 0; |
1404 | ||
4f86d3a8 LB |
1405 | pr = processors[smp_processor_id()]; |
1406 | ||
1407 | if (unlikely(!pr)) | |
1408 | return 0; | |
1409 | ||
e196441b LB |
1410 | if (acpi_idle_suspend) |
1411 | return(acpi_idle_enter_c1(dev, state)); | |
1412 | ||
4f86d3a8 LB |
1413 | local_irq_disable(); |
1414 | current_thread_info()->status &= ~TS_POLLING; | |
1415 | /* | |
1416 | * TS_POLLING-cleared state must be visible before we test | |
1417 | * NEED_RESCHED: | |
1418 | */ | |
1419 | smp_mb(); | |
1420 | ||
1421 | if (unlikely(need_resched())) { | |
1422 | current_thread_info()->status |= TS_POLLING; | |
1423 | local_irq_enable(); | |
1424 | return 0; | |
1425 | } | |
1426 | ||
bde6f5f5 | 1427 | acpi_unlazy_tlb(smp_processor_id()); |
e17bcb43 TG |
1428 | /* |
1429 | * Must be done before busmaster disable as we might need to | |
1430 | * access HPET ! | |
1431 | */ | |
1432 | acpi_state_timer_broadcast(pr, cx, 1); | |
1433 | ||
1434 | if (pr->flags.bm_check) | |
1435 | acpi_idle_update_bm_rld(pr, cx); | |
1436 | ||
4f86d3a8 LB |
1437 | if (cx->type == ACPI_STATE_C3) |
1438 | ACPI_FLUSH_CPU_CACHE(); | |
1439 | ||
1440 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
50629118 VP |
1441 | /* Tell the scheduler that we are going deep-idle: */ |
1442 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1443 | acpi_idle_do_entry(cx); |
1444 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1445 | ||
1446 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1447 | /* TSC could halt in idle, so notify users */ | |
1448 | mark_tsc_unstable("TSC halts in idle");; | |
1449 | #endif | |
50629118 VP |
1450 | sleep_ticks = ticks_elapsed(t1, t2); |
1451 | ||
1452 | /* Tell the scheduler how much we idled: */ | |
1453 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1454 | |
1455 | local_irq_enable(); | |
1456 | current_thread_info()->status |= TS_POLLING; | |
1457 | ||
1458 | cx->usage++; | |
1459 | ||
1460 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1461 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1462 | return ticks_elapsed_in_us(t1, t2); |
1463 | } | |
1464 | ||
1465 | static int c3_cpu_count; | |
1466 | static DEFINE_SPINLOCK(c3_lock); | |
1467 | ||
1468 | /** | |
1469 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
1470 | * @dev: the target CPU | |
1471 | * @state: the state data | |
1472 | * | |
1473 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
1474 | */ | |
1475 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
1476 | struct cpuidle_state *state) | |
1477 | { | |
1478 | struct acpi_processor *pr; | |
1479 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1480 | u32 t1, t2; | |
50629118 VP |
1481 | int sleep_ticks = 0; |
1482 | ||
4f86d3a8 LB |
1483 | pr = processors[smp_processor_id()]; |
1484 | ||
1485 | if (unlikely(!pr)) | |
1486 | return 0; | |
1487 | ||
e196441b LB |
1488 | if (acpi_idle_suspend) |
1489 | return(acpi_idle_enter_c1(dev, state)); | |
1490 | ||
ddc081a1 VP |
1491 | if (acpi_idle_bm_check()) { |
1492 | if (dev->safe_state) { | |
1493 | return dev->safe_state->enter(dev, dev->safe_state); | |
1494 | } else { | |
1495 | acpi_safe_halt(); | |
1496 | return 0; | |
1497 | } | |
1498 | } | |
1499 | ||
4f86d3a8 LB |
1500 | local_irq_disable(); |
1501 | current_thread_info()->status &= ~TS_POLLING; | |
1502 | /* | |
1503 | * TS_POLLING-cleared state must be visible before we test | |
1504 | * NEED_RESCHED: | |
1505 | */ | |
1506 | smp_mb(); | |
1507 | ||
1508 | if (unlikely(need_resched())) { | |
1509 | current_thread_info()->status |= TS_POLLING; | |
1510 | local_irq_enable(); | |
1511 | return 0; | |
1512 | } | |
1513 | ||
50629118 VP |
1514 | /* Tell the scheduler that we are going deep-idle: */ |
1515 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1516 | /* |
1517 | * Must be done before busmaster disable as we might need to | |
1518 | * access HPET ! | |
1519 | */ | |
1520 | acpi_state_timer_broadcast(pr, cx, 1); | |
1521 | ||
ddc081a1 | 1522 | acpi_idle_update_bm_rld(pr, cx); |
4f86d3a8 | 1523 | |
ddc081a1 VP |
1524 | /* |
1525 | * disable bus master | |
1526 | * bm_check implies we need ARB_DIS | |
1527 | * !bm_check implies we need cache flush | |
1528 | * bm_control implies whether we can do ARB_DIS | |
1529 | * | |
1530 | * That leaves a case where bm_check is set and bm_control is | |
1531 | * not set. In that case we cannot do much, we enter C3 | |
1532 | * without doing anything. | |
1533 | */ | |
1534 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1535 | spin_lock(&c3_lock); |
1536 | c3_cpu_count++; | |
1537 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1538 | if (c3_cpu_count == num_online_cpus()) | |
1539 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); | |
1540 | spin_unlock(&c3_lock); | |
ddc081a1 VP |
1541 | } else if (!pr->flags.bm_check) { |
1542 | ACPI_FLUSH_CPU_CACHE(); | |
1543 | } | |
4f86d3a8 | 1544 | |
ddc081a1 VP |
1545 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1546 | acpi_idle_do_entry(cx); | |
1547 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
4f86d3a8 | 1548 | |
ddc081a1 VP |
1549 | /* Re-enable bus master arbitration */ |
1550 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1551 | spin_lock(&c3_lock); |
ddc081a1 | 1552 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1553 | c3_cpu_count--; |
1554 | spin_unlock(&c3_lock); | |
1555 | } | |
1556 | ||
1557 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC) | |
1558 | /* TSC could halt in idle, so notify users */ | |
1559 | mark_tsc_unstable("TSC halts in idle"); | |
1560 | #endif | |
50629118 VP |
1561 | sleep_ticks = ticks_elapsed(t1, t2); |
1562 | /* Tell the scheduler how much we idled: */ | |
1563 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1564 | |
1565 | local_irq_enable(); | |
1566 | current_thread_info()->status |= TS_POLLING; | |
1567 | ||
1568 | cx->usage++; | |
1569 | ||
1570 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1571 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1572 | return ticks_elapsed_in_us(t1, t2); |
1573 | } | |
1574 | ||
1575 | struct cpuidle_driver acpi_idle_driver = { | |
1576 | .name = "acpi_idle", | |
1577 | .owner = THIS_MODULE, | |
1578 | }; | |
1579 | ||
1580 | /** | |
1581 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1582 | * @pr: the ACPI processor | |
1583 | */ | |
1584 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1585 | { | |
1586 | int i, count = 0; | |
1587 | struct acpi_processor_cx *cx; | |
1588 | struct cpuidle_state *state; | |
1589 | struct cpuidle_device *dev = &pr->power.dev; | |
1590 | ||
1591 | if (!pr->flags.power_setup_done) | |
1592 | return -EINVAL; | |
1593 | ||
1594 | if (pr->flags.power == 0) { | |
1595 | return -EINVAL; | |
1596 | } | |
1597 | ||
1598 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { | |
1599 | cx = &pr->power.states[i]; | |
1600 | state = &dev->states[count]; | |
1601 | ||
1602 | if (!cx->valid) | |
1603 | continue; | |
1604 | ||
1605 | #ifdef CONFIG_HOTPLUG_CPU | |
1606 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1607 | !pr->flags.has_cst && | |
1608 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1609 | continue; | |
1fec74a9 | 1610 | #endif |
4f86d3a8 LB |
1611 | cpuidle_set_statedata(state, cx); |
1612 | ||
1613 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
1614 | state->exit_latency = cx->latency; | |
1615 | state->target_residency = cx->latency * 6; | |
1616 | state->power_usage = cx->power; | |
1617 | ||
1618 | state->flags = 0; | |
1619 | switch (cx->type) { | |
1620 | case ACPI_STATE_C1: | |
1621 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
1622 | state->enter = acpi_idle_enter_c1; | |
ddc081a1 | 1623 | dev->safe_state = state; |
4f86d3a8 LB |
1624 | break; |
1625 | ||
1626 | case ACPI_STATE_C2: | |
1627 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1628 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1629 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1630 | dev->safe_state = state; |
4f86d3a8 LB |
1631 | break; |
1632 | ||
1633 | case ACPI_STATE_C3: | |
1634 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1635 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1636 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1637 | state->enter = pr->flags.bm_check ? | |
1638 | acpi_idle_enter_bm : | |
1639 | acpi_idle_enter_simple; | |
1640 | break; | |
1641 | } | |
1642 | ||
1643 | count++; | |
1644 | } | |
1645 | ||
1646 | dev->state_count = count; | |
1647 | ||
1648 | if (!count) | |
1649 | return -EINVAL; | |
1650 | ||
4f86d3a8 LB |
1651 | return 0; |
1652 | } | |
1653 | ||
1654 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1655 | { | |
1656 | int ret; | |
1657 | ||
1658 | if (!pr) | |
1659 | return -EINVAL; | |
1660 | ||
1661 | if (nocst) { | |
1662 | return -ENODEV; | |
1663 | } | |
1664 | ||
1665 | if (!pr->flags.power_setup_done) | |
1666 | return -ENODEV; | |
1667 | ||
1668 | cpuidle_pause_and_lock(); | |
1669 | cpuidle_disable_device(&pr->power.dev); | |
1670 | acpi_processor_get_power_info(pr); | |
1671 | acpi_processor_setup_cpuidle(pr); | |
1672 | ret = cpuidle_enable_device(&pr->power.dev); | |
1673 | cpuidle_resume_and_unlock(); | |
1674 | ||
1675 | return ret; | |
1676 | } | |
1677 | ||
1678 | #endif /* CONFIG_CPU_IDLE */ | |
5c87579e | 1679 | |
7af8b660 | 1680 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1681 | struct acpi_device *device) |
1da177e4 | 1682 | { |
4be44fcd | 1683 | acpi_status status = 0; |
b6835052 | 1684 | static int first_run; |
4be44fcd | 1685 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1686 | unsigned int i; |
1687 | ||
1da177e4 LT |
1688 | |
1689 | if (!first_run) { | |
1690 | dmi_check_system(processor_power_dmi_table); | |
c1c30634 | 1691 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1692 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1693 | printk(KERN_NOTICE |
1694 | "ACPI: processor limited to max C-state %d\n", | |
1695 | max_cstate); | |
1da177e4 | 1696 | first_run++; |
4f86d3a8 | 1697 | #if !defined (CONFIG_CPU_IDLE) && defined (CONFIG_SMP) |
5c87579e | 1698 | register_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1699 | #endif |
1da177e4 LT |
1700 | } |
1701 | ||
02df8b93 | 1702 | if (!pr) |
d550d98d | 1703 | return -EINVAL; |
02df8b93 | 1704 | |
cee324b1 | 1705 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1706 | status = |
cee324b1 | 1707 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1708 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1709 | ACPI_EXCEPTION((AE_INFO, status, |
1710 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1711 | } |
1712 | } | |
1713 | ||
1714 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1715 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1716 | |
1717 | /* | |
1718 | * Install the idle handler if processor power management is supported. | |
1719 | * Note that we use previously set idle handler will be used on | |
1720 | * platforms that only support C1. | |
1721 | */ | |
1722 | if ((pr->flags.power) && (!boot_option_idle_override)) { | |
4f86d3a8 LB |
1723 | #ifdef CONFIG_CPU_IDLE |
1724 | acpi_processor_setup_cpuidle(pr); | |
1725 | pr->power.dev.cpu = pr->id; | |
1726 | if (cpuidle_register_device(&pr->power.dev)) | |
1727 | return -EIO; | |
1728 | #endif | |
1729 | ||
1da177e4 LT |
1730 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1731 | for (i = 1; i <= pr->power.count; i++) | |
1732 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1733 | printk(" C%d[C%d]", i, |
1734 | pr->power.states[i].type); | |
1da177e4 LT |
1735 | printk(")\n"); |
1736 | ||
4f86d3a8 | 1737 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1738 | if (pr->id == 0) { |
1739 | pm_idle_save = pm_idle; | |
1740 | pm_idle = acpi_processor_idle; | |
1741 | } | |
4f86d3a8 | 1742 | #endif |
1da177e4 LT |
1743 | } |
1744 | ||
1745 | /* 'power' [R] */ | |
1746 | entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER, | |
4be44fcd | 1747 | S_IRUGO, acpi_device_dir(device)); |
1da177e4 | 1748 | if (!entry) |
a6fc6720 | 1749 | return -EIO; |
1da177e4 LT |
1750 | else { |
1751 | entry->proc_fops = &acpi_processor_power_fops; | |
1752 | entry->data = acpi_driver_data(device); | |
1753 | entry->owner = THIS_MODULE; | |
1754 | } | |
1755 | ||
d550d98d | 1756 | return 0; |
1da177e4 LT |
1757 | } |
1758 | ||
4be44fcd LB |
1759 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1760 | struct acpi_device *device) | |
1da177e4 | 1761 | { |
4f86d3a8 LB |
1762 | #ifdef CONFIG_CPU_IDLE |
1763 | if ((pr->flags.power) && (!boot_option_idle_override)) | |
1764 | cpuidle_unregister_device(&pr->power.dev); | |
1765 | #endif | |
1da177e4 LT |
1766 | pr->flags.power_setup_done = 0; |
1767 | ||
1768 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1769 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1770 | acpi_device_dir(device)); | |
1da177e4 | 1771 | |
4f86d3a8 LB |
1772 | #ifndef CONFIG_CPU_IDLE |
1773 | ||
1da177e4 LT |
1774 | /* Unregister the idle handler when processor #0 is removed. */ |
1775 | if (pr->id == 0) { | |
1776 | pm_idle = pm_idle_save; | |
1777 | ||
1778 | /* | |
1779 | * We are about to unload the current idle thread pm callback | |
1780 | * (pm_idle), Wait for all processors to update cached/local | |
1781 | * copies of pm_idle before proceeding. | |
1782 | */ | |
1783 | cpu_idle_wait(); | |
1fec74a9 | 1784 | #ifdef CONFIG_SMP |
5c87579e | 1785 | unregister_latency_notifier(&acpi_processor_latency_notifier); |
1fec74a9 | 1786 | #endif |
1da177e4 | 1787 | } |
4f86d3a8 | 1788 | #endif |
1da177e4 | 1789 | |
d550d98d | 1790 | return 0; |
1da177e4 | 1791 | } |