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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
1da177e4 | 44 | #include <scsi/scsi_host.h> |
193515d5 | 45 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 46 | #include <linux/libata.h> |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "ahci" | |
cd70c266 | 49 | #define DRV_VERSION "2.3" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | AHCI_PCI_BAR = 5, | |
648a88be | 54 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
56 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
be5d8218 | 57 | AHCI_USE_CLUSTERING = 1, |
12fad3f9 | 58 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 59 | AHCI_CMD_SZ = 32, |
12fad3f9 | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 61 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
67 | AHCI_RX_FIS_SZ, |
68 | AHCI_IRQ_ON_SG = (1 << 31), | |
69 | AHCI_CMD_ATAPI = (1 << 5), | |
70 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
72 | AHCI_CMD_RESET = (1 << 8), |
73 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
74 | |
75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
648a88be TH |
80 | board_ahci_pi = 1, |
81 | board_ahci_vt8251 = 2, | |
82 | board_ahci_ign_iferr = 3, | |
55a61604 | 83 | board_ahci_sb600 = 4, |
cd70c266 | 84 | board_ahci_mv = 5, |
1da177e4 LT |
85 | |
86 | /* global controller registers */ | |
87 | HOST_CAP = 0x00, /* host capabilities */ | |
88 | HOST_CTL = 0x04, /* global host control */ | |
89 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
90 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
91 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
92 | ||
93 | /* HOST_CTL bits */ | |
94 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
95 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
96 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
97 | ||
98 | /* HOST_CAP bits */ | |
0be0aa98 | 99 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 100 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 101 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 102 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 103 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 104 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
105 | |
106 | /* registers for each SATA port */ | |
107 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
108 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
109 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
110 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
111 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
112 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
113 | PORT_CMD = 0x18, /* port command */ | |
114 | PORT_TFDATA = 0x20, /* taskfile data */ | |
115 | PORT_SIG = 0x24, /* device TF signature */ | |
116 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
117 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
118 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
119 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
120 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 121 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
122 | |
123 | /* PORT_IRQ_{STAT,MASK} bits */ | |
124 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
125 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
126 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
127 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
128 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
129 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
130 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
131 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
132 | ||
133 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
134 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
135 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
136 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
137 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
138 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
139 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
140 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
141 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
142 | ||
78cd52d0 TH |
143 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
144 | PORT_IRQ_IF_ERR | | |
145 | PORT_IRQ_CONNECT | | |
4296971d | 146 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
147 | PORT_IRQ_UNK_FIS, |
148 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
149 | PORT_IRQ_TF_ERR | | |
150 | PORT_IRQ_HBUS_DATA_ERR, | |
151 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
152 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
153 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
154 | |
155 | /* PORT_CMD bits */ | |
02eaa666 | 156 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
157 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
158 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
159 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 160 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
161 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
162 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
163 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
164 | ||
0be0aa98 | 165 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
166 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
167 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
168 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 169 | |
bf2af2a2 | 170 | /* ap->flags bits */ |
4aeb0e32 TH |
171 | AHCI_FLAG_NO_NCQ = (1 << 24), |
172 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | |
648a88be | 173 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
55a61604 | 174 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
c7a42156 | 175 | AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */ |
cd70c266 JG |
176 | AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */ |
177 | AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */ | |
1188c0d8 TH |
178 | |
179 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
180 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
3cadbcc0 TH |
181 | ATA_FLAG_SKIP_D2H_BSY | |
182 | ATA_FLAG_ACPI_SATA, | |
1da177e4 LT |
183 | }; |
184 | ||
185 | struct ahci_cmd_hdr { | |
186 | u32 opts; | |
187 | u32 status; | |
188 | u32 tbl_addr; | |
189 | u32 tbl_addr_hi; | |
190 | u32 reserved[4]; | |
191 | }; | |
192 | ||
193 | struct ahci_sg { | |
194 | u32 addr; | |
195 | u32 addr_hi; | |
196 | u32 reserved; | |
197 | u32 flags_size; | |
198 | }; | |
199 | ||
200 | struct ahci_host_priv { | |
d447df14 TH |
201 | u32 cap; /* cap to use */ |
202 | u32 port_map; /* port map to use */ | |
203 | u32 saved_cap; /* saved initial cap */ | |
204 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
205 | }; |
206 | ||
207 | struct ahci_port_priv { | |
208 | struct ahci_cmd_hdr *cmd_slot; | |
209 | dma_addr_t cmd_slot_dma; | |
210 | void *cmd_tbl; | |
211 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
212 | void *rx_fis; |
213 | dma_addr_t rx_fis_dma; | |
0291f95f | 214 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
215 | unsigned int ncq_saw_d2h:1; |
216 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 217 | unsigned int ncq_saw_sdb:1; |
1da177e4 LT |
218 | }; |
219 | ||
da3dbb17 TH |
220 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
221 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 222 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 223 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 224 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
225 | static int ahci_port_start(struct ata_port *ap); |
226 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
227 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
228 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
229 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
230 | static void ahci_freeze(struct ata_port *ap); |
231 | static void ahci_thaw(struct ata_port *ap); | |
232 | static void ahci_error_handler(struct ata_port *ap); | |
ad616ffb | 233 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 234 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
df69c9c5 | 235 | static int ahci_port_resume(struct ata_port *ap); |
dab632e8 JG |
236 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
237 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
238 | u32 opts); | |
438ac6d5 | 239 | #ifdef CONFIG_PM |
c1332875 | 240 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
241 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
242 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 243 | #endif |
1da177e4 | 244 | |
193515d5 | 245 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
246 | .module = THIS_MODULE, |
247 | .name = DRV_NAME, | |
248 | .ioctl = ata_scsi_ioctl, | |
249 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
250 | .change_queue_depth = ata_scsi_change_queue_depth, |
251 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
252 | .this_id = ATA_SHT_THIS_ID, |
253 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
254 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
255 | .emulated = ATA_SHT_EMULATED, | |
256 | .use_clustering = AHCI_USE_CLUSTERING, | |
257 | .proc_name = DRV_NAME, | |
258 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
259 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 260 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 261 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
262 | }; |
263 | ||
057ace5e | 264 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
265 | .port_disable = ata_port_disable, |
266 | ||
267 | .check_status = ahci_check_status, | |
268 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
269 | .dev_select = ata_noop_dev_select, |
270 | ||
271 | .tf_read = ahci_tf_read, | |
272 | ||
1da177e4 LT |
273 | .qc_prep = ahci_qc_prep, |
274 | .qc_issue = ahci_qc_issue, | |
275 | ||
1da177e4 | 276 | .irq_clear = ahci_irq_clear, |
246ce3b6 AI |
277 | .irq_on = ata_dummy_irq_on, |
278 | .irq_ack = ata_dummy_irq_ack, | |
1da177e4 LT |
279 | |
280 | .scr_read = ahci_scr_read, | |
281 | .scr_write = ahci_scr_write, | |
282 | ||
78cd52d0 TH |
283 | .freeze = ahci_freeze, |
284 | .thaw = ahci_thaw, | |
285 | ||
286 | .error_handler = ahci_error_handler, | |
287 | .post_internal_cmd = ahci_post_internal_cmd, | |
288 | ||
438ac6d5 | 289 | #ifdef CONFIG_PM |
c1332875 TH |
290 | .port_suspend = ahci_port_suspend, |
291 | .port_resume = ahci_port_resume, | |
438ac6d5 | 292 | #endif |
c1332875 | 293 | |
1da177e4 LT |
294 | .port_start = ahci_port_start, |
295 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
296 | }; |
297 | ||
ad616ffb TH |
298 | static const struct ata_port_operations ahci_vt8251_ops = { |
299 | .port_disable = ata_port_disable, | |
300 | ||
301 | .check_status = ahci_check_status, | |
302 | .check_altstatus = ahci_check_status, | |
303 | .dev_select = ata_noop_dev_select, | |
304 | ||
305 | .tf_read = ahci_tf_read, | |
306 | ||
307 | .qc_prep = ahci_qc_prep, | |
308 | .qc_issue = ahci_qc_issue, | |
309 | ||
ad616ffb | 310 | .irq_clear = ahci_irq_clear, |
246ce3b6 AI |
311 | .irq_on = ata_dummy_irq_on, |
312 | .irq_ack = ata_dummy_irq_ack, | |
ad616ffb TH |
313 | |
314 | .scr_read = ahci_scr_read, | |
315 | .scr_write = ahci_scr_write, | |
316 | ||
317 | .freeze = ahci_freeze, | |
318 | .thaw = ahci_thaw, | |
319 | ||
320 | .error_handler = ahci_vt8251_error_handler, | |
321 | .post_internal_cmd = ahci_post_internal_cmd, | |
322 | ||
438ac6d5 | 323 | #ifdef CONFIG_PM |
ad616ffb TH |
324 | .port_suspend = ahci_port_suspend, |
325 | .port_resume = ahci_port_resume, | |
438ac6d5 | 326 | #endif |
ad616ffb TH |
327 | |
328 | .port_start = ahci_port_start, | |
329 | .port_stop = ahci_port_stop, | |
330 | }; | |
331 | ||
98ac62de | 332 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
333 | /* board_ahci */ |
334 | { | |
1188c0d8 | 335 | .flags = AHCI_FLAG_COMMON, |
7da79312 | 336 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 337 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
338 | .port_ops = &ahci_ops, |
339 | }, | |
648a88be TH |
340 | /* board_ahci_pi */ |
341 | { | |
1188c0d8 | 342 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
648a88be | 343 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 344 | .udma_mask = ATA_UDMA6, |
648a88be TH |
345 | .port_ops = &ahci_ops, |
346 | }, | |
bf2af2a2 BJ |
347 | /* board_ahci_vt8251 */ |
348 | { | |
1188c0d8 TH |
349 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
350 | AHCI_FLAG_NO_NCQ, | |
bf2af2a2 | 351 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 352 | .udma_mask = ATA_UDMA6, |
ad616ffb | 353 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 354 | }, |
41669553 TH |
355 | /* board_ahci_ign_iferr */ |
356 | { | |
1188c0d8 | 357 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
41669553 | 358 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 359 | .udma_mask = ATA_UDMA6, |
41669553 TH |
360 | .port_ops = &ahci_ops, |
361 | }, | |
55a61604 CH |
362 | /* board_ahci_sb600 */ |
363 | { | |
1188c0d8 | 364 | .flags = AHCI_FLAG_COMMON | |
c7a42156 TH |
365 | AHCI_FLAG_IGN_SERR_INTERNAL | |
366 | AHCI_FLAG_32BIT_ONLY, | |
55a61604 | 367 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 368 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
369 | .port_ops = &ahci_ops, |
370 | }, | |
cd70c266 JG |
371 | /* board_ahci_mv */ |
372 | { | |
373 | .sht = &ahci_sht, | |
374 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
375 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
376 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI | | |
377 | AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI | | |
378 | AHCI_FLAG_MV_PATA, | |
379 | .pio_mask = 0x1f, /* pio0-4 */ | |
380 | .udma_mask = ATA_UDMA6, | |
381 | .port_ops = &ahci_ops, | |
382 | }, | |
1da177e4 LT |
383 | }; |
384 | ||
3b7d697d | 385 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 386 | /* Intel */ |
54bb3a94 JG |
387 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
388 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
389 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
390 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
391 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 392 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
393 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
394 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
395 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
396 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
648a88be TH |
397 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
398 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ | |
399 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ | |
400 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ | |
401 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ | |
402 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ | |
403 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ | |
404 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ | |
405 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ | |
406 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ | |
407 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ | |
408 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ | |
409 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ | |
8af12cdb | 410 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
648a88be TH |
411 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
412 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ | |
413 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ | |
fe7fa31a | 414 | |
e34bb370 TH |
415 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
416 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
417 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
418 | |
419 | /* ATI */ | |
c65ec1c2 | 420 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
badc2341 | 421 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 IDE */ |
422 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700 AHCI */ | |
423 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700 nraid5 */ | |
424 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700 raid5 */ | |
fe7fa31a JG |
425 | |
426 | /* VIA */ | |
54bb3a94 | 427 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 428 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
429 | |
430 | /* NVIDIA */ | |
54bb3a94 JG |
431 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
432 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
433 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
435 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
436 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
443 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
444 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
451 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
452 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
463 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
fe7fa31a | 475 | |
95916edd | 476 | /* SiS */ |
54bb3a94 JG |
477 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
478 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
479 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 480 | |
cd70c266 JG |
481 | /* Marvell */ |
482 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
483 | ||
415ae2b5 JG |
484 | /* Generic, PCI class code for AHCI */ |
485 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 486 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 487 | |
1da177e4 LT |
488 | { } /* terminate list */ |
489 | }; | |
490 | ||
491 | ||
492 | static struct pci_driver ahci_pci_driver = { | |
493 | .name = DRV_NAME, | |
494 | .id_table = ahci_pci_tbl, | |
495 | .probe = ahci_init_one, | |
24dc5f33 | 496 | .remove = ata_pci_remove_one, |
438ac6d5 | 497 | #ifdef CONFIG_PM |
c1332875 TH |
498 | .suspend = ahci_pci_device_suspend, |
499 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 500 | #endif |
1da177e4 LT |
501 | }; |
502 | ||
503 | ||
98fa4b60 TH |
504 | static inline int ahci_nr_ports(u32 cap) |
505 | { | |
506 | return (cap & 0x1f) + 1; | |
507 | } | |
508 | ||
dab632e8 JG |
509 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
510 | unsigned int port_no) | |
1da177e4 | 511 | { |
dab632e8 | 512 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 513 | |
dab632e8 JG |
514 | return mmio + 0x100 + (port_no * 0x80); |
515 | } | |
516 | ||
517 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
518 | { | |
519 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
520 | } |
521 | ||
d447df14 TH |
522 | /** |
523 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 TH |
524 | * @pdev: target PCI device |
525 | * @pi: associated ATA port info | |
526 | * @hpriv: host private area to store config values | |
d447df14 TH |
527 | * |
528 | * Some registers containing configuration info might be setup by | |
529 | * BIOS and might be cleared on reset. This function saves the | |
530 | * initial values of those registers into @hpriv such that they | |
531 | * can be restored after controller reset. | |
532 | * | |
533 | * If inconsistent, config values are fixed up by this function. | |
534 | * | |
535 | * LOCKING: | |
536 | * None. | |
537 | */ | |
4447d351 TH |
538 | static void ahci_save_initial_config(struct pci_dev *pdev, |
539 | const struct ata_port_info *pi, | |
540 | struct ahci_host_priv *hpriv) | |
d447df14 | 541 | { |
4447d351 | 542 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 543 | u32 cap, port_map; |
17199b18 | 544 | int i; |
d447df14 TH |
545 | |
546 | /* Values prefixed with saved_ are written back to host after | |
547 | * reset. Values without are used for driver operation. | |
548 | */ | |
549 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
550 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
551 | ||
274c1fde | 552 | /* some chips have errata preventing 64bit use */ |
c7a42156 TH |
553 | if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) { |
554 | dev_printk(KERN_INFO, &pdev->dev, | |
555 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
556 | cap &= ~HOST_CAP_64; | |
557 | } | |
558 | ||
274c1fde TH |
559 | if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) { |
560 | dev_printk(KERN_INFO, &pdev->dev, | |
561 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
562 | cap &= ~HOST_CAP_NCQ; | |
563 | } | |
564 | ||
d447df14 TH |
565 | /* fixup zero port_map */ |
566 | if (!port_map) { | |
a3d2cc5e | 567 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
4447d351 | 568 | dev_printk(KERN_WARNING, &pdev->dev, |
d447df14 TH |
569 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); |
570 | ||
571 | /* write the fixed up value to the PI register */ | |
572 | hpriv->saved_port_map = port_map; | |
573 | } | |
574 | ||
cd70c266 JG |
575 | /* |
576 | * Temporary Marvell 6145 hack: PATA port presence | |
577 | * is asserted through the standard AHCI port | |
578 | * presence register, as bit 4 (counting from 0) | |
579 | */ | |
580 | if (pi->flags & AHCI_FLAG_MV_PATA) { | |
581 | dev_printk(KERN_ERR, &pdev->dev, | |
582 | "MV_AHCI HACK: port_map %x -> %x\n", | |
583 | hpriv->port_map, | |
584 | hpriv->port_map & 0xf); | |
585 | ||
586 | port_map &= 0xf; | |
587 | } | |
588 | ||
17199b18 | 589 | /* cross check port_map and cap.n_ports */ |
4447d351 | 590 | if (pi->flags & AHCI_FLAG_HONOR_PI) { |
17199b18 TH |
591 | u32 tmp_port_map = port_map; |
592 | int n_ports = ahci_nr_ports(cap); | |
593 | ||
594 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
595 | if (tmp_port_map & (1 << i)) { | |
596 | n_ports--; | |
597 | tmp_port_map &= ~(1 << i); | |
598 | } | |
599 | } | |
600 | ||
601 | /* Whine if inconsistent. No need to update cap. | |
602 | * port_map is used to determine number of ports. | |
603 | */ | |
604 | if (n_ports || tmp_port_map) | |
4447d351 | 605 | dev_printk(KERN_WARNING, &pdev->dev, |
17199b18 TH |
606 | "nr_ports (%u) and implemented port map " |
607 | "(0x%x) don't match\n", | |
608 | ahci_nr_ports(cap), port_map); | |
609 | } else { | |
610 | /* fabricate port_map from cap.nr_ports */ | |
611 | port_map = (1 << ahci_nr_ports(cap)) - 1; | |
612 | } | |
613 | ||
d447df14 TH |
614 | /* record values to use during operation */ |
615 | hpriv->cap = cap; | |
616 | hpriv->port_map = port_map; | |
617 | } | |
618 | ||
619 | /** | |
620 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 621 | * @host: target ATA host |
d447df14 TH |
622 | * |
623 | * Restore initial config stored by ahci_save_initial_config(). | |
624 | * | |
625 | * LOCKING: | |
626 | * None. | |
627 | */ | |
4447d351 | 628 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 629 | { |
4447d351 TH |
630 | struct ahci_host_priv *hpriv = host->private_data; |
631 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
632 | ||
d447df14 TH |
633 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
634 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
635 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
636 | } | |
637 | ||
203ef6c4 | 638 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 639 | { |
203ef6c4 TH |
640 | static const int offset[] = { |
641 | [SCR_STATUS] = PORT_SCR_STAT, | |
642 | [SCR_CONTROL] = PORT_SCR_CTL, | |
643 | [SCR_ERROR] = PORT_SCR_ERR, | |
644 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
645 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
646 | }; | |
647 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 648 | |
203ef6c4 TH |
649 | if (sc_reg < ARRAY_SIZE(offset) && |
650 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
651 | return offset[sc_reg]; | |
da3dbb17 | 652 | return 0; |
1da177e4 LT |
653 | } |
654 | ||
203ef6c4 | 655 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 656 | { |
203ef6c4 TH |
657 | void __iomem *port_mmio = ahci_port_base(ap); |
658 | int offset = ahci_scr_offset(ap, sc_reg); | |
659 | ||
660 | if (offset) { | |
661 | *val = readl(port_mmio + offset); | |
662 | return 0; | |
1da177e4 | 663 | } |
203ef6c4 TH |
664 | return -EINVAL; |
665 | } | |
1da177e4 | 666 | |
203ef6c4 TH |
667 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
668 | { | |
669 | void __iomem *port_mmio = ahci_port_base(ap); | |
670 | int offset = ahci_scr_offset(ap, sc_reg); | |
671 | ||
672 | if (offset) { | |
673 | writel(val, port_mmio + offset); | |
674 | return 0; | |
675 | } | |
676 | return -EINVAL; | |
1da177e4 LT |
677 | } |
678 | ||
4447d351 | 679 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 680 | { |
4447d351 | 681 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
682 | u32 tmp; |
683 | ||
d8fcd116 | 684 | /* start DMA */ |
9f592056 | 685 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
686 | tmp |= PORT_CMD_START; |
687 | writel(tmp, port_mmio + PORT_CMD); | |
688 | readl(port_mmio + PORT_CMD); /* flush */ | |
689 | } | |
690 | ||
4447d351 | 691 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 692 | { |
4447d351 | 693 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
694 | u32 tmp; |
695 | ||
696 | tmp = readl(port_mmio + PORT_CMD); | |
697 | ||
d8fcd116 | 698 | /* check if the HBA is idle */ |
254950cd TH |
699 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
700 | return 0; | |
701 | ||
d8fcd116 | 702 | /* setting HBA to idle */ |
254950cd TH |
703 | tmp &= ~PORT_CMD_START; |
704 | writel(tmp, port_mmio + PORT_CMD); | |
705 | ||
d8fcd116 | 706 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
707 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
708 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 709 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
710 | return -EIO; |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
4447d351 | 715 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 716 | { |
4447d351 TH |
717 | void __iomem *port_mmio = ahci_port_base(ap); |
718 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
719 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
720 | u32 tmp; |
721 | ||
722 | /* set FIS registers */ | |
4447d351 TH |
723 | if (hpriv->cap & HOST_CAP_64) |
724 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
725 | port_mmio + PORT_LST_ADDR_HI); | |
726 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 727 | |
4447d351 TH |
728 | if (hpriv->cap & HOST_CAP_64) |
729 | writel((pp->rx_fis_dma >> 16) >> 16, | |
730 | port_mmio + PORT_FIS_ADDR_HI); | |
731 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
732 | |
733 | /* enable FIS reception */ | |
734 | tmp = readl(port_mmio + PORT_CMD); | |
735 | tmp |= PORT_CMD_FIS_RX; | |
736 | writel(tmp, port_mmio + PORT_CMD); | |
737 | ||
738 | /* flush */ | |
739 | readl(port_mmio + PORT_CMD); | |
740 | } | |
741 | ||
4447d351 | 742 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 743 | { |
4447d351 | 744 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
745 | u32 tmp; |
746 | ||
747 | /* disable FIS reception */ | |
748 | tmp = readl(port_mmio + PORT_CMD); | |
749 | tmp &= ~PORT_CMD_FIS_RX; | |
750 | writel(tmp, port_mmio + PORT_CMD); | |
751 | ||
752 | /* wait for completion, spec says 500ms, give it 1000 */ | |
753 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
754 | PORT_CMD_FIS_ON, 10, 1000); | |
755 | if (tmp & PORT_CMD_FIS_ON) | |
756 | return -EBUSY; | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
4447d351 | 761 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 762 | { |
4447d351 TH |
763 | struct ahci_host_priv *hpriv = ap->host->private_data; |
764 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
765 | u32 cmd; |
766 | ||
767 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
768 | ||
769 | /* spin up device */ | |
4447d351 | 770 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
771 | cmd |= PORT_CMD_SPIN_UP; |
772 | writel(cmd, port_mmio + PORT_CMD); | |
773 | } | |
774 | ||
775 | /* wake up link */ | |
776 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
777 | } | |
778 | ||
438ac6d5 | 779 | #ifdef CONFIG_PM |
4447d351 | 780 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 781 | { |
4447d351 TH |
782 | struct ahci_host_priv *hpriv = ap->host->private_data; |
783 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
784 | u32 cmd, scontrol; |
785 | ||
4447d351 | 786 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 787 | return; |
0be0aa98 | 788 | |
07c53dac TH |
789 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
790 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
791 | scontrol &= ~0xf; | |
792 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 793 | |
07c53dac TH |
794 | /* then set PxCMD.SUD to 0 */ |
795 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
796 | cmd &= ~PORT_CMD_SPIN_UP; | |
797 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 798 | } |
438ac6d5 | 799 | #endif |
0be0aa98 | 800 | |
df69c9c5 | 801 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 802 | { |
0be0aa98 | 803 | /* enable FIS reception */ |
4447d351 | 804 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
805 | |
806 | /* enable DMA */ | |
4447d351 | 807 | ahci_start_engine(ap); |
0be0aa98 TH |
808 | } |
809 | ||
4447d351 | 810 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
811 | { |
812 | int rc; | |
813 | ||
814 | /* disable DMA */ | |
4447d351 | 815 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
816 | if (rc) { |
817 | *emsg = "failed to stop engine"; | |
818 | return rc; | |
819 | } | |
820 | ||
821 | /* disable FIS reception */ | |
4447d351 | 822 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
823 | if (rc) { |
824 | *emsg = "failed stop FIS RX"; | |
825 | return rc; | |
826 | } | |
827 | ||
0be0aa98 TH |
828 | return 0; |
829 | } | |
830 | ||
4447d351 | 831 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 832 | { |
4447d351 TH |
833 | struct pci_dev *pdev = to_pci_dev(host->dev); |
834 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
d447df14 | 835 | u32 tmp; |
d91542c1 TH |
836 | |
837 | /* global controller reset */ | |
838 | tmp = readl(mmio + HOST_CTL); | |
839 | if ((tmp & HOST_RESET) == 0) { | |
840 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
841 | readl(mmio + HOST_CTL); /* flush */ | |
842 | } | |
843 | ||
844 | /* reset must complete within 1 second, or | |
845 | * the hardware should be considered fried. | |
846 | */ | |
847 | ssleep(1); | |
848 | ||
849 | tmp = readl(mmio + HOST_CTL); | |
850 | if (tmp & HOST_RESET) { | |
4447d351 | 851 | dev_printk(KERN_ERR, host->dev, |
d91542c1 TH |
852 | "controller reset failed (0x%x)\n", tmp); |
853 | return -EIO; | |
854 | } | |
855 | ||
98fa4b60 | 856 | /* turn on AHCI mode */ |
d91542c1 TH |
857 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
858 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 | 859 | |
d447df14 | 860 | /* some registers might be cleared on reset. restore initial values */ |
4447d351 | 861 | ahci_restore_initial_config(host); |
d91542c1 TH |
862 | |
863 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
864 | u16 tmp16; | |
865 | ||
866 | /* configure PCS */ | |
867 | pci_read_config_word(pdev, 0x92, &tmp16); | |
868 | tmp16 |= 0xf; | |
869 | pci_write_config_word(pdev, 0x92, tmp16); | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
2bcd866b JG |
875 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
876 | int port_no, void __iomem *mmio, | |
877 | void __iomem *port_mmio) | |
878 | { | |
879 | const char *emsg = NULL; | |
880 | int rc; | |
881 | u32 tmp; | |
882 | ||
883 | /* make sure port is not active */ | |
884 | rc = ahci_deinit_port(ap, &emsg); | |
885 | if (rc) | |
886 | dev_printk(KERN_WARNING, &pdev->dev, | |
887 | "%s (%d)\n", emsg, rc); | |
888 | ||
889 | /* clear SError */ | |
890 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
891 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
892 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
893 | ||
894 | /* clear port IRQ */ | |
895 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
896 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
897 | if (tmp) | |
898 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
899 | ||
900 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
901 | } | |
902 | ||
4447d351 | 903 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 904 | { |
4447d351 TH |
905 | struct pci_dev *pdev = to_pci_dev(host->dev); |
906 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 907 | int i; |
cd70c266 | 908 | void __iomem *port_mmio; |
d91542c1 TH |
909 | u32 tmp; |
910 | ||
cd70c266 JG |
911 | if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) { |
912 | port_mmio = __ahci_port_base(host, 4); | |
913 | ||
914 | writel(0, port_mmio + PORT_IRQ_MASK); | |
915 | ||
916 | /* clear port IRQ */ | |
917 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
918 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
919 | if (tmp) | |
920 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
921 | } | |
922 | ||
4447d351 TH |
923 | for (i = 0; i < host->n_ports; i++) { |
924 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 925 | |
cd70c266 | 926 | port_mmio = ahci_port_base(ap); |
4447d351 | 927 | if (ata_port_is_dummy(ap)) |
d91542c1 | 928 | continue; |
d91542c1 | 929 | |
2bcd866b | 930 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
931 | } |
932 | ||
933 | tmp = readl(mmio + HOST_CTL); | |
934 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
935 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
936 | tmp = readl(mmio + HOST_CTL); | |
937 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
938 | } | |
939 | ||
422b7595 | 940 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 941 | { |
4447d351 | 942 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 943 | struct ata_taskfile tf; |
422b7595 TH |
944 | u32 tmp; |
945 | ||
946 | tmp = readl(port_mmio + PORT_SIG); | |
947 | tf.lbah = (tmp >> 24) & 0xff; | |
948 | tf.lbam = (tmp >> 16) & 0xff; | |
949 | tf.lbal = (tmp >> 8) & 0xff; | |
950 | tf.nsect = (tmp) & 0xff; | |
951 | ||
952 | return ata_dev_classify(&tf); | |
953 | } | |
954 | ||
12fad3f9 TH |
955 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
956 | u32 opts) | |
cc9278ed | 957 | { |
12fad3f9 TH |
958 | dma_addr_t cmd_tbl_dma; |
959 | ||
960 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
961 | ||
962 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
963 | pp->cmd_slot[tag].status = 0; | |
964 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
965 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
966 | } |
967 | ||
d2e75dff | 968 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 969 | { |
0d5ff566 | 970 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 971 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 | 972 | u32 tmp; |
d2e75dff | 973 | int busy, rc; |
bf2af2a2 | 974 | |
d2e75dff TH |
975 | /* do we need to kick the port? */ |
976 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); | |
977 | if (!busy && !force_restart) | |
978 | return 0; | |
979 | ||
980 | /* stop engine */ | |
981 | rc = ahci_stop_engine(ap); | |
982 | if (rc) | |
983 | goto out_restart; | |
984 | ||
985 | /* need to do CLO? */ | |
986 | if (!busy) { | |
987 | rc = 0; | |
988 | goto out_restart; | |
989 | } | |
990 | ||
991 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
992 | rc = -EOPNOTSUPP; | |
993 | goto out_restart; | |
994 | } | |
bf2af2a2 | 995 | |
d2e75dff | 996 | /* perform CLO */ |
bf2af2a2 BJ |
997 | tmp = readl(port_mmio + PORT_CMD); |
998 | tmp |= PORT_CMD_CLO; | |
999 | writel(tmp, port_mmio + PORT_CMD); | |
1000 | ||
d2e75dff | 1001 | rc = 0; |
bf2af2a2 BJ |
1002 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1003 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1004 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1005 | rc = -EIO; |
bf2af2a2 | 1006 | |
d2e75dff TH |
1007 | /* restart engine */ |
1008 | out_restart: | |
1009 | ahci_start_engine(ap); | |
1010 | return rc; | |
bf2af2a2 BJ |
1011 | } |
1012 | ||
91c4a2e0 TH |
1013 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1014 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1015 | unsigned long timeout_msec) | |
bf2af2a2 | 1016 | { |
91c4a2e0 | 1017 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1018 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1019 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1020 | u8 *fis = pp->cmd_tbl; |
1021 | u32 tmp; | |
1022 | ||
1023 | /* prep the command */ | |
1024 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1025 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1026 | ||
1027 | /* issue & wait */ | |
1028 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1029 | ||
1030 | if (timeout_msec) { | |
1031 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1032 | 1, timeout_msec); | |
1033 | if (tmp & 0x1) { | |
1034 | ahci_kick_engine(ap, 1); | |
1035 | return -EBUSY; | |
1036 | } | |
1037 | } else | |
1038 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
a9cf5e85 TH |
1043 | static int ahci_do_softreset(struct ata_port *ap, unsigned int *class, |
1044 | int pmp, unsigned long deadline) | |
91c4a2e0 | 1045 | { |
4658f79b | 1046 | const char *reason = NULL; |
2cbb79eb | 1047 | unsigned long now, msecs; |
4658f79b | 1048 | struct ata_taskfile tf; |
4658f79b TH |
1049 | int rc; |
1050 | ||
1051 | DPRINTK("ENTER\n"); | |
1052 | ||
81952c54 | 1053 | if (ata_port_offline(ap)) { |
c2a65852 TH |
1054 | DPRINTK("PHY reports no device\n"); |
1055 | *class = ATA_DEV_NONE; | |
1056 | return 0; | |
1057 | } | |
1058 | ||
4658f79b | 1059 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff TH |
1060 | rc = ahci_kick_engine(ap, 1); |
1061 | if (rc) | |
1062 | ata_port_printk(ap, KERN_WARNING, | |
1063 | "failed to reset engine (errno=%d)", rc); | |
4658f79b | 1064 | |
3373efd8 | 1065 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
1066 | |
1067 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1068 | msecs = 0; |
1069 | now = jiffies; | |
1070 | if (time_after(now, deadline)) | |
1071 | msecs = jiffies_to_msecs(deadline - now); | |
1072 | ||
4658f79b | 1073 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1074 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1075 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1076 | rc = -EIO; |
1077 | reason = "1st FIS failed"; | |
1078 | goto fail; | |
1079 | } | |
1080 | ||
1081 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1082 | msleep(1); | |
1083 | ||
1084 | /* issue the second D2H Register FIS */ | |
4658f79b | 1085 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1086 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b TH |
1087 | |
1088 | /* spec mandates ">= 2ms" before checking status. | |
1089 | * We wait 150ms, because that was the magic delay used for | |
1090 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
1091 | * between when the ATA command register is written, and then | |
1092 | * status is checked. Because waiting for "a while" before | |
1093 | * checking status is fine, post SRST, we perform this magic | |
1094 | * delay here as well. | |
1095 | */ | |
1096 | msleep(150); | |
1097 | ||
9b89391c TH |
1098 | rc = ata_wait_ready(ap, deadline); |
1099 | /* link occupied, -ENODEV too is an error */ | |
1100 | if (rc) { | |
1101 | reason = "device not ready"; | |
1102 | goto fail; | |
4658f79b | 1103 | } |
9b89391c | 1104 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1105 | |
1106 | DPRINTK("EXIT, class=%u\n", *class); | |
1107 | return 0; | |
1108 | ||
4658f79b | 1109 | fail: |
f15a1daf | 1110 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1111 | return rc; |
1112 | } | |
1113 | ||
a9cf5e85 TH |
1114 | static int ahci_softreset(struct ata_port *ap, unsigned int *class, |
1115 | unsigned long deadline) | |
1116 | { | |
1117 | return ahci_do_softreset(ap, class, 0, deadline); | |
1118 | } | |
1119 | ||
d4b2bab4 TH |
1120 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class, |
1121 | unsigned long deadline) | |
422b7595 | 1122 | { |
4296971d TH |
1123 | struct ahci_port_priv *pp = ap->private_data; |
1124 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1125 | struct ata_taskfile tf; | |
4bd00f6a TH |
1126 | int rc; |
1127 | ||
1128 | DPRINTK("ENTER\n"); | |
1da177e4 | 1129 | |
4447d351 | 1130 | ahci_stop_engine(ap); |
4296971d TH |
1131 | |
1132 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1133 | ata_tf_init(ap->device, &tf); | |
dfd7a3db | 1134 | tf.command = 0x80; |
9977126c | 1135 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1136 | |
d4b2bab4 | 1137 | rc = sata_std_hardreset(ap, class, deadline); |
4296971d | 1138 | |
4447d351 | 1139 | ahci_start_engine(ap); |
1da177e4 | 1140 | |
81952c54 | 1141 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
1142 | *class = ahci_dev_classify(ap); |
1143 | if (*class == ATA_DEV_UNKNOWN) | |
1144 | *class = ATA_DEV_NONE; | |
1da177e4 | 1145 | |
4bd00f6a TH |
1146 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1147 | return rc; | |
1148 | } | |
1149 | ||
d4b2bab4 TH |
1150 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class, |
1151 | unsigned long deadline) | |
ad616ffb | 1152 | { |
da3dbb17 | 1153 | u32 serror; |
ad616ffb TH |
1154 | int rc; |
1155 | ||
1156 | DPRINTK("ENTER\n"); | |
1157 | ||
4447d351 | 1158 | ahci_stop_engine(ap); |
ad616ffb | 1159 | |
d4b2bab4 TH |
1160 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context), |
1161 | deadline); | |
ad616ffb TH |
1162 | |
1163 | /* vt8251 needs SError cleared for the port to operate */ | |
da3dbb17 TH |
1164 | ahci_scr_read(ap, SCR_ERROR, &serror); |
1165 | ahci_scr_write(ap, SCR_ERROR, serror); | |
ad616ffb | 1166 | |
4447d351 | 1167 | ahci_start_engine(ap); |
ad616ffb TH |
1168 | |
1169 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1170 | ||
1171 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1172 | * request follow-up softreset. | |
1173 | */ | |
1174 | return rc ?: -EAGAIN; | |
1175 | } | |
1176 | ||
4bd00f6a TH |
1177 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
1178 | { | |
4447d351 | 1179 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1180 | u32 new_tmp, tmp; |
1181 | ||
1182 | ata_std_postreset(ap, class); | |
02eaa666 JG |
1183 | |
1184 | /* Make sure port's ATAPI bit is set appropriately */ | |
1185 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1186 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1187 | new_tmp |= PORT_CMD_ATAPI; |
1188 | else | |
1189 | new_tmp &= ~PORT_CMD_ATAPI; | |
1190 | if (new_tmp != tmp) { | |
1191 | writel(new_tmp, port_mmio + PORT_CMD); | |
1192 | readl(port_mmio + PORT_CMD); /* flush */ | |
1193 | } | |
1da177e4 LT |
1194 | } |
1195 | ||
1196 | static u8 ahci_check_status(struct ata_port *ap) | |
1197 | { | |
0d5ff566 | 1198 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1199 | |
1200 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1201 | } | |
1202 | ||
1da177e4 LT |
1203 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1204 | { | |
1205 | struct ahci_port_priv *pp = ap->private_data; | |
1206 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1207 | ||
1208 | ata_tf_from_fis(d2h_fis, tf); | |
1209 | } | |
1210 | ||
12fad3f9 | 1211 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1212 | { |
cedc9a47 JG |
1213 | struct scatterlist *sg; |
1214 | struct ahci_sg *ahci_sg; | |
828d09de | 1215 | unsigned int n_sg = 0; |
1da177e4 LT |
1216 | |
1217 | VPRINTK("ENTER\n"); | |
1218 | ||
1219 | /* | |
1220 | * Next, the S/G list. | |
1221 | */ | |
12fad3f9 | 1222 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
1223 | ata_for_each_sg(sg, qc) { |
1224 | dma_addr_t addr = sg_dma_address(sg); | |
1225 | u32 sg_len = sg_dma_len(sg); | |
1226 | ||
1227 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1228 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1229 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1230 | |
cedc9a47 | 1231 | ahci_sg++; |
828d09de | 1232 | n_sg++; |
1da177e4 | 1233 | } |
828d09de JG |
1234 | |
1235 | return n_sg; | |
1da177e4 LT |
1236 | } |
1237 | ||
1238 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1239 | { | |
a0ea7328 JG |
1240 | struct ata_port *ap = qc->ap; |
1241 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1242 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1243 | void *cmd_tbl; |
1da177e4 LT |
1244 | u32 opts; |
1245 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1246 | unsigned int n_elem; |
1da177e4 | 1247 | |
1da177e4 LT |
1248 | /* |
1249 | * Fill in command table information. First, the header, | |
1250 | * a SATA Register - Host to Device command FIS. | |
1251 | */ | |
12fad3f9 TH |
1252 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1253 | ||
9977126c | 1254 | ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl); |
cc9278ed | 1255 | if (is_atapi) { |
12fad3f9 TH |
1256 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1257 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1258 | } |
1da177e4 | 1259 | |
cc9278ed TH |
1260 | n_elem = 0; |
1261 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1262 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1263 | |
cc9278ed TH |
1264 | /* |
1265 | * Fill in command slot information. | |
1266 | */ | |
1267 | opts = cmd_fis_len | n_elem << 16; | |
1268 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1269 | opts |= AHCI_CMD_WRITE; | |
1270 | if (is_atapi) | |
4b10e559 | 1271 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1272 | |
12fad3f9 | 1273 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1274 | } |
1275 | ||
78cd52d0 | 1276 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1277 | { |
78cd52d0 TH |
1278 | struct ahci_port_priv *pp = ap->private_data; |
1279 | struct ata_eh_info *ehi = &ap->eh_info; | |
1280 | unsigned int err_mask = 0, action = 0; | |
1281 | struct ata_queued_cmd *qc; | |
1282 | u32 serror; | |
1da177e4 | 1283 | |
78cd52d0 | 1284 | ata_ehi_clear_desc(ehi); |
1da177e4 | 1285 | |
78cd52d0 | 1286 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1287 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1288 | ahci_scr_write(ap, SCR_ERROR, serror); |
1da177e4 | 1289 | |
78cd52d0 TH |
1290 | /* analyze @irq_stat */ |
1291 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
1292 | ||
41669553 TH |
1293 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
1294 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) | |
1295 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1296 | ||
55a61604 | 1297 | if (irq_stat & PORT_IRQ_TF_ERR) { |
78cd52d0 | 1298 | err_mask |= AC_ERR_DEV; |
55a61604 CH |
1299 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
1300 | serror &= ~SERR_INTERNAL; | |
1301 | } | |
78cd52d0 TH |
1302 | |
1303 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1304 | err_mask |= AC_ERR_HOST_BUS; | |
1305 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
1306 | } |
1307 | ||
78cd52d0 TH |
1308 | if (irq_stat & PORT_IRQ_IF_ERR) { |
1309 | err_mask |= AC_ERR_ATA_BUS; | |
1310 | action |= ATA_EH_SOFTRESET; | |
b64bbc39 | 1311 | ata_ehi_push_desc(ehi, "interface fatal error"); |
78cd52d0 | 1312 | } |
1da177e4 | 1313 | |
78cd52d0 | 1314 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 1315 | ata_ehi_hotplugged(ehi); |
b64bbc39 | 1316 | ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ? |
78cd52d0 TH |
1317 | "connection status changed" : "PHY RDY changed"); |
1318 | } | |
1319 | ||
1320 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1321 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 1322 | |
78cd52d0 TH |
1323 | err_mask |= AC_ERR_HSM; |
1324 | action |= ATA_EH_SOFTRESET; | |
b64bbc39 | 1325 | ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x", |
78cd52d0 TH |
1326 | unk[0], unk[1], unk[2], unk[3]); |
1327 | } | |
1da177e4 | 1328 | |
78cd52d0 TH |
1329 | /* okay, let's hand over to EH */ |
1330 | ehi->serror |= serror; | |
1331 | ehi->action |= action; | |
b8f6153e | 1332 | |
1da177e4 | 1333 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1334 | if (qc) |
1335 | qc->err_mask |= err_mask; | |
1336 | else | |
1337 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1338 | |
78cd52d0 TH |
1339 | if (irq_stat & PORT_IRQ_FREEZE) |
1340 | ata_port_freeze(ap); | |
1341 | else | |
1342 | ata_port_abort(ap); | |
1da177e4 LT |
1343 | } |
1344 | ||
df69c9c5 | 1345 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1346 | { |
4447d351 | 1347 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
12fad3f9 | 1348 | struct ata_eh_info *ehi = &ap->eh_info; |
0291f95f | 1349 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1350 | u32 status, qc_active; |
0291f95f | 1351 | int rc, known_irq = 0; |
1da177e4 LT |
1352 | |
1353 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1354 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1355 | ||
78cd52d0 TH |
1356 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1357 | ahci_error_intr(ap, status); | |
1358 | return; | |
1da177e4 LT |
1359 | } |
1360 | ||
12fad3f9 TH |
1361 | if (ap->sactive) |
1362 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1363 | else | |
1364 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1365 | ||
1366 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1367 | if (rc > 0) | |
1368 | return; | |
1369 | if (rc < 0) { | |
1370 | ehi->err_mask |= AC_ERR_HSM; | |
1371 | ehi->action |= ATA_EH_SOFTRESET; | |
1372 | ata_port_freeze(ap); | |
1373 | return; | |
1da177e4 LT |
1374 | } |
1375 | ||
2a3917a8 TH |
1376 | /* hmmm... a spurious interupt */ |
1377 | ||
0291f95f TH |
1378 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1379 | * implementation for non-NCQ commands. | |
1380 | */ | |
1381 | if (!ap->sactive) | |
12fad3f9 TH |
1382 | return; |
1383 | ||
0291f95f TH |
1384 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1385 | if (!pp->ncq_saw_d2h) | |
1386 | ata_port_printk(ap, KERN_INFO, | |
1387 | "D2H reg with I during NCQ, " | |
1388 | "this message won't be printed again\n"); | |
1389 | pp->ncq_saw_d2h = 1; | |
1390 | known_irq = 1; | |
1391 | } | |
1392 | ||
1393 | if (status & PORT_IRQ_DMAS_FIS) { | |
1394 | if (!pp->ncq_saw_dmas) | |
1395 | ata_port_printk(ap, KERN_INFO, | |
1396 | "DMAS FIS during NCQ, " | |
1397 | "this message won't be printed again\n"); | |
1398 | pp->ncq_saw_dmas = 1; | |
1399 | known_irq = 1; | |
1400 | } | |
1401 | ||
a2bbd0c9 | 1402 | if (status & PORT_IRQ_SDB_FIS) { |
04d4f7a1 | 1403 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
0291f95f | 1404 | |
afb2d552 TH |
1405 | if (le32_to_cpu(f[1])) { |
1406 | /* SDB FIS containing spurious completions | |
1407 | * might be dangerous, whine and fail commands | |
1408 | * with HSM violation. EH will turn off NCQ | |
1409 | * after several such failures. | |
1410 | */ | |
1411 | ata_ehi_push_desc(ehi, | |
1412 | "spurious completions during NCQ " | |
1413 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", | |
1414 | readl(port_mmio + PORT_CMD_ISSUE), | |
1415 | readl(port_mmio + PORT_SCR_ACT), | |
1416 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1417 | ehi->err_mask |= AC_ERR_HSM; | |
1418 | ehi->action |= ATA_EH_SOFTRESET; | |
1419 | ata_port_freeze(ap); | |
1420 | } else { | |
1421 | if (!pp->ncq_saw_sdb) | |
1422 | ata_port_printk(ap, KERN_INFO, | |
1423 | "spurious SDB FIS %08x:%08x during NCQ, " | |
1424 | "this message won't be printed again\n", | |
1425 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); | |
1426 | pp->ncq_saw_sdb = 1; | |
1427 | } | |
0291f95f TH |
1428 | known_irq = 1; |
1429 | } | |
2a3917a8 | 1430 | |
0291f95f | 1431 | if (!known_irq) |
78cd52d0 | 1432 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1433 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
12fad3f9 | 1434 | status, ap->active_tag, ap->sactive); |
1da177e4 LT |
1435 | } |
1436 | ||
1437 | static void ahci_irq_clear(struct ata_port *ap) | |
1438 | { | |
1439 | /* TODO */ | |
1440 | } | |
1441 | ||
7d12e780 | 1442 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1443 | { |
cca3974e | 1444 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1445 | struct ahci_host_priv *hpriv; |
1446 | unsigned int i, handled = 0; | |
ea6ba10b | 1447 | void __iomem *mmio; |
1da177e4 LT |
1448 | u32 irq_stat, irq_ack = 0; |
1449 | ||
1450 | VPRINTK("ENTER\n"); | |
1451 | ||
cca3974e | 1452 | hpriv = host->private_data; |
0d5ff566 | 1453 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1454 | |
1455 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1456 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1457 | irq_stat &= hpriv->port_map; | |
1458 | if (!irq_stat) | |
1459 | return IRQ_NONE; | |
1460 | ||
cca3974e | 1461 | spin_lock(&host->lock); |
1da177e4 | 1462 | |
cca3974e | 1463 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1464 | struct ata_port *ap; |
1da177e4 | 1465 | |
67846b30 JG |
1466 | if (!(irq_stat & (1 << i))) |
1467 | continue; | |
1468 | ||
cca3974e | 1469 | ap = host->ports[i]; |
67846b30 | 1470 | if (ap) { |
df69c9c5 | 1471 | ahci_port_intr(ap); |
67846b30 JG |
1472 | VPRINTK("port %u\n", i); |
1473 | } else { | |
1474 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1475 | if (ata_ratelimit()) |
cca3974e | 1476 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1477 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1478 | } |
67846b30 JG |
1479 | |
1480 | irq_ack |= (1 << i); | |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | if (irq_ack) { | |
1484 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1485 | handled = 1; | |
1486 | } | |
1487 | ||
cca3974e | 1488 | spin_unlock(&host->lock); |
1da177e4 LT |
1489 | |
1490 | VPRINTK("EXIT\n"); | |
1491 | ||
1492 | return IRQ_RETVAL(handled); | |
1493 | } | |
1494 | ||
9a3d9eb0 | 1495 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1496 | { |
1497 | struct ata_port *ap = qc->ap; | |
4447d351 | 1498 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1499 | |
12fad3f9 TH |
1500 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1501 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1502 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1503 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
78cd52d0 TH |
1508 | static void ahci_freeze(struct ata_port *ap) |
1509 | { | |
4447d351 | 1510 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1511 | |
1512 | /* turn IRQ off */ | |
1513 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1514 | } | |
1515 | ||
1516 | static void ahci_thaw(struct ata_port *ap) | |
1517 | { | |
0d5ff566 | 1518 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1519 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1520 | u32 tmp; |
1521 | ||
1522 | /* clear IRQ */ | |
1523 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1524 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1525 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 TH |
1526 | |
1527 | /* turn IRQ back on */ | |
1528 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1529 | } | |
1530 | ||
1531 | static void ahci_error_handler(struct ata_port *ap) | |
1532 | { | |
b51e9e5d | 1533 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1534 | /* restart engine */ |
4447d351 TH |
1535 | ahci_stop_engine(ap); |
1536 | ahci_start_engine(ap); | |
78cd52d0 TH |
1537 | } |
1538 | ||
1539 | /* perform recovery */ | |
4aeb0e32 | 1540 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1541 | ahci_postreset); |
78cd52d0 TH |
1542 | } |
1543 | ||
ad616ffb TH |
1544 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1545 | { | |
ad616ffb TH |
1546 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
1547 | /* restart engine */ | |
4447d351 TH |
1548 | ahci_stop_engine(ap); |
1549 | ahci_start_engine(ap); | |
ad616ffb TH |
1550 | } |
1551 | ||
1552 | /* perform recovery */ | |
1553 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1554 | ahci_postreset); | |
1555 | } | |
1556 | ||
78cd52d0 TH |
1557 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1558 | { | |
1559 | struct ata_port *ap = qc->ap; | |
1560 | ||
d2e75dff TH |
1561 | /* make DMA engine forget about the failed command */ |
1562 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1563 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1564 | } |
1565 | ||
028a2596 AD |
1566 | static int ahci_port_resume(struct ata_port *ap) |
1567 | { | |
1568 | ahci_power_up(ap); | |
1569 | ahci_start_port(ap); | |
1570 | ||
1571 | return 0; | |
1572 | } | |
1573 | ||
438ac6d5 | 1574 | #ifdef CONFIG_PM |
c1332875 TH |
1575 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1576 | { | |
c1332875 TH |
1577 | const char *emsg = NULL; |
1578 | int rc; | |
1579 | ||
4447d351 | 1580 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1581 | if (rc == 0) |
4447d351 | 1582 | ahci_power_down(ap); |
8e16f941 | 1583 | else { |
c1332875 | 1584 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1585 | ahci_start_port(ap); |
c1332875 TH |
1586 | } |
1587 | ||
1588 | return rc; | |
1589 | } | |
1590 | ||
c1332875 TH |
1591 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1592 | { | |
cca3974e | 1593 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1594 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1595 | u32 ctl; |
1596 | ||
1597 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1598 | /* AHCI spec rev1.1 section 8.3.3: | |
1599 | * Software must disable interrupts prior to requesting a | |
1600 | * transition of the HBA to D3 state. | |
1601 | */ | |
1602 | ctl = readl(mmio + HOST_CTL); | |
1603 | ctl &= ~HOST_IRQ_EN; | |
1604 | writel(ctl, mmio + HOST_CTL); | |
1605 | readl(mmio + HOST_CTL); /* flush */ | |
1606 | } | |
1607 | ||
1608 | return ata_pci_device_suspend(pdev, mesg); | |
1609 | } | |
1610 | ||
1611 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1612 | { | |
cca3974e | 1613 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1614 | int rc; |
1615 | ||
553c4aa6 TH |
1616 | rc = ata_pci_device_do_resume(pdev); |
1617 | if (rc) | |
1618 | return rc; | |
c1332875 TH |
1619 | |
1620 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1621 | rc = ahci_reset_controller(host); |
c1332875 TH |
1622 | if (rc) |
1623 | return rc; | |
1624 | ||
4447d351 | 1625 | ahci_init_controller(host); |
c1332875 TH |
1626 | } |
1627 | ||
cca3974e | 1628 | ata_host_resume(host); |
c1332875 TH |
1629 | |
1630 | return 0; | |
1631 | } | |
438ac6d5 | 1632 | #endif |
c1332875 | 1633 | |
254950cd TH |
1634 | static int ahci_port_start(struct ata_port *ap) |
1635 | { | |
cca3974e | 1636 | struct device *dev = ap->host->dev; |
254950cd | 1637 | struct ahci_port_priv *pp; |
254950cd TH |
1638 | void *mem; |
1639 | dma_addr_t mem_dma; | |
1640 | int rc; | |
1641 | ||
24dc5f33 | 1642 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1643 | if (!pp) |
1644 | return -ENOMEM; | |
254950cd TH |
1645 | |
1646 | rc = ata_pad_alloc(ap, dev); | |
24dc5f33 | 1647 | if (rc) |
254950cd | 1648 | return rc; |
254950cd | 1649 | |
24dc5f33 TH |
1650 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1651 | GFP_KERNEL); | |
1652 | if (!mem) | |
254950cd | 1653 | return -ENOMEM; |
254950cd TH |
1654 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1655 | ||
1656 | /* | |
1657 | * First item in chunk of DMA memory: 32-slot command table, | |
1658 | * 32 bytes each in size | |
1659 | */ | |
1660 | pp->cmd_slot = mem; | |
1661 | pp->cmd_slot_dma = mem_dma; | |
1662 | ||
1663 | mem += AHCI_CMD_SLOT_SZ; | |
1664 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1665 | ||
1666 | /* | |
1667 | * Second item: Received-FIS area | |
1668 | */ | |
1669 | pp->rx_fis = mem; | |
1670 | pp->rx_fis_dma = mem_dma; | |
1671 | ||
1672 | mem += AHCI_RX_FIS_SZ; | |
1673 | mem_dma += AHCI_RX_FIS_SZ; | |
1674 | ||
1675 | /* | |
1676 | * Third item: data area for storing a single command | |
1677 | * and its scatter-gather table | |
1678 | */ | |
1679 | pp->cmd_tbl = mem; | |
1680 | pp->cmd_tbl_dma = mem_dma; | |
1681 | ||
1682 | ap->private_data = pp; | |
1683 | ||
df69c9c5 JG |
1684 | /* engage engines, captain */ |
1685 | return ahci_port_resume(ap); | |
254950cd TH |
1686 | } |
1687 | ||
1688 | static void ahci_port_stop(struct ata_port *ap) | |
1689 | { | |
0be0aa98 TH |
1690 | const char *emsg = NULL; |
1691 | int rc; | |
254950cd | 1692 | |
0be0aa98 | 1693 | /* de-initialize port */ |
4447d351 | 1694 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
1695 | if (rc) |
1696 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1697 | } |
1698 | ||
4447d351 | 1699 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 1700 | { |
1da177e4 | 1701 | int rc; |
1da177e4 | 1702 | |
1da177e4 LT |
1703 | if (using_dac && |
1704 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1705 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1706 | if (rc) { | |
1707 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1708 | if (rc) { | |
a9524a76 JG |
1709 | dev_printk(KERN_ERR, &pdev->dev, |
1710 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1711 | return rc; |
1712 | } | |
1713 | } | |
1da177e4 LT |
1714 | } else { |
1715 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1716 | if (rc) { | |
a9524a76 JG |
1717 | dev_printk(KERN_ERR, &pdev->dev, |
1718 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1719 | return rc; |
1720 | } | |
1721 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1722 | if (rc) { | |
a9524a76 JG |
1723 | dev_printk(KERN_ERR, &pdev->dev, |
1724 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1725 | return rc; |
1726 | } | |
1727 | } | |
1da177e4 LT |
1728 | return 0; |
1729 | } | |
1730 | ||
4447d351 | 1731 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 1732 | { |
4447d351 TH |
1733 | struct ahci_host_priv *hpriv = host->private_data; |
1734 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1735 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
1736 | u32 vers, cap, impl, speed; |
1737 | const char *speed_s; | |
1738 | u16 cc; | |
1739 | const char *scc_s; | |
1740 | ||
1741 | vers = readl(mmio + HOST_VERSION); | |
1742 | cap = hpriv->cap; | |
1743 | impl = hpriv->port_map; | |
1744 | ||
1745 | speed = (cap >> 20) & 0xf; | |
1746 | if (speed == 1) | |
1747 | speed_s = "1.5"; | |
1748 | else if (speed == 2) | |
1749 | speed_s = "3"; | |
1750 | else | |
1751 | speed_s = "?"; | |
1752 | ||
1753 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 1754 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 1755 | scc_s = "IDE"; |
c9f89475 | 1756 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 1757 | scc_s = "SATA"; |
c9f89475 | 1758 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
1759 | scc_s = "RAID"; |
1760 | else | |
1761 | scc_s = "unknown"; | |
1762 | ||
a9524a76 JG |
1763 | dev_printk(KERN_INFO, &pdev->dev, |
1764 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1765 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1766 | , | |
1da177e4 LT |
1767 | |
1768 | (vers >> 24) & 0xff, | |
1769 | (vers >> 16) & 0xff, | |
1770 | (vers >> 8) & 0xff, | |
1771 | vers & 0xff, | |
1772 | ||
1773 | ((cap >> 8) & 0x1f) + 1, | |
1774 | (cap & 0x1f) + 1, | |
1775 | speed_s, | |
1776 | impl, | |
1777 | scc_s); | |
1778 | ||
a9524a76 JG |
1779 | dev_printk(KERN_INFO, &pdev->dev, |
1780 | "flags: " | |
203ef6c4 TH |
1781 | "%s%s%s%s%s%s%s" |
1782 | "%s%s%s%s%s%s%s\n" | |
1da177e4 | 1783 | , |
1da177e4 LT |
1784 | |
1785 | cap & (1 << 31) ? "64bit " : "", | |
1786 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 1787 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
1788 | cap & (1 << 28) ? "ilck " : "", |
1789 | cap & (1 << 27) ? "stag " : "", | |
1790 | cap & (1 << 26) ? "pm " : "", | |
1791 | cap & (1 << 25) ? "led " : "", | |
1792 | ||
1793 | cap & (1 << 24) ? "clo " : "", | |
1794 | cap & (1 << 19) ? "nz " : "", | |
1795 | cap & (1 << 18) ? "only " : "", | |
1796 | cap & (1 << 17) ? "pmp " : "", | |
1797 | cap & (1 << 15) ? "pio " : "", | |
1798 | cap & (1 << 14) ? "slum " : "", | |
1799 | cap & (1 << 13) ? "part " : "" | |
1800 | ); | |
1801 | } | |
1802 | ||
24dc5f33 | 1803 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
1804 | { |
1805 | static int printed_version; | |
4447d351 TH |
1806 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
1807 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 1808 | struct device *dev = &pdev->dev; |
1da177e4 | 1809 | struct ahci_host_priv *hpriv; |
4447d351 TH |
1810 | struct ata_host *host; |
1811 | int i, rc; | |
1da177e4 LT |
1812 | |
1813 | VPRINTK("ENTER\n"); | |
1814 | ||
12fad3f9 TH |
1815 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1816 | ||
1da177e4 | 1817 | if (!printed_version++) |
a9524a76 | 1818 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1819 | |
4447d351 | 1820 | /* acquire resources */ |
24dc5f33 | 1821 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1822 | if (rc) |
1823 | return rc; | |
1824 | ||
0d5ff566 TH |
1825 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
1826 | if (rc == -EBUSY) | |
24dc5f33 | 1827 | pcim_pin_device(pdev); |
0d5ff566 | 1828 | if (rc) |
24dc5f33 | 1829 | return rc; |
1da177e4 | 1830 | |
cd70c266 | 1831 | if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev)) |
907f4678 | 1832 | pci_intx(pdev, 1); |
1da177e4 | 1833 | |
24dc5f33 TH |
1834 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1835 | if (!hpriv) | |
1836 | return -ENOMEM; | |
1da177e4 | 1837 | |
4447d351 TH |
1838 | /* save initial config */ |
1839 | ahci_save_initial_config(pdev, &pi, hpriv); | |
1da177e4 | 1840 | |
4447d351 | 1841 | /* prepare host */ |
274c1fde | 1842 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 1843 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 1844 | |
4447d351 TH |
1845 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
1846 | if (!host) | |
1847 | return -ENOMEM; | |
1848 | host->iomap = pcim_iomap_table(pdev); | |
1849 | host->private_data = hpriv; | |
1850 | ||
1851 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
1852 | struct ata_port *ap = host->ports[i]; |
1853 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 1854 | |
dab632e8 | 1855 | /* standard SATA port setup */ |
203ef6c4 | 1856 | if (hpriv->port_map & (1 << i)) |
4447d351 | 1857 | ap->ioaddr.cmd_addr = port_mmio; |
dab632e8 JG |
1858 | |
1859 | /* disabled/not-implemented port */ | |
1860 | else | |
1861 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 1862 | } |
d447df14 | 1863 | |
4447d351 TH |
1864 | /* initialize adapter */ |
1865 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1866 | if (rc) |
24dc5f33 | 1867 | return rc; |
1da177e4 | 1868 | |
4447d351 TH |
1869 | rc = ahci_reset_controller(host); |
1870 | if (rc) | |
1871 | return rc; | |
1da177e4 | 1872 | |
4447d351 TH |
1873 | ahci_init_controller(host); |
1874 | ahci_print_info(host); | |
1da177e4 | 1875 | |
4447d351 TH |
1876 | pci_set_master(pdev); |
1877 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
1878 | &ahci_sht); | |
907f4678 | 1879 | } |
1da177e4 LT |
1880 | |
1881 | static int __init ahci_init(void) | |
1882 | { | |
b7887196 | 1883 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
1884 | } |
1885 | ||
1da177e4 LT |
1886 | static void __exit ahci_exit(void) |
1887 | { | |
1888 | pci_unregister_driver(&ahci_pci_driver); | |
1889 | } | |
1890 | ||
1891 | ||
1892 | MODULE_AUTHOR("Jeff Garzik"); | |
1893 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1894 | MODULE_LICENSE("GPL"); | |
1895 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1896 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1897 | |
1898 | module_init(ahci_init); | |
1899 | module_exit(ahci_exit); |