]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/ata/ahci.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ipv4: convert dst_metrics.refcnt from atomic_t to refcount_t
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 27 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
ee2aad42 45#include <linux/msi.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
aecec8b6
CH		 49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
365cfa1e 51#include "ahci.h"
1da177e4
LT		 52
53#define DRV_NAME "ahci"
7d50b60b 54#define DRV_VERSION "3.0"
1da177e4 55
1da177e4 56enum {
318893e1 57 AHCI_PCI_BAR_STA2X11 = 0,
b7ae128d 58 AHCI_PCI_BAR_CAVIUM = 0,
7f9c9f8e 59 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 60 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 61};
62
63enum board_ids {
64 /* board IDs by feature in alphabetical order */
65 board_ahci,
66 board_ahci_ign_iferr,
66a7cbc3 67 board_ahci_nomsi,
67809f85 68 board_ahci_noncq,
441577ef 69 board_ahci_nosntf,
5f173107 70 board_ahci_yes_fbs,
1da177e4 71
441577ef 72 /* board IDs for specific chipsets in alphabetical order */
dbfe8ef5 73 board_ahci_avn,
441577ef 74 board_ahci_mcp65,
83f2b963
TH		 75 board_ahci_mcp77,
76 board_ahci_mcp89,
441577ef
TH		 77 board_ahci_mv,
78 board_ahci_sb600,
79 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_vt8251,
81
82 /* aliases */
83 board_ahci_mcp_linux = board_ahci_mcp65,
84 board_ahci_mcp67 = board_ahci_mcp65,
85 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 86 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 87};
88
2dcb407e 89static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
02e53293 90static void ahci_remove_one(struct pci_dev *dev);
a1efdaba
TH		 91static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
dbfe8ef5
DW		 93static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
cb85696d
JL		 95static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
96static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 97static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
98 unsigned long deadline);
02e53293
MW		 99#ifdef CONFIG_PM
100static int ahci_pci_device_runtime_suspend(struct device *dev);
101static int ahci_pci_device_runtime_resume(struct device *dev);
f1d848f9
MW		 102#ifdef CONFIG_PM_SLEEP
103static int ahci_pci_device_suspend(struct device *dev);
104static int ahci_pci_device_resume(struct device *dev);
438ac6d5 105#endif
02e53293 106#endif /* CONFIG_PM */
ad616ffb 107
fad16e7a
TH		 108static struct scsi_host_template ahci_sht = {
109 AHCI_SHT("ahci"),
110};
111
029cfd6b
TH		 112static struct ata_port_operations ahci_vt8251_ops = {
113 .inherits = &ahci_ops,
a1efdaba 114 .hardreset = ahci_vt8251_hardreset,
029cfd6b 115};
edc93052 116
029cfd6b
TH		 117static struct ata_port_operations ahci_p5wdh_ops = {
118 .inherits = &ahci_ops,
a1efdaba 119 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 120};
121
dbfe8ef5
DW		 122static struct ata_port_operations ahci_avn_ops = {
123 .inherits = &ahci_ops,
124 .hardreset = ahci_avn_hardreset,
125};
126
98ac62de 127static const struct ata_port_info ahci_port_info[] = {
441577ef 128 /* by features */
facb8fa6 129 [board_ahci] = {
1188c0d8 130 .flags = AHCI_FLAG_COMMON,
14bdef98 131 .pio_mask = ATA_PIO4,
469248ab 132 .udma_mask = ATA_UDMA6,
1da177e4
LT		 133 .port_ops = &ahci_ops,
134 },
facb8fa6 135 [board_ahci_ign_iferr] = {
441577ef 136 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 137 .flags = AHCI_FLAG_COMMON,
14bdef98 138 .pio_mask = ATA_PIO4,
469248ab 139 .udma_mask = ATA_UDMA6,
441577ef 140 .port_ops = &ahci_ops,
bf2af2a2 141 },
66a7cbc3
TH		 142 [board_ahci_nomsi] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
67809f85
LK		 149 [board_ahci_noncq] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
facb8fa6 156 [board_ahci_nosntf] = {
441577ef 157 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 158 .flags = AHCI_FLAG_COMMON,
14bdef98 159 .pio_mask = ATA_PIO4,
469248ab 160 .udma_mask = ATA_UDMA6,
41669553
TH		 161 .port_ops = &ahci_ops,
162 },
facb8fa6 163 [board_ahci_yes_fbs] = {
5f173107
TH		 164 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
441577ef 170 /* by chipsets */
dbfe8ef5
DW		 171 [board_ahci_avn] = {
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_avn_ops,
176 },
facb8fa6 177 [board_ahci_mcp65] = {
83f2b963
TH		 178 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 AHCI_HFLAG_YES_NCQ),
ae01b249 180 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
facb8fa6 185 [board_ahci_mcp77] = {
83f2b963
TH		 186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
facb8fa6 192 [board_ahci_mcp89] = {
83f2b963 193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 194 .flags = AHCI_FLAG_COMMON,
14bdef98 195 .pio_mask = ATA_PIO4,
469248ab 196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_ops,
55a61604 198 },
facb8fa6 199 [board_ahci_mv] = {
417a1a6d 200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 203 .pio_mask = ATA_PIO4,
cd70c266
JG		 204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
206 },
facb8fa6 207 [board_ahci_sb600] = {
441577ef
TH		 208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
209 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
210 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 211 .flags = AHCI_FLAG_COMMON,
14bdef98 212 .pio_mask = ATA_PIO4,
e39fc8c9 213 .udma_mask = ATA_UDMA6,
345347c5 214 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 215 },
facb8fa6 216 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
345347c5 221 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 222 },
facb8fa6 223 [board_ahci_vt8251] = {
441577ef 224 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
441577ef 228 .port_ops = &ahci_vt8251_ops,
1b677afd 229 },
1da177e4
LT		 230};
231
3b7d697d 232static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 233 /* Intel */
54bb3a94
JG		 234 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
235 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
236 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
237 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
238 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 239 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 240 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 244 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 245 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 246 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
248 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 261 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
262 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 263 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 264 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 265 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 266 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 268 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 269 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 270 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 271 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 272 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 273 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
342decff
AY		 274 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
5623cab8
SH		 294 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
297 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
298 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 300 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
301 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
302 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 303 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 304 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 305 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 311 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 312 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
313 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 320 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
321 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 328 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
dbfe8ef5
DW		 336 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
efda332c
JR		 344 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 346 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
347 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
351 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 354 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 355 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 359 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
360 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
362 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
249cd0a1
DR		 367 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
368 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
369 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
c5967b79 370 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
690000b9 371 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
690000b9 372 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
c5967b79 373 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
690000b9
JR		 374 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
375 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
4d92f009 376 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 377 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
4d92f009 378 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
f5bdd66c 379 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
4d92f009 380 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
4d92f009 381 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 382 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
4d92f009 384 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
4d92f009 385 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
f5bdd66c
AY		 386 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
fe7fa31a 388
e34bb370
TH		 389 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
390 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 392 /* JMicron 362B and 362C have an AHCI function with IDE class code */
393 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
394 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
91f15fb3 395 /* May need to update quirk_jmicron_async_suspend() for additions */
fe7fa31a
JG		 396
397 /* ATI */
c65ec1c2 398 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 399 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 405
e2dd90b1 406 /* AMD */
5deab536 407 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 408 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 409 /* AMD is using RAID class only for ahci controllers */
410 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
412
fe7fa31a 413 /* VIA */
54bb3a94 414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 416
417 /* NVIDIA */
e297d99e
TH		 418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 502
95916edd 503 /* SiS */
20e2de4a
TH		 504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 507
318893e1
AR		 508 /* ST Microelectronics */
509 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
510
cd70c266
JG		 511 /* Marvell */
512 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 513 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 515 .class = PCI_CLASS_STORAGE_SATA_AHCI,
516 .class_mask = 0xffffff,
5f173107 517 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 519 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 520 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 524 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 526 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532 .driver_data = board_ahci_yes_fbs },
a40cf3f3
JT		 533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
534 .driver_data = board_ahci_yes_fbs },
69fd3157 535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 536 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 539 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
540 .driver_data = board_ahci_yes_fbs },
cd70c266 541
c77a036b
MN		 542 /* Promise */
543 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 544 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 545
c9703765 546 /* Asmedia */
7b4f6eca
AC		 547 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
548 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
549 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
550 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
0ce968f3
SL		 551 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
552 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
c9703765 553
67809f85 554 /*
66a7cbc3
TH		 555 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
556 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 557 */
66a7cbc3 558 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 559 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 560
7f9c9f8e
HD		 561 /* Enmotus */
562 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
563
415ae2b5
JG		 564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 567
1da177e4
LT		 568 { } /* terminate list */
569};
570
f1d848f9
MW		 571static const struct dev_pm_ops ahci_pci_pm_ops = {
572 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
02e53293
MW		 573 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
574 ahci_pci_device_runtime_resume, NULL)
f1d848f9 575};
1da177e4
LT		 576
577static struct pci_driver ahci_pci_driver = {
578 .name = DRV_NAME,
579 .id_table = ahci_pci_tbl,
580 .probe = ahci_init_one,
02e53293 581 .remove = ahci_remove_one,
f1d848f9
MW		 582 .driver = {
583 .pm = &ahci_pci_pm_ops,
584 },
365cfa1e 585};
1da177e4 586
5219d653 587#if IS_ENABLED(CONFIG_PATA_MARVELL)
365cfa1e
AV		 588static int marvell_enable;
589#else
590static int marvell_enable = 1;
591#endif
592module_param(marvell_enable, int, 0644);
593MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 594
1da177e4 595
365cfa1e
AV		 596static void ahci_pci_save_initial_config(struct pci_dev *pdev,
597 struct ahci_host_priv *hpriv)
598{
365cfa1e
AV		 599 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
600 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 601 hpriv->force_port_map = 1;
1da177e4
LT		 602 }
603
365cfa1e
AV		 604 /*
605 * Temporary Marvell 6145 hack: PATA port presence
606 * is asserted through the standard AHCI port
607 * presence register, as bit 4 (counting from 0)
d28f87aa 608 */
365cfa1e
AV		 609 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
610 if (pdev->device == 0x6121)
9a23c1d6 611 hpriv->mask_port_map = 0x3;
365cfa1e 612 else
9a23c1d6 613 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 614 dev_info(&pdev->dev,
615 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
616 }
1da177e4 617
725c7b57 618 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 619}
620
365cfa1e 621static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 622{
365cfa1e 623 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 624
365cfa1e 625 ahci_reset_controller(host);
1da177e4 626
365cfa1e
AV		 627 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
628 struct ahci_host_priv *hpriv = host->private_data;
629 u16 tmp16;
d6ef3153 630
365cfa1e
AV		 631 /* configure PCS */
632 pci_read_config_word(pdev, 0x92, &tmp16);
633 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
634 tmp16 |= hpriv->port_map;
635 pci_write_config_word(pdev, 0x92, tmp16);
636 }
d6ef3153
SH		 637 }
638
1da177e4
LT		 639 return 0;
640}
641
365cfa1e 642static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 643{
365cfa1e
AV		 644 struct ahci_host_priv *hpriv = host->private_data;
645 struct pci_dev *pdev = to_pci_dev(host->dev);
646 void __iomem *port_mmio;
78cd52d0 647 u32 tmp;
365cfa1e 648 int mv;
78cd52d0 649
365cfa1e
AV		 650 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
651 if (pdev->device == 0x6121)
652 mv = 2;
653 else
654 mv = 4;
655 port_mmio = __ahci_port_base(host, mv);
78cd52d0 656
365cfa1e 657 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 658
365cfa1e
AV		 659 /* clear port IRQ */
660 tmp = readl(port_mmio + PORT_IRQ_STAT);
661 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
662 if (tmp)
663 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 664 }
665
365cfa1e 666 ahci_init_controller(host);
edc93052
TH		 667}
668
365cfa1e
AV		 669static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
670 unsigned long deadline)
d6ef3153 671{
365cfa1e 672 struct ata_port *ap = link->ap;
039ece38 673 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 674 bool online;
d6ef3153
SH		 675 int rc;
676
365cfa1e 677 DPRINTK("ENTER\n");
d6ef3153 678
365cfa1e 679 ahci_stop_engine(ap);
d6ef3153 680
365cfa1e
AV		 681 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
682 deadline, &online, NULL);
d6ef3153 683
039ece38 684 hpriv->start_engine(ap);
d6ef3153 685
365cfa1e 686 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 687
365cfa1e
AV		 688 /* vt8251 doesn't clear BSY on signature FIS reception,
689 * request follow-up softreset.
690 */
691 return online ? -EAGAIN : rc;
7d50b60b
TH		 692}
693
365cfa1e
AV		 694static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
695 unsigned long deadline)
7d50b60b 696{
365cfa1e 697 struct ata_port *ap = link->ap;
1c954a4d 698 struct ahci_port_priv *pp = ap->private_data;
039ece38 699 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 700 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
701 struct ata_taskfile tf;
702 bool online;
703 int rc;
7d50b60b 704
365cfa1e 705 ahci_stop_engine(ap);
028a2596 706
365cfa1e
AV		 707 /* clear D2H reception area to properly wait for D2H FIS */
708 ata_tf_init(link->device, &tf);
9bbb1b0e 709 tf.command = ATA_BUSY;
365cfa1e 710 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 711
365cfa1e
AV		 712 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
713 deadline, &online, NULL);
028a2596 714
039ece38 715 hpriv->start_engine(ap);
c1332875 716
365cfa1e
AV		 717 /* The pseudo configuration device on SIMG4726 attached to
718 * ASUS P5W-DH Deluxe doesn't send signature FIS after
719 * hardreset if no device is attached to the first downstream
720 * port && the pseudo device locks up on SRST w/ PMP==0. To
721 * work around this, wait for !BSY only briefly. If BSY isn't
722 * cleared, perform CLO and proceed to IDENTIFY (achieved by
723 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
724 *
725 * Wait for two seconds. Devices attached to downstream port
726 * which can't process the following IDENTIFY after this will
727 * have to be reset again. For most cases, this should
728 * suffice while making probing snappish enough.
729 */
730 if (online) {
731 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
732 ahci_check_ready);
733 if (rc)
734 ahci_kick_engine(ap);
c1332875 735 }
c1332875
TH		 736 return rc;
737}
738
dbfe8ef5
DW		 739/*
740 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
741 *
742 * It has been observed with some SSDs that the timing of events in the
743 * link synchronization phase can leave the port in a state that can not
744 * be recovered by a SATA-hard-reset alone. The failing signature is
745 * SStatus.DET stuck at 1 ("Device presence detected but Phy
746 * communication not established"). It was found that unloading and
747 * reloading the driver when this problem occurs allows the drive
748 * connection to be recovered (DET advanced to 0x3). The critical
749 * component of reloading the driver is that the port state machines are
750 * reset by bouncing "port enable" in the AHCI PCS configuration
751 * register. So, reproduce that effect by bouncing a port whenever we
752 * see DET==1 after a reset.
753 */
754static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
755 unsigned long deadline)
756{
757 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
758 struct ata_port *ap = link->ap;
759 struct ahci_port_priv *pp = ap->private_data;
760 struct ahci_host_priv *hpriv = ap->host->private_data;
761 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
762 unsigned long tmo = deadline - jiffies;
763 struct ata_taskfile tf;
764 bool online;
765 int rc, i;
766
767 DPRINTK("ENTER\n");
768
769 ahci_stop_engine(ap);
770
771 for (i = 0; i < 2; i++) {
772 u16 val;
773 u32 sstatus;
774 int port = ap->port_no;
775 struct ata_host *host = ap->host;
776 struct pci_dev *pdev = to_pci_dev(host->dev);
777
778 /* clear D2H reception area to properly wait for D2H FIS */
779 ata_tf_init(link->device, &tf);
780 tf.command = ATA_BUSY;
781 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
782
783 rc = sata_link_hardreset(link, timing, deadline, &online,
784 ahci_check_ready);
785
786 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
787 (sstatus & 0xf) != 1)
788 break;
789
790 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
791 port);
792
793 pci_read_config_word(pdev, 0x92, &val);
794 val &= ~(1 << port);
795 pci_write_config_word(pdev, 0x92, val);
796 ata_msleep(ap, 1000);
797 val |= 1 << port;
798 pci_write_config_word(pdev, 0x92, val);
799 deadline += tmo;
800 }
801
802 hpriv->start_engine(ap);
803
804 if (online)
805 *class = ahci_dev_classify(ap);
806
807 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
808 return rc;
809}
810
811
02e53293
MW		 812#ifdef CONFIG_PM
813static void ahci_pci_disable_interrupts(struct ata_host *host)
c1332875 814{
9b10ae86 815 struct ahci_host_priv *hpriv = host->private_data;
d8993349 816 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 817 u32 ctl;
818
f1d848f9
MW		 819 /* AHCI spec rev1.1 section 8.3.3:
820 * Software must disable interrupts prior to requesting a
821 * transition of the HBA to D3 state.
822 */
823 ctl = readl(mmio + HOST_CTL);
824 ctl &= ~HOST_IRQ_EN;
825 writel(ctl, mmio + HOST_CTL);
826 readl(mmio + HOST_CTL); /* flush */
02e53293
MW		 827}
828
829static int ahci_pci_device_runtime_suspend(struct device *dev)
830{
831 struct pci_dev *pdev = to_pci_dev(dev);
832 struct ata_host *host = pci_get_drvdata(pdev);
c1332875 833
02e53293
MW		 834 ahci_pci_disable_interrupts(host);
835 return 0;
836}
837
838static int ahci_pci_device_runtime_resume(struct device *dev)
839{
840 struct pci_dev *pdev = to_pci_dev(dev);
841 struct ata_host *host = pci_get_drvdata(pdev);
842 int rc;
843
844 rc = ahci_pci_reset_controller(host);
845 if (rc)
846 return rc;
847 ahci_pci_init_controller(host);
848 return 0;
849}
850
851#ifdef CONFIG_PM_SLEEP
852static int ahci_pci_device_suspend(struct device *dev)
853{
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct ata_host *host = pci_get_drvdata(pdev);
856 struct ahci_host_priv *hpriv = host->private_data;
857
858 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
859 dev_err(&pdev->dev,
860 "BIOS update required for suspend/resume\n");
861 return -EIO;
862 }
863
864 ahci_pci_disable_interrupts(host);
f1d848f9 865 return ata_host_suspend(host, PMSG_SUSPEND);
c1332875
TH		 866}
867
f1d848f9 868static int ahci_pci_device_resume(struct device *dev)
c1332875 869{
f1d848f9 870 struct pci_dev *pdev = to_pci_dev(dev);
0a86e1c8 871 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 872 int rc;
873
cb85696d
JL		 874 /* Apple BIOS helpfully mangles the registers on resume */
875 if (is_mcp89_apple(pdev))
876 ahci_mcp89_apple_enable(pdev);
877
c1332875 878 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 879 rc = ahci_pci_reset_controller(host);
c1332875
TH		 880 if (rc)
881 return rc;
882
781d6550 883 ahci_pci_init_controller(host);
c1332875
TH		 884 }
885
cca3974e 886 ata_host_resume(host);
c1332875
TH		 887
888 return 0;
889}
438ac6d5 890#endif
c1332875 891
02e53293
MW		 892#endif /* CONFIG_PM */
893
4447d351 894static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 895{
1da177e4 896 int rc;
1da177e4 897
318893e1
AR		 898 /*
899 * If the device fixup already set the dma_mask to some non-standard
900 * value, don't extend it here. This happens on STA2X11, for example.
901 */
902 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
903 return 0;
904
1da177e4 905 if (using_dac &&
c54c719b
QL		 906 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
907 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 908 if (rc) {
c54c719b 909 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 910 if (rc) {
a44fec1f
JP		 911 dev_err(&pdev->dev,
912 "64-bit DMA enable failed\n");
1da177e4
LT		 913 return rc;
914 }
915 }
1da177e4 916 } else {
c54c719b 917 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 918 if (rc) {
a44fec1f 919 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 920 return rc;
921 }
c54c719b 922 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 923 if (rc) {
a44fec1f
JP		 924 dev_err(&pdev->dev,
925 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 926 return rc;
927 }
928 }
1da177e4
LT		 929 return 0;
930}
931
439fcaec
AV		 932static void ahci_pci_print_info(struct ata_host *host)
933{
934 struct pci_dev *pdev = to_pci_dev(host->dev);
935 u16 cc;
936 const char *scc_s;
937
938 pci_read_config_word(pdev, 0x0a, &cc);
939 if (cc == PCI_CLASS_STORAGE_IDE)
940 scc_s = "IDE";
941 else if (cc == PCI_CLASS_STORAGE_SATA)
942 scc_s = "SATA";
943 else if (cc == PCI_CLASS_STORAGE_RAID)
944 scc_s = "RAID";
945 else
946 scc_s = "unknown";
947
948 ahci_print_info(host, scc_s);
949}
950
edc93052
TH		 951/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
952 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
953 * support PMP and the 4726 either directly exports the device
954 * attached to the first downstream port or acts as a hardware storage
955 * controller and emulate a single ATA device (can be RAID 0/1 or some
956 * other configuration).
957 *
958 * When there's no device attached to the first downstream port of the
959 * 4726, "Config Disk" appears, which is a pseudo ATA device to
960 * configure the 4726. However, ATA emulation of the device is very
961 * lame. It doesn't send signature D2H Reg FIS after the initial
962 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
963 *
964 * The following function works around the problem by always using
965 * hardreset on the port and not depending on receiving signature FIS
966 * afterward. If signature FIS isn't received soon, ATA class is
967 * assumed without follow-up softreset.
968 */
969static void ahci_p5wdh_workaround(struct ata_host *host)
970{
1bd06867 971 static const struct dmi_system_id sysids[] = {
edc93052
TH		 972 {
973 .ident = "P5W DH Deluxe",
974 .matches = {
975 DMI_MATCH(DMI_SYS_VENDOR,
976 "ASUSTEK COMPUTER INC"),
977 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
978 },
979 },
980 { }
981 };
982 struct pci_dev *pdev = to_pci_dev(host->dev);
983
984 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
985 dmi_check_system(sysids)) {
986 struct ata_port *ap = host->ports[1];
987
a44fec1f
JP		 988 dev_info(&pdev->dev,
989 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 990
991 ap->ops = &ahci_p5wdh_ops;
992 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
993 }
994}
995
cb85696d
JL		 996/*
997 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
998 * booting in BIOS compatibility mode. We restore the registers but not ID.
999 */
1000static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1001{
1002 u32 val;
1003
1004 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1005
1006 pci_read_config_dword(pdev, 0xf8, &val);
1007 val |= 1 << 0x1b;
1008 /* the following changes the device ID, but appears not to affect function */
1009 /* val = (val & ~0xf0000000) | 0x80000000; */
1010 pci_write_config_dword(pdev, 0xf8, val);
1011
1012 pci_read_config_dword(pdev, 0x54c, &val);
1013 val |= 1 << 0xc;
1014 pci_write_config_dword(pdev, 0x54c, val);
1015
1016 pci_read_config_dword(pdev, 0x4a4, &val);
1017 val &= 0xff;
1018 val |= 0x01060100;
1019 pci_write_config_dword(pdev, 0x4a4, val);
1020
1021 pci_read_config_dword(pdev, 0x54c, &val);
1022 val &= ~(1 << 0xc);
1023 pci_write_config_dword(pdev, 0x54c, val);
1024
1025 pci_read_config_dword(pdev, 0xf8, &val);
1026 val &= ~(1 << 0x1b);
1027 pci_write_config_dword(pdev, 0xf8, val);
1028}
1029
1030static bool is_mcp89_apple(struct pci_dev *pdev)
1031{
1032 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1033 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1034 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1035 pdev->subsystem_device == 0xcb89;
1036}
1037
2fcad9d2
TH		 1038/* only some SB600 ahci controllers can do 64bit DMA */
1039static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 1040{
1041 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 1042 /*
1043 * The oldest version known to be broken is 0901 and
1044 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 1045 * Enable 64bit DMA on 1501 and anything newer.
1046 *
03d783bf
TH		 1047 * Please read bko#9412 for more info.
1048 */
58a09b38
SH		 1049 {
1050 .ident = "ASUS M2A-VM",
1051 .matches = {
1052 DMI_MATCH(DMI_BOARD_VENDOR,
1053 "ASUSTeK Computer INC."),
1054 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1055 },
03d783bf 1056 .driver_data = "20071026", /* yyyymmdd */
58a09b38 1057 },
e65cc194
MN		 1058 /*
1059 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1060 * support 64bit DMA.
1061 *
1062 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1063 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1064 * This spelling mistake was fixed in BIOS version 1.5, so
1065 * 1.5 and later have the Manufacturer as
1066 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1067 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1068 *
1069 * BIOS versions earlier than 1.9 had a Board Product Name
1070 * DMI field of "MS-7376". This was changed to be
1071 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1072 * match on DMI_BOARD_NAME of "MS-7376".
1073 */
1074 {
1075 .ident = "MSI K9A2 Platinum",
1076 .matches = {
1077 DMI_MATCH(DMI_BOARD_VENDOR,
1078 "MICRO-STAR INTER"),
1079 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1080 },
1081 },
ff0173c1
MN		 1082 /*
1083 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1084 * 64bit DMA.
1085 *
1086 * This board also had the typo mentioned above in the
1087 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1088 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1089 */
1090 {
1091 .ident = "MSI K9AGM2",
1092 .matches = {
1093 DMI_MATCH(DMI_BOARD_VENDOR,
1094 "MICRO-STAR INTER"),
1095 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1096 },
1097 },
3c4aa91f
MN		 1098 /*
1099 * All BIOS versions for the Asus M3A support 64bit DMA.
1100 * (all release versions from 0301 to 1206 were tested)
1101 */
1102 {
1103 .ident = "ASUS M3A",
1104 .matches = {
1105 DMI_MATCH(DMI_BOARD_VENDOR,
1106 "ASUSTeK Computer INC."),
1107 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1108 },
1109 },
58a09b38
SH		 1110 { }
1111 };
03d783bf 1112 const struct dmi_system_id *match;
2fcad9d2
TH		 1113 int year, month, date;
1114 char buf[9];
58a09b38 1115
03d783bf 1116 match = dmi_first_match(sysids);
58a09b38 1117 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 1118 !match)
58a09b38
SH		 1119 return false;
1120
e65cc194
MN		 1121 if (!match->driver_data)
1122 goto enable_64bit;
1123
2fcad9d2
TH		 1124 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1125 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 1126
e65cc194
MN		 1127 if (strcmp(buf, match->driver_data) >= 0)
1128 goto enable_64bit;
1129 else {
a44fec1f
JP		 1130 dev_warn(&pdev->dev,
1131 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1132 match->ident);
2fcad9d2
TH		 1133 return false;
1134 }
e65cc194
MN		 1135
1136enable_64bit:
a44fec1f 1137 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 1138 return true;
58a09b38
SH		 1139}
1140
1fd68434
RW		 1141static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1142{
1143 static const struct dmi_system_id broken_systems[] = {
1144 {
1145 .ident = "HP Compaq nx6310",
1146 .matches = {
1147 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1148 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1149 },
1150 /* PCI slot number of the controller */
1151 .driver_data = (void *)0x1FUL,
1152 },
d2f9c061
MR		 1153 {
1154 .ident = "HP Compaq 6720s",
1155 .matches = {
1156 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1157 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1158 },
1159 /* PCI slot number of the controller */
1160 .driver_data = (void *)0x1FUL,
1161 },
1fd68434
RW		 1162
1163 { } /* terminate list */
1164 };
1165 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1166
1167 if (dmi) {
1168 unsigned long slot = (unsigned long)dmi->driver_data;
1169 /* apply the quirk only to on-board controllers */
1170 return slot == PCI_SLOT(pdev->devfn);
1171 }
1172
1173 return false;
1174}
1175
9b10ae86
TH		 1176static bool ahci_broken_suspend(struct pci_dev *pdev)
1177{
1178 static const struct dmi_system_id sysids[] = {
1179 /*
1180 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1181 * to the harddisk doesn't become online after
1182 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1183 *
1184 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1185 *
1186 * Use dates instead of versions to match as HP is
1187 * apparently recycling both product and version
1188 * strings.
1189 *
1190 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1191 */
1192 {
1193 .ident = "dv4",
1194 .matches = {
1195 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1196 DMI_MATCH(DMI_PRODUCT_NAME,
1197 "HP Pavilion dv4 Notebook PC"),
1198 },
9deb3431 1199 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1200 },
1201 {
1202 .ident = "dv5",
1203 .matches = {
1204 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1205 DMI_MATCH(DMI_PRODUCT_NAME,
1206 "HP Pavilion dv5 Notebook PC"),
1207 },
9deb3431 1208 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1209 },
1210 {
1211 .ident = "dv6",
1212 .matches = {
1213 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1214 DMI_MATCH(DMI_PRODUCT_NAME,
1215 "HP Pavilion dv6 Notebook PC"),
1216 },
9deb3431 1217 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1218 },
1219 {
1220 .ident = "HDX18",
1221 .matches = {
1222 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1223 DMI_MATCH(DMI_PRODUCT_NAME,
1224 "HP HDX18 Notebook PC"),
1225 },
9deb3431 1226 .driver_data = "20090430", /* F.23 */
9b10ae86 1227 },
cedc9bf9
TH		 1228 /*
1229 * Acer eMachines G725 has the same problem. BIOS
1230 * V1.03 is known to be broken. V3.04 is known to
25985edc 1231 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1232 * that we don't have much idea about. For now,
1233 * blacklist anything older than V3.04.
9deb3431
TH		 1234 *
1235 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1236 */
1237 {
1238 .ident = "G725",
1239 .matches = {
1240 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1241 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1242 },
9deb3431 1243 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1244 },
9b10ae86
TH		 1245 { } /* terminate list */
1246 };
1247 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1248 int year, month, date;
1249 char buf[9];
9b10ae86
TH		 1250
1251 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1252 return false;
1253
9deb3431
TH		 1254 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1255 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1256
9deb3431 1257 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1258}
1259
5594639a
TH		 1260static bool ahci_broken_online(struct pci_dev *pdev)
1261{
1262#define ENCODE_BUSDEVFN(bus, slot, func) \
1263 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1264 static const struct dmi_system_id sysids[] = {
1265 /*
1266 * There are several gigabyte boards which use
1267 * SIMG5723s configured as hardware RAID. Certain
1268 * 5723 firmware revisions shipped there keep the link
1269 * online but fail to answer properly to SRST or
1270 * IDENTIFY when no device is attached downstream
1271 * causing libata to retry quite a few times leading
1272 * to excessive detection delay.
1273 *
1274 * As these firmwares respond to the second reset try
1275 * with invalid device signature, considering unknown
1276 * sig as offline works around the problem acceptably.
1277 */
1278 {
1279 .ident = "EP45-DQ6",
1280 .matches = {
1281 DMI_MATCH(DMI_BOARD_VENDOR,
1282 "Gigabyte Technology Co., Ltd."),
1283 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1284 },
1285 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1286 },
1287 {
1288 .ident = "EP45-DS5",
1289 .matches = {
1290 DMI_MATCH(DMI_BOARD_VENDOR,
1291 "Gigabyte Technology Co., Ltd."),
1292 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1293 },
1294 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1295 },
1296 { } /* terminate list */
1297 };
1298#undef ENCODE_BUSDEVFN
1299 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1300 unsigned int val;
1301
1302 if (!dmi)
1303 return false;
1304
1305 val = (unsigned long)dmi->driver_data;
1306
1307 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1308}
1309
0cf4a7d6
JP		 1310static bool ahci_broken_devslp(struct pci_dev *pdev)
1311{
1312 /* device with broken DEVSLP but still showing SDS capability */
1313 static const struct pci_device_id ids[] = {
1314 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1315 {}
1316 };
1317
1318 return pci_match_id(ids, pdev);
1319}
1320
8e513217 1321#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1322static void ahci_gtf_filter_workaround(struct ata_host *host)
1323{
1324 static const struct dmi_system_id sysids[] = {
1325 /*
1326 * Aspire 3810T issues a bunch of SATA enable commands
1327 * via _GTF including an invalid one and one which is
1328 * rejected by the device. Among the successful ones
1329 * is FPDMA non-zero offset enable which when enabled
1330 * only on the drive side leads to NCQ command
1331 * failures. Filter it out.
1332 */
1333 {
1334 .ident = "Aspire 3810T",
1335 .matches = {
1336 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1337 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1338 },
1339 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1340 },
1341 { }
1342 };
1343 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1344 unsigned int filter;
1345 int i;
1346
1347 if (!dmi)
1348 return;
1349
1350 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1351 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1352 filter, dmi->ident);
f80ae7e4
TH		 1353
1354 for (i = 0; i < host->n_ports; i++) {
1355 struct ata_port *ap = host->ports[i];
1356 struct ata_link *link;
1357 struct ata_device *dev;
1358
1359 ata_for_each_link(link, ap, EDGE)
1360 ata_for_each_dev(dev, link, ALL)
1361 dev->gtf_filter |= filter;
1362 }
1363}
8e513217
MT		 1364#else
1365static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1366{}
1367#endif
f80ae7e4 1368
8bfd1743
SC		 1369/*
1370 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1371 * as DUMMY, or detected but eventually get a "link down" and never get up
1372 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1373 * port_map may hold a value of 0x00.
1374 *
1375 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1376 * and can significantly reduce the occurrence of the problem.
1377 *
1378 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1379 */
1380static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1381 struct pci_dev *pdev)
1382{
1383 static const struct dmi_system_id sysids[] = {
1384 {
1385 .ident = "Acer Switch Alpha 12",
1386 .matches = {
1387 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1388 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1389 },
1390 },
1391 { }
1392 };
1393
1394 if (dmi_check_system(sysids)) {
1395 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1396 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1397 hpriv->port_map = 0x7;
1398 hpriv->cap = 0xC734FF02;
1399 }
1400 }
1401}
1402
d243bed3
TC		 1403#ifdef CONFIG_ARM64
1404/*
1405 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1406 * Workaround is to make sure all pending IRQs are served before leaving
1407 * handler.
1408 */
1409static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1410{
1411 struct ata_host *host = dev_instance;
1412 struct ahci_host_priv *hpriv;
1413 unsigned int rc = 0;
1414 void __iomem *mmio;
1415 u32 irq_stat, irq_masked;
1416 unsigned int handled = 1;
1417
1418 VPRINTK("ENTER\n");
1419 hpriv = host->private_data;
1420 mmio = hpriv->mmio;
1421 irq_stat = readl(mmio + HOST_IRQ_STAT);
1422 if (!irq_stat)
1423 return IRQ_NONE;
1424
1425 do {
1426 irq_masked = irq_stat & hpriv->port_map;
1427 spin_lock(&host->lock);
1428 rc = ahci_handle_port_intr(host, irq_masked);
1429 if (!rc)
1430 handled = 0;
1431 writel(irq_stat, mmio + HOST_IRQ_STAT);
1432 irq_stat = readl(mmio + HOST_IRQ_STAT);
1433 spin_unlock(&host->lock);
1434 } while (irq_stat);
1435 VPRINTK("EXIT\n");
1436
1437 return IRQ_RETVAL(handled);
1438}
1439#endif
1440
aecec8b6
CH		 1441static void ahci_remap_check(struct pci_dev *pdev, int bar,
1442 struct ahci_host_priv *hpriv)
1443{
1444 int i, count = 0;
1445 u32 cap;
1446
1447 /*
1448 * Check if this device might have remapped nvme devices.
1449 */
1450 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1451 pci_resource_len(pdev, bar) < SZ_512K ||
1452 bar != AHCI_PCI_BAR_STANDARD ||
1453 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1454 return;
1455
1456 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1457 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1458 if ((cap & (1 << i)) == 0)
1459 continue;
1460 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1461 != PCI_CLASS_STORAGE_EXPRESS)
1462 continue;
1463
1464 /* We've found a remapped device */
1465 count++;
1466 }
1467
1468 if (!count)
1469 return;
1470
1471 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
9b026116
CH		 1472 dev_warn(&pdev->dev,
1473 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1474
1475 /*
1476 * Don't rely on the msi-x capability in the remap case,
1477 * share the legacy interrupt across ahci and remapped devices.
1478 */
1479 hpriv->flags |= AHCI_HFLAG_NO_MSI;
aecec8b6
CH		 1480}
1481
0b9e2988 1482static int ahci_get_irq_vector(struct ata_host *host, int port)
5ca72c4f 1483{
0b9e2988 1484 return pci_irq_vector(to_pci_dev(host->dev), port);
ee2aad42
RR		 1485}
1486
a1c82311
RR		 1487static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1488 struct ahci_host_priv *hpriv)
5ca72c4f 1489{
0b9e2988 1490 int nvec;
5ca72c4f 1491
7b92b4f6 1492 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
a1c82311 1493 return -ENODEV;
7b92b4f6 1494
7b92b4f6
AG		 1495 /*
1496 * If number of MSIs is less than number of ports then Sharing Last
1497 * Message mode could be enforced. In this case assume that advantage
1498 * of multipe MSIs is negated and use single MSI mode instead.
1499 */
17a51f12
CH		 1500 if (n_ports > 1) {
1501 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1502 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1503 if (nvec > 0) {
1504 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1505 hpriv->get_irq_vector = ahci_get_irq_vector;
1506 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1507 return nvec;
1508 }
5ca72c4f 1509
17a51f12
CH		 1510 /*
1511 * Fallback to single MSI mode if the controller
1512 * enforced MRSM mode.
1513 */
1514 printk(KERN_INFO
1515 "ahci: MRSM is on, fallback to single MSI\n");
1516 pci_free_irq_vectors(pdev);
1517 }
a478b097 1518 }
d684a90d 1519
0b9e2988
CH		 1520 /*
1521 * If the host is not capable of supporting per-port vectors, fall
1522 * back to single MSI before finally attempting single MSI-X.
1523 */
1524 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1525 if (nvec == 1)
ee2aad42 1526 return nvec;
0b9e2988 1527 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
5ca72c4f
AG		 1528}
1529
24dc5f33 1530static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1531{
e297d99e
TH		 1532 unsigned int board_id = ent->driver_data;
1533 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1534 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1535 struct device *dev = &pdev->dev;
1da177e4 1536 struct ahci_host_priv *hpriv;
4447d351 1537 struct ata_host *host;
c3ebd6a9 1538 int n_ports, i, rc;
318893e1 1539 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1540
1541 VPRINTK("ENTER\n");
1542
b429dd59 1543 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1544
06296a1e 1545 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1546
5b66c829
AC		 1547 /* The AHCI driver can only drive the SATA ports, the PATA driver
1548 can drive them all so if both drivers are selected make sure
1549 AHCI stays out of the way */
1550 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1551 return -ENODEV;
1552
cb85696d
JL		 1553 /* Apple BIOS on MCP89 prevents us using AHCI */
1554 if (is_mcp89_apple(pdev))
1555 ahci_mcp89_apple_enable(pdev);
c6353b45 1556
7a02267e
MN		 1557 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1558 * At the moment, we can only use the AHCI mode. Let the users know
1559 * that for SAS drives they're out of luck.
1560 */
1561 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1562 dev_info(&pdev->dev,
1563 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1564
b7ae128d 1565 /* Some devices use non-standard BARs */
318893e1
AR		 1566 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1567 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1568 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1569 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
b7ae128d
RR		 1570 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1571 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
318893e1 1572
4447d351 1573 /* acquire resources */
24dc5f33 1574 rc = pcim_enable_device(pdev);
1da177e4
LT		 1575 if (rc)
1576 return rc;
1577
c4f7792c
TH		 1578 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1579 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1580 u8 map;
1581
1582 /* ICH6s share the same PCI ID for both piix and ahci
1583 * modes. Enabling ahci mode while MAP indicates
1584 * combined mode is a bad idea. Yield to ata_piix.
1585 */
1586 pci_read_config_byte(pdev, ICH_MAP, &map);
1587 if (map & 0x3) {
a44fec1f
JP		 1588 dev_info(&pdev->dev,
1589 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1590 return -ENODEV;
1591 }
1592 }
1593
6fec8871
PB		 1594 /* AHCI controllers often implement SFF compatible interface.
1595 * Grab all PCI BARs just in case.
1596 */
1597 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1598 if (rc == -EBUSY)
1599 pcim_pin_device(pdev);
1600 if (rc)
1601 return rc;
1602
24dc5f33
TH		 1603 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1604 if (!hpriv)
1605 return -ENOMEM;
417a1a6d
TH		 1606 hpriv->flags |= (unsigned long)pi.private_data;
1607
e297d99e
TH		 1608 /* MCP65 revision A1 and A2 can't do MSI */
1609 if (board_id == board_ahci_mcp65 &&
1610 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1611 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1612
e427fe04
SH		 1613 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1614 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1615 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1616
2fcad9d2
TH		 1617 /* only some SB600s can do 64bit DMA */
1618 if (ahci_sb600_enable_64bit(pdev))
1619 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1620
318893e1 1621 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1622
aecec8b6
CH		 1623 /* detect remapped nvme devices */
1624 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1625
0cf4a7d6
JP		 1626 /* must set flag prior to save config in order to take effect */
1627 if (ahci_broken_devslp(pdev))
1628 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1629
d243bed3
TC		 1630#ifdef CONFIG_ARM64
1631 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1632 hpriv->irq_handler = ahci_thunderx_irq_handler;
1633#endif
1634
4447d351 1635 /* save initial config */
394d6e53 1636 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1637
4447d351 1638 /* prepare host */
453d3131
RH		 1639 if (hpriv->cap & HOST_CAP_NCQ) {
1640 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1641 /*
1642 * Auto-activate optimization is supposed to be
1643 * supported on all AHCI controllers indicating NCQ
1644 * capability, but it seems to be broken on some
1645 * chipsets including NVIDIAs.
1646 */
1647 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1648 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1649
1650 /*
1651 * All AHCI controllers should be forward-compatible
1652 * with the new auxiliary field. This code should be
1653 * conditionalized if any buggy AHCI controllers are
1654 * encountered.
1655 */
1656 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1657 }
1da177e4 1658
7d50b60b
TH		 1659 if (hpriv->cap & HOST_CAP_PMP)
1660 pi.flags |= ATA_FLAG_PMP;
1661
0cbb0e77 1662 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1663
1fd68434
RW		 1664 if (ahci_broken_system_poweroff(pdev)) {
1665 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1666 dev_info(&pdev->dev,
1667 "quirky BIOS, skipping spindown on poweroff\n");
1668 }
1669
9b10ae86
TH		 1670 if (ahci_broken_suspend(pdev)) {
1671 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1672 dev_warn(&pdev->dev,
1673 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1674 }
1675
5594639a
TH		 1676 if (ahci_broken_online(pdev)) {
1677 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1678 dev_info(&pdev->dev,
1679 "online status unreliable, applying workaround\n");
1680 }
1681
8bfd1743
SC		 1682
1683 /* Acer SA5-271 workaround modifies private_data */
1684 acer_sa5_271_workaround(hpriv, pdev);
1685
837f5f8f
TH		 1686 /* CAP.NP sometimes indicate the index of the last enabled
1687 * port, at other times, that of the last possible port, so
1688 * determining the maximum port number requires looking at
1689 * both CAP.NP and port_map.
1690 */
1691 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1692
1693 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1694 if (!host)
1695 return -ENOMEM;
4447d351 1696 host->private_data = hpriv;
0b9e2988
CH		 1697
1698 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1699 /* legacy intx interrupts */
1700 pci_intx(pdev, 1);
1701 }
0ce57f8a 1702 hpriv->irq = pci_irq_vector(pdev, 0);
21bfd1aa 1703
f3d7f23f 1704 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1705 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1706 else
d2782d96 1707 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1708
18f7ba4c
KCA		 1709 if (pi.flags & ATA_FLAG_EM)
1710 ahci_reset_em(host);
1711
4447d351 1712 for (i = 0; i < host->n_ports; i++) {
dab632e8 1713 struct ata_port *ap = host->ports[i];
4447d351 1714
318893e1
AR		 1715 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1716 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1717 0x100 + ap->port_no * 0x80, "port");
1718
18f7ba4c
KCA		 1719 /* set enclosure management message type */
1720 if (ap->flags & ATA_FLAG_EM)
008dbd61 1721 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1722
1723
dab632e8 1724 /* disabled/not-implemented port */
350756f6 1725 if (!(hpriv->port_map & (1 << i)))
dab632e8 1726 ap->ops = &ata_dummy_port_ops;
4447d351 1727 }
d447df14 1728
edc93052
TH		 1729 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1730 ahci_p5wdh_workaround(host);
1731
f80ae7e4
TH		 1732 /* apply gtf filter quirk */
1733 ahci_gtf_filter_workaround(host);
1734
4447d351
TH		 1735 /* initialize adapter */
1736 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1737 if (rc)
24dc5f33 1738 return rc;
1da177e4 1739
3303040d 1740 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1741 if (rc)
1742 return rc;
1da177e4 1743
781d6550 1744 ahci_pci_init_controller(host);
439fcaec 1745 ahci_pci_print_info(host);
1da177e4 1746
4447d351 1747 pci_set_master(pdev);
5ca72c4f 1748
02e53293
MW		 1749 rc = ahci_host_activate(host, &ahci_sht);
1750 if (rc)
1751 return rc;
1752
1753 pm_runtime_put_noidle(&pdev->dev);
1754 return 0;
1755}
1756
1757static void ahci_remove_one(struct pci_dev *pdev)
1758{
1759 pm_runtime_get_noresume(&pdev->dev);
1760 ata_pci_remove_one(pdev);
907f4678 1761}
1da177e4 1762
2fc75da0 1763module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1764
1765MODULE_AUTHOR("Jeff Garzik");
1766MODULE_DESCRIPTION("AHCI SATA low-level driver");
1767MODULE_LICENSE("GPL");
1768MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1769MODULE_VERSION(DRV_VERSION);
Ubuntu Artful kernel mirror