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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
af36d7f0 JG |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
19285f3c | 27 | * as Documentation/driver-api/libata.rst |
af36d7f0 JG |
28 | * |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
1da177e4 LT |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
87507cfd | 41 | #include <linux/dma-mapping.h> |
a9524a76 | 42 | #include <linux/device.h> |
edc93052 | 43 | #include <linux/dmi.h> |
5a0e3ad6 | 44 | #include <linux/gfp.h> |
ee2aad42 | 45 | #include <linux/msi.h> |
1da177e4 | 46 | #include <scsi/scsi_host.h> |
193515d5 | 47 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 48 | #include <linux/libata.h> |
aecec8b6 CH |
49 | #include <linux/ahci-remap.h> |
50 | #include <linux/io-64-nonatomic-lo-hi.h> | |
365cfa1e | 51 | #include "ahci.h" |
1da177e4 LT |
52 | |
53 | #define DRV_NAME "ahci" | |
7d50b60b | 54 | #define DRV_VERSION "3.0" |
1da177e4 | 55 | |
1da177e4 | 56 | enum { |
318893e1 | 57 | AHCI_PCI_BAR_STA2X11 = 0, |
b7ae128d | 58 | AHCI_PCI_BAR_CAVIUM = 0, |
7f9c9f8e | 59 | AHCI_PCI_BAR_ENMOTUS = 2, |
b1314e3f | 60 | AHCI_PCI_BAR_CAVIUM_GEN5 = 4, |
318893e1 | 61 | AHCI_PCI_BAR_STANDARD = 5, |
441577ef TH |
62 | }; |
63 | ||
64 | enum board_ids { | |
65 | /* board IDs by feature in alphabetical order */ | |
66 | board_ahci, | |
67 | board_ahci_ign_iferr, | |
023e1cc7 | 68 | board_ahci_mobile, |
66a7cbc3 | 69 | board_ahci_nomsi, |
67809f85 | 70 | board_ahci_noncq, |
441577ef | 71 | board_ahci_nosntf, |
5f173107 | 72 | board_ahci_yes_fbs, |
1da177e4 | 73 | |
441577ef | 74 | /* board IDs for specific chipsets in alphabetical order */ |
dbfe8ef5 | 75 | board_ahci_avn, |
441577ef | 76 | board_ahci_mcp65, |
83f2b963 TH |
77 | board_ahci_mcp77, |
78 | board_ahci_mcp89, | |
441577ef TH |
79 | board_ahci_mv, |
80 | board_ahci_sb600, | |
81 | board_ahci_sb700, /* for SB700 and SB800 */ | |
82 | board_ahci_vt8251, | |
83 | ||
84 | /* aliases */ | |
85 | board_ahci_mcp_linux = board_ahci_mcp65, | |
86 | board_ahci_mcp67 = board_ahci_mcp65, | |
87 | board_ahci_mcp73 = board_ahci_mcp65, | |
83f2b963 | 88 | board_ahci_mcp79 = board_ahci_mcp77, |
1da177e4 LT |
89 | }; |
90 | ||
2dcb407e | 91 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
02e53293 | 92 | static void ahci_remove_one(struct pci_dev *dev); |
a1efdaba TH |
93 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
94 | unsigned long deadline); | |
dbfe8ef5 DW |
95 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
96 | unsigned long deadline); | |
cb85696d JL |
97 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev); |
98 | static bool is_mcp89_apple(struct pci_dev *pdev); | |
a1efdaba TH |
99 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
100 | unsigned long deadline); | |
02e53293 MW |
101 | #ifdef CONFIG_PM |
102 | static int ahci_pci_device_runtime_suspend(struct device *dev); | |
103 | static int ahci_pci_device_runtime_resume(struct device *dev); | |
f1d848f9 MW |
104 | #ifdef CONFIG_PM_SLEEP |
105 | static int ahci_pci_device_suspend(struct device *dev); | |
106 | static int ahci_pci_device_resume(struct device *dev); | |
438ac6d5 | 107 | #endif |
02e53293 | 108 | #endif /* CONFIG_PM */ |
ad616ffb | 109 | |
fad16e7a TH |
110 | static struct scsi_host_template ahci_sht = { |
111 | AHCI_SHT("ahci"), | |
112 | }; | |
113 | ||
029cfd6b TH |
114 | static struct ata_port_operations ahci_vt8251_ops = { |
115 | .inherits = &ahci_ops, | |
a1efdaba | 116 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 117 | }; |
edc93052 | 118 | |
029cfd6b TH |
119 | static struct ata_port_operations ahci_p5wdh_ops = { |
120 | .inherits = &ahci_ops, | |
a1efdaba | 121 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
122 | }; |
123 | ||
dbfe8ef5 DW |
124 | static struct ata_port_operations ahci_avn_ops = { |
125 | .inherits = &ahci_ops, | |
126 | .hardreset = ahci_avn_hardreset, | |
127 | }; | |
128 | ||
98ac62de | 129 | static const struct ata_port_info ahci_port_info[] = { |
441577ef | 130 | /* by features */ |
facb8fa6 | 131 | [board_ahci] = { |
1188c0d8 | 132 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 133 | .pio_mask = ATA_PIO4, |
469248ab | 134 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
135 | .port_ops = &ahci_ops, |
136 | }, | |
facb8fa6 | 137 | [board_ahci_ign_iferr] = { |
441577ef | 138 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
417a1a6d | 139 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 140 | .pio_mask = ATA_PIO4, |
469248ab | 141 | .udma_mask = ATA_UDMA6, |
441577ef | 142 | .port_ops = &ahci_ops, |
bf2af2a2 | 143 | }, |
023e1cc7 HG |
144 | [board_ahci_mobile] = { |
145 | AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), | |
146 | .flags = AHCI_FLAG_COMMON, | |
147 | .pio_mask = ATA_PIO4, | |
148 | .udma_mask = ATA_UDMA6, | |
149 | .port_ops = &ahci_ops, | |
150 | }, | |
66a7cbc3 TH |
151 | [board_ahci_nomsi] = { |
152 | AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), | |
153 | .flags = AHCI_FLAG_COMMON, | |
154 | .pio_mask = ATA_PIO4, | |
155 | .udma_mask = ATA_UDMA6, | |
156 | .port_ops = &ahci_ops, | |
157 | }, | |
67809f85 LK |
158 | [board_ahci_noncq] = { |
159 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), | |
160 | .flags = AHCI_FLAG_COMMON, | |
161 | .pio_mask = ATA_PIO4, | |
162 | .udma_mask = ATA_UDMA6, | |
163 | .port_ops = &ahci_ops, | |
164 | }, | |
facb8fa6 | 165 | [board_ahci_nosntf] = { |
441577ef | 166 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), |
417a1a6d | 167 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 168 | .pio_mask = ATA_PIO4, |
469248ab | 169 | .udma_mask = ATA_UDMA6, |
41669553 TH |
170 | .port_ops = &ahci_ops, |
171 | }, | |
facb8fa6 | 172 | [board_ahci_yes_fbs] = { |
5f173107 TH |
173 | AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), |
174 | .flags = AHCI_FLAG_COMMON, | |
175 | .pio_mask = ATA_PIO4, | |
176 | .udma_mask = ATA_UDMA6, | |
177 | .port_ops = &ahci_ops, | |
178 | }, | |
441577ef | 179 | /* by chipsets */ |
dbfe8ef5 DW |
180 | [board_ahci_avn] = { |
181 | .flags = AHCI_FLAG_COMMON, | |
182 | .pio_mask = ATA_PIO4, | |
183 | .udma_mask = ATA_UDMA6, | |
184 | .port_ops = &ahci_avn_ops, | |
185 | }, | |
facb8fa6 | 186 | [board_ahci_mcp65] = { |
83f2b963 TH |
187 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | |
188 | AHCI_HFLAG_YES_NCQ), | |
ae01b249 | 189 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
83f2b963 TH |
190 | .pio_mask = ATA_PIO4, |
191 | .udma_mask = ATA_UDMA6, | |
192 | .port_ops = &ahci_ops, | |
193 | }, | |
facb8fa6 | 194 | [board_ahci_mcp77] = { |
83f2b963 TH |
195 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), |
196 | .flags = AHCI_FLAG_COMMON, | |
197 | .pio_mask = ATA_PIO4, | |
198 | .udma_mask = ATA_UDMA6, | |
199 | .port_ops = &ahci_ops, | |
200 | }, | |
facb8fa6 | 201 | [board_ahci_mcp89] = { |
83f2b963 | 202 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), |
417a1a6d | 203 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 204 | .pio_mask = ATA_PIO4, |
469248ab | 205 | .udma_mask = ATA_UDMA6, |
441577ef | 206 | .port_ops = &ahci_ops, |
55a61604 | 207 | }, |
facb8fa6 | 208 | [board_ahci_mv] = { |
417a1a6d | 209 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 210 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
9cbe056f | 211 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
14bdef98 | 212 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
213 | .udma_mask = ATA_UDMA6, |
214 | .port_ops = &ahci_ops, | |
215 | }, | |
facb8fa6 | 216 | [board_ahci_sb600] = { |
441577ef TH |
217 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
218 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | | |
219 | AHCI_HFLAG_32BIT_ONLY), | |
e39fc8c9 | 220 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 221 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 222 | .udma_mask = ATA_UDMA6, |
345347c5 | 223 | .port_ops = &ahci_pmp_retry_srst_ops, |
e39fc8c9 | 224 | }, |
facb8fa6 | 225 | [board_ahci_sb700] = { /* for SB700 and SB800 */ |
441577ef | 226 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
aa431dd3 TH |
227 | .flags = AHCI_FLAG_COMMON, |
228 | .pio_mask = ATA_PIO4, | |
229 | .udma_mask = ATA_UDMA6, | |
345347c5 | 230 | .port_ops = &ahci_pmp_retry_srst_ops, |
aa431dd3 | 231 | }, |
facb8fa6 | 232 | [board_ahci_vt8251] = { |
441577ef | 233 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
1b677afd SL |
234 | .flags = AHCI_FLAG_COMMON, |
235 | .pio_mask = ATA_PIO4, | |
236 | .udma_mask = ATA_UDMA6, | |
441577ef | 237 | .port_ops = &ahci_vt8251_ops, |
1b677afd | 238 | }, |
1da177e4 LT |
239 | }; |
240 | ||
3b7d697d | 241 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 242 | /* Intel */ |
54bb3a94 JG |
243 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
244 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
245 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
246 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
247 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 248 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
249 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
250 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
251 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
252 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff | 253 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
1b677afd | 254 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ |
7a234aff TH |
255 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
256 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
257 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
258 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
259 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
260 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
261 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
262 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
023e1cc7 HG |
263 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ |
264 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ | |
265 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ | |
266 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ | |
267 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ | |
7a234aff | 268 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
023e1cc7 | 269 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ |
d4155e6f JG |
270 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
271 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 | 272 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
b2dde6af | 273 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
16ad1ad9 | 274 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
c1f57d9b DM |
275 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
276 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ | |
adcb5308 | 277 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 278 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
023e1cc7 | 279 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ |
adcb5308 | 280 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
023e1cc7 | 281 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ |
c1f57d9b | 282 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
342decff AY |
283 | { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ |
284 | { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ | |
285 | { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ | |
286 | { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ | |
287 | { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ | |
288 | { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ | |
289 | { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ | |
290 | { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ | |
291 | { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ | |
292 | { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ | |
293 | { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ | |
294 | { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ | |
295 | { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ | |
296 | { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ | |
297 | { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ | |
298 | { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ | |
299 | { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ | |
300 | { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ | |
301 | { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ | |
302 | { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ | |
5623cab8 | 303 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
023e1cc7 | 304 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ |
5623cab8 | 305 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ |
023e1cc7 | 306 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ |
5623cab8 SH |
307 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ |
308 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ | |
992b3fb9 SH |
309 | { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ |
310 | { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ | |
311 | { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ | |
64a3903d | 312 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ |
a4a461a6 | 313 | { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ |
181e3cea | 314 | { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ |
023e1cc7 | 315 | { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ |
181e3cea SH |
316 | { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ |
317 | { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ | |
318 | { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ | |
023e1cc7 | 319 | { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ |
2cab7a4c | 320 | { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ |
ea4ace66 | 321 | { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ |
023e1cc7 | 322 | { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ |
ea4ace66 | 323 | { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ |
023e1cc7 | 324 | { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ |
ea4ace66 | 325 | { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ |
023e1cc7 | 326 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ |
ea4ace66 | 327 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ |
023e1cc7 HG |
328 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ |
329 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ | |
330 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ | |
331 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ | |
332 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ | |
333 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ | |
334 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ | |
335 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ | |
336 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ | |
29e674dd SH |
337 | { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ |
338 | { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ | |
339 | { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ | |
340 | { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ | |
341 | { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ | |
342 | { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ | |
343 | { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ | |
344 | { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ | |
dbfe8ef5 DW |
345 | { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ |
346 | { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ | |
347 | { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ | |
348 | { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ | |
349 | { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ | |
350 | { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ | |
351 | { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ | |
352 | { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ | |
efda332c JR |
353 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ |
354 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ | |
151743fd JR |
355 | { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ |
356 | { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ | |
357 | { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ | |
358 | { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ | |
359 | { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ | |
360 | { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ | |
361 | { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ | |
362 | { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ | |
1cfc7df3 | 363 | { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ |
023e1cc7 HG |
364 | { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ |
365 | { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ | |
366 | { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ | |
367 | { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ | |
1b071a09 | 368 | { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ |
023e1cc7 | 369 | { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ |
1b071a09 | 370 | { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ |
023e1cc7 | 371 | { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ |
1b071a09 | 372 | { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ |
023e1cc7 | 373 | { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ |
1b071a09 | 374 | { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ |
023e1cc7 HG |
375 | { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ |
376 | { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ | |
377 | { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ | |
378 | { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ | |
c5967b79 | 379 | { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ |
023e1cc7 | 380 | { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ |
690000b9 | 381 | { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ |
c5967b79 | 382 | { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ |
023e1cc7 | 383 | { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ |
690000b9 | 384 | { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ |
4d92f009 | 385 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c | 386 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 387 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c | 388 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ |
4d92f009 | 389 | { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 390 | { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c AY |
391 | { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ |
392 | { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ | |
4d92f009 | 393 | { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ |
4d92f009 | 394 | { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ |
f5bdd66c AY |
395 | { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ |
396 | { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ | |
e7ea95b6 | 397 | { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ |
023e1cc7 HG |
398 | { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ |
399 | { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ | |
400 | { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ | |
401 | { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ | |
fe7fa31a | 402 | |
e34bb370 TH |
403 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
404 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
405 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
1fefb8fd BH |
406 | /* JMicron 362B and 362C have an AHCI function with IDE class code */ |
407 | { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, | |
408 | { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, | |
91f15fb3 | 409 | /* May need to update quirk_jmicron_async_suspend() for additions */ |
fe7fa31a JG |
410 | |
411 | /* ATI */ | |
c65ec1c2 | 412 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
413 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
414 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
415 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
416 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
417 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
418 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a | 419 | |
e2dd90b1 | 420 | /* AMD */ |
5deab536 | 421 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
fafe5c3d | 422 | { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ |
e2dd90b1 SH |
423 | /* AMD is using RAID class only for ahci controllers */ |
424 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
425 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, | |
426 | ||
fe7fa31a | 427 | /* VIA */ |
54bb3a94 | 428 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 429 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
430 | |
431 | /* NVIDIA */ | |
e297d99e TH |
432 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
433 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
435 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
441577ef TH |
440 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ |
441 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ | |
443 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ | |
463 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ | |
475 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ | |
476 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ | |
479 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ | |
480 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ | |
487 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ | |
488 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ | |
491 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ | |
492 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ | |
494 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ | |
495 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ | |
496 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ | |
502 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ | |
509 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ | |
510 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ | |
511 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ | |
512 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ | |
515 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ | |
fe7fa31a | 516 | |
95916edd | 517 | /* SiS */ |
20e2de4a TH |
518 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
519 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
520 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 521 | |
318893e1 AR |
522 | /* ST Microelectronics */ |
523 | { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ | |
524 | ||
cd70c266 JG |
525 | /* Marvell */ |
526 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 527 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
69fd3157 | 528 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), |
10aca06c AH |
529 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
530 | .class_mask = 0xffffff, | |
5f173107 | 531 | .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ |
69fd3157 | 532 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), |
467b41c6 | 533 | .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ |
e098f5cb SG |
534 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, |
535 | PCI_VENDOR_ID_MARVELL_EXT, 0x9170), | |
536 | .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ | |
69fd3157 | 537 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), |
642d8925 | 538 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
fcce9a35 | 539 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), |
c5edfff9 MK |
540 | .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ |
541 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), | |
fcce9a35 | 542 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
69fd3157 | 543 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), |
17c60c6b | 544 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ |
754a292f AS |
545 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), |
546 | .driver_data = board_ahci_yes_fbs }, | |
a40cf3f3 JT |
547 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ |
548 | .driver_data = board_ahci_yes_fbs }, | |
69fd3157 | 549 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), |
50be5e36 | 550 | .driver_data = board_ahci_yes_fbs }, |
6d5278a6 SB |
551 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), |
552 | .driver_data = board_ahci_yes_fbs }, | |
bc869c43 HG |
553 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ |
554 | .driver_data = board_ahci_yes_fbs }, | |
555 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ | |
d2518365 | 556 | .driver_data = board_ahci_yes_fbs }, |
cd70c266 | 557 | |
c77a036b MN |
558 | /* Promise */ |
559 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
b32bfc06 | 560 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
c77a036b | 561 | |
c9703765 | 562 | /* Asmedia */ |
7b4f6eca AC |
563 | { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ |
564 | { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ | |
565 | { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ | |
566 | { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ | |
0ce968f3 SL |
567 | { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ |
568 | { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ | |
c9703765 | 569 | |
67809f85 | 570 | /* |
66a7cbc3 TH |
571 | * Samsung SSDs found on some macbooks. NCQ times out if MSI is |
572 | * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 | |
67809f85 | 573 | */ |
66a7cbc3 | 574 | { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, |
2b21ef0a | 575 | { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, |
67809f85 | 576 | |
7f9c9f8e HD |
577 | /* Enmotus */ |
578 | { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, | |
579 | ||
415ae2b5 JG |
580 | /* Generic, PCI class code for AHCI */ |
581 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 582 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 583 | |
1da177e4 LT |
584 | { } /* terminate list */ |
585 | }; | |
586 | ||
f1d848f9 MW |
587 | static const struct dev_pm_ops ahci_pci_pm_ops = { |
588 | SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) | |
02e53293 MW |
589 | SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, |
590 | ahci_pci_device_runtime_resume, NULL) | |
f1d848f9 | 591 | }; |
1da177e4 LT |
592 | |
593 | static struct pci_driver ahci_pci_driver = { | |
594 | .name = DRV_NAME, | |
595 | .id_table = ahci_pci_tbl, | |
596 | .probe = ahci_init_one, | |
02e53293 | 597 | .remove = ahci_remove_one, |
f1d848f9 MW |
598 | .driver = { |
599 | .pm = &ahci_pci_pm_ops, | |
600 | }, | |
365cfa1e | 601 | }; |
1da177e4 | 602 | |
5219d653 | 603 | #if IS_ENABLED(CONFIG_PATA_MARVELL) |
365cfa1e AV |
604 | static int marvell_enable; |
605 | #else | |
606 | static int marvell_enable = 1; | |
607 | #endif | |
608 | module_param(marvell_enable, int, 0644); | |
609 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
d28f87aa | 610 | |
9897cab0 | 611 | static int mobile_lpm_policy = -1; |
023e1cc7 HG |
612 | module_param(mobile_lpm_policy, int, 0644); |
613 | MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); | |
1da177e4 | 614 | |
365cfa1e AV |
615 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
616 | struct ahci_host_priv *hpriv) | |
617 | { | |
365cfa1e AV |
618 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
619 | dev_info(&pdev->dev, "JMB361 has only one port\n"); | |
9a23c1d6 | 620 | hpriv->force_port_map = 1; |
1da177e4 LT |
621 | } |
622 | ||
365cfa1e AV |
623 | /* |
624 | * Temporary Marvell 6145 hack: PATA port presence | |
625 | * is asserted through the standard AHCI port | |
626 | * presence register, as bit 4 (counting from 0) | |
d28f87aa | 627 | */ |
365cfa1e AV |
628 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
629 | if (pdev->device == 0x6121) | |
9a23c1d6 | 630 | hpriv->mask_port_map = 0x3; |
365cfa1e | 631 | else |
9a23c1d6 | 632 | hpriv->mask_port_map = 0xf; |
365cfa1e AV |
633 | dev_info(&pdev->dev, |
634 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
635 | } | |
1da177e4 | 636 | |
725c7b57 | 637 | ahci_save_initial_config(&pdev->dev, hpriv); |
1da177e4 LT |
638 | } |
639 | ||
365cfa1e | 640 | static int ahci_pci_reset_controller(struct ata_host *host) |
1da177e4 | 641 | { |
365cfa1e | 642 | struct pci_dev *pdev = to_pci_dev(host->dev); |
d312fefe | 643 | int rc; |
7d50b60b | 644 | |
d312fefe AB |
645 | rc = ahci_reset_controller(host); |
646 | if (rc) | |
647 | return rc; | |
1da177e4 | 648 | |
365cfa1e AV |
649 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
650 | struct ahci_host_priv *hpriv = host->private_data; | |
651 | u16 tmp16; | |
d6ef3153 | 652 | |
365cfa1e AV |
653 | /* configure PCS */ |
654 | pci_read_config_word(pdev, 0x92, &tmp16); | |
655 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { | |
656 | tmp16 |= hpriv->port_map; | |
657 | pci_write_config_word(pdev, 0x92, tmp16); | |
658 | } | |
d6ef3153 SH |
659 | } |
660 | ||
1da177e4 LT |
661 | return 0; |
662 | } | |
663 | ||
365cfa1e | 664 | static void ahci_pci_init_controller(struct ata_host *host) |
78cd52d0 | 665 | { |
365cfa1e AV |
666 | struct ahci_host_priv *hpriv = host->private_data; |
667 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
668 | void __iomem *port_mmio; | |
78cd52d0 | 669 | u32 tmp; |
365cfa1e | 670 | int mv; |
78cd52d0 | 671 | |
365cfa1e AV |
672 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
673 | if (pdev->device == 0x6121) | |
674 | mv = 2; | |
675 | else | |
676 | mv = 4; | |
677 | port_mmio = __ahci_port_base(host, mv); | |
78cd52d0 | 678 | |
365cfa1e | 679 | writel(0, port_mmio + PORT_IRQ_MASK); |
78cd52d0 | 680 | |
365cfa1e AV |
681 | /* clear port IRQ */ |
682 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
683 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
684 | if (tmp) | |
685 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
78cd52d0 TH |
686 | } |
687 | ||
365cfa1e | 688 | ahci_init_controller(host); |
edc93052 TH |
689 | } |
690 | ||
365cfa1e AV |
691 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
692 | unsigned long deadline) | |
d6ef3153 | 693 | { |
365cfa1e | 694 | struct ata_port *ap = link->ap; |
039ece38 | 695 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e | 696 | bool online; |
d6ef3153 SH |
697 | int rc; |
698 | ||
365cfa1e | 699 | DPRINTK("ENTER\n"); |
d6ef3153 | 700 | |
76ff34cf | 701 | hpriv->stop_engine(ap); |
d6ef3153 | 702 | |
365cfa1e AV |
703 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
704 | deadline, &online, NULL); | |
d6ef3153 | 705 | |
039ece38 | 706 | hpriv->start_engine(ap); |
d6ef3153 | 707 | |
365cfa1e | 708 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
d6ef3153 | 709 | |
365cfa1e AV |
710 | /* vt8251 doesn't clear BSY on signature FIS reception, |
711 | * request follow-up softreset. | |
712 | */ | |
713 | return online ? -EAGAIN : rc; | |
7d50b60b TH |
714 | } |
715 | ||
365cfa1e AV |
716 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
717 | unsigned long deadline) | |
7d50b60b | 718 | { |
365cfa1e | 719 | struct ata_port *ap = link->ap; |
1c954a4d | 720 | struct ahci_port_priv *pp = ap->private_data; |
039ece38 | 721 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
722 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
723 | struct ata_taskfile tf; | |
724 | bool online; | |
725 | int rc; | |
7d50b60b | 726 | |
76ff34cf | 727 | hpriv->stop_engine(ap); |
028a2596 | 728 | |
365cfa1e AV |
729 | /* clear D2H reception area to properly wait for D2H FIS */ |
730 | ata_tf_init(link->device, &tf); | |
9bbb1b0e | 731 | tf.command = ATA_BUSY; |
365cfa1e | 732 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
7d50b60b | 733 | |
365cfa1e AV |
734 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
735 | deadline, &online, NULL); | |
028a2596 | 736 | |
039ece38 | 737 | hpriv->start_engine(ap); |
c1332875 | 738 | |
365cfa1e AV |
739 | /* The pseudo configuration device on SIMG4726 attached to |
740 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
741 | * hardreset if no device is attached to the first downstream | |
742 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
743 | * work around this, wait for !BSY only briefly. If BSY isn't | |
744 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
745 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
746 | * | |
747 | * Wait for two seconds. Devices attached to downstream port | |
748 | * which can't process the following IDENTIFY after this will | |
749 | * have to be reset again. For most cases, this should | |
750 | * suffice while making probing snappish enough. | |
751 | */ | |
752 | if (online) { | |
753 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
754 | ahci_check_ready); | |
755 | if (rc) | |
756 | ahci_kick_engine(ap); | |
c1332875 | 757 | } |
c1332875 TH |
758 | return rc; |
759 | } | |
760 | ||
dbfe8ef5 DW |
761 | /* |
762 | * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. | |
763 | * | |
764 | * It has been observed with some SSDs that the timing of events in the | |
765 | * link synchronization phase can leave the port in a state that can not | |
766 | * be recovered by a SATA-hard-reset alone. The failing signature is | |
767 | * SStatus.DET stuck at 1 ("Device presence detected but Phy | |
768 | * communication not established"). It was found that unloading and | |
769 | * reloading the driver when this problem occurs allows the drive | |
770 | * connection to be recovered (DET advanced to 0x3). The critical | |
771 | * component of reloading the driver is that the port state machines are | |
772 | * reset by bouncing "port enable" in the AHCI PCS configuration | |
773 | * register. So, reproduce that effect by bouncing a port whenever we | |
774 | * see DET==1 after a reset. | |
775 | */ | |
776 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, | |
777 | unsigned long deadline) | |
778 | { | |
779 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
780 | struct ata_port *ap = link->ap; | |
781 | struct ahci_port_priv *pp = ap->private_data; | |
782 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
783 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
784 | unsigned long tmo = deadline - jiffies; | |
785 | struct ata_taskfile tf; | |
786 | bool online; | |
787 | int rc, i; | |
788 | ||
789 | DPRINTK("ENTER\n"); | |
790 | ||
76ff34cf | 791 | hpriv->stop_engine(ap); |
dbfe8ef5 DW |
792 | |
793 | for (i = 0; i < 2; i++) { | |
794 | u16 val; | |
795 | u32 sstatus; | |
796 | int port = ap->port_no; | |
797 | struct ata_host *host = ap->host; | |
798 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
799 | ||
800 | /* clear D2H reception area to properly wait for D2H FIS */ | |
801 | ata_tf_init(link->device, &tf); | |
802 | tf.command = ATA_BUSY; | |
803 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
804 | ||
805 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
806 | ahci_check_ready); | |
807 | ||
808 | if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || | |
809 | (sstatus & 0xf) != 1) | |
810 | break; | |
811 | ||
812 | ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", | |
813 | port); | |
814 | ||
815 | pci_read_config_word(pdev, 0x92, &val); | |
816 | val &= ~(1 << port); | |
817 | pci_write_config_word(pdev, 0x92, val); | |
818 | ata_msleep(ap, 1000); | |
819 | val |= 1 << port; | |
820 | pci_write_config_word(pdev, 0x92, val); | |
821 | deadline += tmo; | |
822 | } | |
823 | ||
824 | hpriv->start_engine(ap); | |
825 | ||
826 | if (online) | |
827 | *class = ahci_dev_classify(ap); | |
828 | ||
829 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
830 | return rc; | |
831 | } | |
832 | ||
833 | ||
02e53293 MW |
834 | #ifdef CONFIG_PM |
835 | static void ahci_pci_disable_interrupts(struct ata_host *host) | |
c1332875 | 836 | { |
9b10ae86 | 837 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 838 | void __iomem *mmio = hpriv->mmio; |
c1332875 TH |
839 | u32 ctl; |
840 | ||
f1d848f9 MW |
841 | /* AHCI spec rev1.1 section 8.3.3: |
842 | * Software must disable interrupts prior to requesting a | |
843 | * transition of the HBA to D3 state. | |
844 | */ | |
845 | ctl = readl(mmio + HOST_CTL); | |
846 | ctl &= ~HOST_IRQ_EN; | |
847 | writel(ctl, mmio + HOST_CTL); | |
848 | readl(mmio + HOST_CTL); /* flush */ | |
02e53293 MW |
849 | } |
850 | ||
851 | static int ahci_pci_device_runtime_suspend(struct device *dev) | |
852 | { | |
853 | struct pci_dev *pdev = to_pci_dev(dev); | |
854 | struct ata_host *host = pci_get_drvdata(pdev); | |
c1332875 | 855 | |
02e53293 MW |
856 | ahci_pci_disable_interrupts(host); |
857 | return 0; | |
858 | } | |
859 | ||
860 | static int ahci_pci_device_runtime_resume(struct device *dev) | |
861 | { | |
862 | struct pci_dev *pdev = to_pci_dev(dev); | |
863 | struct ata_host *host = pci_get_drvdata(pdev); | |
864 | int rc; | |
865 | ||
866 | rc = ahci_pci_reset_controller(host); | |
867 | if (rc) | |
868 | return rc; | |
869 | ahci_pci_init_controller(host); | |
870 | return 0; | |
871 | } | |
872 | ||
873 | #ifdef CONFIG_PM_SLEEP | |
874 | static int ahci_pci_device_suspend(struct device *dev) | |
875 | { | |
876 | struct pci_dev *pdev = to_pci_dev(dev); | |
877 | struct ata_host *host = pci_get_drvdata(pdev); | |
878 | struct ahci_host_priv *hpriv = host->private_data; | |
879 | ||
880 | if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
881 | dev_err(&pdev->dev, | |
882 | "BIOS update required for suspend/resume\n"); | |
883 | return -EIO; | |
884 | } | |
885 | ||
886 | ahci_pci_disable_interrupts(host); | |
f1d848f9 | 887 | return ata_host_suspend(host, PMSG_SUSPEND); |
c1332875 TH |
888 | } |
889 | ||
f1d848f9 | 890 | static int ahci_pci_device_resume(struct device *dev) |
c1332875 | 891 | { |
f1d848f9 | 892 | struct pci_dev *pdev = to_pci_dev(dev); |
0a86e1c8 | 893 | struct ata_host *host = pci_get_drvdata(pdev); |
c1332875 TH |
894 | int rc; |
895 | ||
cb85696d JL |
896 | /* Apple BIOS helpfully mangles the registers on resume */ |
897 | if (is_mcp89_apple(pdev)) | |
898 | ahci_mcp89_apple_enable(pdev); | |
899 | ||
c1332875 | 900 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
3303040d | 901 | rc = ahci_pci_reset_controller(host); |
c1332875 TH |
902 | if (rc) |
903 | return rc; | |
904 | ||
781d6550 | 905 | ahci_pci_init_controller(host); |
c1332875 TH |
906 | } |
907 | ||
cca3974e | 908 | ata_host_resume(host); |
c1332875 TH |
909 | |
910 | return 0; | |
911 | } | |
438ac6d5 | 912 | #endif |
c1332875 | 913 | |
02e53293 MW |
914 | #endif /* CONFIG_PM */ |
915 | ||
4447d351 | 916 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 917 | { |
1da177e4 | 918 | int rc; |
1da177e4 | 919 | |
318893e1 AR |
920 | /* |
921 | * If the device fixup already set the dma_mask to some non-standard | |
922 | * value, don't extend it here. This happens on STA2X11, for example. | |
923 | */ | |
924 | if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) | |
925 | return 0; | |
926 | ||
1da177e4 | 927 | if (using_dac && |
c54c719b QL |
928 | !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
929 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
1da177e4 | 930 | if (rc) { |
c54c719b | 931 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 932 | if (rc) { |
a44fec1f JP |
933 | dev_err(&pdev->dev, |
934 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
935 | return rc; |
936 | } | |
937 | } | |
1da177e4 | 938 | } else { |
c54c719b | 939 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 940 | if (rc) { |
a44fec1f | 941 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
1da177e4 LT |
942 | return rc; |
943 | } | |
c54c719b | 944 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 945 | if (rc) { |
a44fec1f JP |
946 | dev_err(&pdev->dev, |
947 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
948 | return rc; |
949 | } | |
950 | } | |
1da177e4 LT |
951 | return 0; |
952 | } | |
953 | ||
439fcaec AV |
954 | static void ahci_pci_print_info(struct ata_host *host) |
955 | { | |
956 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
957 | u16 cc; | |
958 | const char *scc_s; | |
959 | ||
960 | pci_read_config_word(pdev, 0x0a, &cc); | |
961 | if (cc == PCI_CLASS_STORAGE_IDE) | |
962 | scc_s = "IDE"; | |
963 | else if (cc == PCI_CLASS_STORAGE_SATA) | |
964 | scc_s = "SATA"; | |
965 | else if (cc == PCI_CLASS_STORAGE_RAID) | |
966 | scc_s = "RAID"; | |
967 | else | |
968 | scc_s = "unknown"; | |
969 | ||
970 | ahci_print_info(host, scc_s); | |
971 | } | |
972 | ||
edc93052 TH |
973 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
974 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
975 | * support PMP and the 4726 either directly exports the device | |
976 | * attached to the first downstream port or acts as a hardware storage | |
977 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
978 | * other configuration). | |
979 | * | |
980 | * When there's no device attached to the first downstream port of the | |
981 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
982 | * configure the 4726. However, ATA emulation of the device is very | |
983 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
984 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
985 | * | |
986 | * The following function works around the problem by always using | |
987 | * hardreset on the port and not depending on receiving signature FIS | |
988 | * afterward. If signature FIS isn't received soon, ATA class is | |
989 | * assumed without follow-up softreset. | |
990 | */ | |
991 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
992 | { | |
1bd06867 | 993 | static const struct dmi_system_id sysids[] = { |
edc93052 TH |
994 | { |
995 | .ident = "P5W DH Deluxe", | |
996 | .matches = { | |
997 | DMI_MATCH(DMI_SYS_VENDOR, | |
998 | "ASUSTEK COMPUTER INC"), | |
999 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
1000 | }, | |
1001 | }, | |
1002 | { } | |
1003 | }; | |
1004 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1005 | ||
1006 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
1007 | dmi_check_system(sysids)) { | |
1008 | struct ata_port *ap = host->ports[1]; | |
1009 | ||
a44fec1f JP |
1010 | dev_info(&pdev->dev, |
1011 | "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); | |
edc93052 TH |
1012 | |
1013 | ap->ops = &ahci_p5wdh_ops; | |
1014 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
1015 | } | |
1016 | } | |
1017 | ||
cb85696d JL |
1018 | /* |
1019 | * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when | |
1020 | * booting in BIOS compatibility mode. We restore the registers but not ID. | |
1021 | */ | |
1022 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev) | |
1023 | { | |
1024 | u32 val; | |
1025 | ||
1026 | printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); | |
1027 | ||
1028 | pci_read_config_dword(pdev, 0xf8, &val); | |
1029 | val |= 1 << 0x1b; | |
1030 | /* the following changes the device ID, but appears not to affect function */ | |
1031 | /* val = (val & ~0xf0000000) | 0x80000000; */ | |
1032 | pci_write_config_dword(pdev, 0xf8, val); | |
1033 | ||
1034 | pci_read_config_dword(pdev, 0x54c, &val); | |
1035 | val |= 1 << 0xc; | |
1036 | pci_write_config_dword(pdev, 0x54c, val); | |
1037 | ||
1038 | pci_read_config_dword(pdev, 0x4a4, &val); | |
1039 | val &= 0xff; | |
1040 | val |= 0x01060100; | |
1041 | pci_write_config_dword(pdev, 0x4a4, val); | |
1042 | ||
1043 | pci_read_config_dword(pdev, 0x54c, &val); | |
1044 | val &= ~(1 << 0xc); | |
1045 | pci_write_config_dword(pdev, 0x54c, val); | |
1046 | ||
1047 | pci_read_config_dword(pdev, 0xf8, &val); | |
1048 | val &= ~(1 << 0x1b); | |
1049 | pci_write_config_dword(pdev, 0xf8, val); | |
1050 | } | |
1051 | ||
1052 | static bool is_mcp89_apple(struct pci_dev *pdev) | |
1053 | { | |
1054 | return pdev->vendor == PCI_VENDOR_ID_NVIDIA && | |
1055 | pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && | |
1056 | pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
1057 | pdev->subsystem_device == 0xcb89; | |
1058 | } | |
1059 | ||
2fcad9d2 TH |
1060 | /* only some SB600 ahci controllers can do 64bit DMA */ |
1061 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) | |
58a09b38 SH |
1062 | { |
1063 | static const struct dmi_system_id sysids[] = { | |
03d783bf TH |
1064 | /* |
1065 | * The oldest version known to be broken is 0901 and | |
1066 | * working is 1501 which was released on 2007-10-26. | |
2fcad9d2 TH |
1067 | * Enable 64bit DMA on 1501 and anything newer. |
1068 | * | |
03d783bf TH |
1069 | * Please read bko#9412 for more info. |
1070 | */ | |
58a09b38 SH |
1071 | { |
1072 | .ident = "ASUS M2A-VM", | |
1073 | .matches = { | |
1074 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1075 | "ASUSTeK Computer INC."), | |
1076 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), | |
1077 | }, | |
03d783bf | 1078 | .driver_data = "20071026", /* yyyymmdd */ |
58a09b38 | 1079 | }, |
e65cc194 MN |
1080 | /* |
1081 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) | |
1082 | * support 64bit DMA. | |
1083 | * | |
1084 | * BIOS versions earlier than 1.5 had the Manufacturer DMI | |
1085 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". | |
1086 | * This spelling mistake was fixed in BIOS version 1.5, so | |
1087 | * 1.5 and later have the Manufacturer as | |
1088 | * "MICRO-STAR INTERNATIONAL CO.,LTD". | |
1089 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". | |
1090 | * | |
1091 | * BIOS versions earlier than 1.9 had a Board Product Name | |
1092 | * DMI field of "MS-7376". This was changed to be | |
1093 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still | |
1094 | * match on DMI_BOARD_NAME of "MS-7376". | |
1095 | */ | |
1096 | { | |
1097 | .ident = "MSI K9A2 Platinum", | |
1098 | .matches = { | |
1099 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1100 | "MICRO-STAR INTER"), | |
1101 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), | |
1102 | }, | |
1103 | }, | |
ff0173c1 MN |
1104 | /* |
1105 | * All BIOS versions for the MSI K9AGM2 (MS-7327) support | |
1106 | * 64bit DMA. | |
1107 | * | |
1108 | * This board also had the typo mentioned above in the | |
1109 | * Manufacturer DMI field (fixed in BIOS version 1.5), so | |
1110 | * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. | |
1111 | */ | |
1112 | { | |
1113 | .ident = "MSI K9AGM2", | |
1114 | .matches = { | |
1115 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1116 | "MICRO-STAR INTER"), | |
1117 | DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), | |
1118 | }, | |
1119 | }, | |
3c4aa91f MN |
1120 | /* |
1121 | * All BIOS versions for the Asus M3A support 64bit DMA. | |
1122 | * (all release versions from 0301 to 1206 were tested) | |
1123 | */ | |
1124 | { | |
1125 | .ident = "ASUS M3A", | |
1126 | .matches = { | |
1127 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1128 | "ASUSTeK Computer INC."), | |
1129 | DMI_MATCH(DMI_BOARD_NAME, "M3A"), | |
1130 | }, | |
1131 | }, | |
58a09b38 SH |
1132 | { } |
1133 | }; | |
03d783bf | 1134 | const struct dmi_system_id *match; |
2fcad9d2 TH |
1135 | int year, month, date; |
1136 | char buf[9]; | |
58a09b38 | 1137 | |
03d783bf | 1138 | match = dmi_first_match(sysids); |
58a09b38 | 1139 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
03d783bf | 1140 | !match) |
58a09b38 SH |
1141 | return false; |
1142 | ||
e65cc194 MN |
1143 | if (!match->driver_data) |
1144 | goto enable_64bit; | |
1145 | ||
2fcad9d2 TH |
1146 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1147 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
03d783bf | 1148 | |
e65cc194 MN |
1149 | if (strcmp(buf, match->driver_data) >= 0) |
1150 | goto enable_64bit; | |
1151 | else { | |
a44fec1f JP |
1152 | dev_warn(&pdev->dev, |
1153 | "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", | |
1154 | match->ident); | |
2fcad9d2 TH |
1155 | return false; |
1156 | } | |
e65cc194 MN |
1157 | |
1158 | enable_64bit: | |
a44fec1f | 1159 | dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); |
e65cc194 | 1160 | return true; |
58a09b38 SH |
1161 | } |
1162 | ||
1fd68434 RW |
1163 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
1164 | { | |
1165 | static const struct dmi_system_id broken_systems[] = { | |
1166 | { | |
1167 | .ident = "HP Compaq nx6310", | |
1168 | .matches = { | |
1169 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1170 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
1171 | }, | |
1172 | /* PCI slot number of the controller */ | |
1173 | .driver_data = (void *)0x1FUL, | |
1174 | }, | |
d2f9c061 MR |
1175 | { |
1176 | .ident = "HP Compaq 6720s", | |
1177 | .matches = { | |
1178 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1179 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
1180 | }, | |
1181 | /* PCI slot number of the controller */ | |
1182 | .driver_data = (void *)0x1FUL, | |
1183 | }, | |
1fd68434 RW |
1184 | |
1185 | { } /* terminate list */ | |
1186 | }; | |
1187 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1188 | ||
1189 | if (dmi) { | |
1190 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1191 | /* apply the quirk only to on-board controllers */ | |
1192 | return slot == PCI_SLOT(pdev->devfn); | |
1193 | } | |
1194 | ||
1195 | return false; | |
1196 | } | |
1197 | ||
9b10ae86 TH |
1198 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
1199 | { | |
1200 | static const struct dmi_system_id sysids[] = { | |
1201 | /* | |
1202 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
1203 | * to the harddisk doesn't become online after | |
1204 | * resuming from STR. Warn and fail suspend. | |
9deb3431 TH |
1205 | * |
1206 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 | |
1207 | * | |
1208 | * Use dates instead of versions to match as HP is | |
1209 | * apparently recycling both product and version | |
1210 | * strings. | |
1211 | * | |
1212 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 | |
9b10ae86 TH |
1213 | */ |
1214 | { | |
1215 | .ident = "dv4", | |
1216 | .matches = { | |
1217 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1218 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1219 | "HP Pavilion dv4 Notebook PC"), | |
1220 | }, | |
9deb3431 | 1221 | .driver_data = "20090105", /* F.30 */ |
9b10ae86 TH |
1222 | }, |
1223 | { | |
1224 | .ident = "dv5", | |
1225 | .matches = { | |
1226 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1227 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1228 | "HP Pavilion dv5 Notebook PC"), | |
1229 | }, | |
9deb3431 | 1230 | .driver_data = "20090506", /* F.16 */ |
9b10ae86 TH |
1231 | }, |
1232 | { | |
1233 | .ident = "dv6", | |
1234 | .matches = { | |
1235 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1236 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1237 | "HP Pavilion dv6 Notebook PC"), | |
1238 | }, | |
9deb3431 | 1239 | .driver_data = "20090423", /* F.21 */ |
9b10ae86 TH |
1240 | }, |
1241 | { | |
1242 | .ident = "HDX18", | |
1243 | .matches = { | |
1244 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1245 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1246 | "HP HDX18 Notebook PC"), | |
1247 | }, | |
9deb3431 | 1248 | .driver_data = "20090430", /* F.23 */ |
9b10ae86 | 1249 | }, |
cedc9bf9 TH |
1250 | /* |
1251 | * Acer eMachines G725 has the same problem. BIOS | |
1252 | * V1.03 is known to be broken. V3.04 is known to | |
25985edc | 1253 | * work. Between, there are V1.06, V2.06 and V3.03 |
cedc9bf9 TH |
1254 | * that we don't have much idea about. For now, |
1255 | * blacklist anything older than V3.04. | |
9deb3431 TH |
1256 | * |
1257 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 | |
cedc9bf9 TH |
1258 | */ |
1259 | { | |
1260 | .ident = "G725", | |
1261 | .matches = { | |
1262 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), | |
1263 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), | |
1264 | }, | |
9deb3431 | 1265 | .driver_data = "20091216", /* V3.04 */ |
cedc9bf9 | 1266 | }, |
9b10ae86 TH |
1267 | { } /* terminate list */ |
1268 | }; | |
1269 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
9deb3431 TH |
1270 | int year, month, date; |
1271 | char buf[9]; | |
9b10ae86 TH |
1272 | |
1273 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
1274 | return false; | |
1275 | ||
9deb3431 TH |
1276 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1277 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
9b10ae86 | 1278 | |
9deb3431 | 1279 | return strcmp(buf, dmi->driver_data) < 0; |
9b10ae86 TH |
1280 | } |
1281 | ||
069f8827 HG |
1282 | static bool ahci_broken_lpm(struct pci_dev *pdev) |
1283 | { | |
1284 | static const struct dmi_system_id sysids[] = { | |
1285 | /* Various Lenovo 50 series have LPM issues with older BIOSen */ | |
1286 | { | |
1287 | .matches = { | |
1288 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1289 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), | |
1290 | }, | |
1291 | .driver_data = "20180406", /* 1.31 */ | |
1292 | }, | |
1293 | { | |
1294 | .matches = { | |
1295 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1296 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), | |
1297 | }, | |
1298 | .driver_data = "20180420", /* 1.28 */ | |
1299 | }, | |
1300 | { | |
1301 | .matches = { | |
1302 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1303 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), | |
1304 | }, | |
1305 | .driver_data = "20180315", /* 1.33 */ | |
1306 | }, | |
1307 | { | |
1308 | .matches = { | |
1309 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1310 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), | |
1311 | }, | |
1312 | /* | |
1313 | * Note date based on release notes, 2.35 has been | |
1314 | * reported to be good, but I've been unable to get | |
1315 | * a hold of the reporter to get the DMI BIOS date. | |
1316 | * TODO: fix this. | |
1317 | */ | |
1318 | .driver_data = "20180310", /* 2.35 */ | |
1319 | }, | |
1320 | { } /* terminate list */ | |
1321 | }; | |
1322 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1323 | int year, month, date; | |
1324 | char buf[9]; | |
1325 | ||
1326 | if (!dmi) | |
1327 | return false; | |
1328 | ||
1329 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); | |
1330 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
1331 | ||
1332 | return strcmp(buf, dmi->driver_data) < 0; | |
1333 | } | |
1334 | ||
5594639a TH |
1335 | static bool ahci_broken_online(struct pci_dev *pdev) |
1336 | { | |
1337 | #define ENCODE_BUSDEVFN(bus, slot, func) \ | |
1338 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) | |
1339 | static const struct dmi_system_id sysids[] = { | |
1340 | /* | |
1341 | * There are several gigabyte boards which use | |
1342 | * SIMG5723s configured as hardware RAID. Certain | |
1343 | * 5723 firmware revisions shipped there keep the link | |
1344 | * online but fail to answer properly to SRST or | |
1345 | * IDENTIFY when no device is attached downstream | |
1346 | * causing libata to retry quite a few times leading | |
1347 | * to excessive detection delay. | |
1348 | * | |
1349 | * As these firmwares respond to the second reset try | |
1350 | * with invalid device signature, considering unknown | |
1351 | * sig as offline works around the problem acceptably. | |
1352 | */ | |
1353 | { | |
1354 | .ident = "EP45-DQ6", | |
1355 | .matches = { | |
1356 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1357 | "Gigabyte Technology Co., Ltd."), | |
1358 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), | |
1359 | }, | |
1360 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), | |
1361 | }, | |
1362 | { | |
1363 | .ident = "EP45-DS5", | |
1364 | .matches = { | |
1365 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1366 | "Gigabyte Technology Co., Ltd."), | |
1367 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), | |
1368 | }, | |
1369 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), | |
1370 | }, | |
1371 | { } /* terminate list */ | |
1372 | }; | |
1373 | #undef ENCODE_BUSDEVFN | |
1374 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1375 | unsigned int val; | |
1376 | ||
1377 | if (!dmi) | |
1378 | return false; | |
1379 | ||
1380 | val = (unsigned long)dmi->driver_data; | |
1381 | ||
1382 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); | |
1383 | } | |
1384 | ||
0cf4a7d6 JP |
1385 | static bool ahci_broken_devslp(struct pci_dev *pdev) |
1386 | { | |
1387 | /* device with broken DEVSLP but still showing SDS capability */ | |
1388 | static const struct pci_device_id ids[] = { | |
1389 | { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ | |
1390 | {} | |
1391 | }; | |
1392 | ||
1393 | return pci_match_id(ids, pdev); | |
1394 | } | |
1395 | ||
8e513217 | 1396 | #ifdef CONFIG_ATA_ACPI |
f80ae7e4 TH |
1397 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
1398 | { | |
1399 | static const struct dmi_system_id sysids[] = { | |
1400 | /* | |
1401 | * Aspire 3810T issues a bunch of SATA enable commands | |
1402 | * via _GTF including an invalid one and one which is | |
1403 | * rejected by the device. Among the successful ones | |
1404 | * is FPDMA non-zero offset enable which when enabled | |
1405 | * only on the drive side leads to NCQ command | |
1406 | * failures. Filter it out. | |
1407 | */ | |
1408 | { | |
1409 | .ident = "Aspire 3810T", | |
1410 | .matches = { | |
1411 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1412 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), | |
1413 | }, | |
1414 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, | |
1415 | }, | |
1416 | { } | |
1417 | }; | |
1418 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1419 | unsigned int filter; | |
1420 | int i; | |
1421 | ||
1422 | if (!dmi) | |
1423 | return; | |
1424 | ||
1425 | filter = (unsigned long)dmi->driver_data; | |
a44fec1f JP |
1426 | dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", |
1427 | filter, dmi->ident); | |
f80ae7e4 TH |
1428 | |
1429 | for (i = 0; i < host->n_ports; i++) { | |
1430 | struct ata_port *ap = host->ports[i]; | |
1431 | struct ata_link *link; | |
1432 | struct ata_device *dev; | |
1433 | ||
1434 | ata_for_each_link(link, ap, EDGE) | |
1435 | ata_for_each_dev(dev, link, ALL) | |
1436 | dev->gtf_filter |= filter; | |
1437 | } | |
1438 | } | |
8e513217 MT |
1439 | #else |
1440 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) | |
1441 | {} | |
1442 | #endif | |
f80ae7e4 | 1443 | |
8bfd1743 SC |
1444 | /* |
1445 | * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected | |
1446 | * as DUMMY, or detected but eventually get a "link down" and never get up | |
1447 | * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the | |
1448 | * port_map may hold a value of 0x00. | |
1449 | * | |
1450 | * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports | |
1451 | * and can significantly reduce the occurrence of the problem. | |
1452 | * | |
1453 | * https://bugzilla.kernel.org/show_bug.cgi?id=189471 | |
1454 | */ | |
1455 | static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, | |
1456 | struct pci_dev *pdev) | |
1457 | { | |
1458 | static const struct dmi_system_id sysids[] = { | |
1459 | { | |
1460 | .ident = "Acer Switch Alpha 12", | |
1461 | .matches = { | |
1462 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1463 | DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") | |
1464 | }, | |
1465 | }, | |
1466 | { } | |
1467 | }; | |
1468 | ||
1469 | if (dmi_check_system(sysids)) { | |
1470 | dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); | |
1471 | if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { | |
1472 | hpriv->port_map = 0x7; | |
1473 | hpriv->cap = 0xC734FF02; | |
1474 | } | |
1475 | } | |
1476 | } | |
1477 | ||
d243bed3 TC |
1478 | #ifdef CONFIG_ARM64 |
1479 | /* | |
1480 | * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. | |
1481 | * Workaround is to make sure all pending IRQs are served before leaving | |
1482 | * handler. | |
1483 | */ | |
1484 | static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) | |
1485 | { | |
1486 | struct ata_host *host = dev_instance; | |
1487 | struct ahci_host_priv *hpriv; | |
1488 | unsigned int rc = 0; | |
1489 | void __iomem *mmio; | |
1490 | u32 irq_stat, irq_masked; | |
1491 | unsigned int handled = 1; | |
1492 | ||
1493 | VPRINTK("ENTER\n"); | |
1494 | hpriv = host->private_data; | |
1495 | mmio = hpriv->mmio; | |
1496 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1497 | if (!irq_stat) | |
1498 | return IRQ_NONE; | |
1499 | ||
1500 | do { | |
1501 | irq_masked = irq_stat & hpriv->port_map; | |
1502 | spin_lock(&host->lock); | |
1503 | rc = ahci_handle_port_intr(host, irq_masked); | |
1504 | if (!rc) | |
1505 | handled = 0; | |
1506 | writel(irq_stat, mmio + HOST_IRQ_STAT); | |
1507 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1508 | spin_unlock(&host->lock); | |
1509 | } while (irq_stat); | |
1510 | VPRINTK("EXIT\n"); | |
1511 | ||
1512 | return IRQ_RETVAL(handled); | |
1513 | } | |
1514 | #endif | |
1515 | ||
aecec8b6 CH |
1516 | static void ahci_remap_check(struct pci_dev *pdev, int bar, |
1517 | struct ahci_host_priv *hpriv) | |
1518 | { | |
1519 | int i, count = 0; | |
1520 | u32 cap; | |
1521 | ||
1522 | /* | |
1523 | * Check if this device might have remapped nvme devices. | |
1524 | */ | |
1525 | if (pdev->vendor != PCI_VENDOR_ID_INTEL || | |
1526 | pci_resource_len(pdev, bar) < SZ_512K || | |
1527 | bar != AHCI_PCI_BAR_STANDARD || | |
1528 | !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) | |
1529 | return; | |
1530 | ||
1531 | cap = readq(hpriv->mmio + AHCI_REMAP_CAP); | |
1532 | for (i = 0; i < AHCI_MAX_REMAP; i++) { | |
1533 | if ((cap & (1 << i)) == 0) | |
1534 | continue; | |
1535 | if (readl(hpriv->mmio + ahci_remap_dcc(i)) | |
1536 | != PCI_CLASS_STORAGE_EXPRESS) | |
1537 | continue; | |
1538 | ||
1539 | /* We've found a remapped device */ | |
1540 | count++; | |
1541 | } | |
1542 | ||
1543 | if (!count) | |
1544 | return; | |
1545 | ||
1546 | dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); | |
f723fa4e CH |
1547 | dev_warn(&pdev->dev, |
1548 | "Switch your BIOS from RAID to AHCI mode to use them.\n"); | |
1549 | ||
1550 | /* | |
1551 | * Don't rely on the msi-x capability in the remap case, | |
1552 | * share the legacy interrupt across ahci and remapped devices. | |
1553 | */ | |
1554 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
aecec8b6 CH |
1555 | } |
1556 | ||
0b9e2988 | 1557 | static int ahci_get_irq_vector(struct ata_host *host, int port) |
5ca72c4f | 1558 | { |
0b9e2988 | 1559 | return pci_irq_vector(to_pci_dev(host->dev), port); |
ee2aad42 RR |
1560 | } |
1561 | ||
a1c82311 RR |
1562 | static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, |
1563 | struct ahci_host_priv *hpriv) | |
5ca72c4f | 1564 | { |
0b9e2988 | 1565 | int nvec; |
5ca72c4f | 1566 | |
7b92b4f6 | 1567 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
a1c82311 | 1568 | return -ENODEV; |
7b92b4f6 | 1569 | |
7b92b4f6 AG |
1570 | /* |
1571 | * If number of MSIs is less than number of ports then Sharing Last | |
1572 | * Message mode could be enforced. In this case assume that advantage | |
1573 | * of multipe MSIs is negated and use single MSI mode instead. | |
1574 | */ | |
17a51f12 CH |
1575 | if (n_ports > 1) { |
1576 | nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, | |
1577 | PCI_IRQ_MSIX | PCI_IRQ_MSI); | |
1578 | if (nvec > 0) { | |
1579 | if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { | |
1580 | hpriv->get_irq_vector = ahci_get_irq_vector; | |
1581 | hpriv->flags |= AHCI_HFLAG_MULTI_MSI; | |
1582 | return nvec; | |
1583 | } | |
5ca72c4f | 1584 | |
17a51f12 CH |
1585 | /* |
1586 | * Fallback to single MSI mode if the controller | |
1587 | * enforced MRSM mode. | |
1588 | */ | |
1589 | printk(KERN_INFO | |
1590 | "ahci: MRSM is on, fallback to single MSI\n"); | |
1591 | pci_free_irq_vectors(pdev); | |
1592 | } | |
a478b097 | 1593 | } |
d684a90d | 1594 | |
0b9e2988 CH |
1595 | /* |
1596 | * If the host is not capable of supporting per-port vectors, fall | |
1597 | * back to single MSI before finally attempting single MSI-X. | |
1598 | */ | |
1599 | nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); | |
1600 | if (nvec == 1) | |
ee2aad42 | 1601 | return nvec; |
0b9e2988 | 1602 | return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); |
5ca72c4f AG |
1603 | } |
1604 | ||
9897cab0 SP |
1605 | static void ahci_update_initial_lpm_policy(struct ata_port *ap, |
1606 | struct ahci_host_priv *hpriv) | |
1607 | { | |
1608 | int policy = CONFIG_SATA_MOBILE_LPM_POLICY; | |
1609 | ||
1610 | ||
1611 | /* Ignore processing for non mobile platforms */ | |
1612 | if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) | |
1613 | return; | |
1614 | ||
1615 | /* user modified policy via module param */ | |
1616 | if (mobile_lpm_policy != -1) { | |
1617 | policy = mobile_lpm_policy; | |
1618 | goto update_policy; | |
1619 | } | |
1620 | ||
1621 | #ifdef CONFIG_ACPI | |
1622 | if (policy > ATA_LPM_MED_POWER && | |
1623 | (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { | |
1624 | if (hpriv->cap & HOST_CAP_PART) | |
1625 | policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; | |
1626 | else if (hpriv->cap & HOST_CAP_SSC) | |
1627 | policy = ATA_LPM_MIN_POWER; | |
1628 | } | |
1629 | #endif | |
1630 | ||
1631 | update_policy: | |
1632 | if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) | |
1633 | ap->target_lpm_policy = policy; | |
1634 | } | |
1635 | ||
24dc5f33 | 1636 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1637 | { |
e297d99e TH |
1638 | unsigned int board_id = ent->driver_data; |
1639 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 1640 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 1641 | struct device *dev = &pdev->dev; |
1da177e4 | 1642 | struct ahci_host_priv *hpriv; |
4447d351 | 1643 | struct ata_host *host; |
c3ebd6a9 | 1644 | int n_ports, i, rc; |
318893e1 | 1645 | int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; |
1da177e4 LT |
1646 | |
1647 | VPRINTK("ENTER\n"); | |
1648 | ||
b429dd59 | 1649 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
12fad3f9 | 1650 | |
06296a1e | 1651 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1652 | |
5b66c829 AC |
1653 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
1654 | can drive them all so if both drivers are selected make sure | |
1655 | AHCI stays out of the way */ | |
1656 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
1657 | return -ENODEV; | |
1658 | ||
cb85696d JL |
1659 | /* Apple BIOS on MCP89 prevents us using AHCI */ |
1660 | if (is_mcp89_apple(pdev)) | |
1661 | ahci_mcp89_apple_enable(pdev); | |
c6353b45 | 1662 | |
7a02267e MN |
1663 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
1664 | * At the moment, we can only use the AHCI mode. Let the users know | |
1665 | * that for SAS drives they're out of luck. | |
1666 | */ | |
1667 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) | |
a44fec1f JP |
1668 | dev_info(&pdev->dev, |
1669 | "PDC42819 can only drive SATA devices with this driver\n"); | |
7a02267e | 1670 | |
b7ae128d | 1671 | /* Some devices use non-standard BARs */ |
318893e1 AR |
1672 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) |
1673 | ahci_pci_bar = AHCI_PCI_BAR_STA2X11; | |
7f9c9f8e HD |
1674 | else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) |
1675 | ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; | |
b1314e3f RMC |
1676 | else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { |
1677 | if (pdev->device == 0xa01c) | |
1678 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; | |
1679 | if (pdev->device == 0xa084) | |
1680 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; | |
1681 | } | |
318893e1 | 1682 | |
4447d351 | 1683 | /* acquire resources */ |
24dc5f33 | 1684 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1685 | if (rc) |
1686 | return rc; | |
1687 | ||
c4f7792c TH |
1688 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
1689 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
1690 | u8 map; | |
1691 | ||
1692 | /* ICH6s share the same PCI ID for both piix and ahci | |
1693 | * modes. Enabling ahci mode while MAP indicates | |
1694 | * combined mode is a bad idea. Yield to ata_piix. | |
1695 | */ | |
1696 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
1697 | if (map & 0x3) { | |
a44fec1f JP |
1698 | dev_info(&pdev->dev, |
1699 | "controller is in combined mode, can't enable AHCI mode\n"); | |
c4f7792c TH |
1700 | return -ENODEV; |
1701 | } | |
1702 | } | |
1703 | ||
6fec8871 PB |
1704 | /* AHCI controllers often implement SFF compatible interface. |
1705 | * Grab all PCI BARs just in case. | |
1706 | */ | |
1707 | rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); | |
1708 | if (rc == -EBUSY) | |
1709 | pcim_pin_device(pdev); | |
1710 | if (rc) | |
1711 | return rc; | |
1712 | ||
24dc5f33 TH |
1713 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1714 | if (!hpriv) | |
1715 | return -ENOMEM; | |
417a1a6d TH |
1716 | hpriv->flags |= (unsigned long)pi.private_data; |
1717 | ||
e297d99e TH |
1718 | /* MCP65 revision A1 and A2 can't do MSI */ |
1719 | if (board_id == board_ahci_mcp65 && | |
1720 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
1721 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
1722 | ||
e427fe04 SH |
1723 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
1724 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
1725 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
1726 | ||
2fcad9d2 TH |
1727 | /* only some SB600s can do 64bit DMA */ |
1728 | if (ahci_sb600_enable_64bit(pdev)) | |
1729 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; | |
58a09b38 | 1730 | |
318893e1 | 1731 | hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; |
d8993349 | 1732 | |
aecec8b6 CH |
1733 | /* detect remapped nvme devices */ |
1734 | ahci_remap_check(pdev, ahci_pci_bar, hpriv); | |
1735 | ||
0cf4a7d6 JP |
1736 | /* must set flag prior to save config in order to take effect */ |
1737 | if (ahci_broken_devslp(pdev)) | |
1738 | hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; | |
1739 | ||
d243bed3 TC |
1740 | #ifdef CONFIG_ARM64 |
1741 | if (pdev->vendor == 0x177d && pdev->device == 0xa01c) | |
1742 | hpriv->irq_handler = ahci_thunderx_irq_handler; | |
1743 | #endif | |
1744 | ||
4447d351 | 1745 | /* save initial config */ |
394d6e53 | 1746 | ahci_pci_save_initial_config(pdev, hpriv); |
1da177e4 | 1747 | |
4447d351 | 1748 | /* prepare host */ |
453d3131 RH |
1749 | if (hpriv->cap & HOST_CAP_NCQ) { |
1750 | pi.flags |= ATA_FLAG_NCQ; | |
83f2b963 TH |
1751 | /* |
1752 | * Auto-activate optimization is supposed to be | |
1753 | * supported on all AHCI controllers indicating NCQ | |
1754 | * capability, but it seems to be broken on some | |
1755 | * chipsets including NVIDIAs. | |
1756 | */ | |
1757 | if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) | |
453d3131 | 1758 | pi.flags |= ATA_FLAG_FPDMA_AA; |
40fb59e7 MC |
1759 | |
1760 | /* | |
1761 | * All AHCI controllers should be forward-compatible | |
1762 | * with the new auxiliary field. This code should be | |
1763 | * conditionalized if any buggy AHCI controllers are | |
1764 | * encountered. | |
1765 | */ | |
1766 | pi.flags |= ATA_FLAG_FPDMA_AUX; | |
453d3131 | 1767 | } |
1da177e4 | 1768 | |
7d50b60b TH |
1769 | if (hpriv->cap & HOST_CAP_PMP) |
1770 | pi.flags |= ATA_FLAG_PMP; | |
1771 | ||
0cbb0e77 | 1772 | ahci_set_em_messages(hpriv, &pi); |
18f7ba4c | 1773 | |
1fd68434 RW |
1774 | if (ahci_broken_system_poweroff(pdev)) { |
1775 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
1776 | dev_info(&pdev->dev, | |
1777 | "quirky BIOS, skipping spindown on poweroff\n"); | |
1778 | } | |
1779 | ||
069f8827 HG |
1780 | if (ahci_broken_lpm(pdev)) { |
1781 | pi.flags |= ATA_FLAG_NO_LPM; | |
1782 | dev_warn(&pdev->dev, | |
1783 | "BIOS update required for Link Power Management support\n"); | |
1784 | } | |
1785 | ||
9b10ae86 TH |
1786 | if (ahci_broken_suspend(pdev)) { |
1787 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
a44fec1f JP |
1788 | dev_warn(&pdev->dev, |
1789 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
1790 | } |
1791 | ||
5594639a TH |
1792 | if (ahci_broken_online(pdev)) { |
1793 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; | |
1794 | dev_info(&pdev->dev, | |
1795 | "online status unreliable, applying workaround\n"); | |
1796 | } | |
1797 | ||
8bfd1743 SC |
1798 | |
1799 | /* Acer SA5-271 workaround modifies private_data */ | |
1800 | acer_sa5_271_workaround(hpriv, pdev); | |
1801 | ||
837f5f8f TH |
1802 | /* CAP.NP sometimes indicate the index of the last enabled |
1803 | * port, at other times, that of the last possible port, so | |
1804 | * determining the maximum port number requires looking at | |
1805 | * both CAP.NP and port_map. | |
1806 | */ | |
1807 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
1808 | ||
1809 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
1810 | if (!host) |
1811 | return -ENOMEM; | |
4447d351 | 1812 | host->private_data = hpriv; |
0b9e2988 CH |
1813 | |
1814 | if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { | |
1815 | /* legacy intx interrupts */ | |
1816 | pci_intx(pdev, 1); | |
1817 | } | |
0ce57f8a | 1818 | hpriv->irq = pci_irq_vector(pdev, 0); |
21bfd1aa | 1819 | |
f3d7f23f | 1820 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 1821 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f | 1822 | else |
d2782d96 | 1823 | dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); |
886ad09f | 1824 | |
18f7ba4c KCA |
1825 | if (pi.flags & ATA_FLAG_EM) |
1826 | ahci_reset_em(host); | |
1827 | ||
4447d351 | 1828 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 1829 | struct ata_port *ap = host->ports[i]; |
4447d351 | 1830 | |
318893e1 AR |
1831 | ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); |
1832 | ata_port_pbar_desc(ap, ahci_pci_bar, | |
cbcdd875 TH |
1833 | 0x100 + ap->port_no * 0x80, "port"); |
1834 | ||
18f7ba4c KCA |
1835 | /* set enclosure management message type */ |
1836 | if (ap->flags & ATA_FLAG_EM) | |
008dbd61 | 1837 | ap->em_message_type = hpriv->em_msg_type; |
18f7ba4c | 1838 | |
9897cab0 | 1839 | ahci_update_initial_lpm_policy(ap, hpriv); |
18f7ba4c | 1840 | |
dab632e8 | 1841 | /* disabled/not-implemented port */ |
350756f6 | 1842 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 1843 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 1844 | } |
d447df14 | 1845 | |
edc93052 TH |
1846 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
1847 | ahci_p5wdh_workaround(host); | |
1848 | ||
f80ae7e4 TH |
1849 | /* apply gtf filter quirk */ |
1850 | ahci_gtf_filter_workaround(host); | |
1851 | ||
4447d351 TH |
1852 | /* initialize adapter */ |
1853 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1854 | if (rc) |
24dc5f33 | 1855 | return rc; |
1da177e4 | 1856 | |
3303040d | 1857 | rc = ahci_pci_reset_controller(host); |
4447d351 TH |
1858 | if (rc) |
1859 | return rc; | |
1da177e4 | 1860 | |
781d6550 | 1861 | ahci_pci_init_controller(host); |
439fcaec | 1862 | ahci_pci_print_info(host); |
1da177e4 | 1863 | |
4447d351 | 1864 | pci_set_master(pdev); |
5ca72c4f | 1865 | |
02e53293 MW |
1866 | rc = ahci_host_activate(host, &ahci_sht); |
1867 | if (rc) | |
1868 | return rc; | |
1869 | ||
1870 | pm_runtime_put_noidle(&pdev->dev); | |
1871 | return 0; | |
1872 | } | |
1873 | ||
1874 | static void ahci_remove_one(struct pci_dev *pdev) | |
1875 | { | |
1876 | pm_runtime_get_noresume(&pdev->dev); | |
1877 | ata_pci_remove_one(pdev); | |
907f4678 | 1878 | } |
1da177e4 | 1879 | |
2fc75da0 | 1880 | module_pci_driver(ahci_pci_driver); |
1da177e4 LT |
1881 | |
1882 | MODULE_AUTHOR("Jeff Garzik"); | |
1883 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1884 | MODULE_LICENSE("GPL"); | |
1885 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1886 | MODULE_VERSION(DRV_VERSION); |