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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
a22e6444 TH |
52 | static int ahci_skip_host_reset; |
53 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); | |
54 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
55 | ||
31556594 KCA |
56 | static int ahci_enable_alpm(struct ata_port *ap, |
57 | enum link_pm policy); | |
58 | static void ahci_disable_alpm(struct ata_port *ap); | |
1da177e4 LT |
59 | |
60 | enum { | |
61 | AHCI_PCI_BAR = 5, | |
648a88be | 62 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
63 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
64 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
12fad3f9 | 65 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 66 | AHCI_CMD_SZ = 32, |
12fad3f9 | 67 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 68 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 69 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
70 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
71 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
72 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
73 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
74 | AHCI_RX_FIS_SZ, |
75 | AHCI_IRQ_ON_SG = (1 << 31), | |
76 | AHCI_CMD_ATAPI = (1 << 5), | |
77 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 78 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
79 | AHCI_CMD_RESET = (1 << 8), |
80 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
81 | |
82 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 83 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 84 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
85 | |
86 | board_ahci = 0, | |
7a234aff TH |
87 | board_ahci_vt8251 = 1, |
88 | board_ahci_ign_iferr = 2, | |
89 | board_ahci_sb600 = 3, | |
90 | board_ahci_mv = 4, | |
e39fc8c9 | 91 | board_ahci_sb700 = 5, |
1da177e4 LT |
92 | |
93 | /* global controller registers */ | |
94 | HOST_CAP = 0x00, /* host capabilities */ | |
95 | HOST_CTL = 0x04, /* global host control */ | |
96 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
97 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
98 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
99 | ||
100 | /* HOST_CTL bits */ | |
101 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
102 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
103 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
104 | ||
105 | /* HOST_CAP bits */ | |
0be0aa98 | 106 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 107 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 108 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 109 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 110 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 111 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 112 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 113 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
114 | |
115 | /* registers for each SATA port */ | |
116 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
117 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
118 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
119 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
120 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
121 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
122 | PORT_CMD = 0x18, /* port command */ | |
123 | PORT_TFDATA = 0x20, /* taskfile data */ | |
124 | PORT_SIG = 0x24, /* device TF signature */ | |
125 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
126 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
127 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
128 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
129 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 130 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
131 | |
132 | /* PORT_IRQ_{STAT,MASK} bits */ | |
133 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
134 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
135 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
136 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
137 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
138 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
139 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
140 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
141 | ||
142 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
143 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
144 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
145 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
146 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
147 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
148 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
149 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
150 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
151 | ||
78cd52d0 TH |
152 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
153 | PORT_IRQ_IF_ERR | | |
154 | PORT_IRQ_CONNECT | | |
4296971d | 155 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
156 | PORT_IRQ_UNK_FIS | |
157 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
158 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
159 | PORT_IRQ_TF_ERR | | |
160 | PORT_IRQ_HBUS_DATA_ERR, | |
161 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
162 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
163 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
164 | |
165 | /* PORT_CMD bits */ | |
31556594 KCA |
166 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
167 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 168 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 169 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
170 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
171 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
172 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 173 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
174 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
175 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
176 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
177 | ||
0be0aa98 | 178 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
179 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
180 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
181 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 182 | |
417a1a6d TH |
183 | /* hpriv->flags bits */ |
184 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
185 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
186 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
187 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
188 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
189 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 190 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 191 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
a878539e | 192 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
417a1a6d | 193 | |
bf2af2a2 | 194 | /* ap->flags bits */ |
1188c0d8 TH |
195 | |
196 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
197 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
198 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
199 | ATA_FLAG_IPM, | |
c4f7792c TH |
200 | |
201 | ICH_MAP = 0x90, /* ICH MAP register */ | |
1da177e4 LT |
202 | }; |
203 | ||
204 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
205 | __le32 opts; |
206 | __le32 status; | |
207 | __le32 tbl_addr; | |
208 | __le32 tbl_addr_hi; | |
209 | __le32 reserved[4]; | |
1da177e4 LT |
210 | }; |
211 | ||
212 | struct ahci_sg { | |
4ca4e439 AV |
213 | __le32 addr; |
214 | __le32 addr_hi; | |
215 | __le32 reserved; | |
216 | __le32 flags_size; | |
1da177e4 LT |
217 | }; |
218 | ||
219 | struct ahci_host_priv { | |
417a1a6d | 220 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
221 | u32 cap; /* cap to use */ |
222 | u32 port_map; /* port map to use */ | |
223 | u32 saved_cap; /* saved initial cap */ | |
224 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
225 | }; |
226 | ||
227 | struct ahci_port_priv { | |
7d50b60b | 228 | struct ata_link *active_link; |
1da177e4 LT |
229 | struct ahci_cmd_hdr *cmd_slot; |
230 | dma_addr_t cmd_slot_dma; | |
231 | void *cmd_tbl; | |
232 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
233 | void *rx_fis; |
234 | dma_addr_t rx_fis_dma; | |
0291f95f | 235 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
236 | unsigned int ncq_saw_d2h:1; |
237 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 238 | unsigned int ncq_saw_sdb:1; |
a7384925 | 239 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
240 | }; |
241 | ||
da3dbb17 TH |
242 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
243 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
2dcb407e | 244 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 245 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 LT |
246 | static int ahci_port_start(struct ata_port *ap); |
247 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
248 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
249 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
250 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
251 | static void ahci_freeze(struct ata_port *ap); |
252 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
253 | static void ahci_pmp_attach(struct ata_port *ap); |
254 | static void ahci_pmp_detach(struct ata_port *ap); | |
a1efdaba TH |
255 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
256 | unsigned long deadline); | |
257 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, | |
258 | unsigned long deadline); | |
259 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, | |
260 | unsigned long deadline); | |
261 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, | |
262 | unsigned long deadline); | |
263 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
264 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, | |
265 | unsigned long deadline); | |
78cd52d0 TH |
266 | static void ahci_error_handler(struct ata_port *ap); |
267 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
df69c9c5 | 268 | static int ahci_port_resume(struct ata_port *ap); |
a878539e | 269 | static void ahci_dev_config(struct ata_device *dev); |
dab632e8 JG |
270 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
271 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
272 | u32 opts); | |
438ac6d5 | 273 | #ifdef CONFIG_PM |
c1332875 | 274 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
275 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
276 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 277 | #endif |
1da177e4 | 278 | |
31556594 KCA |
279 | static struct class_device_attribute *ahci_shost_attrs[] = { |
280 | &class_device_attr_link_power_management_policy, | |
281 | NULL | |
282 | }; | |
283 | ||
193515d5 | 284 | static struct scsi_host_template ahci_sht = { |
68d1d07b | 285 | ATA_NCQ_SHT(DRV_NAME), |
12fad3f9 | 286 | .can_queue = AHCI_MAX_CMDS - 1, |
1da177e4 | 287 | .sg_tablesize = AHCI_MAX_SG, |
1da177e4 | 288 | .dma_boundary = AHCI_DMA_BOUNDARY, |
31556594 | 289 | .shost_attrs = ahci_shost_attrs, |
1da177e4 LT |
290 | }; |
291 | ||
029cfd6b TH |
292 | static struct ata_port_operations ahci_ops = { |
293 | .inherits = &sata_pmp_port_ops, | |
294 | ||
5682ed33 TH |
295 | .sff_check_status = ahci_check_status, |
296 | .sff_check_altstatus = ahci_check_status, | |
a878539e | 297 | |
5682ed33 | 298 | .sff_tf_read = ahci_tf_read, |
7d50b60b | 299 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
300 | .qc_prep = ahci_qc_prep, |
301 | .qc_issue = ahci_qc_issue, | |
302 | ||
78cd52d0 TH |
303 | .freeze = ahci_freeze, |
304 | .thaw = ahci_thaw, | |
a1efdaba TH |
305 | .softreset = ahci_softreset, |
306 | .hardreset = ahci_hardreset, | |
307 | .postreset = ahci_postreset, | |
308 | .pmp_softreset = ahci_pmp_softreset, | |
78cd52d0 TH |
309 | .error_handler = ahci_error_handler, |
310 | .post_internal_cmd = ahci_post_internal_cmd, | |
6bd99b4e TH |
311 | .dev_config = ahci_dev_config, |
312 | ||
ad616ffb TH |
313 | .scr_read = ahci_scr_read, |
314 | .scr_write = ahci_scr_write, | |
7d50b60b TH |
315 | .pmp_attach = ahci_pmp_attach, |
316 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 317 | |
029cfd6b TH |
318 | .enable_pm = ahci_enable_alpm, |
319 | .disable_pm = ahci_disable_alpm, | |
438ac6d5 | 320 | #ifdef CONFIG_PM |
ad616ffb TH |
321 | .port_suspend = ahci_port_suspend, |
322 | .port_resume = ahci_port_resume, | |
438ac6d5 | 323 | #endif |
ad616ffb TH |
324 | .port_start = ahci_port_start, |
325 | .port_stop = ahci_port_stop, | |
326 | }; | |
327 | ||
029cfd6b TH |
328 | static struct ata_port_operations ahci_vt8251_ops = { |
329 | .inherits = &ahci_ops, | |
a1efdaba | 330 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 331 | }; |
edc93052 | 332 | |
029cfd6b TH |
333 | static struct ata_port_operations ahci_p5wdh_ops = { |
334 | .inherits = &ahci_ops, | |
a1efdaba | 335 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
336 | }; |
337 | ||
417a1a6d TH |
338 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
339 | ||
98ac62de | 340 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
341 | /* board_ahci */ |
342 | { | |
1188c0d8 | 343 | .flags = AHCI_FLAG_COMMON, |
7da79312 | 344 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 345 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
346 | .port_ops = &ahci_ops, |
347 | }, | |
bf2af2a2 BJ |
348 | /* board_ahci_vt8251 */ |
349 | { | |
6949b914 | 350 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 351 | .flags = AHCI_FLAG_COMMON, |
bf2af2a2 | 352 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 353 | .udma_mask = ATA_UDMA6, |
ad616ffb | 354 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 355 | }, |
41669553 TH |
356 | /* board_ahci_ign_iferr */ |
357 | { | |
417a1a6d TH |
358 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
359 | .flags = AHCI_FLAG_COMMON, | |
41669553 | 360 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 361 | .udma_mask = ATA_UDMA6, |
41669553 TH |
362 | .port_ops = &ahci_ops, |
363 | }, | |
55a61604 CH |
364 | /* board_ahci_sb600 */ |
365 | { | |
417a1a6d | 366 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
4cde32fc | 367 | AHCI_HFLAG_32BIT_ONLY | |
a878539e | 368 | AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP), |
417a1a6d | 369 | .flags = AHCI_FLAG_COMMON, |
55a61604 | 370 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 371 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
372 | .port_ops = &ahci_ops, |
373 | }, | |
cd70c266 JG |
374 | /* board_ahci_mv */ |
375 | { | |
417a1a6d TH |
376 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
377 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 378 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 379 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
cd70c266 JG |
380 | .pio_mask = 0x1f, /* pio0-4 */ |
381 | .udma_mask = ATA_UDMA6, | |
382 | .port_ops = &ahci_ops, | |
383 | }, | |
e39fc8c9 SH |
384 | /* board_ahci_sb700 */ |
385 | { | |
386 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | | |
387 | AHCI_HFLAG_NO_PMP), | |
388 | .flags = AHCI_FLAG_COMMON, | |
e39fc8c9 SH |
389 | .pio_mask = 0x1f, /* pio0-4 */ |
390 | .udma_mask = ATA_UDMA6, | |
391 | .port_ops = &ahci_ops, | |
392 | }, | |
1da177e4 LT |
393 | }; |
394 | ||
3b7d697d | 395 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 396 | /* Intel */ |
54bb3a94 JG |
397 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
398 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
399 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
400 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
401 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 402 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
403 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
404 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
405 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
406 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
407 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
408 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
409 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
410 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
411 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
412 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
413 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
414 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
415 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
416 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
417 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
418 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
419 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
420 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
421 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
422 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
423 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
424 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
425 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 JG |
426 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
427 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ | |
fe7fa31a | 428 | |
e34bb370 TH |
429 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
430 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
431 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
432 | |
433 | /* ATI */ | |
c65ec1c2 | 434 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
435 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
436 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
437 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
438 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
439 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
440 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
441 | |
442 | /* VIA */ | |
54bb3a94 | 443 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 444 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
445 | |
446 | /* NVIDIA */ | |
54bb3a94 JG |
447 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
448 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
451 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
452 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
459 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
460 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
463 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
467 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
468 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
475 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
476 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
479 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
480 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
487 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
488 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 491 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
492 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
494 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
495 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
496 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
499 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
500 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
502 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
70d562cf | 503 | { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */ |
504 | { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ | |
509 | { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ | |
510 | { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ | |
511 | { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */ | |
512 | { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */ | |
513 | { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */ | |
514 | { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */ | |
fe7fa31a | 515 | |
95916edd | 516 | /* SiS */ |
54bb3a94 JG |
517 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
518 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
519 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 520 | |
cd70c266 JG |
521 | /* Marvell */ |
522 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 523 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
cd70c266 | 524 | |
415ae2b5 JG |
525 | /* Generic, PCI class code for AHCI */ |
526 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 527 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 528 | |
1da177e4 LT |
529 | { } /* terminate list */ |
530 | }; | |
531 | ||
532 | ||
533 | static struct pci_driver ahci_pci_driver = { | |
534 | .name = DRV_NAME, | |
535 | .id_table = ahci_pci_tbl, | |
536 | .probe = ahci_init_one, | |
24dc5f33 | 537 | .remove = ata_pci_remove_one, |
438ac6d5 | 538 | #ifdef CONFIG_PM |
c1332875 TH |
539 | .suspend = ahci_pci_device_suspend, |
540 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 541 | #endif |
1da177e4 LT |
542 | }; |
543 | ||
544 | ||
98fa4b60 TH |
545 | static inline int ahci_nr_ports(u32 cap) |
546 | { | |
547 | return (cap & 0x1f) + 1; | |
548 | } | |
549 | ||
dab632e8 JG |
550 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
551 | unsigned int port_no) | |
1da177e4 | 552 | { |
dab632e8 | 553 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 554 | |
dab632e8 JG |
555 | return mmio + 0x100 + (port_no * 0x80); |
556 | } | |
557 | ||
558 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
559 | { | |
560 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
561 | } |
562 | ||
b710a1f4 TH |
563 | static void ahci_enable_ahci(void __iomem *mmio) |
564 | { | |
565 | u32 tmp; | |
566 | ||
567 | /* turn on AHCI_EN */ | |
568 | tmp = readl(mmio + HOST_CTL); | |
569 | if (!(tmp & HOST_AHCI_EN)) { | |
570 | tmp |= HOST_AHCI_EN; | |
571 | writel(tmp, mmio + HOST_CTL); | |
572 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
573 | WARN_ON(!(tmp & HOST_AHCI_EN)); | |
574 | } | |
575 | } | |
576 | ||
d447df14 TH |
577 | /** |
578 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 579 | * @pdev: target PCI device |
4447d351 | 580 | * @hpriv: host private area to store config values |
d447df14 TH |
581 | * |
582 | * Some registers containing configuration info might be setup by | |
583 | * BIOS and might be cleared on reset. This function saves the | |
584 | * initial values of those registers into @hpriv such that they | |
585 | * can be restored after controller reset. | |
586 | * | |
587 | * If inconsistent, config values are fixed up by this function. | |
588 | * | |
589 | * LOCKING: | |
590 | * None. | |
591 | */ | |
4447d351 | 592 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 593 | struct ahci_host_priv *hpriv) |
d447df14 | 594 | { |
4447d351 | 595 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 596 | u32 cap, port_map; |
17199b18 | 597 | int i; |
c40e7cb8 | 598 | int mv; |
d447df14 | 599 | |
b710a1f4 TH |
600 | /* make sure AHCI mode is enabled before accessing CAP */ |
601 | ahci_enable_ahci(mmio); | |
602 | ||
d447df14 TH |
603 | /* Values prefixed with saved_ are written back to host after |
604 | * reset. Values without are used for driver operation. | |
605 | */ | |
606 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
607 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
608 | ||
274c1fde | 609 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 610 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
611 | dev_printk(KERN_INFO, &pdev->dev, |
612 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
613 | cap &= ~HOST_CAP_64; | |
614 | } | |
615 | ||
417a1a6d | 616 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
617 | dev_printk(KERN_INFO, &pdev->dev, |
618 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
619 | cap &= ~HOST_CAP_NCQ; | |
620 | } | |
621 | ||
258cd846 | 622 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
6949b914 TH |
623 | dev_printk(KERN_INFO, &pdev->dev, |
624 | "controller can't do PMP, turning off CAP_PMP\n"); | |
625 | cap &= ~HOST_CAP_PMP; | |
626 | } | |
627 | ||
cd70c266 JG |
628 | /* |
629 | * Temporary Marvell 6145 hack: PATA port presence | |
630 | * is asserted through the standard AHCI port | |
631 | * presence register, as bit 4 (counting from 0) | |
632 | */ | |
417a1a6d | 633 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
634 | if (pdev->device == 0x6121) |
635 | mv = 0x3; | |
636 | else | |
637 | mv = 0xf; | |
cd70c266 JG |
638 | dev_printk(KERN_ERR, &pdev->dev, |
639 | "MV_AHCI HACK: port_map %x -> %x\n", | |
c40e7cb8 JAR |
640 | port_map, |
641 | port_map & mv); | |
cd70c266 | 642 | |
c40e7cb8 | 643 | port_map &= mv; |
cd70c266 JG |
644 | } |
645 | ||
17199b18 | 646 | /* cross check port_map and cap.n_ports */ |
7a234aff | 647 | if (port_map) { |
837f5f8f | 648 | int map_ports = 0; |
17199b18 | 649 | |
837f5f8f TH |
650 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
651 | if (port_map & (1 << i)) | |
652 | map_ports++; | |
17199b18 | 653 | |
837f5f8f TH |
654 | /* If PI has more ports than n_ports, whine, clear |
655 | * port_map and let it be generated from n_ports. | |
17199b18 | 656 | */ |
837f5f8f | 657 | if (map_ports > ahci_nr_ports(cap)) { |
4447d351 | 658 | dev_printk(KERN_WARNING, &pdev->dev, |
837f5f8f TH |
659 | "implemented port map (0x%x) contains more " |
660 | "ports than nr_ports (%u), using nr_ports\n", | |
661 | port_map, ahci_nr_ports(cap)); | |
7a234aff TH |
662 | port_map = 0; |
663 | } | |
664 | } | |
665 | ||
666 | /* fabricate port_map from cap.nr_ports */ | |
667 | if (!port_map) { | |
17199b18 | 668 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
669 | dev_printk(KERN_WARNING, &pdev->dev, |
670 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
671 | ||
672 | /* write the fixed up value to the PI register */ | |
673 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
674 | } |
675 | ||
d447df14 TH |
676 | /* record values to use during operation */ |
677 | hpriv->cap = cap; | |
678 | hpriv->port_map = port_map; | |
679 | } | |
680 | ||
681 | /** | |
682 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 683 | * @host: target ATA host |
d447df14 TH |
684 | * |
685 | * Restore initial config stored by ahci_save_initial_config(). | |
686 | * | |
687 | * LOCKING: | |
688 | * None. | |
689 | */ | |
4447d351 | 690 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 691 | { |
4447d351 TH |
692 | struct ahci_host_priv *hpriv = host->private_data; |
693 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
694 | ||
d447df14 TH |
695 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
696 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
697 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
698 | } | |
699 | ||
203ef6c4 | 700 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 701 | { |
203ef6c4 TH |
702 | static const int offset[] = { |
703 | [SCR_STATUS] = PORT_SCR_STAT, | |
704 | [SCR_CONTROL] = PORT_SCR_CTL, | |
705 | [SCR_ERROR] = PORT_SCR_ERR, | |
706 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
707 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
708 | }; | |
709 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 710 | |
203ef6c4 TH |
711 | if (sc_reg < ARRAY_SIZE(offset) && |
712 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
713 | return offset[sc_reg]; | |
da3dbb17 | 714 | return 0; |
1da177e4 LT |
715 | } |
716 | ||
203ef6c4 | 717 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 718 | { |
203ef6c4 TH |
719 | void __iomem *port_mmio = ahci_port_base(ap); |
720 | int offset = ahci_scr_offset(ap, sc_reg); | |
721 | ||
722 | if (offset) { | |
723 | *val = readl(port_mmio + offset); | |
724 | return 0; | |
1da177e4 | 725 | } |
203ef6c4 TH |
726 | return -EINVAL; |
727 | } | |
1da177e4 | 728 | |
203ef6c4 TH |
729 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
730 | { | |
731 | void __iomem *port_mmio = ahci_port_base(ap); | |
732 | int offset = ahci_scr_offset(ap, sc_reg); | |
733 | ||
734 | if (offset) { | |
735 | writel(val, port_mmio + offset); | |
736 | return 0; | |
737 | } | |
738 | return -EINVAL; | |
1da177e4 LT |
739 | } |
740 | ||
4447d351 | 741 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 742 | { |
4447d351 | 743 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
744 | u32 tmp; |
745 | ||
d8fcd116 | 746 | /* start DMA */ |
9f592056 | 747 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
748 | tmp |= PORT_CMD_START; |
749 | writel(tmp, port_mmio + PORT_CMD); | |
750 | readl(port_mmio + PORT_CMD); /* flush */ | |
751 | } | |
752 | ||
4447d351 | 753 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 754 | { |
4447d351 | 755 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
756 | u32 tmp; |
757 | ||
758 | tmp = readl(port_mmio + PORT_CMD); | |
759 | ||
d8fcd116 | 760 | /* check if the HBA is idle */ |
254950cd TH |
761 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
762 | return 0; | |
763 | ||
d8fcd116 | 764 | /* setting HBA to idle */ |
254950cd TH |
765 | tmp &= ~PORT_CMD_START; |
766 | writel(tmp, port_mmio + PORT_CMD); | |
767 | ||
d8fcd116 | 768 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 769 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 770 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 771 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
772 | return -EIO; |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
4447d351 | 777 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 778 | { |
4447d351 TH |
779 | void __iomem *port_mmio = ahci_port_base(ap); |
780 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
781 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
782 | u32 tmp; |
783 | ||
784 | /* set FIS registers */ | |
4447d351 TH |
785 | if (hpriv->cap & HOST_CAP_64) |
786 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
787 | port_mmio + PORT_LST_ADDR_HI); | |
788 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 789 | |
4447d351 TH |
790 | if (hpriv->cap & HOST_CAP_64) |
791 | writel((pp->rx_fis_dma >> 16) >> 16, | |
792 | port_mmio + PORT_FIS_ADDR_HI); | |
793 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
794 | |
795 | /* enable FIS reception */ | |
796 | tmp = readl(port_mmio + PORT_CMD); | |
797 | tmp |= PORT_CMD_FIS_RX; | |
798 | writel(tmp, port_mmio + PORT_CMD); | |
799 | ||
800 | /* flush */ | |
801 | readl(port_mmio + PORT_CMD); | |
802 | } | |
803 | ||
4447d351 | 804 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 805 | { |
4447d351 | 806 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
807 | u32 tmp; |
808 | ||
809 | /* disable FIS reception */ | |
810 | tmp = readl(port_mmio + PORT_CMD); | |
811 | tmp &= ~PORT_CMD_FIS_RX; | |
812 | writel(tmp, port_mmio + PORT_CMD); | |
813 | ||
814 | /* wait for completion, spec says 500ms, give it 1000 */ | |
815 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
816 | PORT_CMD_FIS_ON, 10, 1000); | |
817 | if (tmp & PORT_CMD_FIS_ON) | |
818 | return -EBUSY; | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
4447d351 | 823 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 824 | { |
4447d351 TH |
825 | struct ahci_host_priv *hpriv = ap->host->private_data; |
826 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
827 | u32 cmd; |
828 | ||
829 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
830 | ||
831 | /* spin up device */ | |
4447d351 | 832 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
833 | cmd |= PORT_CMD_SPIN_UP; |
834 | writel(cmd, port_mmio + PORT_CMD); | |
835 | } | |
836 | ||
837 | /* wake up link */ | |
838 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
839 | } | |
840 | ||
31556594 KCA |
841 | static void ahci_disable_alpm(struct ata_port *ap) |
842 | { | |
843 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
844 | void __iomem *port_mmio = ahci_port_base(ap); | |
845 | u32 cmd; | |
846 | struct ahci_port_priv *pp = ap->private_data; | |
847 | ||
848 | /* IPM bits should be disabled by libata-core */ | |
849 | /* get the existing command bits */ | |
850 | cmd = readl(port_mmio + PORT_CMD); | |
851 | ||
852 | /* disable ALPM and ASP */ | |
853 | cmd &= ~PORT_CMD_ASP; | |
854 | cmd &= ~PORT_CMD_ALPE; | |
855 | ||
856 | /* force the interface back to active */ | |
857 | cmd |= PORT_CMD_ICC_ACTIVE; | |
858 | ||
859 | /* write out new cmd value */ | |
860 | writel(cmd, port_mmio + PORT_CMD); | |
861 | cmd = readl(port_mmio + PORT_CMD); | |
862 | ||
863 | /* wait 10ms to be sure we've come out of any low power state */ | |
864 | msleep(10); | |
865 | ||
866 | /* clear out any PhyRdy stuff from interrupt status */ | |
867 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
868 | ||
869 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
870 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
871 | ||
872 | /* | |
873 | * Clear flag to indicate that we should ignore all PhyRdy | |
874 | * state changes | |
875 | */ | |
876 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
877 | ||
878 | /* | |
879 | * Enable interrupts on Phy Ready. | |
880 | */ | |
881 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
882 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
883 | ||
884 | /* | |
885 | * don't change the link pm policy - we can be called | |
886 | * just to turn of link pm temporarily | |
887 | */ | |
888 | } | |
889 | ||
890 | static int ahci_enable_alpm(struct ata_port *ap, | |
891 | enum link_pm policy) | |
892 | { | |
893 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
894 | void __iomem *port_mmio = ahci_port_base(ap); | |
895 | u32 cmd; | |
896 | struct ahci_port_priv *pp = ap->private_data; | |
897 | u32 asp; | |
898 | ||
899 | /* Make sure the host is capable of link power management */ | |
900 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
901 | return -EINVAL; | |
902 | ||
903 | switch (policy) { | |
904 | case MAX_PERFORMANCE: | |
905 | case NOT_AVAILABLE: | |
906 | /* | |
907 | * if we came here with NOT_AVAILABLE, | |
908 | * it just means this is the first time we | |
909 | * have tried to enable - default to max performance, | |
910 | * and let the user go to lower power modes on request. | |
911 | */ | |
912 | ahci_disable_alpm(ap); | |
913 | return 0; | |
914 | case MIN_POWER: | |
915 | /* configure HBA to enter SLUMBER */ | |
916 | asp = PORT_CMD_ASP; | |
917 | break; | |
918 | case MEDIUM_POWER: | |
919 | /* configure HBA to enter PARTIAL */ | |
920 | asp = 0; | |
921 | break; | |
922 | default: | |
923 | return -EINVAL; | |
924 | } | |
925 | ||
926 | /* | |
927 | * Disable interrupts on Phy Ready. This keeps us from | |
928 | * getting woken up due to spurious phy ready interrupts | |
929 | * TBD - Hot plug should be done via polling now, is | |
930 | * that even supported? | |
931 | */ | |
932 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
933 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
934 | ||
935 | /* | |
936 | * Set a flag to indicate that we should ignore all PhyRdy | |
937 | * state changes since these can happen now whenever we | |
938 | * change link state | |
939 | */ | |
940 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
941 | ||
942 | /* get the existing command bits */ | |
943 | cmd = readl(port_mmio + PORT_CMD); | |
944 | ||
945 | /* | |
946 | * Set ASP based on Policy | |
947 | */ | |
948 | cmd |= asp; | |
949 | ||
950 | /* | |
951 | * Setting this bit will instruct the HBA to aggressively | |
952 | * enter a lower power link state when it's appropriate and | |
953 | * based on the value set above for ASP | |
954 | */ | |
955 | cmd |= PORT_CMD_ALPE; | |
956 | ||
957 | /* write out new cmd value */ | |
958 | writel(cmd, port_mmio + PORT_CMD); | |
959 | cmd = readl(port_mmio + PORT_CMD); | |
960 | ||
961 | /* IPM bits should be set by libata-core */ | |
962 | return 0; | |
963 | } | |
964 | ||
438ac6d5 | 965 | #ifdef CONFIG_PM |
4447d351 | 966 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 967 | { |
4447d351 TH |
968 | struct ahci_host_priv *hpriv = ap->host->private_data; |
969 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
970 | u32 cmd, scontrol; |
971 | ||
4447d351 | 972 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 973 | return; |
0be0aa98 | 974 | |
07c53dac TH |
975 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
976 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
977 | scontrol &= ~0xf; | |
978 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 979 | |
07c53dac TH |
980 | /* then set PxCMD.SUD to 0 */ |
981 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
982 | cmd &= ~PORT_CMD_SPIN_UP; | |
983 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 984 | } |
438ac6d5 | 985 | #endif |
0be0aa98 | 986 | |
df69c9c5 | 987 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 988 | { |
0be0aa98 | 989 | /* enable FIS reception */ |
4447d351 | 990 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
991 | |
992 | /* enable DMA */ | |
4447d351 | 993 | ahci_start_engine(ap); |
0be0aa98 TH |
994 | } |
995 | ||
4447d351 | 996 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
997 | { |
998 | int rc; | |
999 | ||
1000 | /* disable DMA */ | |
4447d351 | 1001 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
1002 | if (rc) { |
1003 | *emsg = "failed to stop engine"; | |
1004 | return rc; | |
1005 | } | |
1006 | ||
1007 | /* disable FIS reception */ | |
4447d351 | 1008 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1009 | if (rc) { |
1010 | *emsg = "failed stop FIS RX"; | |
1011 | return rc; | |
1012 | } | |
1013 | ||
0be0aa98 TH |
1014 | return 0; |
1015 | } | |
1016 | ||
4447d351 | 1017 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1018 | { |
4447d351 | 1019 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1020 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1021 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1022 | u32 tmp; |
d91542c1 | 1023 | |
3cc3eb11 JG |
1024 | /* we must be in AHCI mode, before using anything |
1025 | * AHCI-specific, such as HOST_RESET. | |
1026 | */ | |
b710a1f4 | 1027 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1028 | |
1029 | /* global controller reset */ | |
a22e6444 TH |
1030 | if (!ahci_skip_host_reset) { |
1031 | tmp = readl(mmio + HOST_CTL); | |
1032 | if ((tmp & HOST_RESET) == 0) { | |
1033 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1034 | readl(mmio + HOST_CTL); /* flush */ | |
1035 | } | |
d91542c1 | 1036 | |
a22e6444 TH |
1037 | /* reset must complete within 1 second, or |
1038 | * the hardware should be considered fried. | |
1039 | */ | |
1040 | ssleep(1); | |
d91542c1 | 1041 | |
a22e6444 TH |
1042 | tmp = readl(mmio + HOST_CTL); |
1043 | if (tmp & HOST_RESET) { | |
1044 | dev_printk(KERN_ERR, host->dev, | |
1045 | "controller reset failed (0x%x)\n", tmp); | |
1046 | return -EIO; | |
1047 | } | |
d91542c1 | 1048 | |
a22e6444 TH |
1049 | /* turn on AHCI mode */ |
1050 | ahci_enable_ahci(mmio); | |
98fa4b60 | 1051 | |
a22e6444 TH |
1052 | /* Some registers might be cleared on reset. Restore |
1053 | * initial values. | |
1054 | */ | |
1055 | ahci_restore_initial_config(host); | |
1056 | } else | |
1057 | dev_printk(KERN_INFO, host->dev, | |
1058 | "skipping global host reset\n"); | |
d91542c1 TH |
1059 | |
1060 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1061 | u16 tmp16; | |
1062 | ||
1063 | /* configure PCS */ | |
1064 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1065 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1066 | tmp16 |= hpriv->port_map; | |
1067 | pci_write_config_word(pdev, 0x92, tmp16); | |
1068 | } | |
d91542c1 TH |
1069 | } |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
2bcd866b JG |
1074 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1075 | int port_no, void __iomem *mmio, | |
1076 | void __iomem *port_mmio) | |
1077 | { | |
1078 | const char *emsg = NULL; | |
1079 | int rc; | |
1080 | u32 tmp; | |
1081 | ||
1082 | /* make sure port is not active */ | |
1083 | rc = ahci_deinit_port(ap, &emsg); | |
1084 | if (rc) | |
1085 | dev_printk(KERN_WARNING, &pdev->dev, | |
1086 | "%s (%d)\n", emsg, rc); | |
1087 | ||
1088 | /* clear SError */ | |
1089 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1090 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1091 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1092 | ||
1093 | /* clear port IRQ */ | |
1094 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1095 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1096 | if (tmp) | |
1097 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1098 | ||
1099 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1100 | } | |
1101 | ||
4447d351 | 1102 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1103 | { |
417a1a6d | 1104 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1105 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1106 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1107 | int i; |
cd70c266 | 1108 | void __iomem *port_mmio; |
d91542c1 | 1109 | u32 tmp; |
c40e7cb8 | 1110 | int mv; |
d91542c1 | 1111 | |
417a1a6d | 1112 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
1113 | if (pdev->device == 0x6121) |
1114 | mv = 2; | |
1115 | else | |
1116 | mv = 4; | |
1117 | port_mmio = __ahci_port_base(host, mv); | |
cd70c266 JG |
1118 | |
1119 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1120 | ||
1121 | /* clear port IRQ */ | |
1122 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1123 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1124 | if (tmp) | |
1125 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1126 | } | |
1127 | ||
4447d351 TH |
1128 | for (i = 0; i < host->n_ports; i++) { |
1129 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1130 | |
cd70c266 | 1131 | port_mmio = ahci_port_base(ap); |
4447d351 | 1132 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1133 | continue; |
d91542c1 | 1134 | |
2bcd866b | 1135 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1136 | } |
1137 | ||
1138 | tmp = readl(mmio + HOST_CTL); | |
1139 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1140 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1141 | tmp = readl(mmio + HOST_CTL); | |
1142 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1143 | } | |
1144 | ||
a878539e JG |
1145 | static void ahci_dev_config(struct ata_device *dev) |
1146 | { | |
1147 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1148 | ||
4cde32fc | 1149 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
a878539e | 1150 | dev->max_sectors = 255; |
4cde32fc JG |
1151 | ata_dev_printk(dev, KERN_INFO, |
1152 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
1153 | } | |
a878539e JG |
1154 | } |
1155 | ||
422b7595 | 1156 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1157 | { |
4447d351 | 1158 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1159 | struct ata_taskfile tf; |
422b7595 TH |
1160 | u32 tmp; |
1161 | ||
1162 | tmp = readl(port_mmio + PORT_SIG); | |
1163 | tf.lbah = (tmp >> 24) & 0xff; | |
1164 | tf.lbam = (tmp >> 16) & 0xff; | |
1165 | tf.lbal = (tmp >> 8) & 0xff; | |
1166 | tf.nsect = (tmp) & 0xff; | |
1167 | ||
1168 | return ata_dev_classify(&tf); | |
1169 | } | |
1170 | ||
12fad3f9 TH |
1171 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1172 | u32 opts) | |
cc9278ed | 1173 | { |
12fad3f9 TH |
1174 | dma_addr_t cmd_tbl_dma; |
1175 | ||
1176 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1177 | ||
1178 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1179 | pp->cmd_slot[tag].status = 0; | |
1180 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1181 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1182 | } |
1183 | ||
d2e75dff | 1184 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1185 | { |
0d5ff566 | 1186 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
cca3974e | 1187 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 | 1188 | u32 tmp; |
d2e75dff | 1189 | int busy, rc; |
bf2af2a2 | 1190 | |
d2e75dff TH |
1191 | /* do we need to kick the port? */ |
1192 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); | |
1193 | if (!busy && !force_restart) | |
1194 | return 0; | |
1195 | ||
1196 | /* stop engine */ | |
1197 | rc = ahci_stop_engine(ap); | |
1198 | if (rc) | |
1199 | goto out_restart; | |
1200 | ||
1201 | /* need to do CLO? */ | |
1202 | if (!busy) { | |
1203 | rc = 0; | |
1204 | goto out_restart; | |
1205 | } | |
1206 | ||
1207 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1208 | rc = -EOPNOTSUPP; | |
1209 | goto out_restart; | |
1210 | } | |
bf2af2a2 | 1211 | |
d2e75dff | 1212 | /* perform CLO */ |
bf2af2a2 BJ |
1213 | tmp = readl(port_mmio + PORT_CMD); |
1214 | tmp |= PORT_CMD_CLO; | |
1215 | writel(tmp, port_mmio + PORT_CMD); | |
1216 | ||
d2e75dff | 1217 | rc = 0; |
bf2af2a2 BJ |
1218 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1219 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1220 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1221 | rc = -EIO; |
bf2af2a2 | 1222 | |
d2e75dff TH |
1223 | /* restart engine */ |
1224 | out_restart: | |
1225 | ahci_start_engine(ap); | |
1226 | return rc; | |
bf2af2a2 BJ |
1227 | } |
1228 | ||
91c4a2e0 TH |
1229 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1230 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1231 | unsigned long timeout_msec) | |
bf2af2a2 | 1232 | { |
91c4a2e0 | 1233 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1234 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1235 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1236 | u8 *fis = pp->cmd_tbl; |
1237 | u32 tmp; | |
1238 | ||
1239 | /* prep the command */ | |
1240 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1241 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1242 | ||
1243 | /* issue & wait */ | |
1244 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1245 | ||
1246 | if (timeout_msec) { | |
1247 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1248 | 1, timeout_msec); | |
1249 | if (tmp & 0x1) { | |
1250 | ahci_kick_engine(ap, 1); | |
1251 | return -EBUSY; | |
1252 | } | |
1253 | } else | |
1254 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
cc0680a5 | 1259 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 | 1260 | int pmp, unsigned long deadline) |
91c4a2e0 | 1261 | { |
cc0680a5 | 1262 | struct ata_port *ap = link->ap; |
4658f79b | 1263 | const char *reason = NULL; |
2cbb79eb | 1264 | unsigned long now, msecs; |
4658f79b | 1265 | struct ata_taskfile tf; |
4658f79b TH |
1266 | int rc; |
1267 | ||
1268 | DPRINTK("ENTER\n"); | |
1269 | ||
cc0680a5 | 1270 | if (ata_link_offline(link)) { |
c2a65852 TH |
1271 | DPRINTK("PHY reports no device\n"); |
1272 | *class = ATA_DEV_NONE; | |
1273 | return 0; | |
1274 | } | |
1275 | ||
4658f79b | 1276 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff | 1277 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1278 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1279 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1280 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1281 | |
cc0680a5 | 1282 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1283 | |
1284 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1285 | msecs = 0; |
1286 | now = jiffies; | |
1287 | if (time_after(now, deadline)) | |
1288 | msecs = jiffies_to_msecs(deadline - now); | |
1289 | ||
4658f79b | 1290 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1291 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1292 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1293 | rc = -EIO; |
1294 | reason = "1st FIS failed"; | |
1295 | goto fail; | |
1296 | } | |
1297 | ||
1298 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1299 | msleep(1); | |
1300 | ||
1301 | /* issue the second D2H Register FIS */ | |
4658f79b | 1302 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1303 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1304 | |
88ff6eaf | 1305 | /* wait a while before checking status */ |
9363c382 | 1306 | ata_sff_wait_after_reset(ap, deadline); |
4658f79b | 1307 | |
9363c382 | 1308 | rc = ata_sff_wait_ready(ap, deadline); |
9b89391c TH |
1309 | /* link occupied, -ENODEV too is an error */ |
1310 | if (rc) { | |
1311 | reason = "device not ready"; | |
1312 | goto fail; | |
4658f79b | 1313 | } |
9b89391c | 1314 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1315 | |
1316 | DPRINTK("EXIT, class=%u\n", *class); | |
1317 | return 0; | |
1318 | ||
4658f79b | 1319 | fail: |
cc0680a5 | 1320 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1321 | return rc; |
1322 | } | |
1323 | ||
cc0680a5 | 1324 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 TH |
1325 | unsigned long deadline) |
1326 | { | |
7d50b60b TH |
1327 | int pmp = 0; |
1328 | ||
1329 | if (link->ap->flags & ATA_FLAG_PMP) | |
1330 | pmp = SATA_PMP_CTRL_PORT; | |
1331 | ||
1332 | return ahci_do_softreset(link, class, pmp, deadline); | |
a9cf5e85 TH |
1333 | } |
1334 | ||
cc0680a5 | 1335 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1336 | unsigned long deadline) |
422b7595 | 1337 | { |
cc0680a5 | 1338 | struct ata_port *ap = link->ap; |
4296971d TH |
1339 | struct ahci_port_priv *pp = ap->private_data; |
1340 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1341 | struct ata_taskfile tf; | |
4bd00f6a TH |
1342 | int rc; |
1343 | ||
1344 | DPRINTK("ENTER\n"); | |
1da177e4 | 1345 | |
4447d351 | 1346 | ahci_stop_engine(ap); |
4296971d TH |
1347 | |
1348 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1349 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1350 | tf.command = 0x80; |
9977126c | 1351 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1352 | |
9363c382 | 1353 | rc = sata_sff_hardreset(link, class, deadline); |
4296971d | 1354 | |
4447d351 | 1355 | ahci_start_engine(ap); |
1da177e4 | 1356 | |
cc0680a5 | 1357 | if (rc == 0 && ata_link_online(link)) |
4bd00f6a | 1358 | *class = ahci_dev_classify(ap); |
7d50b60b | 1359 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
4bd00f6a | 1360 | *class = ATA_DEV_NONE; |
1da177e4 | 1361 | |
4bd00f6a TH |
1362 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1363 | return rc; | |
1364 | } | |
1365 | ||
cc0680a5 | 1366 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1367 | unsigned long deadline) |
ad616ffb | 1368 | { |
cc0680a5 | 1369 | struct ata_port *ap = link->ap; |
da3dbb17 | 1370 | u32 serror; |
ad616ffb TH |
1371 | int rc; |
1372 | ||
1373 | DPRINTK("ENTER\n"); | |
1374 | ||
4447d351 | 1375 | ahci_stop_engine(ap); |
ad616ffb | 1376 | |
cc0680a5 | 1377 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
d4b2bab4 | 1378 | deadline); |
ad616ffb TH |
1379 | |
1380 | /* vt8251 needs SError cleared for the port to operate */ | |
da3dbb17 TH |
1381 | ahci_scr_read(ap, SCR_ERROR, &serror); |
1382 | ahci_scr_write(ap, SCR_ERROR, serror); | |
ad616ffb | 1383 | |
4447d351 | 1384 | ahci_start_engine(ap); |
ad616ffb TH |
1385 | |
1386 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1387 | ||
1388 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1389 | * request follow-up softreset. | |
1390 | */ | |
1391 | return rc ?: -EAGAIN; | |
1392 | } | |
1393 | ||
edc93052 TH |
1394 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1395 | unsigned long deadline) | |
1396 | { | |
1397 | struct ata_port *ap = link->ap; | |
1398 | struct ahci_port_priv *pp = ap->private_data; | |
1399 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1400 | struct ata_taskfile tf; | |
1401 | int rc; | |
1402 | ||
1403 | ahci_stop_engine(ap); | |
1404 | ||
1405 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1406 | ata_tf_init(link->device, &tf); | |
1407 | tf.command = 0x80; | |
1408 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1409 | ||
1410 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
1411 | deadline); | |
1412 | ||
1413 | ahci_start_engine(ap); | |
1414 | ||
1415 | if (rc || ata_link_offline(link)) | |
1416 | return rc; | |
1417 | ||
1418 | /* spec mandates ">= 2ms" before checking status */ | |
1419 | msleep(150); | |
1420 | ||
1421 | /* The pseudo configuration device on SIMG4726 attached to | |
1422 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1423 | * hardreset if no device is attached to the first downstream | |
1424 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1425 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1426 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1427 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1428 | * | |
1429 | * Wait for two seconds. Devices attached to downstream port | |
1430 | * which can't process the following IDENTIFY after this will | |
1431 | * have to be reset again. For most cases, this should | |
1432 | * suffice while making probing snappish enough. | |
1433 | */ | |
9363c382 | 1434 | rc = ata_sff_wait_ready(ap, jiffies + 2 * HZ); |
edc93052 TH |
1435 | if (rc) |
1436 | ahci_kick_engine(ap, 0); | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
cc0680a5 | 1441 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1442 | { |
cc0680a5 | 1443 | struct ata_port *ap = link->ap; |
4447d351 | 1444 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1445 | u32 new_tmp, tmp; |
1446 | ||
9363c382 | 1447 | ata_sff_postreset(link, class); |
02eaa666 JG |
1448 | |
1449 | /* Make sure port's ATAPI bit is set appropriately */ | |
1450 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1451 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1452 | new_tmp |= PORT_CMD_ATAPI; |
1453 | else | |
1454 | new_tmp &= ~PORT_CMD_ATAPI; | |
1455 | if (new_tmp != tmp) { | |
1456 | writel(new_tmp, port_mmio + PORT_CMD); | |
1457 | readl(port_mmio + PORT_CMD); /* flush */ | |
1458 | } | |
1da177e4 LT |
1459 | } |
1460 | ||
7d50b60b TH |
1461 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
1462 | unsigned long deadline) | |
1463 | { | |
1464 | return ahci_do_softreset(link, class, link->pmp, deadline); | |
1465 | } | |
1466 | ||
1da177e4 LT |
1467 | static u8 ahci_check_status(struct ata_port *ap) |
1468 | { | |
0d5ff566 | 1469 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
1da177e4 LT |
1470 | |
1471 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
1472 | } | |
1473 | ||
1da177e4 LT |
1474 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
1475 | { | |
1476 | struct ahci_port_priv *pp = ap->private_data; | |
1477 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1478 | ||
1479 | ata_tf_from_fis(d2h_fis, tf); | |
1480 | } | |
1481 | ||
12fad3f9 | 1482 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1483 | { |
cedc9a47 | 1484 | struct scatterlist *sg; |
ff2aeb1e TH |
1485 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
1486 | unsigned int si; | |
1da177e4 LT |
1487 | |
1488 | VPRINTK("ENTER\n"); | |
1489 | ||
1490 | /* | |
1491 | * Next, the S/G list. | |
1492 | */ | |
ff2aeb1e | 1493 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
1494 | dma_addr_t addr = sg_dma_address(sg); |
1495 | u32 sg_len = sg_dma_len(sg); | |
1496 | ||
ff2aeb1e TH |
1497 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
1498 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1499 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 1500 | } |
828d09de | 1501 | |
ff2aeb1e | 1502 | return si; |
1da177e4 LT |
1503 | } |
1504 | ||
1505 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1506 | { | |
a0ea7328 JG |
1507 | struct ata_port *ap = qc->ap; |
1508 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1509 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1510 | void *cmd_tbl; |
1da177e4 LT |
1511 | u32 opts; |
1512 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1513 | unsigned int n_elem; |
1da177e4 | 1514 | |
1da177e4 LT |
1515 | /* |
1516 | * Fill in command table information. First, the header, | |
1517 | * a SATA Register - Host to Device command FIS. | |
1518 | */ | |
12fad3f9 TH |
1519 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1520 | ||
7d50b60b | 1521 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1522 | if (is_atapi) { |
12fad3f9 TH |
1523 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1524 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1525 | } |
1da177e4 | 1526 | |
cc9278ed TH |
1527 | n_elem = 0; |
1528 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1529 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1530 | |
cc9278ed TH |
1531 | /* |
1532 | * Fill in command slot information. | |
1533 | */ | |
7d50b60b | 1534 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1535 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1536 | opts |= AHCI_CMD_WRITE; | |
1537 | if (is_atapi) | |
4b10e559 | 1538 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1539 | |
12fad3f9 | 1540 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1541 | } |
1542 | ||
78cd52d0 | 1543 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1544 | { |
417a1a6d | 1545 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1546 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1547 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1548 | struct ata_link *link = NULL; | |
1549 | struct ata_queued_cmd *active_qc; | |
1550 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1551 | u32 serror; |
1da177e4 | 1552 | |
7d50b60b TH |
1553 | /* determine active link */ |
1554 | ata_port_for_each_link(link, ap) | |
1555 | if (ata_link_active(link)) | |
1556 | break; | |
1557 | if (!link) | |
1558 | link = &ap->link; | |
1559 | ||
1560 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1561 | active_ehi = &link->eh_info; | |
1562 | ||
1563 | /* record irq stat */ | |
1564 | ata_ehi_clear_desc(host_ehi); | |
1565 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1566 | |
78cd52d0 | 1567 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1568 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1569 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1570 | host_ehi->serror |= serror; |
78cd52d0 | 1571 | |
41669553 | 1572 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1573 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1574 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1575 | ||
55a61604 | 1576 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1577 | /* If qc is active, charge it; otherwise, the active |
1578 | * link. There's no active qc on NCQ errors. It will | |
1579 | * be determined by EH by reading log page 10h. | |
1580 | */ | |
1581 | if (active_qc) | |
1582 | active_qc->err_mask |= AC_ERR_DEV; | |
1583 | else | |
1584 | active_ehi->err_mask |= AC_ERR_DEV; | |
1585 | ||
417a1a6d | 1586 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1587 | host_ehi->serror &= ~SERR_INTERNAL; |
1588 | } | |
1589 | ||
1590 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1591 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1592 | ||
1593 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1594 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b TH |
1595 | ata_ehi_push_desc(active_ehi, |
1596 | "unknown FIS %08x %08x %08x %08x" , | |
1597 | unk[0], unk[1], unk[2], unk[3]); | |
1598 | } | |
1599 | ||
1600 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1601 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1602 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1603 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
55a61604 | 1604 | } |
78cd52d0 TH |
1605 | |
1606 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b | 1607 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
cf480626 | 1608 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1609 | ata_ehi_push_desc(host_ehi, "host bus error"); |
1da177e4 LT |
1610 | } |
1611 | ||
78cd52d0 | 1612 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b | 1613 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
cf480626 | 1614 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1615 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
78cd52d0 | 1616 | } |
1da177e4 | 1617 | |
78cd52d0 | 1618 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1619 | ata_ehi_hotplugged(host_ehi); |
1620 | ata_ehi_push_desc(host_ehi, "%s", | |
1621 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1622 | "connection status changed" : "PHY RDY changed"); |
1623 | } | |
1624 | ||
78cd52d0 | 1625 | /* okay, let's hand over to EH */ |
a72ec4ce | 1626 | |
78cd52d0 TH |
1627 | if (irq_stat & PORT_IRQ_FREEZE) |
1628 | ata_port_freeze(ap); | |
1629 | else | |
1630 | ata_port_abort(ap); | |
1da177e4 LT |
1631 | } |
1632 | ||
df69c9c5 | 1633 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1634 | { |
4447d351 | 1635 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
9af5c9c9 | 1636 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1637 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 1638 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 1639 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 1640 | u32 status, qc_active; |
459ad688 | 1641 | int rc; |
1da177e4 LT |
1642 | |
1643 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1644 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1645 | ||
b06ce3e5 TH |
1646 | /* ignore BAD_PMP while resetting */ |
1647 | if (unlikely(resetting)) | |
1648 | status &= ~PORT_IRQ_BAD_PMP; | |
1649 | ||
31556594 KCA |
1650 | /* If we are getting PhyRdy, this is |
1651 | * just a power state change, we should | |
1652 | * clear out this, plus the PhyRdy/Comm | |
1653 | * Wake bits from Serror | |
1654 | */ | |
1655 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
1656 | (status & PORT_IRQ_PHYRDY)) { | |
1657 | status &= ~PORT_IRQ_PHYRDY; | |
1658 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
1659 | } | |
1660 | ||
78cd52d0 TH |
1661 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1662 | ahci_error_intr(ap, status); | |
1663 | return; | |
1da177e4 LT |
1664 | } |
1665 | ||
2f294968 | 1666 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
1667 | /* If SNotification is available, leave notification |
1668 | * handling to sata_async_notification(). If not, | |
1669 | * emulate it by snooping SDB FIS RX area. | |
1670 | * | |
1671 | * Snooping FIS RX area is probably cheaper than | |
1672 | * poking SNotification but some constrollers which | |
1673 | * implement SNotification, ICH9 for example, don't | |
1674 | * store AN SDB FIS into receive area. | |
2f294968 | 1675 | */ |
5f226c6b | 1676 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 1677 | sata_async_notification(ap); |
5f226c6b TH |
1678 | else { |
1679 | /* If the 'N' bit in word 0 of the FIS is set, | |
1680 | * we just received asynchronous notification. | |
1681 | * Tell libata about it. | |
1682 | */ | |
1683 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1684 | u32 f0 = le32_to_cpu(f[0]); | |
1685 | ||
1686 | if (f0 & (1 << 15)) | |
1687 | sata_async_notification(ap); | |
1688 | } | |
2f294968 KCA |
1689 | } |
1690 | ||
7d50b60b TH |
1691 | /* pp->active_link is valid iff any command is in flight */ |
1692 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1693 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1694 | else | |
1695 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1696 | ||
1697 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
b06ce3e5 | 1698 | |
459ad688 TH |
1699 | /* while resetting, invalid completions are expected */ |
1700 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 | 1701 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1702 | ehi->action |= ATA_EH_RESET; |
12fad3f9 | 1703 | ata_port_freeze(ap); |
1da177e4 | 1704 | } |
1da177e4 LT |
1705 | } |
1706 | ||
7d12e780 | 1707 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1708 | { |
cca3974e | 1709 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1710 | struct ahci_host_priv *hpriv; |
1711 | unsigned int i, handled = 0; | |
ea6ba10b | 1712 | void __iomem *mmio; |
1da177e4 LT |
1713 | u32 irq_stat, irq_ack = 0; |
1714 | ||
1715 | VPRINTK("ENTER\n"); | |
1716 | ||
cca3974e | 1717 | hpriv = host->private_data; |
0d5ff566 | 1718 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1719 | |
1720 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1721 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1722 | irq_stat &= hpriv->port_map; | |
1723 | if (!irq_stat) | |
1724 | return IRQ_NONE; | |
1725 | ||
2dcb407e | 1726 | spin_lock(&host->lock); |
1da177e4 | 1727 | |
2dcb407e | 1728 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1729 | struct ata_port *ap; |
1da177e4 | 1730 | |
67846b30 JG |
1731 | if (!(irq_stat & (1 << i))) |
1732 | continue; | |
1733 | ||
cca3974e | 1734 | ap = host->ports[i]; |
67846b30 | 1735 | if (ap) { |
df69c9c5 | 1736 | ahci_port_intr(ap); |
67846b30 JG |
1737 | VPRINTK("port %u\n", i); |
1738 | } else { | |
1739 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1740 | if (ata_ratelimit()) |
cca3974e | 1741 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1742 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1743 | } |
67846b30 JG |
1744 | |
1745 | irq_ack |= (1 << i); | |
1da177e4 LT |
1746 | } |
1747 | ||
1748 | if (irq_ack) { | |
1749 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1750 | handled = 1; | |
1751 | } | |
1752 | ||
cca3974e | 1753 | spin_unlock(&host->lock); |
1da177e4 LT |
1754 | |
1755 | VPRINTK("EXIT\n"); | |
1756 | ||
1757 | return IRQ_RETVAL(handled); | |
1758 | } | |
1759 | ||
9a3d9eb0 | 1760 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1761 | { |
1762 | struct ata_port *ap = qc->ap; | |
4447d351 | 1763 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1764 | struct ahci_port_priv *pp = ap->private_data; |
1765 | ||
1766 | /* Keep track of the currently active link. It will be used | |
1767 | * in completion path to determine whether NCQ phase is in | |
1768 | * progress. | |
1769 | */ | |
1770 | pp->active_link = qc->dev->link; | |
1da177e4 | 1771 | |
12fad3f9 TH |
1772 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1773 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1774 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1775 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
78cd52d0 TH |
1780 | static void ahci_freeze(struct ata_port *ap) |
1781 | { | |
4447d351 | 1782 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1783 | |
1784 | /* turn IRQ off */ | |
1785 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1786 | } | |
1787 | ||
1788 | static void ahci_thaw(struct ata_port *ap) | |
1789 | { | |
0d5ff566 | 1790 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1791 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1792 | u32 tmp; |
a7384925 | 1793 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1794 | |
1795 | /* clear IRQ */ | |
1796 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1797 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1798 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1799 | |
1c954a4d TH |
1800 | /* turn IRQ back on */ |
1801 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1802 | } |
1803 | ||
1804 | static void ahci_error_handler(struct ata_port *ap) | |
1805 | { | |
b51e9e5d | 1806 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1807 | /* restart engine */ |
4447d351 TH |
1808 | ahci_stop_engine(ap); |
1809 | ahci_start_engine(ap); | |
78cd52d0 TH |
1810 | } |
1811 | ||
a1efdaba | 1812 | sata_pmp_error_handler(ap); |
edc93052 TH |
1813 | } |
1814 | ||
78cd52d0 TH |
1815 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1816 | { | |
1817 | struct ata_port *ap = qc->ap; | |
1818 | ||
d2e75dff TH |
1819 | /* make DMA engine forget about the failed command */ |
1820 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1821 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1822 | } |
1823 | ||
7d50b60b TH |
1824 | static void ahci_pmp_attach(struct ata_port *ap) |
1825 | { | |
1826 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1827 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1828 | u32 cmd; |
1829 | ||
1830 | cmd = readl(port_mmio + PORT_CMD); | |
1831 | cmd |= PORT_CMD_PMP; | |
1832 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1833 | |
1834 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
1835 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1836 | } |
1837 | ||
1838 | static void ahci_pmp_detach(struct ata_port *ap) | |
1839 | { | |
1840 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1841 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1842 | u32 cmd; |
1843 | ||
1844 | cmd = readl(port_mmio + PORT_CMD); | |
1845 | cmd &= ~PORT_CMD_PMP; | |
1846 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1847 | |
1848 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
1849 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1850 | } |
1851 | ||
028a2596 AD |
1852 | static int ahci_port_resume(struct ata_port *ap) |
1853 | { | |
1854 | ahci_power_up(ap); | |
1855 | ahci_start_port(ap); | |
1856 | ||
7d50b60b TH |
1857 | if (ap->nr_pmp_links) |
1858 | ahci_pmp_attach(ap); | |
1859 | else | |
1860 | ahci_pmp_detach(ap); | |
1861 | ||
028a2596 AD |
1862 | return 0; |
1863 | } | |
1864 | ||
438ac6d5 | 1865 | #ifdef CONFIG_PM |
c1332875 TH |
1866 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1867 | { | |
c1332875 TH |
1868 | const char *emsg = NULL; |
1869 | int rc; | |
1870 | ||
4447d351 | 1871 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1872 | if (rc == 0) |
4447d351 | 1873 | ahci_power_down(ap); |
8e16f941 | 1874 | else { |
c1332875 | 1875 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1876 | ahci_start_port(ap); |
c1332875 TH |
1877 | } |
1878 | ||
1879 | return rc; | |
1880 | } | |
1881 | ||
c1332875 TH |
1882 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1883 | { | |
cca3974e | 1884 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1885 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1886 | u32 ctl; |
1887 | ||
3a2d5b70 | 1888 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
1889 | /* AHCI spec rev1.1 section 8.3.3: |
1890 | * Software must disable interrupts prior to requesting a | |
1891 | * transition of the HBA to D3 state. | |
1892 | */ | |
1893 | ctl = readl(mmio + HOST_CTL); | |
1894 | ctl &= ~HOST_IRQ_EN; | |
1895 | writel(ctl, mmio + HOST_CTL); | |
1896 | readl(mmio + HOST_CTL); /* flush */ | |
1897 | } | |
1898 | ||
1899 | return ata_pci_device_suspend(pdev, mesg); | |
1900 | } | |
1901 | ||
1902 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1903 | { | |
cca3974e | 1904 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1905 | int rc; |
1906 | ||
553c4aa6 TH |
1907 | rc = ata_pci_device_do_resume(pdev); |
1908 | if (rc) | |
1909 | return rc; | |
c1332875 TH |
1910 | |
1911 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1912 | rc = ahci_reset_controller(host); |
c1332875 TH |
1913 | if (rc) |
1914 | return rc; | |
1915 | ||
4447d351 | 1916 | ahci_init_controller(host); |
c1332875 TH |
1917 | } |
1918 | ||
cca3974e | 1919 | ata_host_resume(host); |
c1332875 TH |
1920 | |
1921 | return 0; | |
1922 | } | |
438ac6d5 | 1923 | #endif |
c1332875 | 1924 | |
254950cd TH |
1925 | static int ahci_port_start(struct ata_port *ap) |
1926 | { | |
cca3974e | 1927 | struct device *dev = ap->host->dev; |
254950cd | 1928 | struct ahci_port_priv *pp; |
254950cd TH |
1929 | void *mem; |
1930 | dma_addr_t mem_dma; | |
254950cd | 1931 | |
24dc5f33 | 1932 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1933 | if (!pp) |
1934 | return -ENOMEM; | |
254950cd | 1935 | |
24dc5f33 TH |
1936 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1937 | GFP_KERNEL); | |
1938 | if (!mem) | |
254950cd | 1939 | return -ENOMEM; |
254950cd TH |
1940 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1941 | ||
1942 | /* | |
1943 | * First item in chunk of DMA memory: 32-slot command table, | |
1944 | * 32 bytes each in size | |
1945 | */ | |
1946 | pp->cmd_slot = mem; | |
1947 | pp->cmd_slot_dma = mem_dma; | |
1948 | ||
1949 | mem += AHCI_CMD_SLOT_SZ; | |
1950 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1951 | ||
1952 | /* | |
1953 | * Second item: Received-FIS area | |
1954 | */ | |
1955 | pp->rx_fis = mem; | |
1956 | pp->rx_fis_dma = mem_dma; | |
1957 | ||
1958 | mem += AHCI_RX_FIS_SZ; | |
1959 | mem_dma += AHCI_RX_FIS_SZ; | |
1960 | ||
1961 | /* | |
1962 | * Third item: data area for storing a single command | |
1963 | * and its scatter-gather table | |
1964 | */ | |
1965 | pp->cmd_tbl = mem; | |
1966 | pp->cmd_tbl_dma = mem_dma; | |
1967 | ||
a7384925 | 1968 | /* |
2dcb407e JG |
1969 | * Save off initial list of interrupts to be enabled. |
1970 | * This could be changed later | |
1971 | */ | |
a7384925 KCA |
1972 | pp->intr_mask = DEF_PORT_IRQ; |
1973 | ||
254950cd TH |
1974 | ap->private_data = pp; |
1975 | ||
df69c9c5 JG |
1976 | /* engage engines, captain */ |
1977 | return ahci_port_resume(ap); | |
254950cd TH |
1978 | } |
1979 | ||
1980 | static void ahci_port_stop(struct ata_port *ap) | |
1981 | { | |
0be0aa98 TH |
1982 | const char *emsg = NULL; |
1983 | int rc; | |
254950cd | 1984 | |
0be0aa98 | 1985 | /* de-initialize port */ |
4447d351 | 1986 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
1987 | if (rc) |
1988 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1989 | } |
1990 | ||
4447d351 | 1991 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 1992 | { |
1da177e4 | 1993 | int rc; |
1da177e4 | 1994 | |
1da177e4 LT |
1995 | if (using_dac && |
1996 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1997 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1998 | if (rc) { | |
1999 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2000 | if (rc) { | |
a9524a76 JG |
2001 | dev_printk(KERN_ERR, &pdev->dev, |
2002 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
2003 | return rc; |
2004 | } | |
2005 | } | |
1da177e4 LT |
2006 | } else { |
2007 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2008 | if (rc) { | |
a9524a76 JG |
2009 | dev_printk(KERN_ERR, &pdev->dev, |
2010 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2011 | return rc; |
2012 | } | |
2013 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2014 | if (rc) { | |
a9524a76 JG |
2015 | dev_printk(KERN_ERR, &pdev->dev, |
2016 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2017 | return rc; |
2018 | } | |
2019 | } | |
1da177e4 LT |
2020 | return 0; |
2021 | } | |
2022 | ||
4447d351 | 2023 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2024 | { |
4447d351 TH |
2025 | struct ahci_host_priv *hpriv = host->private_data; |
2026 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2027 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2028 | u32 vers, cap, impl, speed; |
2029 | const char *speed_s; | |
2030 | u16 cc; | |
2031 | const char *scc_s; | |
2032 | ||
2033 | vers = readl(mmio + HOST_VERSION); | |
2034 | cap = hpriv->cap; | |
2035 | impl = hpriv->port_map; | |
2036 | ||
2037 | speed = (cap >> 20) & 0xf; | |
2038 | if (speed == 1) | |
2039 | speed_s = "1.5"; | |
2040 | else if (speed == 2) | |
2041 | speed_s = "3"; | |
2042 | else | |
2043 | speed_s = "?"; | |
2044 | ||
2045 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2046 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2047 | scc_s = "IDE"; |
c9f89475 | 2048 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2049 | scc_s = "SATA"; |
c9f89475 | 2050 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2051 | scc_s = "RAID"; |
2052 | else | |
2053 | scc_s = "unknown"; | |
2054 | ||
a9524a76 JG |
2055 | dev_printk(KERN_INFO, &pdev->dev, |
2056 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2057 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2058 | , |
1da177e4 | 2059 | |
2dcb407e JG |
2060 | (vers >> 24) & 0xff, |
2061 | (vers >> 16) & 0xff, | |
2062 | (vers >> 8) & 0xff, | |
2063 | vers & 0xff, | |
1da177e4 LT |
2064 | |
2065 | ((cap >> 8) & 0x1f) + 1, | |
2066 | (cap & 0x1f) + 1, | |
2067 | speed_s, | |
2068 | impl, | |
2069 | scc_s); | |
2070 | ||
a9524a76 JG |
2071 | dev_printk(KERN_INFO, &pdev->dev, |
2072 | "flags: " | |
203ef6c4 TH |
2073 | "%s%s%s%s%s%s%s" |
2074 | "%s%s%s%s%s%s%s\n" | |
2dcb407e | 2075 | , |
1da177e4 LT |
2076 | |
2077 | cap & (1 << 31) ? "64bit " : "", | |
2078 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2079 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2080 | cap & (1 << 28) ? "ilck " : "", |
2081 | cap & (1 << 27) ? "stag " : "", | |
2082 | cap & (1 << 26) ? "pm " : "", | |
2083 | cap & (1 << 25) ? "led " : "", | |
2084 | ||
2085 | cap & (1 << 24) ? "clo " : "", | |
2086 | cap & (1 << 19) ? "nz " : "", | |
2087 | cap & (1 << 18) ? "only " : "", | |
2088 | cap & (1 << 17) ? "pmp " : "", | |
2089 | cap & (1 << 15) ? "pio " : "", | |
2090 | cap & (1 << 14) ? "slum " : "", | |
2091 | cap & (1 << 13) ? "part " : "" | |
2092 | ); | |
2093 | } | |
2094 | ||
edc93052 TH |
2095 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2096 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2097 | * support PMP and the 4726 either directly exports the device | |
2098 | * attached to the first downstream port or acts as a hardware storage | |
2099 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2100 | * other configuration). | |
2101 | * | |
2102 | * When there's no device attached to the first downstream port of the | |
2103 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2104 | * configure the 4726. However, ATA emulation of the device is very | |
2105 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2106 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2107 | * | |
2108 | * The following function works around the problem by always using | |
2109 | * hardreset on the port and not depending on receiving signature FIS | |
2110 | * afterward. If signature FIS isn't received soon, ATA class is | |
2111 | * assumed without follow-up softreset. | |
2112 | */ | |
2113 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2114 | { | |
2115 | static struct dmi_system_id sysids[] = { | |
2116 | { | |
2117 | .ident = "P5W DH Deluxe", | |
2118 | .matches = { | |
2119 | DMI_MATCH(DMI_SYS_VENDOR, | |
2120 | "ASUSTEK COMPUTER INC"), | |
2121 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2122 | }, | |
2123 | }, | |
2124 | { } | |
2125 | }; | |
2126 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2127 | ||
2128 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2129 | dmi_check_system(sysids)) { | |
2130 | struct ata_port *ap = host->ports[1]; | |
2131 | ||
2132 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2133 | "Deluxe on-board SIMG4726 workaround\n"); | |
2134 | ||
2135 | ap->ops = &ahci_p5wdh_ops; | |
2136 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2137 | } | |
2138 | } | |
2139 | ||
24dc5f33 | 2140 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2141 | { |
2142 | static int printed_version; | |
4447d351 TH |
2143 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
2144 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 2145 | struct device *dev = &pdev->dev; |
1da177e4 | 2146 | struct ahci_host_priv *hpriv; |
4447d351 | 2147 | struct ata_host *host; |
837f5f8f | 2148 | int n_ports, i, rc; |
1da177e4 LT |
2149 | |
2150 | VPRINTK("ENTER\n"); | |
2151 | ||
12fad3f9 TH |
2152 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2153 | ||
1da177e4 | 2154 | if (!printed_version++) |
a9524a76 | 2155 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2156 | |
4447d351 | 2157 | /* acquire resources */ |
24dc5f33 | 2158 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2159 | if (rc) |
2160 | return rc; | |
2161 | ||
dea55137 TH |
2162 | /* AHCI controllers often implement SFF compatible interface. |
2163 | * Grab all PCI BARs just in case. | |
2164 | */ | |
2165 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
0d5ff566 | 2166 | if (rc == -EBUSY) |
24dc5f33 | 2167 | pcim_pin_device(pdev); |
0d5ff566 | 2168 | if (rc) |
24dc5f33 | 2169 | return rc; |
1da177e4 | 2170 | |
c4f7792c TH |
2171 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2172 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2173 | u8 map; | |
2174 | ||
2175 | /* ICH6s share the same PCI ID for both piix and ahci | |
2176 | * modes. Enabling ahci mode while MAP indicates | |
2177 | * combined mode is a bad idea. Yield to ata_piix. | |
2178 | */ | |
2179 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2180 | if (map & 0x3) { | |
2181 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2182 | "combined mode, can't enable AHCI mode\n"); | |
2183 | return -ENODEV; | |
2184 | } | |
2185 | } | |
2186 | ||
24dc5f33 TH |
2187 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2188 | if (!hpriv) | |
2189 | return -ENOMEM; | |
417a1a6d TH |
2190 | hpriv->flags |= (unsigned long)pi.private_data; |
2191 | ||
2192 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) | |
2193 | pci_intx(pdev, 1); | |
1da177e4 | 2194 | |
4447d351 | 2195 | /* save initial config */ |
417a1a6d | 2196 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2197 | |
4447d351 | 2198 | /* prepare host */ |
274c1fde | 2199 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2200 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2201 | |
7d50b60b TH |
2202 | if (hpriv->cap & HOST_CAP_PMP) |
2203 | pi.flags |= ATA_FLAG_PMP; | |
2204 | ||
837f5f8f TH |
2205 | /* CAP.NP sometimes indicate the index of the last enabled |
2206 | * port, at other times, that of the last possible port, so | |
2207 | * determining the maximum port number requires looking at | |
2208 | * both CAP.NP and port_map. | |
2209 | */ | |
2210 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
2211 | ||
2212 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
2213 | if (!host) |
2214 | return -ENOMEM; | |
2215 | host->iomap = pcim_iomap_table(pdev); | |
2216 | host->private_data = hpriv; | |
2217 | ||
2218 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 JG |
2219 | struct ata_port *ap = host->ports[i]; |
2220 | void __iomem *port_mmio = ahci_port_base(ap); | |
4447d351 | 2221 | |
cbcdd875 TH |
2222 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2223 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2224 | 0x100 + ap->port_no * 0x80, "port"); | |
2225 | ||
31556594 KCA |
2226 | /* set initial link pm policy */ |
2227 | ap->pm_policy = NOT_AVAILABLE; | |
2228 | ||
dab632e8 | 2229 | /* standard SATA port setup */ |
203ef6c4 | 2230 | if (hpriv->port_map & (1 << i)) |
4447d351 | 2231 | ap->ioaddr.cmd_addr = port_mmio; |
dab632e8 JG |
2232 | |
2233 | /* disabled/not-implemented port */ | |
2234 | else | |
2235 | ap->ops = &ata_dummy_port_ops; | |
4447d351 | 2236 | } |
d447df14 | 2237 | |
edc93052 TH |
2238 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2239 | ahci_p5wdh_workaround(host); | |
2240 | ||
4447d351 TH |
2241 | /* initialize adapter */ |
2242 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2243 | if (rc) |
24dc5f33 | 2244 | return rc; |
1da177e4 | 2245 | |
4447d351 TH |
2246 | rc = ahci_reset_controller(host); |
2247 | if (rc) | |
2248 | return rc; | |
1da177e4 | 2249 | |
4447d351 TH |
2250 | ahci_init_controller(host); |
2251 | ahci_print_info(host); | |
1da177e4 | 2252 | |
4447d351 TH |
2253 | pci_set_master(pdev); |
2254 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2255 | &ahci_sht); | |
907f4678 | 2256 | } |
1da177e4 LT |
2257 | |
2258 | static int __init ahci_init(void) | |
2259 | { | |
b7887196 | 2260 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2261 | } |
2262 | ||
1da177e4 LT |
2263 | static void __exit ahci_exit(void) |
2264 | { | |
2265 | pci_unregister_driver(&ahci_pci_driver); | |
2266 | } | |
2267 | ||
2268 | ||
2269 | MODULE_AUTHOR("Jeff Garzik"); | |
2270 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2271 | MODULE_LICENSE("GPL"); | |
2272 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2273 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2274 | |
2275 | module_init(ahci_init); | |
2276 | module_exit(ahci_exit); |