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[libata] ARM: add ixp4xx PATA driver
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
8676ce07 51#define DRV_VERSION "2.0"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
12fad3f9 59 AHCI_MAX_CMDS = 32,
dd410ff1 60 AHCI_CMD_SZ = 32,
12fad3f9 61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
41669553 81 board_ahci_ign_iferr = 2,
1da177e4
LT		 82
83 /* global controller registers */
84 HOST_CAP = 0x00, /* host capabilities */
85 HOST_CTL = 0x04, /* global host control */
86 HOST_IRQ_STAT = 0x08, /* interrupt status */
87 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
88 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
89
90 /* HOST_CTL bits */
91 HOST_RESET = (1 << 0), /* reset controller; self-clear */
92 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
94
95 /* HOST_CAP bits */
0be0aa98 96 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 97 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 99 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 100 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 101
102 /* registers for each SATA port */
103 PORT_LST_ADDR = 0x00, /* command list DMA addr */
104 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
105 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
106 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
107 PORT_IRQ_STAT = 0x10, /* interrupt status */
108 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
109 PORT_CMD = 0x18, /* port command */
110 PORT_TFDATA = 0x20, /* taskfile data */
111 PORT_SIG = 0x24, /* device TF signature */
112 PORT_CMD_ISSUE = 0x38, /* command issue */
113 PORT_SCR = 0x28, /* SATA phy register block */
114 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
115 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
116 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
117 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
118
119 /* PORT_IRQ_{STAT,MASK} bits */
120 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
121 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
122 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
123 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
124 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
125 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
126 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
127 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
128
129 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
130 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
131 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
132 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
133 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
134 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
135 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
136 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
137 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
138
78cd52d0
TH		 139 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
140 PORT_IRQ_IF_ERR |
141 PORT_IRQ_CONNECT |
4296971d 142 PORT_IRQ_PHYRDY |
78cd52d0
TH		 143 PORT_IRQ_UNK_FIS,
144 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
145 PORT_IRQ_TF_ERR |
146 PORT_IRQ_HBUS_DATA_ERR,
147 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
148 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
149 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 150
151 /* PORT_CMD bits */
02eaa666 152 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 153 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
154 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
155 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 156 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 157 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
158 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
159 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
160
0be0aa98 161 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 162 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
163 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
164 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 165
166 /* hpriv->flags bits */
167 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 168
169 /* ap->flags bits */
4aeb0e32
TH		 170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
1da177e4
LT		 172};
173
174struct ahci_cmd_hdr {
175 u32 opts;
176 u32 status;
177 u32 tbl_addr;
178 u32 tbl_addr_hi;
179 u32 reserved[4];
180};
181
182struct ahci_sg {
183 u32 addr;
184 u32 addr_hi;
185 u32 reserved;
186 u32 flags_size;
187};
188
189struct ahci_host_priv {
190 unsigned long flags;
191 u32 cap; /* cache of HOST_CAP register */
192 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
193};
194
195struct ahci_port_priv {
196 struct ahci_cmd_hdr *cmd_slot;
197 dma_addr_t cmd_slot_dma;
198 void *cmd_tbl;
199 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 200 void *rx_fis;
201 dma_addr_t rx_fis_dma;
202};
203
204static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
205static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
206static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 207static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
7d12e780 208static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
1da177e4 209static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 210static int ahci_port_start(struct ata_port *ap);
211static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 212static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
213static void ahci_qc_prep(struct ata_queued_cmd *qc);
214static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 215static void ahci_freeze(struct ata_port *ap);
216static void ahci_thaw(struct ata_port *ap);
217static void ahci_error_handler(struct ata_port *ap);
ad616ffb 218static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 219static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
c1332875
TH		 220static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
221static int ahci_port_resume(struct ata_port *ap);
222static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
223static int ahci_pci_device_resume(struct pci_dev *pdev);
907f4678 224static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 225
193515d5 226static struct scsi_host_template ahci_sht = {
1da177e4
LT		 227 .module = THIS_MODULE,
228 .name = DRV_NAME,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 231 .change_queue_depth = ata_scsi_change_queue_depth,
232 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 233 .this_id = ATA_SHT_THIS_ID,
234 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 235 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
236 .emulated = ATA_SHT_EMULATED,
237 .use_clustering = AHCI_USE_CLUSTERING,
238 .proc_name = DRV_NAME,
239 .dma_boundary = AHCI_DMA_BOUNDARY,
240 .slave_configure = ata_scsi_slave_config,
ccf68c34 241 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 242 .bios_param = ata_std_bios_param,
c1332875
TH		 243 .suspend = ata_scsi_device_suspend,
244 .resume = ata_scsi_device_resume,
1da177e4
LT		 245};
246
057ace5e 247static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 248 .port_disable = ata_port_disable,
249
250 .check_status = ahci_check_status,
251 .check_altstatus = ahci_check_status,
1da177e4
LT		 252 .dev_select = ata_noop_dev_select,
253
254 .tf_read = ahci_tf_read,
255
1da177e4
LT		 256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
258
1da177e4
LT		 259 .irq_handler = ahci_interrupt,
260 .irq_clear = ahci_irq_clear,
261
262 .scr_read = ahci_scr_read,
263 .scr_write = ahci_scr_write,
264
78cd52d0
TH		 265 .freeze = ahci_freeze,
266 .thaw = ahci_thaw,
267
268 .error_handler = ahci_error_handler,
269 .post_internal_cmd = ahci_post_internal_cmd,
270
c1332875
TH		 271 .port_suspend = ahci_port_suspend,
272 .port_resume = ahci_port_resume,
273
1da177e4
LT		 274 .port_start = ahci_port_start,
275 .port_stop = ahci_port_stop,
1da177e4
LT		 276};
277
ad616ffb
TH		 278static const struct ata_port_operations ahci_vt8251_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = ahci_check_status,
282 .check_altstatus = ahci_check_status,
283 .dev_select = ata_noop_dev_select,
284
285 .tf_read = ahci_tf_read,
286
287 .qc_prep = ahci_qc_prep,
288 .qc_issue = ahci_qc_issue,
289
290 .irq_handler = ahci_interrupt,
291 .irq_clear = ahci_irq_clear,
292
293 .scr_read = ahci_scr_read,
294 .scr_write = ahci_scr_write,
295
296 .freeze = ahci_freeze,
297 .thaw = ahci_thaw,
298
299 .error_handler = ahci_vt8251_error_handler,
300 .post_internal_cmd = ahci_post_internal_cmd,
301
302 .port_suspend = ahci_port_suspend,
303 .port_resume = ahci_port_resume,
304
305 .port_start = ahci_port_start,
306 .port_stop = ahci_port_stop,
307};
308
98ac62de 309static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 310 /* board_ahci */
311 {
312 .sht = &ahci_sht,
cca3974e 313 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 314 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
315 ATA_FLAG_SKIP_D2H_BSY,
7da79312 316 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 317 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
318 .port_ops = &ahci_ops,
319 },
bf2af2a2
BJ		 320 /* board_ahci_vt8251 */
321 {
322 .sht = &ahci_sht,
cca3974e 323 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 324 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 325 ATA_FLAG_SKIP_D2H_BSY |
326 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 327 .pio_mask = 0x1f, /* pio0-4 */
328 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 329 .port_ops = &ahci_vt8251_ops,
bf2af2a2 330 },
41669553
TH		 331 /* board_ahci_ign_iferr */
332 {
333 .sht = &ahci_sht,
334 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
335 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
336 ATA_FLAG_SKIP_D2H_BSY |
337 AHCI_FLAG_IGN_IRQ_IF_ERR,
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
340 .port_ops = &ahci_ops,
341 },
1da177e4
LT		 342};
343
3b7d697d 344static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 345 /* Intel */
54bb3a94
JG		 346 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
347 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
348 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
349 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
350 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
351 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
352 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
353 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
354 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
355 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
356 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
357 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
358 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
359 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
360 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
f33d625f
JG		 361 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
362 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
363 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
364 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
365 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
366 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
367 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
368 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
369 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
370 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
371 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
fe7fa31a
JG		 372
373 /* JMicron */
41669553
TH		 374 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
375 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
376 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
377 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
378 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
fe7fa31a
JG		 379
380 /* ATI */
54bb3a94
JG		 381 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
382 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
fe7fa31a
JG		 383
384 /* VIA */
54bb3a94 385 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 386
387 /* NVIDIA */
54bb3a94
JG		 388 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
389 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
390 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
391 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
895663cd
PC		 392 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
398 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
399 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 400
95916edd 401 /* SiS */
54bb3a94
JG		 402 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
403 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
404 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 405
415ae2b5
JG		 406 /* Generic, PCI class code for AHCI */
407 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 0x010601, 0xffffff, board_ahci },
409
1da177e4
LT		 410 { } /* terminate list */
411};
412
413
414static struct pci_driver ahci_pci_driver = {
415 .name = DRV_NAME,
416 .id_table = ahci_pci_tbl,
417 .probe = ahci_init_one,
c1332875
TH		 418 .suspend = ahci_pci_device_suspend,
419 .resume = ahci_pci_device_resume,
907f4678 420 .remove = ahci_remove_one,
1da177e4
LT		 421};
422
423
98fa4b60
TH		 424static inline int ahci_nr_ports(u32 cap)
425{
426 return (cap & 0x1f) + 1;
427}
428
1da177e4
LT		 429static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
430{
431 return base + 0x100 + (port * 0x80);
432}
433
ea6ba10b 434static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 435{
ea6ba10b 436 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 437}
438
1da177e4
LT		 439static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
440{
441 unsigned int sc_reg;
442
443 switch (sc_reg_in) {
444 case SCR_STATUS: sc_reg = 0; break;
445 case SCR_CONTROL: sc_reg = 1; break;
446 case SCR_ERROR: sc_reg = 2; break;
447 case SCR_ACTIVE: sc_reg = 3; break;
448 default:
449 return 0xffffffffU;
450 }
451
1e4f2a96 452 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 453}
454
455
456static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
457 u32 val)
458{
459 unsigned int sc_reg;
460
461 switch (sc_reg_in) {
462 case SCR_STATUS: sc_reg = 0; break;
463 case SCR_CONTROL: sc_reg = 1; break;
464 case SCR_ERROR: sc_reg = 2; break;
465 case SCR_ACTIVE: sc_reg = 3; break;
466 default:
467 return;
468 }
469
1e4f2a96 470 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 471}
472
9f592056 473static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 474{
7c76d1e8
TH		 475 u32 tmp;
476
d8fcd116 477 /* start DMA */
9f592056 478 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 479 tmp |= PORT_CMD_START;
480 writel(tmp, port_mmio + PORT_CMD);
481 readl(port_mmio + PORT_CMD); /* flush */
482}
483
254950cd
TH		 484static int ahci_stop_engine(void __iomem *port_mmio)
485{
486 u32 tmp;
487
488 tmp = readl(port_mmio + PORT_CMD);
489
d8fcd116 490 /* check if the HBA is idle */
254950cd
TH		 491 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
492 return 0;
493
d8fcd116 494 /* setting HBA to idle */
254950cd
TH		 495 tmp &= ~PORT_CMD_START;
496 writel(tmp, port_mmio + PORT_CMD);
497
d8fcd116 498 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 499 tmp = ata_wait_register(port_mmio + PORT_CMD,
500 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 501 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 502 return -EIO;
503
504 return 0;
505}
506
0be0aa98
TH		 507static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
508 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
509{
510 u32 tmp;
511
512 /* set FIS registers */
513 if (cap & HOST_CAP_64)
514 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
515 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
516
517 if (cap & HOST_CAP_64)
518 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
519 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
520
521 /* enable FIS reception */
522 tmp = readl(port_mmio + PORT_CMD);
523 tmp |= PORT_CMD_FIS_RX;
524 writel(tmp, port_mmio + PORT_CMD);
525
526 /* flush */
527 readl(port_mmio + PORT_CMD);
528}
529
530static int ahci_stop_fis_rx(void __iomem *port_mmio)
531{
532 u32 tmp;
533
534 /* disable FIS reception */
535 tmp = readl(port_mmio + PORT_CMD);
536 tmp &= ~PORT_CMD_FIS_RX;
537 writel(tmp, port_mmio + PORT_CMD);
538
539 /* wait for completion, spec says 500ms, give it 1000 */
540 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
541 PORT_CMD_FIS_ON, 10, 1000);
542 if (tmp & PORT_CMD_FIS_ON)
543 return -EBUSY;
544
545 return 0;
546}
547
548static void ahci_power_up(void __iomem *port_mmio, u32 cap)
549{
550 u32 cmd;
551
552 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
553
554 /* spin up device */
555 if (cap & HOST_CAP_SSS) {
556 cmd |= PORT_CMD_SPIN_UP;
557 writel(cmd, port_mmio + PORT_CMD);
558 }
559
560 /* wake up link */
561 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
562}
563
564static void ahci_power_down(void __iomem *port_mmio, u32 cap)
565{
566 u32 cmd, scontrol;
567
568 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
569
570 if (cap & HOST_CAP_SSC) {
571 /* enable transitions to slumber mode */
572 scontrol = readl(port_mmio + PORT_SCR_CTL);
573 if ((scontrol & 0x0f00) > 0x100) {
574 scontrol &= ~0xf00;
575 writel(scontrol, port_mmio + PORT_SCR_CTL);
576 }
577
578 /* put device into slumber mode */
579 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
580
581 /* wait for the transition to complete */
582 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
583 PORT_CMD_ICC_SLUMBER, 1, 50);
584 }
585
586 /* put device into listen mode */
587 if (cap & HOST_CAP_SSS) {
588 /* first set PxSCTL.DET to 0 */
589 scontrol = readl(port_mmio + PORT_SCR_CTL);
590 scontrol &= ~0xf;
591 writel(scontrol, port_mmio + PORT_SCR_CTL);
592
593 /* then set PxCMD.SUD to 0 */
594 cmd &= ~PORT_CMD_SPIN_UP;
595 writel(cmd, port_mmio + PORT_CMD);
596 }
597}
598
599static void ahci_init_port(void __iomem *port_mmio, u32 cap,
600 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
601{
602 /* power up */
603 ahci_power_up(port_mmio, cap);
604
605 /* enable FIS reception */
606 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
607
608 /* enable DMA */
609 ahci_start_engine(port_mmio);
610}
611
612static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
613{
614 int rc;
615
616 /* disable DMA */
617 rc = ahci_stop_engine(port_mmio);
618 if (rc) {
619 *emsg = "failed to stop engine";
620 return rc;
621 }
622
623 /* disable FIS reception */
624 rc = ahci_stop_fis_rx(port_mmio);
625 if (rc) {
626 *emsg = "failed stop FIS RX";
627 return rc;
628 }
629
630 /* put device into slumber mode */
631 ahci_power_down(port_mmio, cap);
632
633 return 0;
634}
635
d91542c1
TH		 636static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
637{
98fa4b60 638 u32 cap_save, impl_save, tmp;
d91542c1
TH		 639
640 cap_save = readl(mmio + HOST_CAP);
641 cap_save &= ( (1<<28) | (1<<17) );
642 cap_save |= (1 << 27);
98fa4b60 643 impl_save = readl(mmio + HOST_PORTS_IMPL);
d91542c1
TH		 644
645 /* global controller reset */
646 tmp = readl(mmio + HOST_CTL);
647 if ((tmp & HOST_RESET) == 0) {
648 writel(tmp | HOST_RESET, mmio + HOST_CTL);
649 readl(mmio + HOST_CTL); /* flush */
650 }
651
652 /* reset must complete within 1 second, or
653 * the hardware should be considered fried.
654 */
655 ssleep(1);
656
657 tmp = readl(mmio + HOST_CTL);
658 if (tmp & HOST_RESET) {
659 dev_printk(KERN_ERR, &pdev->dev,
660 "controller reset failed (0x%x)\n", tmp);
661 return -EIO;
662 }
663
98fa4b60 664 /* turn on AHCI mode */
d91542c1
TH		 665 writel(HOST_AHCI_EN, mmio + HOST_CTL);
666 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60
TH		 667
668 /* These write-once registers are normally cleared on reset.
669 * Restore BIOS values... which we HOPE were present before
670 * reset.
671 */
672 if (!impl_save) {
673 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
674 dev_printk(KERN_WARNING, &pdev->dev,
675 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
676 }
d91542c1 677 writel(cap_save, mmio + HOST_CAP);
98fa4b60 678 writel(impl_save, mmio + HOST_PORTS_IMPL);
d91542c1
TH		 679 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
680
681 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
682 u16 tmp16;
683
684 /* configure PCS */
685 pci_read_config_word(pdev, 0x92, &tmp16);
686 tmp16 |= 0xf;
687 pci_write_config_word(pdev, 0x92, tmp16);
688 }
689
690 return 0;
691}
692
693static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
694 int n_ports, u32 cap)
695{
696 int i, rc;
697 u32 tmp;
698
699 for (i = 0; i < n_ports; i++) {
700 void __iomem *port_mmio = ahci_port_base(mmio, i);
701 const char *emsg = NULL;
702
703#if 0 /* BIOSen initialize this incorrectly */
704 if (!(hpriv->port_map & (1 << i)))
705 continue;
706#endif
707
708 /* make sure port is not active */
709 rc = ahci_deinit_port(port_mmio, cap, &emsg);
710 if (rc)
711 dev_printk(KERN_WARNING, &pdev->dev,
712 "%s (%d)\n", emsg, rc);
713
714 /* clear SError */
715 tmp = readl(port_mmio + PORT_SCR_ERR);
716 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
717 writel(tmp, port_mmio + PORT_SCR_ERR);
718
f4b5cc87 719 /* clear port IRQ */
d91542c1
TH		 720 tmp = readl(port_mmio + PORT_IRQ_STAT);
721 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
722 if (tmp)
723 writel(tmp, port_mmio + PORT_IRQ_STAT);
724
725 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 726 }
727
728 tmp = readl(mmio + HOST_CTL);
729 VPRINTK("HOST_CTL 0x%x\n", tmp);
730 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
731 tmp = readl(mmio + HOST_CTL);
732 VPRINTK("HOST_CTL 0x%x\n", tmp);
733}
734
422b7595 735static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 736{
737 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
738 struct ata_taskfile tf;
422b7595
TH		 739 u32 tmp;
740
741 tmp = readl(port_mmio + PORT_SIG);
742 tf.lbah = (tmp >> 24) & 0xff;
743 tf.lbam = (tmp >> 16) & 0xff;
744 tf.lbal = (tmp >> 8) & 0xff;
745 tf.nsect = (tmp) & 0xff;
746
747 return ata_dev_classify(&tf);
748}
749
12fad3f9
TH		 750static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
751 u32 opts)
cc9278ed 752{
12fad3f9
TH		 753 dma_addr_t cmd_tbl_dma;
754
755 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
756
757 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
758 pp->cmd_slot[tag].status = 0;
759 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
760 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 761}
762
bf2af2a2 763static int ahci_clo(struct ata_port *ap)
4658f79b 764{
bf2af2a2 765 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
cca3974e 766 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 767 u32 tmp;
768
769 if (!(hpriv->cap & HOST_CAP_CLO))
770 return -EOPNOTSUPP;
771
772 tmp = readl(port_mmio + PORT_CMD);
773 tmp |= PORT_CMD_CLO;
774 writel(tmp, port_mmio + PORT_CMD);
775
776 tmp = ata_wait_register(port_mmio + PORT_CMD,
777 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
778 if (tmp & PORT_CMD_CLO)
779 return -EIO;
780
781 return 0;
782}
783
784static int ahci_softreset(struct ata_port *ap, unsigned int *class)
785{
4658f79b 786 struct ahci_port_priv *pp = ap->private_data;
cca3974e 787 void __iomem *mmio = ap->host->mmio_base;
4658f79b
TH		 788 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
789 const u32 cmd_fis_len = 5; /* five dwords */
790 const char *reason = NULL;
791 struct ata_taskfile tf;
75fe1806 792 u32 tmp;
4658f79b
TH		 793 u8 *fis;
794 int rc;
795
796 DPRINTK("ENTER\n");
797
81952c54 798 if (ata_port_offline(ap)) {
c2a65852
TH		 799 DPRINTK("PHY reports no device\n");
800 *class = ATA_DEV_NONE;
801 return 0;
802 }
803
4658f79b 804 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 805 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 806 if (rc) {
807 reason = "failed to stop engine";
808 goto fail_restart;
809 }
810
811 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 812 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 813 rc = ahci_clo(ap);
4658f79b 814
bf2af2a2
BJ		 815 if (rc == -EOPNOTSUPP) {
816 reason = "port busy but CLO unavailable";
817 goto fail_restart;
818 } else if (rc) {
819 reason = "port busy but CLO failed";
4658f79b
TH		 820 goto fail_restart;
821 }
822 }
823
824 /* restart engine */
5457f219 825 ahci_start_engine(port_mmio);
4658f79b 826
3373efd8 827 ata_tf_init(ap->device, &tf);
4658f79b
TH		 828 fis = pp->cmd_tbl;
829
830 /* issue the first D2H Register FIS */
12fad3f9
TH		 831 ahci_fill_cmd_slot(pp, 0,
832 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 833
834 tf.ctl |= ATA_SRST;
835 ata_tf_to_fis(&tf, fis, 0);
836 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
837
838 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 839
75fe1806
TH		 840 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
841 if (tmp & 0x1) {
4658f79b
TH		 842 rc = -EIO;
843 reason = "1st FIS failed";
844 goto fail;
845 }
846
847 /* spec says at least 5us, but be generous and sleep for 1ms */
848 msleep(1);
849
850 /* issue the second D2H Register FIS */
12fad3f9 851 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 852
853 tf.ctl &= ~ATA_SRST;
854 ata_tf_to_fis(&tf, fis, 0);
855 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
856
857 writel(1, port_mmio + PORT_CMD_ISSUE);
858 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
859
860 /* spec mandates ">= 2ms" before checking status.
861 * We wait 150ms, because that was the magic delay used for
862 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
863 * between when the ATA command register is written, and then
864 * status is checked. Because waiting for "a while" before
865 * checking status is fine, post SRST, we perform this magic
866 * delay here as well.
867 */
868 msleep(150);
869
870 *class = ATA_DEV_NONE;
81952c54 871 if (ata_port_online(ap)) {
4658f79b
TH		 872 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
873 rc = -EIO;
874 reason = "device not ready";
875 goto fail;
876 }
877 *class = ahci_dev_classify(ap);
878 }
879
880 DPRINTK("EXIT, class=%u\n", *class);
881 return 0;
882
883 fail_restart:
5457f219 884 ahci_start_engine(port_mmio);
4658f79b 885 fail:
f15a1daf 886 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 887 return rc;
888}
889
2bf2cb26 890static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 891{
4296971d
TH		 892 struct ahci_port_priv *pp = ap->private_data;
893 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
894 struct ata_taskfile tf;
cca3974e 895 void __iomem *mmio = ap->host->mmio_base;
5457f219 896 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 897 int rc;
898
899 DPRINTK("ENTER\n");
1da177e4 900
5457f219 901 ahci_stop_engine(port_mmio);
4296971d
TH		 902
903 /* clear D2H reception area to properly wait for D2H FIS */
904 ata_tf_init(ap->device, &tf);
905 tf.command = 0xff;
906 ata_tf_to_fis(&tf, d2h_fis, 0);
907
2bf2cb26 908 rc = sata_std_hardreset(ap, class);
4296971d 909
5457f219 910 ahci_start_engine(port_mmio);
1da177e4 911
81952c54 912 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 913 *class = ahci_dev_classify(ap);
914 if (*class == ATA_DEV_UNKNOWN)
915 *class = ATA_DEV_NONE;
1da177e4 916
4bd00f6a
TH		 917 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
918 return rc;
919}
920
ad616ffb
TH		 921static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
922{
923 void __iomem *mmio = ap->host->mmio_base;
924 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
925 int rc;
926
927 DPRINTK("ENTER\n");
928
929 ahci_stop_engine(port_mmio);
930
931 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
932
933 /* vt8251 needs SError cleared for the port to operate */
934 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
935
936 ahci_start_engine(port_mmio);
937
938 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
939
940 /* vt8251 doesn't clear BSY on signature FIS reception,
941 * request follow-up softreset.
942 */
943 return rc ?: -EAGAIN;
944}
945
4bd00f6a
TH		 946static void ahci_postreset(struct ata_port *ap, unsigned int *class)
947{
948 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
949 u32 new_tmp, tmp;
950
951 ata_std_postreset(ap, class);
02eaa666
JG		 952
953 /* Make sure port's ATAPI bit is set appropriately */
954 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 955 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 956 new_tmp |= PORT_CMD_ATAPI;
957 else
958 new_tmp &= ~PORT_CMD_ATAPI;
959 if (new_tmp != tmp) {
960 writel(new_tmp, port_mmio + PORT_CMD);
961 readl(port_mmio + PORT_CMD); /* flush */
962 }
1da177e4
LT		 963}
964
965static u8 ahci_check_status(struct ata_port *ap)
966{
1e4f2a96 967 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 968
969 return readl(mmio + PORT_TFDATA) & 0xFF;
970}
971
1da177e4
LT		 972static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
973{
974 struct ahci_port_priv *pp = ap->private_data;
975 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
976
977 ata_tf_from_fis(d2h_fis, tf);
978}
979
12fad3f9 980static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 981{
cedc9a47
JG		 982 struct scatterlist *sg;
983 struct ahci_sg *ahci_sg;
828d09de 984 unsigned int n_sg = 0;
1da177e4
LT		 985
986 VPRINTK("ENTER\n");
987
988 /*
989 * Next, the S/G list.
990 */
12fad3f9 991 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 992 ata_for_each_sg(sg, qc) {
993 dma_addr_t addr = sg_dma_address(sg);
994 u32 sg_len = sg_dma_len(sg);
995
996 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
997 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
998 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 999
cedc9a47 1000 ahci_sg++;
828d09de 1001 n_sg++;
1da177e4 1002 }
828d09de
JG		 1003
1004 return n_sg;
1da177e4
LT		 1005}
1006
1007static void ahci_qc_prep(struct ata_queued_cmd *qc)
1008{
a0ea7328
JG		 1009 struct ata_port *ap = qc->ap;
1010 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1011 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1012 void *cmd_tbl;
1da177e4
LT		 1013 u32 opts;
1014 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1015 unsigned int n_elem;
1da177e4 1016
1da177e4
LT		 1017 /*
1018 * Fill in command table information. First, the header,
1019 * a SATA Register - Host to Device command FIS.
1020 */
12fad3f9
TH		 1021 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1022
1023 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1024 if (is_atapi) {
12fad3f9
TH		 1025 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1026 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1027 }
1da177e4 1028
cc9278ed
TH		 1029 n_elem = 0;
1030 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1031 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1032
cc9278ed
TH		 1033 /*
1034 * Fill in command slot information.
1035 */
1036 opts = cmd_fis_len | n_elem << 16;
1037 if (qc->tf.flags & ATA_TFLAG_WRITE)
1038 opts |= AHCI_CMD_WRITE;
1039 if (is_atapi)
4b10e559 1040 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1041
12fad3f9 1042 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1043}
1044
78cd52d0 1045static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1046{
78cd52d0
TH		 1047 struct ahci_port_priv *pp = ap->private_data;
1048 struct ata_eh_info *ehi = &ap->eh_info;
1049 unsigned int err_mask = 0, action = 0;
1050 struct ata_queued_cmd *qc;
1051 u32 serror;
1da177e4 1052
78cd52d0 1053 ata_ehi_clear_desc(ehi);
1da177e4 1054
78cd52d0
TH		 1055 /* AHCI needs SError cleared; otherwise, it might lock up */
1056 serror = ahci_scr_read(ap, SCR_ERROR);
1057 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1058
78cd52d0
TH		 1059 /* analyze @irq_stat */
1060 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1061
41669553
TH		 1062 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1063 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1064 irq_stat &= ~PORT_IRQ_IF_ERR;
1065
78cd52d0
TH		 1066 if (irq_stat & PORT_IRQ_TF_ERR)
1067 err_mask |= AC_ERR_DEV;
1068
1069 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1070 err_mask |= AC_ERR_HOST_BUS;
1071 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1072 }
1073
78cd52d0
TH		 1074 if (irq_stat & PORT_IRQ_IF_ERR) {
1075 err_mask |= AC_ERR_ATA_BUS;
1076 action |= ATA_EH_SOFTRESET;
1077 ata_ehi_push_desc(ehi, ", interface fatal error");
1078 }
1da177e4 1079
78cd52d0 1080 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1081 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1082 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1083 "connection status changed" : "PHY RDY changed");
1084 }
1085
1086 if (irq_stat & PORT_IRQ_UNK_FIS) {
1087 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1088
78cd52d0
TH		 1089 err_mask |= AC_ERR_HSM;
1090 action |= ATA_EH_SOFTRESET;
1091 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1092 unk[0], unk[1], unk[2], unk[3]);
1093 }
1da177e4 1094
78cd52d0
TH		 1095 /* okay, let's hand over to EH */
1096 ehi->serror |= serror;
1097 ehi->action |= action;
b8f6153e 1098
1da177e4 1099 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1100 if (qc)
1101 qc->err_mask |= err_mask;
1102 else
1103 ehi->err_mask |= err_mask;
a72ec4ce 1104
78cd52d0
TH		 1105 if (irq_stat & PORT_IRQ_FREEZE)
1106 ata_port_freeze(ap);
1107 else
1108 ata_port_abort(ap);
1da177e4
LT		 1109}
1110
78cd52d0 1111static void ahci_host_intr(struct ata_port *ap)
1da177e4 1112{
cca3974e 1113 void __iomem *mmio = ap->host->mmio_base;
ea6ba10b 1114 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 1115 struct ata_eh_info *ehi = &ap->eh_info;
1116 u32 status, qc_active;
1117 int rc;
1da177e4
LT		 1118
1119 status = readl(port_mmio + PORT_IRQ_STAT);
1120 writel(status, port_mmio + PORT_IRQ_STAT);
1121
78cd52d0
TH		 1122 if (unlikely(status & PORT_IRQ_ERROR)) {
1123 ahci_error_intr(ap, status);
1124 return;
1da177e4
LT		 1125 }
1126
12fad3f9
TH		 1127 if (ap->sactive)
1128 qc_active = readl(port_mmio + PORT_SCR_ACT);
1129 else
1130 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1131
1132 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1133 if (rc > 0)
1134 return;
1135 if (rc < 0) {
1136 ehi->err_mask |= AC_ERR_HSM;
1137 ehi->action |= ATA_EH_SOFTRESET;
1138 ata_port_freeze(ap);
1139 return;
1da177e4
LT		 1140 }
1141
2a3917a8
TH		 1142 /* hmmm... a spurious interupt */
1143
12fad3f9 1144 /* some devices send D2H reg with I bit set during NCQ command phase */
12a87d36 1145 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
12fad3f9
TH		 1146 return;
1147
2a3917a8 1148 /* ignore interim PIO setup fis interrupts */
9bec2e38 1149 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
f1d39b29 1150 return;
2a3917a8 1151
78cd52d0
TH		 1152 if (ata_ratelimit())
1153 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 1154 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1155 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1156}
1157
1158static void ahci_irq_clear(struct ata_port *ap)
1159{
1160 /* TODO */
1161}
1162
7d12e780 1163static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1164{
cca3974e 1165 struct ata_host *host = dev_instance;
1da177e4
LT		 1166 struct ahci_host_priv *hpriv;
1167 unsigned int i, handled = 0;
ea6ba10b 1168 void __iomem *mmio;
1da177e4
LT		 1169 u32 irq_stat, irq_ack = 0;
1170
1171 VPRINTK("ENTER\n");
1172
cca3974e
JG		 1173 hpriv = host->private_data;
1174 mmio = host->mmio_base;
1da177e4
LT		 1175
1176 /* sigh. 0xffffffff is a valid return from h/w */
1177 irq_stat = readl(mmio + HOST_IRQ_STAT);
1178 irq_stat &= hpriv->port_map;
1179 if (!irq_stat)
1180 return IRQ_NONE;
1181
cca3974e 1182 spin_lock(&host->lock);
1da177e4 1183
cca3974e 1184 for (i = 0; i < host->n_ports; i++) {
1da177e4 1185 struct ata_port *ap;
1da177e4 1186
67846b30
JG		 1187 if (!(irq_stat & (1 << i)))
1188 continue;
1189
cca3974e 1190 ap = host->ports[i];
67846b30 1191 if (ap) {
78cd52d0 1192 ahci_host_intr(ap);
67846b30
JG		 1193 VPRINTK("port %u\n", i);
1194 } else {
1195 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1196 if (ata_ratelimit())
cca3974e 1197 dev_printk(KERN_WARNING, host->dev,
a9524a76 1198 "interrupt on disabled port %u\n", i);
1da177e4 1199 }
67846b30
JG		 1200
1201 irq_ack |= (1 << i);
1da177e4
LT		 1202 }
1203
1204 if (irq_ack) {
1205 writel(irq_ack, mmio + HOST_IRQ_STAT);
1206 handled = 1;
1207 }
1208
cca3974e 1209 spin_unlock(&host->lock);
1da177e4
LT		 1210
1211 VPRINTK("EXIT\n");
1212
1213 return IRQ_RETVAL(handled);
1214}
1215
9a3d9eb0 1216static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1217{
1218 struct ata_port *ap = qc->ap;
ea6ba10b 1219 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 1220
12fad3f9
TH		 1221 if (qc->tf.protocol == ATA_PROT_NCQ)
1222 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1223 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1224 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1225
1226 return 0;
1227}
1228
78cd52d0
TH		 1229static void ahci_freeze(struct ata_port *ap)
1230{
cca3974e 1231 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1232 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1233
1234 /* turn IRQ off */
1235 writel(0, port_mmio + PORT_IRQ_MASK);
1236}
1237
1238static void ahci_thaw(struct ata_port *ap)
1239{
cca3974e 1240 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1241 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1242 u32 tmp;
1243
1244 /* clear IRQ */
1245 tmp = readl(port_mmio + PORT_IRQ_STAT);
1246 writel(tmp, port_mmio + PORT_IRQ_STAT);
1247 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1248
1249 /* turn IRQ back on */
1250 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1251}
1252
1253static void ahci_error_handler(struct ata_port *ap)
1254{
cca3974e 1255 void __iomem *mmio = ap->host->mmio_base;
5457f219 1256 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1257
b51e9e5d 1258 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1259 /* restart engine */
5457f219 1260 ahci_stop_engine(port_mmio);
1261 ahci_start_engine(port_mmio);
78cd52d0
TH		 1262 }
1263
1264 /* perform recovery */
4aeb0e32 1265 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1266 ahci_postreset);
78cd52d0
TH		 1267}
1268
ad616ffb
TH		 1269static void ahci_vt8251_error_handler(struct ata_port *ap)
1270{
1271 void __iomem *mmio = ap->host->mmio_base;
1272 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1273
1274 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1275 /* restart engine */
1276 ahci_stop_engine(port_mmio);
1277 ahci_start_engine(port_mmio);
1278 }
1279
1280 /* perform recovery */
1281 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1282 ahci_postreset);
1283}
1284
78cd52d0
TH		 1285static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1286{
1287 struct ata_port *ap = qc->ap;
cca3974e 1288 void __iomem *mmio = ap->host->mmio_base;
5457f219 1289 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 1290
1291 if (qc->flags & ATA_QCFLAG_FAILED)
1292 qc->err_mask |= AC_ERR_OTHER;
1293
1294 if (qc->err_mask) {
1295 /* make DMA engine forget about the failed command */
5457f219 1296 ahci_stop_engine(port_mmio);
1297 ahci_start_engine(port_mmio);
78cd52d0
TH		 1298 }
1299}
1300
c1332875
TH		 1301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1302{
cca3974e 1303 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1304 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1305 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1306 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1307 const char *emsg = NULL;
1308 int rc;
1309
1310 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1311 if (rc) {
1312 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1313 ahci_init_port(port_mmio, hpriv->cap,
1314 pp->cmd_slot_dma, pp->rx_fis_dma);
1315 }
1316
1317 return rc;
1318}
1319
1320static int ahci_port_resume(struct ata_port *ap)
1321{
1322 struct ahci_port_priv *pp = ap->private_data;
cca3974e
JG		 1323 struct ahci_host_priv *hpriv = ap->host->private_data;
1324 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1325 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1326
1327 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1328
1329 return 0;
1330}
1331
1332static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1333{
cca3974e
JG		 1334 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1335 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1336 u32 ctl;
1337
1338 if (mesg.event == PM_EVENT_SUSPEND) {
1339 /* AHCI spec rev1.1 section 8.3.3:
1340 * Software must disable interrupts prior to requesting a
1341 * transition of the HBA to D3 state.
1342 */
1343 ctl = readl(mmio + HOST_CTL);
1344 ctl &= ~HOST_IRQ_EN;
1345 writel(ctl, mmio + HOST_CTL);
1346 readl(mmio + HOST_CTL); /* flush */
1347 }
1348
1349 return ata_pci_device_suspend(pdev, mesg);
1350}
1351
1352static int ahci_pci_device_resume(struct pci_dev *pdev)
1353{
cca3974e
JG		 1354 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1355 struct ahci_host_priv *hpriv = host->private_data;
1356 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1357 int rc;
1358
1359 ata_pci_device_do_resume(pdev);
1360
1361 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1362 rc = ahci_reset_controller(mmio, pdev);
1363 if (rc)
1364 return rc;
1365
cca3974e 1366 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
c1332875
TH		 1367 }
1368
cca3974e 1369 ata_host_resume(host);
c1332875
TH		 1370
1371 return 0;
1372}
1373
254950cd
TH		 1374static int ahci_port_start(struct ata_port *ap)
1375{
cca3974e
JG		 1376 struct device *dev = ap->host->dev;
1377 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1378 struct ahci_port_priv *pp;
cca3974e 1379 void __iomem *mmio = ap->host->mmio_base;
254950cd
TH		 1380 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1381 void *mem;
1382 dma_addr_t mem_dma;
1383 int rc;
1384
1385 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1386 if (!pp)
1387 return -ENOMEM;
1388 memset(pp, 0, sizeof(*pp));
1389
1390 rc = ata_pad_alloc(ap, dev);
1391 if (rc) {
1392 kfree(pp);
1393 return rc;
1394 }
1395
1396 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1397 if (!mem) {
1398 ata_pad_free(ap, dev);
1399 kfree(pp);
1400 return -ENOMEM;
1401 }
1402 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1403
1404 /*
1405 * First item in chunk of DMA memory: 32-slot command table,
1406 * 32 bytes each in size
1407 */
1408 pp->cmd_slot = mem;
1409 pp->cmd_slot_dma = mem_dma;
1410
1411 mem += AHCI_CMD_SLOT_SZ;
1412 mem_dma += AHCI_CMD_SLOT_SZ;
1413
1414 /*
1415 * Second item: Received-FIS area
1416 */
1417 pp->rx_fis = mem;
1418 pp->rx_fis_dma = mem_dma;
1419
1420 mem += AHCI_RX_FIS_SZ;
1421 mem_dma += AHCI_RX_FIS_SZ;
1422
1423 /*
1424 * Third item: data area for storing a single command
1425 * and its scatter-gather table
1426 */
1427 pp->cmd_tbl = mem;
1428 pp->cmd_tbl_dma = mem_dma;
1429
1430 ap->private_data = pp;
1431
0be0aa98
TH		 1432 /* initialize port */
1433 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1434
1435 return 0;
1436}
1437
1438static void ahci_port_stop(struct ata_port *ap)
1439{
cca3974e
JG		 1440 struct device *dev = ap->host->dev;
1441 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1442 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1443 void __iomem *mmio = ap->host->mmio_base;
254950cd 1444 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1445 const char *emsg = NULL;
1446 int rc;
254950cd 1447
0be0aa98
TH		 1448 /* de-initialize port */
1449 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1450 if (rc)
1451 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1452
1453 ap->private_data = NULL;
1454 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1455 pp->cmd_slot, pp->cmd_slot_dma);
1456 ata_pad_free(ap, dev);
1457 kfree(pp);
1458}
1459
1da177e4
LT		 1460static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1461 unsigned int port_idx)
1462{
1463 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1464 base = ahci_port_base_ul(base, port_idx);
1465 VPRINTK("base now==0x%lx\n", base);
1466
1467 port->cmd_addr = base;
1468 port->scr_addr = base + PORT_SCR;
1469
1470 VPRINTK("EXIT\n");
1471}
1472
1473static int ahci_host_init(struct ata_probe_ent *probe_ent)
1474{
1475 struct ahci_host_priv *hpriv = probe_ent->private_data;
1476 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1477 void __iomem *mmio = probe_ent->mmio_base;
0be0aa98 1478 unsigned int i, using_dac;
1da177e4 1479 int rc;
1da177e4 1480
d91542c1
TH		 1481 rc = ahci_reset_controller(mmio, pdev);
1482 if (rc)
1483 return rc;
1da177e4
LT		 1484
1485 hpriv->cap = readl(mmio + HOST_CAP);
1486 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
98fa4b60 1487 probe_ent->n_ports = ahci_nr_ports(hpriv->cap);
1da177e4
LT		 1488
1489 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1490 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1491
1492 using_dac = hpriv->cap & HOST_CAP_64;
1493 if (using_dac &&
1494 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1495 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1496 if (rc) {
1497 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1498 if (rc) {
a9524a76
JG		 1499 dev_printk(KERN_ERR, &pdev->dev,
1500 "64-bit DMA enable failed\n");
1da177e4
LT		 1501 return rc;
1502 }
1503 }
1da177e4
LT		 1504 } else {
1505 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1506 if (rc) {
a9524a76
JG		 1507 dev_printk(KERN_ERR, &pdev->dev,
1508 "32-bit DMA enable failed\n");
1da177e4
LT		 1509 return rc;
1510 }
1511 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1512 if (rc) {
a9524a76
JG		 1513 dev_printk(KERN_ERR, &pdev->dev,
1514 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1515 return rc;
1516 }
1517 }
1518
d91542c1
TH		 1519 for (i = 0; i < probe_ent->n_ports; i++)
1520 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1da177e4 1521
d91542c1 1522 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1da177e4
LT		 1523
1524 pci_set_master(pdev);
1525
1526 return 0;
1527}
1528
1da177e4
LT		 1529static void ahci_print_info(struct ata_probe_ent *probe_ent)
1530{
1531 struct ahci_host_priv *hpriv = probe_ent->private_data;
1532 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1533 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1534 u32 vers, cap, impl, speed;
1535 const char *speed_s;
1536 u16 cc;
1537 const char *scc_s;
1538
1539 vers = readl(mmio + HOST_VERSION);
1540 cap = hpriv->cap;
1541 impl = hpriv->port_map;
1542
1543 speed = (cap >> 20) & 0xf;
1544 if (speed == 1)
1545 speed_s = "1.5";
1546 else if (speed == 2)
1547 speed_s = "3";
1548 else
1549 speed_s = "?";
1550
1551 pci_read_config_word(pdev, 0x0a, &cc);
1552 if (cc == 0x0101)
1553 scc_s = "IDE";
1554 else if (cc == 0x0106)
1555 scc_s = "SATA";
1556 else if (cc == 0x0104)
1557 scc_s = "RAID";
1558 else
1559 scc_s = "unknown";
1560
a9524a76
JG		 1561 dev_printk(KERN_INFO, &pdev->dev,
1562 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1563 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1564 ,
1da177e4
LT		 1565
1566 (vers >> 24) & 0xff,
1567 (vers >> 16) & 0xff,
1568 (vers >> 8) & 0xff,
1569 vers & 0xff,
1570
1571 ((cap >> 8) & 0x1f) + 1,
1572 (cap & 0x1f) + 1,
1573 speed_s,
1574 impl,
1575 scc_s);
1576
a9524a76
JG		 1577 dev_printk(KERN_INFO, &pdev->dev,
1578 "flags: "
1da177e4
LT		 1579 "%s%s%s%s%s%s"
1580 "%s%s%s%s%s%s%s\n"
1581 ,
1da177e4
LT		 1582
1583 cap & (1 << 31) ? "64bit " : "",
1584 cap & (1 << 30) ? "ncq " : "",
1585 cap & (1 << 28) ? "ilck " : "",
1586 cap & (1 << 27) ? "stag " : "",
1587 cap & (1 << 26) ? "pm " : "",
1588 cap & (1 << 25) ? "led " : "",
1589
1590 cap & (1 << 24) ? "clo " : "",
1591 cap & (1 << 19) ? "nz " : "",
1592 cap & (1 << 18) ? "only " : "",
1593 cap & (1 << 17) ? "pmp " : "",
1594 cap & (1 << 15) ? "pio " : "",
1595 cap & (1 << 14) ? "slum " : "",
1596 cap & (1 << 13) ? "part " : ""
1597 );
1598}
1599
1600static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1601{
1602 static int printed_version;
1603 struct ata_probe_ent *probe_ent = NULL;
1604 struct ahci_host_priv *hpriv;
1605 unsigned long base;
ea6ba10b 1606 void __iomem *mmio_base;
1da177e4 1607 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1608 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1609 int rc;
1610
1611 VPRINTK("ENTER\n");
1612
12fad3f9
TH		 1613 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1614
1da177e4 1615 if (!printed_version++)
a9524a76 1616 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1617
9545b578
AC		 1618 /* JMicron-specific fixup: make sure we're in AHCI mode */
1619 /* This is protected from races with ata_jmicron by the pci probe
1620 locking */
1621 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1622 /* AHCI enable, AHCI on function 0 */
1623 pci_write_config_byte(pdev, 0x41, 0xa1);
1624 /* Function 1 is the PATA controller */
1625 if (PCI_FUNC(pdev->devfn))
1626 return -ENODEV;
1627 }
1628
1da177e4
LT		 1629 rc = pci_enable_device(pdev);
1630 if (rc)
1631 return rc;
1632
1633 rc = pci_request_regions(pdev, DRV_NAME);
1634 if (rc) {
1635 pci_dev_busy = 1;
1636 goto err_out;
1637 }
1638
907f4678
JG		 1639 if (pci_enable_msi(pdev) == 0)
1640 have_msi = 1;
1641 else {
1642 pci_intx(pdev, 1);
1643 have_msi = 0;
1644 }
1da177e4
LT		 1645
1646 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1647 if (probe_ent == NULL) {
1648 rc = -ENOMEM;
907f4678 1649 goto err_out_msi;
1da177e4
LT		 1650 }
1651
1652 memset(probe_ent, 0, sizeof(*probe_ent));
1653 probe_ent->dev = pci_dev_to_dev(pdev);
1654 INIT_LIST_HEAD(&probe_ent->node);
1655
374b1873 1656 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1657 if (mmio_base == NULL) {
1658 rc = -ENOMEM;
1659 goto err_out_free_ent;
1660 }
1661 base = (unsigned long) mmio_base;
1662
1663 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1664 if (!hpriv) {
1665 rc = -ENOMEM;
1666 goto err_out_iounmap;
1667 }
1668 memset(hpriv, 0, sizeof(*hpriv));
1669
1670 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1671 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1672 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1673 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1674 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1675
1676 probe_ent->irq = pdev->irq;
1d6f359a 1677 probe_ent->irq_flags = IRQF_SHARED;
1da177e4
LT		 1678 probe_ent->mmio_base = mmio_base;
1679 probe_ent->private_data = hpriv;
1680
4b0060f4
JG		 1681 if (have_msi)
1682 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1683
1da177e4
LT		 1684 /* initialize adapter */
1685 rc = ahci_host_init(probe_ent);
1686 if (rc)
1687 goto err_out_hpriv;
1688
cca3974e 1689 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1690 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1691 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1692
1da177e4
LT		 1693 ahci_print_info(probe_ent);
1694
1695 /* FIXME: check ata_device_add return value */
1696 ata_device_add(probe_ent);
1697 kfree(probe_ent);
1698
1699 return 0;
1700
1701err_out_hpriv:
1702 kfree(hpriv);
1703err_out_iounmap:
374b1873 1704 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1705err_out_free_ent:
1706 kfree(probe_ent);
907f4678
JG		 1707err_out_msi:
1708 if (have_msi)
1709 pci_disable_msi(pdev);
1710 else
1711 pci_intx(pdev, 0);
1da177e4
LT		 1712 pci_release_regions(pdev);
1713err_out:
1714 if (!pci_dev_busy)
1715 pci_disable_device(pdev);
1716 return rc;
1717}
1718
907f4678
JG		 1719static void ahci_remove_one (struct pci_dev *pdev)
1720{
1721 struct device *dev = pci_dev_to_dev(pdev);
cca3974e
JG		 1722 struct ata_host *host = dev_get_drvdata(dev);
1723 struct ahci_host_priv *hpriv = host->private_data;
907f4678
JG		 1724 unsigned int i;
1725 int have_msi;
1726
cca3974e
JG		 1727 for (i = 0; i < host->n_ports; i++)
1728 ata_port_detach(host->ports[i]);
907f4678 1729
4b0060f4 1730 have_msi = hpriv->flags & AHCI_FLAG_MSI;
cca3974e 1731 free_irq(host->irq, host);
907f4678 1732
cca3974e
JG		 1733 for (i = 0; i < host->n_ports; i++) {
1734 struct ata_port *ap = host->ports[i];
907f4678 1735
cca3974e
JG		 1736 ata_scsi_release(ap->scsi_host);
1737 scsi_host_put(ap->scsi_host);
907f4678
JG		 1738 }
1739
e005f01d 1740 kfree(hpriv);
cca3974e
JG		 1741 pci_iounmap(pdev, host->mmio_base);
1742 kfree(host);
ead5de99 1743
907f4678
JG		 1744 if (have_msi)
1745 pci_disable_msi(pdev);
1746 else
1747 pci_intx(pdev, 0);
1748 pci_release_regions(pdev);
907f4678
JG		 1749 pci_disable_device(pdev);
1750 dev_set_drvdata(dev, NULL);
1751}
1da177e4
LT		 1752
1753static int __init ahci_init(void)
1754{
b7887196 1755 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1756}
1757
1da177e4
LT		 1758static void __exit ahci_exit(void)
1759{
1760 pci_unregister_driver(&ahci_pci_driver);
1761}
1762
1763
1764MODULE_AUTHOR("Jeff Garzik");
1765MODULE_DESCRIPTION("AHCI SATA low-level driver");
1766MODULE_LICENSE("GPL");
1767MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1768MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1769
1770module_init(ahci_init);
1771module_exit(ahci_exit);
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