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[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
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1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
87943acf
DM		 52/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
a22e6444 63static int ahci_skip_host_reset;
f3d7f23f
AV		 64static int ahci_ignore_sss;
65
a22e6444
TH		 66module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
f3d7f23f
AV		 69module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
31556594
KCA		 72static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 75static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
1da177e4
LT		 80
81enum {
82 AHCI_PCI_BAR = 5,
648a88be 83 AHCI_MAX_PORTS = 32,
1da177e4
LT		 84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 86 AHCI_MAX_CMDS = 32,
dd410ff1 87 AHCI_CMD_SZ = 32,
12fad3f9 88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 89 AHCI_RX_FIS_SZ = 256,
a0ea7328 90 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 95 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
4b10e559 99 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 106
107 board_ahci = 0,
7a234aff
TH		 108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
e427fe04 112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
e297d99e 113 board_ahci_mcp65 = 6,
9a3b103c 114 board_ahci_nopmp = 7,
aa431dd3 115 board_ahci_yesncq = 8,
1da177e4
LT		 116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
1da177e4
LT		 125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
18f7ba4c 132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
0be0aa98 133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
78cd52d0
TH		 179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
4296971d 182 PORT_IRQ_PHYRDY |
7d50b60b
TH		 183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 191
192 /* PORT_CMD bits */
31556594
KCA		 193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 200 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
0be0aa98 205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 209
417a1a6d
TH		 210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
9b10ae86 221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
5594639a
TH		 222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
223 link offline */
417a1a6d 224
bf2af2a2 225 /* ap->flags bits */
1188c0d8
TH		 226
227 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 229 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
230 ATA_FLAG_IPM,
c4f7792c
TH		 231
232 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c 233
d50ce07d
TH		 234 /* em constants */
235 EM_MAX_SLOTS = 8,
236 EM_MAX_RETRY = 5,
237
18f7ba4c
KCA		 238 /* em_ctl bits */
239 EM_CTL_RST = (1 << 9), /* Reset */
240 EM_CTL_TM = (1 << 8), /* Transmit Message */
241 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 242};
243
244struct ahci_cmd_hdr {
4ca4e439
AV		 245 __le32 opts;
246 __le32 status;
247 __le32 tbl_addr;
248 __le32 tbl_addr_hi;
249 __le32 reserved[4];
1da177e4
LT		 250};
251
252struct ahci_sg {
4ca4e439
AV		 253 __le32 addr;
254 __le32 addr_hi;
255 __le32 reserved;
256 __le32 flags_size;
1da177e4
LT		 257};
258
18f7ba4c
KCA		 259struct ahci_em_priv {
260 enum sw_activity blink_policy;
261 struct timer_list timer;
262 unsigned long saved_activity;
263 unsigned long activity;
264 unsigned long led_state;
265};
266
1da177e4 267struct ahci_host_priv {
417a1a6d 268 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 269 u32 cap; /* cap to use */
270 u32 port_map; /* port map to use */
271 u32 saved_cap; /* saved initial cap */
272 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 273 u32 em_loc; /* enclosure management location */
1da177e4
LT		 274};
275
276struct ahci_port_priv {
7d50b60b 277 struct ata_link *active_link;
1da177e4
LT		 278 struct ahci_cmd_hdr *cmd_slot;
279 dma_addr_t cmd_slot_dma;
280 void *cmd_tbl;
281 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 282 void *rx_fis;
283 dma_addr_t rx_fis_dma;
0291f95f 284 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 285 unsigned int ncq_saw_d2h:1;
286 unsigned int ncq_saw_dmas:1;
afb2d552 287 unsigned int ncq_saw_sdb:1;
a7384925 288 u32 intr_mask; /* interrupts to enable */
d50ce07d
TH		 289 /* enclosure management info per PM slot */
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
1da177e4
LT		 291};
292
82ef04fb
TH		 293static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
294static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
2dcb407e 295static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 296static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 297static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 298static int ahci_port_start(struct ata_port *ap);
299static void ahci_port_stop(struct ata_port *ap);
1da177e4 300static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 301static void ahci_freeze(struct ata_port *ap);
302static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 303static void ahci_pmp_attach(struct ata_port *ap);
304static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 305static int ahci_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
bd17243a
SH		 307static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
a1efdaba
TH		 309static int ahci_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
311static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline);
313static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
314 unsigned long deadline);
315static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 316static void ahci_error_handler(struct ata_port *ap);
317static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 318static int ahci_port_resume(struct ata_port *ap);
a878539e 319static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 320static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
321 u32 opts);
438ac6d5 322#ifdef CONFIG_PM
c1332875 323static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 324static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
325static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 326#endif
18f7ba4c
KCA		 327static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
328static ssize_t ahci_activity_store(struct ata_device *dev,
329 enum sw_activity val);
330static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 331
77cdec1a
MG		 332static ssize_t ahci_show_host_caps(struct device *dev,
333 struct device_attribute *attr, char *buf);
334static ssize_t ahci_show_host_version(struct device *dev,
335 struct device_attribute *attr, char *buf);
336static ssize_t ahci_show_port_cmd(struct device *dev,
337 struct device_attribute *attr, char *buf);
338
339DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
340DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
341DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
342
ee959b00
TJ		 343static struct device_attribute *ahci_shost_attrs[] = {
344 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 345 &dev_attr_em_message_type,
346 &dev_attr_em_message,
77cdec1a
MG		 347 &dev_attr_ahci_host_caps,
348 &dev_attr_ahci_host_version,
349 &dev_attr_ahci_port_cmd,
18f7ba4c
KCA		 350 NULL
351};
352
353static struct device_attribute *ahci_sdev_attrs[] = {
354 &dev_attr_sw_activity,
45fabbb7 355 &dev_attr_unload_heads,
31556594
KCA		 356 NULL
357};
358
193515d5 359static struct scsi_host_template ahci_sht = {
68d1d07b 360 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 361 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 362 .sg_tablesize = AHCI_MAX_SG,
1da177e4 363 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 364 .shost_attrs = ahci_shost_attrs,
18f7ba4c 365 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 366};
367
029cfd6b
TH		 368static struct ata_port_operations ahci_ops = {
369 .inherits = &sata_pmp_port_ops,
370
7d50b60b 371 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 372 .qc_prep = ahci_qc_prep,
373 .qc_issue = ahci_qc_issue,
4c9bf4e7 374 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 375
78cd52d0
TH		 376 .freeze = ahci_freeze,
377 .thaw = ahci_thaw,
a1efdaba
TH		 378 .softreset = ahci_softreset,
379 .hardreset = ahci_hardreset,
380 .postreset = ahci_postreset,
071f44b1 381 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 382 .error_handler = ahci_error_handler,
383 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 384 .dev_config = ahci_dev_config,
385
ad616ffb
TH		 386 .scr_read = ahci_scr_read,
387 .scr_write = ahci_scr_write,
7d50b60b
TH		 388 .pmp_attach = ahci_pmp_attach,
389 .pmp_detach = ahci_pmp_detach,
7d50b60b 390
029cfd6b
TH		 391 .enable_pm = ahci_enable_alpm,
392 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 393 .em_show = ahci_led_show,
394 .em_store = ahci_led_store,
395 .sw_activity_show = ahci_activity_show,
396 .sw_activity_store = ahci_activity_store,
438ac6d5 397#ifdef CONFIG_PM
ad616ffb
TH		 398 .port_suspend = ahci_port_suspend,
399 .port_resume = ahci_port_resume,
438ac6d5 400#endif
ad616ffb
TH		 401 .port_start = ahci_port_start,
402 .port_stop = ahci_port_stop,
403};
404
029cfd6b
TH		 405static struct ata_port_operations ahci_vt8251_ops = {
406 .inherits = &ahci_ops,
a1efdaba 407 .hardreset = ahci_vt8251_hardreset,
029cfd6b 408};
edc93052 409
029cfd6b
TH		 410static struct ata_port_operations ahci_p5wdh_ops = {
411 .inherits = &ahci_ops,
a1efdaba 412 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 413};
414
bd17243a
SH		 415static struct ata_port_operations ahci_sb600_ops = {
416 .inherits = &ahci_ops,
417 .softreset = ahci_sb600_softreset,
418 .pmp_softreset = ahci_sb600_softreset,
419};
420
417a1a6d
TH		 421#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
422
98ac62de 423static const struct ata_port_info ahci_port_info[] = {
4da646b7 424 [board_ahci] =
1da177e4 425 {
1188c0d8 426 .flags = AHCI_FLAG_COMMON,
14bdef98 427 .pio_mask = ATA_PIO4,
469248ab 428 .udma_mask = ATA_UDMA6,
1da177e4
LT		 429 .port_ops = &ahci_ops,
430 },
4da646b7 431 [board_ahci_vt8251] =
bf2af2a2 432 {
6949b914 433 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 434 .flags = AHCI_FLAG_COMMON,
14bdef98 435 .pio_mask = ATA_PIO4,
469248ab 436 .udma_mask = ATA_UDMA6,
ad616ffb 437 .port_ops = &ahci_vt8251_ops,
bf2af2a2 438 },
4da646b7 439 [board_ahci_ign_iferr] =
41669553 440 {
417a1a6d
TH		 441 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
442 .flags = AHCI_FLAG_COMMON,
14bdef98 443 .pio_mask = ATA_PIO4,
469248ab 444 .udma_mask = ATA_UDMA6,
41669553
TH		 445 .port_ops = &ahci_ops,
446 },
4da646b7 447 [board_ahci_sb600] =
55a61604 448 {
417a1a6d 449 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
58a09b38 450 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
417a1a6d 451 .flags = AHCI_FLAG_COMMON,
14bdef98 452 .pio_mask = ATA_PIO4,
469248ab 453 .udma_mask = ATA_UDMA6,
bd17243a 454 .port_ops = &ahci_sb600_ops,
55a61604 455 },
4da646b7 456 [board_ahci_mv] =
cd70c266 457 {
417a1a6d 458 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 459 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 460 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 461 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 462 .pio_mask = ATA_PIO4,
cd70c266
JG		 463 .udma_mask = ATA_UDMA6,
464 .port_ops = &ahci_ops,
465 },
4da646b7 466 [board_ahci_sb700] = /* for SB700 and SB800 */
e39fc8c9 467 {
bd17243a 468 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 469 .flags = AHCI_FLAG_COMMON,
14bdef98 470 .pio_mask = ATA_PIO4,
e39fc8c9 471 .udma_mask = ATA_UDMA6,
bd17243a 472 .port_ops = &ahci_sb600_ops,
e39fc8c9 473 },
4da646b7 474 [board_ahci_mcp65] =
e297d99e
TH		 475 {
476 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
477 .flags = AHCI_FLAG_COMMON,
14bdef98 478 .pio_mask = ATA_PIO4,
e297d99e
TH		 479 .udma_mask = ATA_UDMA6,
480 .port_ops = &ahci_ops,
481 },
4da646b7 482 [board_ahci_nopmp] =
9a3b103c
TH		 483 {
484 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
485 .flags = AHCI_FLAG_COMMON,
14bdef98 486 .pio_mask = ATA_PIO4,
9a3b103c
TH		 487 .udma_mask = ATA_UDMA6,
488 .port_ops = &ahci_ops,
489 },
aa431dd3
TH		 490 /* board_ahci_yesncq */
491 {
492 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
493 .flags = AHCI_FLAG_COMMON,
494 .pio_mask = ATA_PIO4,
495 .udma_mask = ATA_UDMA6,
496 .port_ops = &ahci_ops,
497 },
1da177e4
LT		 498};
499
3b7d697d 500static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 501 /* Intel */
54bb3a94
JG		 502 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
503 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
504 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
505 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
506 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 507 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 508 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
509 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
510 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
511 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 512 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
513 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
514 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
515 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
516 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
517 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
518 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
519 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
520 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
521 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
522 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
523 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
524 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
525 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
526 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
527 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
528 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 529 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
530 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 531 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 532 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 533 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 534 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
535 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 536 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 537 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 538 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 539 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 540 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 541 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
fe7fa31a 542
e34bb370
TH		 543 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
544 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
545 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 546
547 /* ATI */
c65ec1c2 548 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 549 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
550 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
551 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
552 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
553 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
554 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 555
556 /* VIA */
54bb3a94 557 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 558 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 559
560 /* NVIDIA */
e297d99e
TH		 561 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
562 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
563 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
564 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
565 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
566 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
567 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
568 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
aa431dd3
TH		 569 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
570 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
571 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
572 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
573 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
574 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
575 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
576 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
577 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
578 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
579 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
580 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
581 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
582 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
583 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
584 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
585 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
586 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
587 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
588 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
589 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
590 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
591 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
592 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
0522b286
PC		 593 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
594 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
595 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
596 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
597 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
598 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
599 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
600 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
601 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
602 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
603 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
604 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 605 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
606 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
607 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
608 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 609 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
610 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
611 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
612 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
613 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
614 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
615 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
616 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
7adbe46b 617 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
618 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
619 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
620 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
621 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
622 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
623 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
624 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
625 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
626 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
627 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
628 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
fe7fa31a 629
95916edd 630 /* SiS */
20e2de4a
TH		 631 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
632 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
633 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 634
cd70c266
JG		 635 /* Marvell */
636 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 637 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 638
c77a036b
MN		 639 /* Promise */
640 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
641
415ae2b5
JG		 642 /* Generic, PCI class code for AHCI */
643 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 644 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 645
1da177e4
LT		 646 { } /* terminate list */
647};
648
649
650static struct pci_driver ahci_pci_driver = {
651 .name = DRV_NAME,
652 .id_table = ahci_pci_tbl,
653 .probe = ahci_init_one,
24dc5f33 654 .remove = ata_pci_remove_one,
438ac6d5 655#ifdef CONFIG_PM
c1332875
TH		 656 .suspend = ahci_pci_device_suspend,
657 .resume = ahci_pci_device_resume,
438ac6d5 658#endif
1da177e4
LT		 659};
660
18f7ba4c
KCA		 661static int ahci_em_messages = 1;
662module_param(ahci_em_messages, int, 0444);
663/* add other LED protocol types when they become supported */
664MODULE_PARM_DESC(ahci_em_messages,
665 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 666
5b66c829
AC		 667#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
668static int marvell_enable;
669#else
670static int marvell_enable = 1;
671#endif
672module_param(marvell_enable, int, 0644);
673MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
674
675
98fa4b60
TH		 676static inline int ahci_nr_ports(u32 cap)
677{
678 return (cap & 0x1f) + 1;
679}
680
dab632e8
JG		 681static inline void __iomem *__ahci_port_base(struct ata_host *host,
682 unsigned int port_no)
1da177e4 683{
dab632e8 684 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 685
dab632e8
JG		 686 return mmio + 0x100 + (port_no * 0x80);
687}
688
689static inline void __iomem *ahci_port_base(struct ata_port *ap)
690{
691 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 692}
693
b710a1f4
TH		 694static void ahci_enable_ahci(void __iomem *mmio)
695{
15fe982e 696 int i;
b710a1f4
TH		 697 u32 tmp;
698
699 /* turn on AHCI_EN */
700 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 701 if (tmp & HOST_AHCI_EN)
702 return;
703
704 /* Some controllers need AHCI_EN to be written multiple times.
705 * Try a few times before giving up.
706 */
707 for (i = 0; i < 5; i++) {
b710a1f4
TH		 708 tmp |= HOST_AHCI_EN;
709 writel(tmp, mmio + HOST_CTL);
710 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 711 if (tmp & HOST_AHCI_EN)
712 return;
713 msleep(10);
b710a1f4 714 }
15fe982e
TH		 715
716 WARN_ON(1);
b710a1f4
TH		 717}
718
77cdec1a
MG		 719static ssize_t ahci_show_host_caps(struct device *dev,
720 struct device_attribute *attr, char *buf)
721{
722 struct Scsi_Host *shost = class_to_shost(dev);
723 struct ata_port *ap = ata_shost_to_port(shost);
724 struct ahci_host_priv *hpriv = ap->host->private_data;
725
726 return sprintf(buf, "%x\n", hpriv->cap);
727}
728
729static ssize_t ahci_show_host_version(struct device *dev,
730 struct device_attribute *attr, char *buf)
731{
732 struct Scsi_Host *shost = class_to_shost(dev);
733 struct ata_port *ap = ata_shost_to_port(shost);
734 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
735
736 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
737}
738
739static ssize_t ahci_show_port_cmd(struct device *dev,
740 struct device_attribute *attr, char *buf)
741{
742 struct Scsi_Host *shost = class_to_shost(dev);
743 struct ata_port *ap = ata_shost_to_port(shost);
744 void __iomem *port_mmio = ahci_port_base(ap);
745
746 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
747}
748
d447df14
TH		 749/**
750 * ahci_save_initial_config - Save and fixup initial config values
4447d351 751 * @pdev: target PCI device
4447d351 752 * @hpriv: host private area to store config values
d447df14
TH		 753 *
754 * Some registers containing configuration info might be setup by
755 * BIOS and might be cleared on reset. This function saves the
756 * initial values of those registers into @hpriv such that they
757 * can be restored after controller reset.
758 *
759 * If inconsistent, config values are fixed up by this function.
760 *
761 * LOCKING:
762 * None.
763 */
4447d351 764static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 765 struct ahci_host_priv *hpriv)
d447df14 766{
4447d351 767 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 768 u32 cap, port_map;
17199b18 769 int i;
c40e7cb8 770 int mv;
d447df14 771
b710a1f4
TH		 772 /* make sure AHCI mode is enabled before accessing CAP */
773 ahci_enable_ahci(mmio);
774
d447df14
TH		 775 /* Values prefixed with saved_ are written back to host after
776 * reset. Values without are used for driver operation.
777 */
778 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
779 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
780
274c1fde 781 /* some chips have errata preventing 64bit use */
417a1a6d 782 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 783 dev_printk(KERN_INFO, &pdev->dev,
784 "controller can't do 64bit DMA, forcing 32bit\n");
785 cap &= ~HOST_CAP_64;
786 }
787
417a1a6d 788 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 789 dev_printk(KERN_INFO, &pdev->dev,
790 "controller can't do NCQ, turning off CAP_NCQ\n");
791 cap &= ~HOST_CAP_NCQ;
792 }
793
e297d99e
TH		 794 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
795 dev_printk(KERN_INFO, &pdev->dev,
796 "controller can do NCQ, turning on CAP_NCQ\n");
797 cap |= HOST_CAP_NCQ;
798 }
799
258cd846 800 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 801 dev_printk(KERN_INFO, &pdev->dev,
802 "controller can't do PMP, turning off CAP_PMP\n");
803 cap &= ~HOST_CAP_PMP;
804 }
805
d799e083
TH		 806 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
807 port_map != 1) {
808 dev_printk(KERN_INFO, &pdev->dev,
809 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
810 port_map, 1);
811 port_map = 1;
812 }
813
cd70c266
JG		 814 /*
815 * Temporary Marvell 6145 hack: PATA port presence
816 * is asserted through the standard AHCI port
817 * presence register, as bit 4 (counting from 0)
818 */
417a1a6d 819 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 820 if (pdev->device == 0x6121)
821 mv = 0x3;
822 else
823 mv = 0xf;
cd70c266
JG		 824 dev_printk(KERN_ERR, &pdev->dev,
825 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 826 port_map,
827 port_map & mv);
5b66c829
AC		 828 dev_printk(KERN_ERR, &pdev->dev,
829 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
cd70c266 830
c40e7cb8 831 port_map &= mv;
cd70c266
JG		 832 }
833
17199b18 834 /* cross check port_map and cap.n_ports */
7a234aff 835 if (port_map) {
837f5f8f 836 int map_ports = 0;
17199b18 837
837f5f8f
TH		 838 for (i = 0; i < AHCI_MAX_PORTS; i++)
839 if (port_map & (1 << i))
840 map_ports++;
17199b18 841
837f5f8f
TH		 842 /* If PI has more ports than n_ports, whine, clear
843 * port_map and let it be generated from n_ports.
17199b18 844 */
837f5f8f 845 if (map_ports > ahci_nr_ports(cap)) {
4447d351 846 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 847 "implemented port map (0x%x) contains more "
848 "ports than nr_ports (%u), using nr_ports\n",
849 port_map, ahci_nr_ports(cap));
7a234aff
TH		 850 port_map = 0;
851 }
852 }
853
854 /* fabricate port_map from cap.nr_ports */
855 if (!port_map) {
17199b18 856 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 857 dev_printk(KERN_WARNING, &pdev->dev,
858 "forcing PORTS_IMPL to 0x%x\n", port_map);
859
860 /* write the fixed up value to the PI register */
861 hpriv->saved_port_map = port_map;
17199b18
TH		 862 }
863
d447df14
TH		 864 /* record values to use during operation */
865 hpriv->cap = cap;
866 hpriv->port_map = port_map;
867}
868
869/**
870 * ahci_restore_initial_config - Restore initial config
4447d351 871 * @host: target ATA host
d447df14
TH		 872 *
873 * Restore initial config stored by ahci_save_initial_config().
874 *
875 * LOCKING:
876 * None.
877 */
4447d351 878static void ahci_restore_initial_config(struct ata_host *host)
d447df14 879{
4447d351
TH		 880 struct ahci_host_priv *hpriv = host->private_data;
881 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
882
d447df14
TH		 883 writel(hpriv->saved_cap, mmio + HOST_CAP);
884 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
885 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
886}
887
203ef6c4 888static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 889{
203ef6c4
TH		 890 static const int offset[] = {
891 [SCR_STATUS] = PORT_SCR_STAT,
892 [SCR_CONTROL] = PORT_SCR_CTL,
893 [SCR_ERROR] = PORT_SCR_ERR,
894 [SCR_ACTIVE] = PORT_SCR_ACT,
895 [SCR_NOTIFICATION] = PORT_SCR_NTF,
896 };
897 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 898
203ef6c4
TH		 899 if (sc_reg < ARRAY_SIZE(offset) &&
900 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
901 return offset[sc_reg];
da3dbb17 902 return 0;
1da177e4
LT		 903}
904
82ef04fb 905static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1da177e4 906{
82ef04fb
TH		 907 void __iomem *port_mmio = ahci_port_base(link->ap);
908 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 909
910 if (offset) {
911 *val = readl(port_mmio + offset);
912 return 0;
1da177e4 913 }
203ef6c4
TH		 914 return -EINVAL;
915}
1da177e4 916
82ef04fb 917static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
203ef6c4 918{
82ef04fb
TH		 919 void __iomem *port_mmio = ahci_port_base(link->ap);
920 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 921
922 if (offset) {
923 writel(val, port_mmio + offset);
924 return 0;
925 }
926 return -EINVAL;
1da177e4
LT		 927}
928
4447d351 929static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 930{
4447d351 931 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 932 u32 tmp;
933
d8fcd116 934 /* start DMA */
9f592056 935 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 936 tmp |= PORT_CMD_START;
937 writel(tmp, port_mmio + PORT_CMD);
938 readl(port_mmio + PORT_CMD); /* flush */
939}
940
4447d351 941static int ahci_stop_engine(struct ata_port *ap)
254950cd 942{
4447d351 943 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 944 u32 tmp;
945
946 tmp = readl(port_mmio + PORT_CMD);
947
d8fcd116 948 /* check if the HBA is idle */
254950cd
TH		 949 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
950 return 0;
951
d8fcd116 952 /* setting HBA to idle */
254950cd
TH		 953 tmp &= ~PORT_CMD_START;
954 writel(tmp, port_mmio + PORT_CMD);
955
d8fcd116 956 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 957 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 958 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 959 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 960 return -EIO;
961
962 return 0;
963}
964
4447d351 965static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 966{
4447d351
TH		 967 void __iomem *port_mmio = ahci_port_base(ap);
968 struct ahci_host_priv *hpriv = ap->host->private_data;
969 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 970 u32 tmp;
971
972 /* set FIS registers */
4447d351
TH		 973 if (hpriv->cap & HOST_CAP_64)
974 writel((pp->cmd_slot_dma >> 16) >> 16,
975 port_mmio + PORT_LST_ADDR_HI);
976 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 977
4447d351
TH		 978 if (hpriv->cap & HOST_CAP_64)
979 writel((pp->rx_fis_dma >> 16) >> 16,
980 port_mmio + PORT_FIS_ADDR_HI);
981 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 982
983 /* enable FIS reception */
984 tmp = readl(port_mmio + PORT_CMD);
985 tmp |= PORT_CMD_FIS_RX;
986 writel(tmp, port_mmio + PORT_CMD);
987
988 /* flush */
989 readl(port_mmio + PORT_CMD);
990}
991
4447d351 992static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 993{
4447d351 994 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 995 u32 tmp;
996
997 /* disable FIS reception */
998 tmp = readl(port_mmio + PORT_CMD);
999 tmp &= ~PORT_CMD_FIS_RX;
1000 writel(tmp, port_mmio + PORT_CMD);
1001
1002 /* wait for completion, spec says 500ms, give it 1000 */
1003 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1004 PORT_CMD_FIS_ON, 10, 1000);
1005 if (tmp & PORT_CMD_FIS_ON)
1006 return -EBUSY;
1007
1008 return 0;
1009}
1010
4447d351 1011static void ahci_power_up(struct ata_port *ap)
0be0aa98 1012{
4447d351
TH		 1013 struct ahci_host_priv *hpriv = ap->host->private_data;
1014 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1015 u32 cmd;
1016
1017 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1018
1019 /* spin up device */
4447d351 1020 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 1021 cmd |= PORT_CMD_SPIN_UP;
1022 writel(cmd, port_mmio + PORT_CMD);
1023 }
1024
1025 /* wake up link */
1026 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1027}
1028
31556594
KCA		 1029static void ahci_disable_alpm(struct ata_port *ap)
1030{
1031 struct ahci_host_priv *hpriv = ap->host->private_data;
1032 void __iomem *port_mmio = ahci_port_base(ap);
1033 u32 cmd;
1034 struct ahci_port_priv *pp = ap->private_data;
1035
1036 /* IPM bits should be disabled by libata-core */
1037 /* get the existing command bits */
1038 cmd = readl(port_mmio + PORT_CMD);
1039
1040 /* disable ALPM and ASP */
1041 cmd &= ~PORT_CMD_ASP;
1042 cmd &= ~PORT_CMD_ALPE;
1043
1044 /* force the interface back to active */
1045 cmd |= PORT_CMD_ICC_ACTIVE;
1046
1047 /* write out new cmd value */
1048 writel(cmd, port_mmio + PORT_CMD);
1049 cmd = readl(port_mmio + PORT_CMD);
1050
1051 /* wait 10ms to be sure we've come out of any low power state */
1052 msleep(10);
1053
1054 /* clear out any PhyRdy stuff from interrupt status */
1055 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1056
1057 /* go ahead and clean out PhyRdy Change from Serror too */
82ef04fb 1058 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 1059
1060 /*
1061 * Clear flag to indicate that we should ignore all PhyRdy
1062 * state changes
1063 */
1064 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1065
1066 /*
1067 * Enable interrupts on Phy Ready.
1068 */
1069 pp->intr_mask |= PORT_IRQ_PHYRDY;
1070 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1071
1072 /*
1073 * don't change the link pm policy - we can be called
1074 * just to turn of link pm temporarily
1075 */
1076}
1077
1078static int ahci_enable_alpm(struct ata_port *ap,
1079 enum link_pm policy)
1080{
1081 struct ahci_host_priv *hpriv = ap->host->private_data;
1082 void __iomem *port_mmio = ahci_port_base(ap);
1083 u32 cmd;
1084 struct ahci_port_priv *pp = ap->private_data;
1085 u32 asp;
1086
1087 /* Make sure the host is capable of link power management */
1088 if (!(hpriv->cap & HOST_CAP_ALPM))
1089 return -EINVAL;
1090
1091 switch (policy) {
1092 case MAX_PERFORMANCE:
1093 case NOT_AVAILABLE:
1094 /*
1095 * if we came here with NOT_AVAILABLE,
1096 * it just means this is the first time we
1097 * have tried to enable - default to max performance,
1098 * and let the user go to lower power modes on request.
1099 */
1100 ahci_disable_alpm(ap);
1101 return 0;
1102 case MIN_POWER:
1103 /* configure HBA to enter SLUMBER */
1104 asp = PORT_CMD_ASP;
1105 break;
1106 case MEDIUM_POWER:
1107 /* configure HBA to enter PARTIAL */
1108 asp = 0;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113
1114 /*
1115 * Disable interrupts on Phy Ready. This keeps us from
1116 * getting woken up due to spurious phy ready interrupts
1117 * TBD - Hot plug should be done via polling now, is
1118 * that even supported?
1119 */
1120 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1121 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1122
1123 /*
1124 * Set a flag to indicate that we should ignore all PhyRdy
1125 * state changes since these can happen now whenever we
1126 * change link state
1127 */
1128 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1129
1130 /* get the existing command bits */
1131 cmd = readl(port_mmio + PORT_CMD);
1132
1133 /*
1134 * Set ASP based on Policy
1135 */
1136 cmd |= asp;
1137
1138 /*
1139 * Setting this bit will instruct the HBA to aggressively
1140 * enter a lower power link state when it's appropriate and
1141 * based on the value set above for ASP
1142 */
1143 cmd |= PORT_CMD_ALPE;
1144
1145 /* write out new cmd value */
1146 writel(cmd, port_mmio + PORT_CMD);
1147 cmd = readl(port_mmio + PORT_CMD);
1148
1149 /* IPM bits should be set by libata-core */
1150 return 0;
1151}
1152
438ac6d5 1153#ifdef CONFIG_PM
4447d351 1154static void ahci_power_down(struct ata_port *ap)
0be0aa98 1155{
4447d351
TH		 1156 struct ahci_host_priv *hpriv = ap->host->private_data;
1157 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1158 u32 cmd, scontrol;
1159
4447d351 1160 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1161 return;
0be0aa98 1162
07c53dac
TH		 1163 /* put device into listen mode, first set PxSCTL.DET to 0 */
1164 scontrol = readl(port_mmio + PORT_SCR_CTL);
1165 scontrol &= ~0xf;
1166 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1167
07c53dac
TH		 1168 /* then set PxCMD.SUD to 0 */
1169 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1170 cmd &= ~PORT_CMD_SPIN_UP;
1171 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1172}
438ac6d5 1173#endif
0be0aa98 1174
df69c9c5 1175static void ahci_start_port(struct ata_port *ap)
0be0aa98 1176{
18f7ba4c
KCA		 1177 struct ahci_port_priv *pp = ap->private_data;
1178 struct ata_link *link;
1179 struct ahci_em_priv *emp;
4c1e9aa4
DM		 1180 ssize_t rc;
1181 int i;
18f7ba4c 1182
0be0aa98 1183 /* enable FIS reception */
4447d351 1184 ahci_start_fis_rx(ap);
0be0aa98
TH		 1185
1186 /* enable DMA */
4447d351 1187 ahci_start_engine(ap);
18f7ba4c
KCA		 1188
1189 /* turn on LEDs */
1190 if (ap->flags & ATA_FLAG_EM) {
1eca4365 1191 ata_for_each_link(link, ap, EDGE) {
18f7ba4c 1192 emp = &pp->em_priv[link->pmp];
4c1e9aa4
DM		 1193
1194 /* EM Transmit bit maybe busy during init */
d50ce07d 1195 for (i = 0; i < EM_MAX_RETRY; i++) {
4c1e9aa4
DM		 1196 rc = ahci_transmit_led_message(ap,
1197 emp->led_state,
1198 4);
1199 if (rc == -EBUSY)
d50ce07d 1200 msleep(1);
4c1e9aa4
DM		 1201 else
1202 break;
1203 }
18f7ba4c
KCA		 1204 }
1205 }
1206
1207 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1eca4365 1208 ata_for_each_link(link, ap, EDGE)
18f7ba4c
KCA		 1209 ahci_init_sw_activity(link);
1210
0be0aa98
TH		 1211}
1212
4447d351 1213static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1214{
1215 int rc;
1216
1217 /* disable DMA */
4447d351 1218 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1219 if (rc) {
1220 *emsg = "failed to stop engine";
1221 return rc;
1222 }
1223
1224 /* disable FIS reception */
4447d351 1225 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1226 if (rc) {
1227 *emsg = "failed stop FIS RX";
1228 return rc;
1229 }
1230
0be0aa98
TH		 1231 return 0;
1232}
1233
4447d351 1234static int ahci_reset_controller(struct ata_host *host)
d91542c1 1235{
4447d351 1236 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1237 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1238 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1239 u32 tmp;
d91542c1 1240
3cc3eb11
JG		 1241 /* we must be in AHCI mode, before using anything
1242 * AHCI-specific, such as HOST_RESET.
1243 */
b710a1f4 1244 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1245
1246 /* global controller reset */
a22e6444
TH		 1247 if (!ahci_skip_host_reset) {
1248 tmp = readl(mmio + HOST_CTL);
1249 if ((tmp & HOST_RESET) == 0) {
1250 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1251 readl(mmio + HOST_CTL); /* flush */
1252 }
d91542c1 1253
24920c8a
ZR		 1254 /*
1255 * to perform host reset, OS should set HOST_RESET
1256 * and poll until this bit is read to be "0".
1257 * reset must complete within 1 second, or
a22e6444
TH		 1258 * the hardware should be considered fried.
1259 */
24920c8a
ZR		 1260 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1261 HOST_RESET, 10, 1000);
d91542c1 1262
a22e6444
TH		 1263 if (tmp & HOST_RESET) {
1264 dev_printk(KERN_ERR, host->dev,
1265 "controller reset failed (0x%x)\n", tmp);
1266 return -EIO;
1267 }
d91542c1 1268
a22e6444
TH		 1269 /* turn on AHCI mode */
1270 ahci_enable_ahci(mmio);
98fa4b60 1271
a22e6444
TH		 1272 /* Some registers might be cleared on reset. Restore
1273 * initial values.
1274 */
1275 ahci_restore_initial_config(host);
1276 } else
1277 dev_printk(KERN_INFO, host->dev,
1278 "skipping global host reset\n");
d91542c1
TH		 1279
1280 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1281 u16 tmp16;
1282
1283 /* configure PCS */
1284 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1285 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1286 tmp16 |= hpriv->port_map;
1287 pci_write_config_word(pdev, 0x92, tmp16);
1288 }
d91542c1
TH		 1289 }
1290
1291 return 0;
1292}
1293
18f7ba4c
KCA		 1294static void ahci_sw_activity(struct ata_link *link)
1295{
1296 struct ata_port *ap = link->ap;
1297 struct ahci_port_priv *pp = ap->private_data;
1298 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1299
1300 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1301 return;
1302
1303 emp->activity++;
1304 if (!timer_pending(&emp->timer))
1305 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1306}
1307
1308static void ahci_sw_activity_blink(unsigned long arg)
1309{
1310 struct ata_link *link = (struct ata_link *)arg;
1311 struct ata_port *ap = link->ap;
1312 struct ahci_port_priv *pp = ap->private_data;
1313 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1314 unsigned long led_message = emp->led_state;
1315 u32 activity_led_state;
eb40963c 1316 unsigned long flags;
18f7ba4c 1317
87943acf 1318 led_message &= EM_MSG_LED_VALUE;
18f7ba4c
KCA		 1319 led_message |= ap->port_no | (link->pmp << 8);
1320
1321 /* check to see if we've had activity. If so,
1322 * toggle state of LED and reset timer. If not,
1323 * turn LED to desired idle state.
1324 */
eb40963c 1325 spin_lock_irqsave(ap->lock, flags);
18f7ba4c
KCA		 1326 if (emp->saved_activity != emp->activity) {
1327 emp->saved_activity = emp->activity;
1328 /* get the current LED state */
87943acf 1329 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
18f7ba4c
KCA		 1330
1331 if (activity_led_state)
1332 activity_led_state = 0;
1333 else
1334 activity_led_state = 1;
1335
1336 /* clear old state */
87943acf 1337 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1338
1339 /* toggle state */
1340 led_message |= (activity_led_state << 16);
1341 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1342 } else {
1343 /* switch to idle */
87943acf 1344 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1345 if (emp->blink_policy == BLINK_OFF)
1346 led_message |= (1 << 16);
1347 }
eb40963c 1348 spin_unlock_irqrestore(ap->lock, flags);
18f7ba4c
KCA		 1349 ahci_transmit_led_message(ap, led_message, 4);
1350}
1351
1352static void ahci_init_sw_activity(struct ata_link *link)
1353{
1354 struct ata_port *ap = link->ap;
1355 struct ahci_port_priv *pp = ap->private_data;
1356 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1357
1358 /* init activity stats, setup timer */
1359 emp->saved_activity = emp->activity = 0;
1360 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1361
1362 /* check our blink policy and set flag for link if it's enabled */
1363 if (emp->blink_policy)
1364 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1365}
1366
1367static int ahci_reset_em(struct ata_host *host)
1368{
1369 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1370 u32 em_ctl;
1371
1372 em_ctl = readl(mmio + HOST_EM_CTL);
1373 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1374 return -EINVAL;
1375
1376 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1377 return 0;
1378}
1379
1380static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1381 ssize_t size)
1382{
1383 struct ahci_host_priv *hpriv = ap->host->private_data;
1384 struct ahci_port_priv *pp = ap->private_data;
1385 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1386 u32 em_ctl;
1387 u32 message[] = {0, 0};
93082f0b 1388 unsigned long flags;
18f7ba4c
KCA		 1389 int pmp;
1390 struct ahci_em_priv *emp;
1391
1392 /* get the slot number from the message */
87943acf 1393 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
d50ce07d 1394 if (pmp < EM_MAX_SLOTS)
18f7ba4c
KCA		 1395 emp = &pp->em_priv[pmp];
1396 else
1397 return -EINVAL;
1398
1399 spin_lock_irqsave(ap->lock, flags);
1400
1401 /*
1402 * if we are still busy transmitting a previous message,
1403 * do not allow
1404 */
1405 em_ctl = readl(mmio + HOST_EM_CTL);
1406 if (em_ctl & EM_CTL_TM) {
1407 spin_unlock_irqrestore(ap->lock, flags);
4c1e9aa4 1408 return -EBUSY;
18f7ba4c
KCA		 1409 }
1410
1411 /*
1412 * create message header - this is all zero except for
1413 * the message size, which is 4 bytes.
1414 */
1415 message[0] |= (4 << 8);
1416
1417 /* ignore 0:4 of byte zero, fill in port info yourself */
87943acf 1418 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
18f7ba4c
KCA		 1419
1420 /* write message to EM_LOC */
1421 writel(message[0], mmio + hpriv->em_loc);
1422 writel(message[1], mmio + hpriv->em_loc+4);
1423
1424 /* save off new led state for port/slot */
208f2a88 1425 emp->led_state = state;
18f7ba4c
KCA		 1426
1427 /*
1428 * tell hardware to transmit the message
1429 */
1430 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1431
1432 spin_unlock_irqrestore(ap->lock, flags);
1433 return size;
1434}
1435
1436static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1437{
1438 struct ahci_port_priv *pp = ap->private_data;
1439 struct ata_link *link;
1440 struct ahci_em_priv *emp;
1441 int rc = 0;
1442
1eca4365 1443 ata_for_each_link(link, ap, EDGE) {
18f7ba4c
KCA		 1444 emp = &pp->em_priv[link->pmp];
1445 rc += sprintf(buf, "%lx\n", emp->led_state);
1446 }
1447 return rc;
1448}
1449
1450static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1451 size_t size)
1452{
1453 int state;
1454 int pmp;
1455 struct ahci_port_priv *pp = ap->private_data;
1456 struct ahci_em_priv *emp;
1457
1458 state = simple_strtoul(buf, NULL, 0);
1459
1460 /* get the slot number from the message */
87943acf 1461 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
d50ce07d 1462 if (pmp < EM_MAX_SLOTS)
18f7ba4c
KCA		 1463 emp = &pp->em_priv[pmp];
1464 else
1465 return -EINVAL;
1466
1467 /* mask off the activity bits if we are in sw_activity
1468 * mode, user should turn off sw_activity before setting
1469 * activity led through em_message
1470 */
1471 if (emp->blink_policy)
87943acf 1472 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1473
1474 return ahci_transmit_led_message(ap, state, size);
1475}
1476
1477static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1478{
1479 struct ata_link *link = dev->link;
1480 struct ata_port *ap = link->ap;
1481 struct ahci_port_priv *pp = ap->private_data;
1482 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1483 u32 port_led_state = emp->led_state;
1484
1485 /* save the desired Activity LED behavior */
1486 if (val == OFF) {
1487 /* clear LFLAG */
1488 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1489
1490 /* set the LED to OFF */
87943acf 1491 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c
KCA		 1492 port_led_state |= (ap->port_no | (link->pmp << 8));
1493 ahci_transmit_led_message(ap, port_led_state, 4);
1494 } else {
1495 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1496 if (val == BLINK_OFF) {
1497 /* set LED to ON for idle */
87943acf 1498 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c 1499 port_led_state |= (ap->port_no | (link->pmp << 8));
87943acf 1500 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
18f7ba4c
KCA		 1501 ahci_transmit_led_message(ap, port_led_state, 4);
1502 }
1503 }
1504 emp->blink_policy = val;
1505 return 0;
1506}
1507
1508static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1509{
1510 struct ata_link *link = dev->link;
1511 struct ata_port *ap = link->ap;
1512 struct ahci_port_priv *pp = ap->private_data;
1513 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1514
1515 /* display the saved value of activity behavior for this
1516 * disk.
1517 */
1518 return sprintf(buf, "%d\n", emp->blink_policy);
1519}
1520
2bcd866b
JG		 1521static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1522 int port_no, void __iomem *mmio,
1523 void __iomem *port_mmio)
1524{
1525 const char *emsg = NULL;
1526 int rc;
1527 u32 tmp;
1528
1529 /* make sure port is not active */
1530 rc = ahci_deinit_port(ap, &emsg);
1531 if (rc)
1532 dev_printk(KERN_WARNING, &pdev->dev,
1533 "%s (%d)\n", emsg, rc);
1534
1535 /* clear SError */
1536 tmp = readl(port_mmio + PORT_SCR_ERR);
1537 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1538 writel(tmp, port_mmio + PORT_SCR_ERR);
1539
1540 /* clear port IRQ */
1541 tmp = readl(port_mmio + PORT_IRQ_STAT);
1542 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1543 if (tmp)
1544 writel(tmp, port_mmio + PORT_IRQ_STAT);
1545
1546 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1547}
1548
4447d351 1549static void ahci_init_controller(struct ata_host *host)
d91542c1 1550{
417a1a6d 1551 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1552 struct pci_dev *pdev = to_pci_dev(host->dev);
1553 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1554 int i;
cd70c266 1555 void __iomem *port_mmio;
d91542c1 1556 u32 tmp;
c40e7cb8 1557 int mv;
d91542c1 1558
417a1a6d 1559 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1560 if (pdev->device == 0x6121)
1561 mv = 2;
1562 else
1563 mv = 4;
1564 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1565
1566 writel(0, port_mmio + PORT_IRQ_MASK);
1567
1568 /* clear port IRQ */
1569 tmp = readl(port_mmio + PORT_IRQ_STAT);
1570 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1571 if (tmp)
1572 writel(tmp, port_mmio + PORT_IRQ_STAT);
1573 }
1574
4447d351
TH		 1575 for (i = 0; i < host->n_ports; i++) {
1576 struct ata_port *ap = host->ports[i];
d91542c1 1577
cd70c266 1578 port_mmio = ahci_port_base(ap);
4447d351 1579 if (ata_port_is_dummy(ap))
d91542c1 1580 continue;
d91542c1 1581
2bcd866b 1582 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1583 }
1584
1585 tmp = readl(mmio + HOST_CTL);
1586 VPRINTK("HOST_CTL 0x%x\n", tmp);
1587 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1588 tmp = readl(mmio + HOST_CTL);
1589 VPRINTK("HOST_CTL 0x%x\n", tmp);
1590}
1591
a878539e
JG		 1592static void ahci_dev_config(struct ata_device *dev)
1593{
1594 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1595
4cde32fc 1596 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1597 dev->max_sectors = 255;
4cde32fc
JG		 1598 ata_dev_printk(dev, KERN_INFO,
1599 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1600 }
a878539e
JG		 1601}
1602
422b7595 1603static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1604{
4447d351 1605 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1606 struct ata_taskfile tf;
422b7595
TH		 1607 u32 tmp;
1608
1609 tmp = readl(port_mmio + PORT_SIG);
1610 tf.lbah = (tmp >> 24) & 0xff;
1611 tf.lbam = (tmp >> 16) & 0xff;
1612 tf.lbal = (tmp >> 8) & 0xff;
1613 tf.nsect = (tmp) & 0xff;
1614
1615 return ata_dev_classify(&tf);
1616}
1617
12fad3f9
TH		 1618static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1619 u32 opts)
cc9278ed 1620{
12fad3f9
TH		 1621 dma_addr_t cmd_tbl_dma;
1622
1623 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1624
1625 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1626 pp->cmd_slot[tag].status = 0;
1627 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1628 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1629}
1630
d2e75dff 1631static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1632{
350756f6 1633 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1634 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1635 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1636 u32 tmp;
d2e75dff 1637 int busy, rc;
bf2af2a2 1638
d2e75dff 1639 /* do we need to kick the port? */
520d06f9 1640 busy = status & (ATA_BUSY | ATA_DRQ);
d2e75dff
TH		 1641 if (!busy && !force_restart)
1642 return 0;
1643
1644 /* stop engine */
1645 rc = ahci_stop_engine(ap);
1646 if (rc)
1647 goto out_restart;
1648
1649 /* need to do CLO? */
1650 if (!busy) {
1651 rc = 0;
1652 goto out_restart;
1653 }
1654
1655 if (!(hpriv->cap & HOST_CAP_CLO)) {
1656 rc = -EOPNOTSUPP;
1657 goto out_restart;
1658 }
bf2af2a2 1659
d2e75dff 1660 /* perform CLO */
bf2af2a2
BJ		 1661 tmp = readl(port_mmio + PORT_CMD);
1662 tmp |= PORT_CMD_CLO;
1663 writel(tmp, port_mmio + PORT_CMD);
1664
d2e75dff 1665 rc = 0;
bf2af2a2
BJ		 1666 tmp = ata_wait_register(port_mmio + PORT_CMD,
1667 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1668 if (tmp & PORT_CMD_CLO)
d2e75dff 1669 rc = -EIO;
bf2af2a2 1670
d2e75dff
TH		 1671 /* restart engine */
1672 out_restart:
1673 ahci_start_engine(ap);
1674 return rc;
bf2af2a2
BJ		 1675}
1676
91c4a2e0
TH		 1677static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1678 struct ata_taskfile *tf, int is_cmd, u16 flags,
1679 unsigned long timeout_msec)
bf2af2a2 1680{
91c4a2e0 1681 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1682 struct ahci_port_priv *pp = ap->private_data;
4447d351 1683 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1684 u8 *fis = pp->cmd_tbl;
1685 u32 tmp;
1686
1687 /* prep the command */
1688 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1689 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1690
1691 /* issue & wait */
1692 writel(1, port_mmio + PORT_CMD_ISSUE);
1693
1694 if (timeout_msec) {
1695 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1696 1, timeout_msec);
1697 if (tmp & 0x1) {
1698 ahci_kick_engine(ap, 1);
1699 return -EBUSY;
1700 }
1701 } else
1702 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1703
1704 return 0;
1705}
1706
bd17243a
SH		 1707static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1708 int pmp, unsigned long deadline,
1709 int (*check_ready)(struct ata_link *link))
91c4a2e0 1710{
cc0680a5 1711 struct ata_port *ap = link->ap;
5594639a 1712 struct ahci_host_priv *hpriv = ap->host->private_data;
4658f79b 1713 const char *reason = NULL;
2cbb79eb 1714 unsigned long now, msecs;
4658f79b 1715 struct ata_taskfile tf;
4658f79b
TH		 1716 int rc;
1717
1718 DPRINTK("ENTER\n");
1719
1720 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1721 rc = ahci_kick_engine(ap, 1);
994056d7 1722 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1723 ata_link_printk(link, KERN_WARNING,
994056d7 1724 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1725
cc0680a5 1726 ata_tf_init(link->device, &tf);
4658f79b
TH		 1727
1728 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1729 msecs = 0;
1730 now = jiffies;
1731 if (time_after(now, deadline))
1732 msecs = jiffies_to_msecs(deadline - now);
1733
4658f79b 1734 tf.ctl |= ATA_SRST;
a9cf5e85 1735 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1736 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1737 rc = -EIO;
1738 reason = "1st FIS failed";
1739 goto fail;
1740 }
1741
1742 /* spec says at least 5us, but be generous and sleep for 1ms */
1743 msleep(1);
1744
1745 /* issue the second D2H Register FIS */
4658f79b 1746 tf.ctl &= ~ATA_SRST;
a9cf5e85 1747 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1748
705e76be 1749 /* wait for link to become ready */
bd17243a 1750 rc = ata_wait_after_reset(link, deadline, check_ready);
5594639a
TH		 1751 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1752 /*
1753 * Workaround for cases where link online status can't
1754 * be trusted. Treat device readiness timeout as link
1755 * offline.
1756 */
1757 ata_link_printk(link, KERN_INFO,
1758 "device not ready, treating as offline\n");
1759 *class = ATA_DEV_NONE;
1760 } else if (rc) {
1761 /* link occupied, -ENODEV too is an error */
9b89391c
TH		 1762 reason = "device not ready";
1763 goto fail;
5594639a
TH		 1764 } else
1765 *class = ahci_dev_classify(ap);
4658f79b
TH		 1766
1767 DPRINTK("EXIT, class=%u\n", *class);
1768 return 0;
1769
4658f79b 1770 fail:
cc0680a5 1771 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1772 return rc;
1773}
1774
bd17243a
SH		 1775static int ahci_check_ready(struct ata_link *link)
1776{
1777 void __iomem *port_mmio = ahci_port_base(link->ap);
1778 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1779
1780 return ata_check_ready(status);
1781}
1782
1783static int ahci_softreset(struct ata_link *link, unsigned int *class,
1784 unsigned long deadline)
1785{
1786 int pmp = sata_srst_pmp(link);
1787
1788 DPRINTK("ENTER\n");
1789
1790 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1791}
1792
1793static int ahci_sb600_check_ready(struct ata_link *link)
1794{
1795 void __iomem *port_mmio = ahci_port_base(link->ap);
1796 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1797 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1798
1799 /*
1800 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1801 * which can save timeout delay.
1802 */
1803 if (irq_status & PORT_IRQ_BAD_PMP)
1804 return -EIO;
1805
1806 return ata_check_ready(status);
1807}
1808
1809static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1810 unsigned long deadline)
1811{
1812 struct ata_port *ap = link->ap;
1813 void __iomem *port_mmio = ahci_port_base(ap);
1814 int pmp = sata_srst_pmp(link);
1815 int rc;
1816 u32 irq_sts;
1817
1818 DPRINTK("ENTER\n");
1819
1820 rc = ahci_do_softreset(link, class, pmp, deadline,
1821 ahci_sb600_check_ready);
1822
1823 /*
1824 * Soft reset fails on some ATI chips with IPMS set when PMP
1825 * is enabled but SATA HDD/ODD is connected to SATA port,
1826 * do soft reset again to port 0.
1827 */
1828 if (rc == -EIO) {
1829 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1830 if (irq_sts & PORT_IRQ_BAD_PMP) {
1831 ata_link_printk(link, KERN_WARNING,
b6931c1f
SH		 1832 "applying SB600 PMP SRST workaround "
1833 "and retrying\n");
bd17243a
SH		 1834 rc = ahci_do_softreset(link, class, 0, deadline,
1835 ahci_check_ready);
1836 }
1837 }
1838
1839 return rc;
1840}
1841
cc0680a5 1842static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1843 unsigned long deadline)
422b7595 1844{
9dadd45b 1845 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1846 struct ata_port *ap = link->ap;
4296971d
TH		 1847 struct ahci_port_priv *pp = ap->private_data;
1848 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1849 struct ata_taskfile tf;
9dadd45b 1850 bool online;
4bd00f6a
TH		 1851 int rc;
1852
1853 DPRINTK("ENTER\n");
1da177e4 1854
4447d351 1855 ahci_stop_engine(ap);
4296971d
TH		 1856
1857 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1858 ata_tf_init(link->device, &tf);
dfd7a3db 1859 tf.command = 0x80;
9977126c 1860 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1861
9dadd45b
TH		 1862 rc = sata_link_hardreset(link, timing, deadline, &online,
1863 ahci_check_ready);
4296971d 1864
4447d351 1865 ahci_start_engine(ap);
1da177e4 1866
9dadd45b 1867 if (online)
4bd00f6a 1868 *class = ahci_dev_classify(ap);
1da177e4 1869
4bd00f6a
TH		 1870 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1871 return rc;
1872}
1873
cc0680a5 1874static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1875 unsigned long deadline)
ad616ffb 1876{
cc0680a5 1877 struct ata_port *ap = link->ap;
9dadd45b 1878 bool online;
ad616ffb
TH		 1879 int rc;
1880
1881 DPRINTK("ENTER\n");
1882
4447d351 1883 ahci_stop_engine(ap);
ad616ffb 1884
cc0680a5 1885 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1886 deadline, &online, NULL);
ad616ffb 1887
4447d351 1888 ahci_start_engine(ap);
ad616ffb
TH		 1889
1890 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1891
1892 /* vt8251 doesn't clear BSY on signature FIS reception,
1893 * request follow-up softreset.
1894 */
9dadd45b 1895 return online ? -EAGAIN : rc;
ad616ffb
TH		 1896}
1897
edc93052
TH		 1898static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1899 unsigned long deadline)
1900{
1901 struct ata_port *ap = link->ap;
1902 struct ahci_port_priv *pp = ap->private_data;
1903 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1904 struct ata_taskfile tf;
9dadd45b 1905 bool online;
edc93052
TH		 1906 int rc;
1907
1908 ahci_stop_engine(ap);
1909
1910 /* clear D2H reception area to properly wait for D2H FIS */
1911 ata_tf_init(link->device, &tf);
1912 tf.command = 0x80;
1913 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1914
1915 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1916 deadline, &online, NULL);
edc93052
TH		 1917
1918 ahci_start_engine(ap);
1919
edc93052
TH		 1920 /* The pseudo configuration device on SIMG4726 attached to
1921 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1922 * hardreset if no device is attached to the first downstream
1923 * port && the pseudo device locks up on SRST w/ PMP==0. To
1924 * work around this, wait for !BSY only briefly. If BSY isn't
1925 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1926 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1927 *
1928 * Wait for two seconds. Devices attached to downstream port
1929 * which can't process the following IDENTIFY after this will
1930 * have to be reset again. For most cases, this should
1931 * suffice while making probing snappish enough.
1932 */
9dadd45b
TH		 1933 if (online) {
1934 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1935 ahci_check_ready);
1936 if (rc)
1937 ahci_kick_engine(ap, 0);
1938 }
9dadd45b 1939 return rc;
edc93052
TH		 1940}
1941
cc0680a5 1942static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1943{
cc0680a5 1944 struct ata_port *ap = link->ap;
4447d351 1945 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1946 u32 new_tmp, tmp;
1947
203c75b8 1948 ata_std_postreset(link, class);
02eaa666
JG		 1949
1950 /* Make sure port's ATAPI bit is set appropriately */
1951 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1952 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1953 new_tmp |= PORT_CMD_ATAPI;
1954 else
1955 new_tmp &= ~PORT_CMD_ATAPI;
1956 if (new_tmp != tmp) {
1957 writel(new_tmp, port_mmio + PORT_CMD);
1958 readl(port_mmio + PORT_CMD); /* flush */
1959 }
1da177e4
LT		 1960}
1961
12fad3f9 1962static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1963{
cedc9a47 1964 struct scatterlist *sg;
ff2aeb1e
TH		 1965 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1966 unsigned int si;
1da177e4
LT		 1967
1968 VPRINTK("ENTER\n");
1969
1970 /*
1971 * Next, the S/G list.
1972 */
ff2aeb1e 1973 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1974 dma_addr_t addr = sg_dma_address(sg);
1975 u32 sg_len = sg_dma_len(sg);
1976
ff2aeb1e
TH		 1977 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1978 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1979 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1980 }
828d09de 1981
ff2aeb1e 1982 return si;
1da177e4
LT		 1983}
1984
1985static void ahci_qc_prep(struct ata_queued_cmd *qc)
1986{
a0ea7328
JG		 1987 struct ata_port *ap = qc->ap;
1988 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1989 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1990 void *cmd_tbl;
1da177e4
LT		 1991 u32 opts;
1992 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1993 unsigned int n_elem;
1da177e4 1994
1da177e4
LT		 1995 /*
1996 * Fill in command table information. First, the header,
1997 * a SATA Register - Host to Device command FIS.
1998 */
12fad3f9
TH		 1999 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2000
7d50b60b 2001 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 2002 if (is_atapi) {
12fad3f9
TH		 2003 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2004 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 2005 }
1da177e4 2006
cc9278ed
TH		 2007 n_elem = 0;
2008 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 2009 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 2010
cc9278ed
TH		 2011 /*
2012 * Fill in command slot information.
2013 */
7d50b60b 2014 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 2015 if (qc->tf.flags & ATA_TFLAG_WRITE)
2016 opts |= AHCI_CMD_WRITE;
2017 if (is_atapi)
4b10e559 2018 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 2019
12fad3f9 2020 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 2021}
2022
78cd52d0 2023static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 2024{
417a1a6d 2025 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 2026 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2027 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2028 struct ata_link *link = NULL;
2029 struct ata_queued_cmd *active_qc;
2030 struct ata_eh_info *active_ehi;
78cd52d0 2031 u32 serror;
1da177e4 2032
7d50b60b 2033 /* determine active link */
1eca4365 2034 ata_for_each_link(link, ap, EDGE)
7d50b60b
TH		 2035 if (ata_link_active(link))
2036 break;
2037 if (!link)
2038 link = &ap->link;
2039
2040 active_qc = ata_qc_from_tag(ap, link->active_tag);
2041 active_ehi = &link->eh_info;
2042
2043 /* record irq stat */
2044 ata_ehi_clear_desc(host_ehi);
2045 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 2046
78cd52d0 2047 /* AHCI needs SError cleared; otherwise, it might lock up */
82ef04fb
TH		 2048 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2049 ahci_scr_write(&ap->link, SCR_ERROR, serror);
7d50b60b 2050 host_ehi->serror |= serror;
78cd52d0 2051
41669553 2052 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 2053 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 2054 irq_stat &= ~PORT_IRQ_IF_ERR;
2055
55a61604 2056 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 2057 /* If qc is active, charge it; otherwise, the active
2058 * link. There's no active qc on NCQ errors. It will
2059 * be determined by EH by reading log page 10h.
2060 */
2061 if (active_qc)
2062 active_qc->err_mask |= AC_ERR_DEV;
2063 else
2064 active_ehi->err_mask |= AC_ERR_DEV;
2065
417a1a6d 2066 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 2067 host_ehi->serror &= ~SERR_INTERNAL;
2068 }
2069
2070 if (irq_stat & PORT_IRQ_UNK_FIS) {
2071 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2072
2073 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2074 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 2075 ata_ehi_push_desc(active_ehi,
2076 "unknown FIS %08x %08x %08x %08x" ,
2077 unk[0], unk[1], unk[2], unk[3]);
2078 }
2079
071f44b1 2080 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 2081 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2082 active_ehi->action |= ATA_EH_RESET;
7d50b60b 2083 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 2084 }
78cd52d0
TH		 2085
2086 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 2087 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 2088 host_ehi->action |= ATA_EH_RESET;
7d50b60b 2089 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 2090 }
2091
78cd52d0 2092 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 2093 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 2094 host_ehi->action |= ATA_EH_RESET;
7d50b60b 2095 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 2096 }
1da177e4 2097
78cd52d0 2098 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 2099 ata_ehi_hotplugged(host_ehi);
2100 ata_ehi_push_desc(host_ehi, "%s",
2101 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 2102 "connection status changed" : "PHY RDY changed");
2103 }
2104
78cd52d0 2105 /* okay, let's hand over to EH */
a72ec4ce 2106
78cd52d0
TH		 2107 if (irq_stat & PORT_IRQ_FREEZE)
2108 ata_port_freeze(ap);
2109 else
2110 ata_port_abort(ap);
1da177e4
LT		 2111}
2112
df69c9c5 2113static void ahci_port_intr(struct ata_port *ap)
1da177e4 2114{
350756f6 2115 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 2116 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 2117 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 2118 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 2119 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 2120 u32 status, qc_active;
459ad688 2121 int rc;
1da177e4
LT		 2122
2123 status = readl(port_mmio + PORT_IRQ_STAT);
2124 writel(status, port_mmio + PORT_IRQ_STAT);
2125
b06ce3e5
TH		 2126 /* ignore BAD_PMP while resetting */
2127 if (unlikely(resetting))
2128 status &= ~PORT_IRQ_BAD_PMP;
2129
31556594
KCA		 2130 /* If we are getting PhyRdy, this is
2131 * just a power state change, we should
2132 * clear out this, plus the PhyRdy/Comm
2133 * Wake bits from Serror
2134 */
2135 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2136 (status & PORT_IRQ_PHYRDY)) {
2137 status &= ~PORT_IRQ_PHYRDY;
82ef04fb 2138 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 2139 }
2140
78cd52d0
TH		 2141 if (unlikely(status & PORT_IRQ_ERROR)) {
2142 ahci_error_intr(ap, status);
2143 return;
1da177e4
LT		 2144 }
2145
2f294968 2146 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2147 /* If SNotification is available, leave notification
2148 * handling to sata_async_notification(). If not,
2149 * emulate it by snooping SDB FIS RX area.
2150 *
2151 * Snooping FIS RX area is probably cheaper than
2152 * poking SNotification but some constrollers which
2153 * implement SNotification, ICH9 for example, don't
2154 * store AN SDB FIS into receive area.
2f294968 2155 */
5f226c6b 2156 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2157 sata_async_notification(ap);
5f226c6b
TH		 2158 else {
2159 /* If the 'N' bit in word 0 of the FIS is set,
2160 * we just received asynchronous notification.
2161 * Tell libata about it.
2162 */
2163 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2164 u32 f0 = le32_to_cpu(f[0]);
2165
2166 if (f0 & (1 << 15))
2167 sata_async_notification(ap);
2168 }
2f294968
KCA		 2169 }
2170
7d50b60b
TH		 2171 /* pp->active_link is valid iff any command is in flight */
2172 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2173 qc_active = readl(port_mmio + PORT_SCR_ACT);
2174 else
2175 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2176
79f97dad 2177 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2178
459ad688
TH		 2179 /* while resetting, invalid completions are expected */
2180 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2181 ehi->err_mask |= AC_ERR_HSM;
cf480626 2182 ehi->action |= ATA_EH_RESET;
12fad3f9 2183 ata_port_freeze(ap);
1da177e4 2184 }
1da177e4
LT		 2185}
2186
7d12e780 2187static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2188{
cca3974e 2189 struct ata_host *host = dev_instance;
1da177e4
LT		 2190 struct ahci_host_priv *hpriv;
2191 unsigned int i, handled = 0;
ea6ba10b 2192 void __iomem *mmio;
d28f87aa 2193 u32 irq_stat, irq_masked;
1da177e4
LT		 2194
2195 VPRINTK("ENTER\n");
2196
cca3974e 2197 hpriv = host->private_data;
0d5ff566 2198 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2199
2200 /* sigh. 0xffffffff is a valid return from h/w */
2201 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2202 if (!irq_stat)
2203 return IRQ_NONE;
2204
d28f87aa
TH		 2205 irq_masked = irq_stat & hpriv->port_map;
2206
2dcb407e 2207 spin_lock(&host->lock);
1da177e4 2208
2dcb407e 2209 for (i = 0; i < host->n_ports; i++) {
1da177e4 2210 struct ata_port *ap;
1da177e4 2211
d28f87aa 2212 if (!(irq_masked & (1 << i)))
67846b30
JG		 2213 continue;
2214
cca3974e 2215 ap = host->ports[i];
67846b30 2216 if (ap) {
df69c9c5 2217 ahci_port_intr(ap);
67846b30
JG		 2218 VPRINTK("port %u\n", i);
2219 } else {
2220 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2221 if (ata_ratelimit())
cca3974e 2222 dev_printk(KERN_WARNING, host->dev,
a9524a76 2223 "interrupt on disabled port %u\n", i);
1da177e4 2224 }
67846b30 2225
1da177e4
LT		 2226 handled = 1;
2227 }
2228
d28f87aa
TH		 2229 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2230 * it should be cleared after all the port events are cleared;
2231 * otherwise, it will raise a spurious interrupt after each
2232 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2233 * information.
2234 *
2235 * Also, use the unmasked value to clear interrupt as spurious
2236 * pending event on a dummy port might cause screaming IRQ.
2237 */
ea0c62f7
TH		 2238 writel(irq_stat, mmio + HOST_IRQ_STAT);
2239
cca3974e 2240 spin_unlock(&host->lock);
1da177e4
LT		 2241
2242 VPRINTK("EXIT\n");
2243
2244 return IRQ_RETVAL(handled);
2245}
2246
9a3d9eb0 2247static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2248{
2249 struct ata_port *ap = qc->ap;
4447d351 2250 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2251 struct ahci_port_priv *pp = ap->private_data;
2252
2253 /* Keep track of the currently active link. It will be used
2254 * in completion path to determine whether NCQ phase is in
2255 * progress.
2256 */
2257 pp->active_link = qc->dev->link;
1da177e4 2258
12fad3f9
TH		 2259 if (qc->tf.protocol == ATA_PROT_NCQ)
2260 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2261 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2262
18f7ba4c
KCA		 2263 ahci_sw_activity(qc->dev->link);
2264
1da177e4
LT		 2265 return 0;
2266}
2267
4c9bf4e7
TH		 2268static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2269{
2270 struct ahci_port_priv *pp = qc->ap->private_data;
2271 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2272
2273 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2274 return true;
2275}
2276
78cd52d0
TH		 2277static void ahci_freeze(struct ata_port *ap)
2278{
4447d351 2279 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2280
2281 /* turn IRQ off */
2282 writel(0, port_mmio + PORT_IRQ_MASK);
2283}
2284
2285static void ahci_thaw(struct ata_port *ap)
2286{
0d5ff566 2287 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2288 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2289 u32 tmp;
a7384925 2290 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2291
2292 /* clear IRQ */
2293 tmp = readl(port_mmio + PORT_IRQ_STAT);
2294 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2295 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2296
1c954a4d
TH		 2297 /* turn IRQ back on */
2298 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2299}
2300
2301static void ahci_error_handler(struct ata_port *ap)
2302{
b51e9e5d 2303 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2304 /* restart engine */
4447d351
TH		 2305 ahci_stop_engine(ap);
2306 ahci_start_engine(ap);
78cd52d0
TH		 2307 }
2308
a1efdaba 2309 sata_pmp_error_handler(ap);
edc93052
TH		 2310}
2311
78cd52d0
TH		 2312static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2313{
2314 struct ata_port *ap = qc->ap;
2315
d2e75dff
TH		 2316 /* make DMA engine forget about the failed command */
2317 if (qc->flags & ATA_QCFLAG_FAILED)
2318 ahci_kick_engine(ap, 1);
78cd52d0
TH		 2319}
2320
7d50b60b
TH		 2321static void ahci_pmp_attach(struct ata_port *ap)
2322{
2323 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2324 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2325 u32 cmd;
2326
2327 cmd = readl(port_mmio + PORT_CMD);
2328 cmd |= PORT_CMD_PMP;
2329 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2330
2331 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2332 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2333}
2334
2335static void ahci_pmp_detach(struct ata_port *ap)
2336{
2337 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2338 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2339 u32 cmd;
2340
2341 cmd = readl(port_mmio + PORT_CMD);
2342 cmd &= ~PORT_CMD_PMP;
2343 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2344
2345 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2346 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2347}
2348
028a2596
AD		 2349static int ahci_port_resume(struct ata_port *ap)
2350{
2351 ahci_power_up(ap);
2352 ahci_start_port(ap);
2353
071f44b1 2354 if (sata_pmp_attached(ap))
7d50b60b
TH		 2355 ahci_pmp_attach(ap);
2356 else
2357 ahci_pmp_detach(ap);
2358
028a2596
AD		 2359 return 0;
2360}
2361
438ac6d5 2362#ifdef CONFIG_PM
c1332875
TH		 2363static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2364{
c1332875
TH		 2365 const char *emsg = NULL;
2366 int rc;
2367
4447d351 2368 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2369 if (rc == 0)
4447d351 2370 ahci_power_down(ap);
8e16f941 2371 else {
c1332875 2372 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2373 ahci_start_port(ap);
c1332875
TH		 2374 }
2375
2376 return rc;
2377}
2378
c1332875
TH		 2379static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2380{
cca3974e 2381 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 2382 struct ahci_host_priv *hpriv = host->private_data;
0d5ff566 2383 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2384 u32 ctl;
2385
9b10ae86
TH		 2386 if (mesg.event & PM_EVENT_SUSPEND &&
2387 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2388 dev_printk(KERN_ERR, &pdev->dev,
2389 "BIOS update required for suspend/resume\n");
2390 return -EIO;
2391 }
2392
3a2d5b70 2393 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2394 /* AHCI spec rev1.1 section 8.3.3:
2395 * Software must disable interrupts prior to requesting a
2396 * transition of the HBA to D3 state.
2397 */
2398 ctl = readl(mmio + HOST_CTL);
2399 ctl &= ~HOST_IRQ_EN;
2400 writel(ctl, mmio + HOST_CTL);
2401 readl(mmio + HOST_CTL); /* flush */
2402 }
2403
2404 return ata_pci_device_suspend(pdev, mesg);
2405}
2406
2407static int ahci_pci_device_resume(struct pci_dev *pdev)
2408{
cca3974e 2409 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2410 int rc;
2411
553c4aa6
TH		 2412 rc = ata_pci_device_do_resume(pdev);
2413 if (rc)
2414 return rc;
c1332875
TH		 2415
2416 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2417 rc = ahci_reset_controller(host);
c1332875
TH		 2418 if (rc)
2419 return rc;
2420
4447d351 2421 ahci_init_controller(host);
c1332875
TH		 2422 }
2423
cca3974e 2424 ata_host_resume(host);
c1332875
TH		 2425
2426 return 0;
2427}
438ac6d5 2428#endif
c1332875 2429
254950cd
TH		 2430static int ahci_port_start(struct ata_port *ap)
2431{
cca3974e 2432 struct device *dev = ap->host->dev;
254950cd 2433 struct ahci_port_priv *pp;
254950cd
TH		 2434 void *mem;
2435 dma_addr_t mem_dma;
254950cd 2436
24dc5f33 2437 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2438 if (!pp)
2439 return -ENOMEM;
254950cd 2440
24dc5f33
TH		 2441 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2442 GFP_KERNEL);
2443 if (!mem)
254950cd 2444 return -ENOMEM;
254950cd
TH		 2445 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2446
2447 /*
2448 * First item in chunk of DMA memory: 32-slot command table,
2449 * 32 bytes each in size
2450 */
2451 pp->cmd_slot = mem;
2452 pp->cmd_slot_dma = mem_dma;
2453
2454 mem += AHCI_CMD_SLOT_SZ;
2455 mem_dma += AHCI_CMD_SLOT_SZ;
2456
2457 /*
2458 * Second item: Received-FIS area
2459 */
2460 pp->rx_fis = mem;
2461 pp->rx_fis_dma = mem_dma;
2462
2463 mem += AHCI_RX_FIS_SZ;
2464 mem_dma += AHCI_RX_FIS_SZ;
2465
2466 /*
2467 * Third item: data area for storing a single command
2468 * and its scatter-gather table
2469 */
2470 pp->cmd_tbl = mem;
2471 pp->cmd_tbl_dma = mem_dma;
2472
a7384925 2473 /*
2dcb407e
JG		 2474 * Save off initial list of interrupts to be enabled.
2475 * This could be changed later
2476 */
a7384925
KCA		 2477 pp->intr_mask = DEF_PORT_IRQ;
2478
254950cd
TH		 2479 ap->private_data = pp;
2480
df69c9c5
JG		 2481 /* engage engines, captain */
2482 return ahci_port_resume(ap);
254950cd
TH		 2483}
2484
2485static void ahci_port_stop(struct ata_port *ap)
2486{
0be0aa98
TH		 2487 const char *emsg = NULL;
2488 int rc;
254950cd 2489
0be0aa98 2490 /* de-initialize port */
4447d351 2491 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2492 if (rc)
2493 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2494}
2495
4447d351 2496static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2497{
1da177e4 2498 int rc;
1da177e4 2499
1da177e4 2500 if (using_dac &&
6a35528a
YH		 2501 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2502 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 2503 if (rc) {
284901a9 2504 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2505 if (rc) {
a9524a76
JG		 2506 dev_printk(KERN_ERR, &pdev->dev,
2507 "64-bit DMA enable failed\n");
1da177e4
LT		 2508 return rc;
2509 }
2510 }
1da177e4 2511 } else {
284901a9 2512 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2513 if (rc) {
a9524a76
JG		 2514 dev_printk(KERN_ERR, &pdev->dev,
2515 "32-bit DMA enable failed\n");
1da177e4
LT		 2516 return rc;
2517 }
284901a9 2518 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2519 if (rc) {
a9524a76
JG		 2520 dev_printk(KERN_ERR, &pdev->dev,
2521 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2522 return rc;
2523 }
2524 }
1da177e4
LT		 2525 return 0;
2526}
2527
4447d351 2528static void ahci_print_info(struct ata_host *host)
1da177e4 2529{
4447d351
TH		 2530 struct ahci_host_priv *hpriv = host->private_data;
2531 struct pci_dev *pdev = to_pci_dev(host->dev);
2532 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2533 u32 vers, cap, impl, speed;
2534 const char *speed_s;
2535 u16 cc;
2536 const char *scc_s;
2537
2538 vers = readl(mmio + HOST_VERSION);
2539 cap = hpriv->cap;
2540 impl = hpriv->port_map;
2541
2542 speed = (cap >> 20) & 0xf;
2543 if (speed == 1)
2544 speed_s = "1.5";
2545 else if (speed == 2)
2546 speed_s = "3";
8522ee25
SH		 2547 else if (speed == 3)
2548 speed_s = "6";
1da177e4
LT		 2549 else
2550 speed_s = "?";
2551
2552 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2553 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2554 scc_s = "IDE";
c9f89475 2555 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2556 scc_s = "SATA";
c9f89475 2557 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2558 scc_s = "RAID";
2559 else
2560 scc_s = "unknown";
2561
a9524a76
JG		 2562 dev_printk(KERN_INFO, &pdev->dev,
2563 "AHCI %02x%02x.%02x%02x "
1da177e4 2564 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2565 ,
1da177e4 2566
2dcb407e
JG		 2567 (vers >> 24) & 0xff,
2568 (vers >> 16) & 0xff,
2569 (vers >> 8) & 0xff,
2570 vers & 0xff,
1da177e4
LT		 2571
2572 ((cap >> 8) & 0x1f) + 1,
2573 (cap & 0x1f) + 1,
2574 speed_s,
2575 impl,
2576 scc_s);
2577
a9524a76
JG		 2578 dev_printk(KERN_INFO, &pdev->dev,
2579 "flags: "
203ef6c4 2580 "%s%s%s%s%s%s%s"
18f7ba4c
KCA		 2581 "%s%s%s%s%s%s%s"
2582 "%s\n"
2dcb407e 2583 ,
1da177e4
LT		 2584
2585 cap & (1 << 31) ? "64bit " : "",
2586 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2587 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2588 cap & (1 << 28) ? "ilck " : "",
2589 cap & (1 << 27) ? "stag " : "",
2590 cap & (1 << 26) ? "pm " : "",
2591 cap & (1 << 25) ? "led " : "",
2592
2593 cap & (1 << 24) ? "clo " : "",
2594 cap & (1 << 19) ? "nz " : "",
2595 cap & (1 << 18) ? "only " : "",
2596 cap & (1 << 17) ? "pmp " : "",
2597 cap & (1 << 15) ? "pio " : "",
2598 cap & (1 << 14) ? "slum " : "",
18f7ba4c
KCA		 2599 cap & (1 << 13) ? "part " : "",
2600 cap & (1 << 6) ? "ems ": ""
1da177e4
LT		 2601 );
2602}
2603
edc93052
TH		 2604/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2605 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2606 * support PMP and the 4726 either directly exports the device
2607 * attached to the first downstream port or acts as a hardware storage
2608 * controller and emulate a single ATA device (can be RAID 0/1 or some
2609 * other configuration).
2610 *
2611 * When there's no device attached to the first downstream port of the
2612 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2613 * configure the 4726. However, ATA emulation of the device is very
2614 * lame. It doesn't send signature D2H Reg FIS after the initial
2615 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2616 *
2617 * The following function works around the problem by always using
2618 * hardreset on the port and not depending on receiving signature FIS
2619 * afterward. If signature FIS isn't received soon, ATA class is
2620 * assumed without follow-up softreset.
2621 */
2622static void ahci_p5wdh_workaround(struct ata_host *host)
2623{
2624 static struct dmi_system_id sysids[] = {
2625 {
2626 .ident = "P5W DH Deluxe",
2627 .matches = {
2628 DMI_MATCH(DMI_SYS_VENDOR,
2629 "ASUSTEK COMPUTER INC"),
2630 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2631 },
2632 },
2633 { }
2634 };
2635 struct pci_dev *pdev = to_pci_dev(host->dev);
2636
2637 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2638 dmi_check_system(sysids)) {
2639 struct ata_port *ap = host->ports[1];
2640
2641 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2642 "Deluxe on-board SIMG4726 workaround\n");
2643
2644 ap->ops = &ahci_p5wdh_ops;
2645 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2646 }
2647}
2648
58a09b38
SH		 2649/*
2650 * SB600 ahci controller on ASUS M2A-VM can't do 64bit DMA with older
2651 * BIOS. The oldest version known to be broken is 0901 and working is
2652 * 1501 which was released on 2007-10-26. Force 32bit DMA on anything
2653 * older than 1501. Please read bko#9412 for more info.
2654 */
2655static bool ahci_asus_m2a_vm_32bit_only(struct pci_dev *pdev)
2656{
2657 static const struct dmi_system_id sysids[] = {
2658 {
2659 .ident = "ASUS M2A-VM",
2660 .matches = {
2661 DMI_MATCH(DMI_BOARD_VENDOR,
2662 "ASUSTeK Computer INC."),
2663 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2664 },
2665 },
2666 { }
2667 };
2668 const char *cutoff_mmdd = "10/26";
2669 const char *date;
2670 int year;
2671
2672 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2673 !dmi_check_system(sysids))
2674 return false;
2675
2676 /*
2677 * Argh.... both version and date are free form strings.
2678 * Let's hope they're using the same date format across
2679 * different versions.
2680 */
2681 date = dmi_get_system_info(DMI_BIOS_DATE);
3e5cd1f2 2682 dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL);
58a09b38
SH		 2683 if (date && strlen(date) >= 10 && date[2] == '/' && date[5] == '/' &&
2684 (year > 2007 ||
2685 (year == 2007 && strncmp(date, cutoff_mmdd, 5) >= 0)))
2686 return false;
2687
2688 dev_printk(KERN_WARNING, &pdev->dev, "ASUS M2A-VM: BIOS too old, "
2689 "forcing 32bit DMA, update BIOS\n");
2690
2691 return true;
2692}
2693
1fd68434
RW		 2694static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2695{
2696 static const struct dmi_system_id broken_systems[] = {
2697 {
2698 .ident = "HP Compaq nx6310",
2699 .matches = {
2700 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2701 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2702 },
2703 /* PCI slot number of the controller */
2704 .driver_data = (void *)0x1FUL,
2705 },
d2f9c061
MR		 2706 {
2707 .ident = "HP Compaq 6720s",
2708 .matches = {
2709 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2710 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2711 },
2712 /* PCI slot number of the controller */
2713 .driver_data = (void *)0x1FUL,
2714 },
1fd68434
RW		 2715
2716 { } /* terminate list */
2717 };
2718 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2719
2720 if (dmi) {
2721 unsigned long slot = (unsigned long)dmi->driver_data;
2722 /* apply the quirk only to on-board controllers */
2723 return slot == PCI_SLOT(pdev->devfn);
2724 }
2725
2726 return false;
2727}
2728
9b10ae86
TH		 2729static bool ahci_broken_suspend(struct pci_dev *pdev)
2730{
2731 static const struct dmi_system_id sysids[] = {
2732 /*
2733 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2734 * to the harddisk doesn't become online after
2735 * resuming from STR. Warn and fail suspend.
2736 */
2737 {
2738 .ident = "dv4",
2739 .matches = {
2740 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2741 DMI_MATCH(DMI_PRODUCT_NAME,
2742 "HP Pavilion dv4 Notebook PC"),
2743 },
2744 .driver_data = "F.30", /* cutoff BIOS version */
2745 },
2746 {
2747 .ident = "dv5",
2748 .matches = {
2749 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2750 DMI_MATCH(DMI_PRODUCT_NAME,
2751 "HP Pavilion dv5 Notebook PC"),
2752 },
2753 .driver_data = "F.16", /* cutoff BIOS version */
2754 },
2755 {
2756 .ident = "dv6",
2757 .matches = {
2758 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2759 DMI_MATCH(DMI_PRODUCT_NAME,
2760 "HP Pavilion dv6 Notebook PC"),
2761 },
2762 .driver_data = "F.21", /* cutoff BIOS version */
2763 },
2764 {
2765 .ident = "HDX18",
2766 .matches = {
2767 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2768 DMI_MATCH(DMI_PRODUCT_NAME,
2769 "HP HDX18 Notebook PC"),
2770 },
2771 .driver_data = "F.23", /* cutoff BIOS version */
2772 },
2773 { } /* terminate list */
2774 };
2775 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2776 const char *ver;
2777
2778 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2779 return false;
2780
2781 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2782
2783 return !ver || strcmp(ver, dmi->driver_data) < 0;
2784}
2785
5594639a
TH		 2786static bool ahci_broken_online(struct pci_dev *pdev)
2787{
2788#define ENCODE_BUSDEVFN(bus, slot, func) \
2789 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2790 static const struct dmi_system_id sysids[] = {
2791 /*
2792 * There are several gigabyte boards which use
2793 * SIMG5723s configured as hardware RAID. Certain
2794 * 5723 firmware revisions shipped there keep the link
2795 * online but fail to answer properly to SRST or
2796 * IDENTIFY when no device is attached downstream
2797 * causing libata to retry quite a few times leading
2798 * to excessive detection delay.
2799 *
2800 * As these firmwares respond to the second reset try
2801 * with invalid device signature, considering unknown
2802 * sig as offline works around the problem acceptably.
2803 */
2804 {
2805 .ident = "EP45-DQ6",
2806 .matches = {
2807 DMI_MATCH(DMI_BOARD_VENDOR,
2808 "Gigabyte Technology Co., Ltd."),
2809 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2810 },
2811 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2812 },
2813 {
2814 .ident = "EP45-DS5",
2815 .matches = {
2816 DMI_MATCH(DMI_BOARD_VENDOR,
2817 "Gigabyte Technology Co., Ltd."),
2818 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2819 },
2820 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2821 },
2822 { } /* terminate list */
2823 };
2824#undef ENCODE_BUSDEVFN
2825 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2826 unsigned int val;
2827
2828 if (!dmi)
2829 return false;
2830
2831 val = (unsigned long)dmi->driver_data;
2832
2833 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2834}
2835
24dc5f33 2836static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2837{
2838 static int printed_version;
e297d99e
TH		 2839 unsigned int board_id = ent->driver_data;
2840 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 2841 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2842 struct device *dev = &pdev->dev;
1da177e4 2843 struct ahci_host_priv *hpriv;
4447d351 2844 struct ata_host *host;
837f5f8f 2845 int n_ports, i, rc;
1da177e4
LT		 2846
2847 VPRINTK("ENTER\n");
2848
12fad3f9
TH		 2849 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2850
1da177e4 2851 if (!printed_version++)
a9524a76 2852 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2853
5b66c829
AC		 2854 /* The AHCI driver can only drive the SATA ports, the PATA driver
2855 can drive them all so if both drivers are selected make sure
2856 AHCI stays out of the way */
2857 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2858 return -ENODEV;
2859
4447d351 2860 /* acquire resources */
24dc5f33 2861 rc = pcim_enable_device(pdev);
1da177e4
LT		 2862 if (rc)
2863 return rc;
2864
dea55137
TH		 2865 /* AHCI controllers often implement SFF compatible interface.
2866 * Grab all PCI BARs just in case.
2867 */
2868 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2869 if (rc == -EBUSY)
24dc5f33 2870 pcim_pin_device(pdev);
0d5ff566 2871 if (rc)
24dc5f33 2872 return rc;
1da177e4 2873
c4f7792c
TH		 2874 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2875 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2876 u8 map;
2877
2878 /* ICH6s share the same PCI ID for both piix and ahci
2879 * modes. Enabling ahci mode while MAP indicates
2880 * combined mode is a bad idea. Yield to ata_piix.
2881 */
2882 pci_read_config_byte(pdev, ICH_MAP, &map);
2883 if (map & 0x3) {
2884 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2885 "combined mode, can't enable AHCI mode\n");
2886 return -ENODEV;
2887 }
2888 }
2889
24dc5f33
TH		 2890 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2891 if (!hpriv)
2892 return -ENOMEM;
417a1a6d
TH		 2893 hpriv->flags |= (unsigned long)pi.private_data;
2894
e297d99e
TH		 2895 /* MCP65 revision A1 and A2 can't do MSI */
2896 if (board_id == board_ahci_mcp65 &&
2897 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2898 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2899
e427fe04
SH		 2900 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2901 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2902 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2903
58a09b38
SH		 2904 /* apply ASUS M2A_VM quirk */
2905 if (ahci_asus_m2a_vm_32bit_only(pdev))
2906 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2907
a5bfc471
TH		 2908 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2909 pci_enable_msi(pdev);
1da177e4 2910
4447d351 2911 /* save initial config */
417a1a6d 2912 ahci_save_initial_config(pdev, hpriv);
1da177e4 2913
4447d351 2914 /* prepare host */
274c1fde 2915 if (hpriv->cap & HOST_CAP_NCQ)
388539f3 2916 pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
1da177e4 2917
7d50b60b
TH		 2918 if (hpriv->cap & HOST_CAP_PMP)
2919 pi.flags |= ATA_FLAG_PMP;
2920
18f7ba4c
KCA		 2921 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2922 u8 messages;
2923 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2924 u32 em_loc = readl(mmio + HOST_EM_LOC);
2925 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2926
87943acf 2927 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
18f7ba4c
KCA		 2928
2929 /* we only support LED message type right now */
2930 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2931 /* store em_loc */
2932 hpriv->em_loc = ((em_loc >> 16) * 4);
2933 pi.flags |= ATA_FLAG_EM;
2934 if (!(em_ctl & EM_CTL_ALHD))
2935 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2936 }
2937 }
2938
1fd68434
RW		 2939 if (ahci_broken_system_poweroff(pdev)) {
2940 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2941 dev_info(&pdev->dev,
2942 "quirky BIOS, skipping spindown on poweroff\n");
2943 }
2944
9b10ae86
TH		 2945 if (ahci_broken_suspend(pdev)) {
2946 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2947 dev_printk(KERN_WARNING, &pdev->dev,
2948 "BIOS update required for suspend/resume\n");
2949 }
2950
5594639a
TH		 2951 if (ahci_broken_online(pdev)) {
2952 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2953 dev_info(&pdev->dev,
2954 "online status unreliable, applying workaround\n");
2955 }
2956
837f5f8f
TH		 2957 /* CAP.NP sometimes indicate the index of the last enabled
2958 * port, at other times, that of the last possible port, so
2959 * determining the maximum port number requires looking at
2960 * both CAP.NP and port_map.
2961 */
2962 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2963
2964 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2965 if (!host)
2966 return -ENOMEM;
2967 host->iomap = pcim_iomap_table(pdev);
2968 host->private_data = hpriv;
2969
f3d7f23f 2970 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 2971 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 2972 else
2973 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 2974
18f7ba4c
KCA		 2975 if (pi.flags & ATA_FLAG_EM)
2976 ahci_reset_em(host);
2977
4447d351 2978 for (i = 0; i < host->n_ports; i++) {
dab632e8 2979 struct ata_port *ap = host->ports[i];
4447d351 2980
cbcdd875
TH		 2981 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2982 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2983 0x100 + ap->port_no * 0x80, "port");
2984
31556594
KCA		 2985 /* set initial link pm policy */
2986 ap->pm_policy = NOT_AVAILABLE;
2987
18f7ba4c
KCA		 2988 /* set enclosure management message type */
2989 if (ap->flags & ATA_FLAG_EM)
2990 ap->em_message_type = ahci_em_messages;
2991
2992
dab632e8 2993 /* disabled/not-implemented port */
350756f6 2994 if (!(hpriv->port_map & (1 << i)))
dab632e8 2995 ap->ops = &ata_dummy_port_ops;
4447d351 2996 }
d447df14 2997
edc93052
TH		 2998 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2999 ahci_p5wdh_workaround(host);
3000
4447d351
TH		 3001 /* initialize adapter */
3002 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 3003 if (rc)
24dc5f33 3004 return rc;
1da177e4 3005
4447d351
TH		 3006 rc = ahci_reset_controller(host);
3007 if (rc)
3008 return rc;
1da177e4 3009
4447d351
TH		 3010 ahci_init_controller(host);
3011 ahci_print_info(host);
1da177e4 3012
4447d351
TH		 3013 pci_set_master(pdev);
3014 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3015 &ahci_sht);
907f4678 3016}
1da177e4
LT		 3017
3018static int __init ahci_init(void)
3019{
b7887196 3020 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 3021}
3022
1da177e4
LT		 3023static void __exit ahci_exit(void)
3024{
3025 pci_unregister_driver(&ahci_pci_driver);
3026}
3027
3028
3029MODULE_AUTHOR("Jeff Garzik");
3030MODULE_DESCRIPTION("AHCI SATA low-level driver");
3031MODULE_LICENSE("GPL");
3032MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 3033MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 3034
3035module_init(ahci_init);
3036module_exit(ahci_exit);
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