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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
87507cfd | 42 | #include <linux/dma-mapping.h> |
a9524a76 | 43 | #include <linux/device.h> |
edc93052 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 47 | #include <linux/libata.h> |
1da177e4 LT |
48 | |
49 | #define DRV_NAME "ahci" | |
7d50b60b | 50 | #define DRV_VERSION "3.0" |
1da177e4 | 51 | |
a22e6444 TH |
52 | static int ahci_skip_host_reset; |
53 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); | |
54 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); | |
55 | ||
31556594 KCA |
56 | static int ahci_enable_alpm(struct ata_port *ap, |
57 | enum link_pm policy); | |
58 | static void ahci_disable_alpm(struct ata_port *ap); | |
1da177e4 LT |
59 | |
60 | enum { | |
61 | AHCI_PCI_BAR = 5, | |
648a88be | 62 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
63 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
64 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
12fad3f9 | 65 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 66 | AHCI_CMD_SZ = 32, |
12fad3f9 | 67 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 68 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 69 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
70 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
71 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
72 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
73 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
74 | AHCI_RX_FIS_SZ, |
75 | AHCI_IRQ_ON_SG = (1 << 31), | |
76 | AHCI_CMD_ATAPI = (1 << 5), | |
77 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 78 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
79 | AHCI_CMD_RESET = (1 << 8), |
80 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
81 | |
82 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 83 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 84 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
85 | |
86 | board_ahci = 0, | |
7a234aff TH |
87 | board_ahci_vt8251 = 1, |
88 | board_ahci_ign_iferr = 2, | |
89 | board_ahci_sb600 = 3, | |
90 | board_ahci_mv = 4, | |
e39fc8c9 | 91 | board_ahci_sb700 = 5, |
1da177e4 LT |
92 | |
93 | /* global controller registers */ | |
94 | HOST_CAP = 0x00, /* host capabilities */ | |
95 | HOST_CTL = 0x04, /* global host control */ | |
96 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
97 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
98 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
99 | ||
100 | /* HOST_CTL bits */ | |
101 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
102 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
103 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
104 | ||
105 | /* HOST_CAP bits */ | |
0be0aa98 | 106 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
7d50b60b | 107 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
22b49985 | 108 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
31556594 | 109 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
0be0aa98 | 110 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
203ef6c4 | 111 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
979db803 | 112 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 113 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
114 | |
115 | /* registers for each SATA port */ | |
116 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
117 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
118 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
119 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
120 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
121 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
122 | PORT_CMD = 0x18, /* port command */ | |
123 | PORT_TFDATA = 0x20, /* taskfile data */ | |
124 | PORT_SIG = 0x24, /* device TF signature */ | |
125 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
1da177e4 LT |
126 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
127 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
128 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
129 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
203ef6c4 | 130 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
1da177e4 LT |
131 | |
132 | /* PORT_IRQ_{STAT,MASK} bits */ | |
133 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
134 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
135 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
136 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
137 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
138 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
139 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
140 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
141 | ||
142 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
143 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
144 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
145 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
146 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
147 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
148 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
149 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
150 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
151 | ||
78cd52d0 TH |
152 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
153 | PORT_IRQ_IF_ERR | | |
154 | PORT_IRQ_CONNECT | | |
4296971d | 155 | PORT_IRQ_PHYRDY | |
7d50b60b TH |
156 | PORT_IRQ_UNK_FIS | |
157 | PORT_IRQ_BAD_PMP, | |
78cd52d0 TH |
158 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
159 | PORT_IRQ_TF_ERR | | |
160 | PORT_IRQ_HBUS_DATA_ERR, | |
161 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
162 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
163 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
164 | |
165 | /* PORT_CMD bits */ | |
31556594 KCA |
166 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
167 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ | |
02eaa666 | 168 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
7d50b60b | 169 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
1da177e4 LT |
170 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
171 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
172 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 173 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
174 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
175 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
176 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
177 | ||
0be0aa98 | 178 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
179 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
180 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
181 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 | 182 | |
417a1a6d TH |
183 | /* hpriv->flags bits */ |
184 | AHCI_HFLAG_NO_NCQ = (1 << 0), | |
185 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ | |
186 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ | |
187 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ | |
188 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ | |
189 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ | |
6949b914 | 190 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
31556594 | 191 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
a878539e | 192 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
417a1a6d | 193 | |
bf2af2a2 | 194 | /* ap->flags bits */ |
1188c0d8 TH |
195 | |
196 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
197 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
31556594 KCA |
198 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
199 | ATA_FLAG_IPM, | |
c4f7792c TH |
200 | |
201 | ICH_MAP = 0x90, /* ICH MAP register */ | |
1da177e4 LT |
202 | }; |
203 | ||
204 | struct ahci_cmd_hdr { | |
4ca4e439 AV |
205 | __le32 opts; |
206 | __le32 status; | |
207 | __le32 tbl_addr; | |
208 | __le32 tbl_addr_hi; | |
209 | __le32 reserved[4]; | |
1da177e4 LT |
210 | }; |
211 | ||
212 | struct ahci_sg { | |
4ca4e439 AV |
213 | __le32 addr; |
214 | __le32 addr_hi; | |
215 | __le32 reserved; | |
216 | __le32 flags_size; | |
1da177e4 LT |
217 | }; |
218 | ||
219 | struct ahci_host_priv { | |
417a1a6d | 220 | unsigned int flags; /* AHCI_HFLAG_* */ |
d447df14 TH |
221 | u32 cap; /* cap to use */ |
222 | u32 port_map; /* port map to use */ | |
223 | u32 saved_cap; /* saved initial cap */ | |
224 | u32 saved_port_map; /* saved initial port_map */ | |
1da177e4 LT |
225 | }; |
226 | ||
227 | struct ahci_port_priv { | |
7d50b60b | 228 | struct ata_link *active_link; |
1da177e4 LT |
229 | struct ahci_cmd_hdr *cmd_slot; |
230 | dma_addr_t cmd_slot_dma; | |
231 | void *cmd_tbl; | |
232 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
233 | void *rx_fis; |
234 | dma_addr_t rx_fis_dma; | |
0291f95f | 235 | /* for NCQ spurious interrupt analysis */ |
0291f95f TH |
236 | unsigned int ncq_saw_d2h:1; |
237 | unsigned int ncq_saw_dmas:1; | |
afb2d552 | 238 | unsigned int ncq_saw_sdb:1; |
a7384925 | 239 | u32 intr_mask; /* interrupts to enable */ |
1da177e4 LT |
240 | }; |
241 | ||
da3dbb17 TH |
242 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
243 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
2dcb407e | 244 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
9a3d9eb0 | 245 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
4c9bf4e7 | 246 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
1da177e4 LT |
247 | static int ahci_port_start(struct ata_port *ap); |
248 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 | 249 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
78cd52d0 TH |
250 | static void ahci_freeze(struct ata_port *ap); |
251 | static void ahci_thaw(struct ata_port *ap); | |
7d50b60b TH |
252 | static void ahci_pmp_attach(struct ata_port *ap); |
253 | static void ahci_pmp_detach(struct ata_port *ap); | |
a1efdaba TH |
254 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
255 | unsigned long deadline); | |
256 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, | |
257 | unsigned long deadline); | |
258 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, | |
259 | unsigned long deadline); | |
260 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, | |
261 | unsigned long deadline); | |
262 | static void ahci_postreset(struct ata_link *link, unsigned int *class); | |
263 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, | |
264 | unsigned long deadline); | |
78cd52d0 TH |
265 | static void ahci_error_handler(struct ata_port *ap); |
266 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
df69c9c5 | 267 | static int ahci_port_resume(struct ata_port *ap); |
a878539e | 268 | static void ahci_dev_config(struct ata_device *dev); |
dab632e8 JG |
269 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
270 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, | |
271 | u32 opts); | |
438ac6d5 | 272 | #ifdef CONFIG_PM |
c1332875 | 273 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
c1332875 TH |
274 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
275 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 276 | #endif |
1da177e4 | 277 | |
31556594 KCA |
278 | static struct class_device_attribute *ahci_shost_attrs[] = { |
279 | &class_device_attr_link_power_management_policy, | |
280 | NULL | |
281 | }; | |
282 | ||
193515d5 | 283 | static struct scsi_host_template ahci_sht = { |
68d1d07b | 284 | ATA_NCQ_SHT(DRV_NAME), |
12fad3f9 | 285 | .can_queue = AHCI_MAX_CMDS - 1, |
1da177e4 | 286 | .sg_tablesize = AHCI_MAX_SG, |
1da177e4 | 287 | .dma_boundary = AHCI_DMA_BOUNDARY, |
31556594 | 288 | .shost_attrs = ahci_shost_attrs, |
1da177e4 LT |
289 | }; |
290 | ||
029cfd6b TH |
291 | static struct ata_port_operations ahci_ops = { |
292 | .inherits = &sata_pmp_port_ops, | |
293 | ||
7d50b60b | 294 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
1da177e4 LT |
295 | .qc_prep = ahci_qc_prep, |
296 | .qc_issue = ahci_qc_issue, | |
4c9bf4e7 | 297 | .qc_fill_rtf = ahci_qc_fill_rtf, |
1da177e4 | 298 | |
78cd52d0 TH |
299 | .freeze = ahci_freeze, |
300 | .thaw = ahci_thaw, | |
a1efdaba TH |
301 | .softreset = ahci_softreset, |
302 | .hardreset = ahci_hardreset, | |
303 | .postreset = ahci_postreset, | |
304 | .pmp_softreset = ahci_pmp_softreset, | |
78cd52d0 TH |
305 | .error_handler = ahci_error_handler, |
306 | .post_internal_cmd = ahci_post_internal_cmd, | |
6bd99b4e TH |
307 | .dev_config = ahci_dev_config, |
308 | ||
ad616ffb TH |
309 | .scr_read = ahci_scr_read, |
310 | .scr_write = ahci_scr_write, | |
7d50b60b TH |
311 | .pmp_attach = ahci_pmp_attach, |
312 | .pmp_detach = ahci_pmp_detach, | |
7d50b60b | 313 | |
029cfd6b TH |
314 | .enable_pm = ahci_enable_alpm, |
315 | .disable_pm = ahci_disable_alpm, | |
438ac6d5 | 316 | #ifdef CONFIG_PM |
ad616ffb TH |
317 | .port_suspend = ahci_port_suspend, |
318 | .port_resume = ahci_port_resume, | |
438ac6d5 | 319 | #endif |
ad616ffb TH |
320 | .port_start = ahci_port_start, |
321 | .port_stop = ahci_port_stop, | |
322 | }; | |
323 | ||
029cfd6b TH |
324 | static struct ata_port_operations ahci_vt8251_ops = { |
325 | .inherits = &ahci_ops, | |
a1efdaba | 326 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 327 | }; |
edc93052 | 328 | |
029cfd6b TH |
329 | static struct ata_port_operations ahci_p5wdh_ops = { |
330 | .inherits = &ahci_ops, | |
a1efdaba | 331 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
332 | }; |
333 | ||
417a1a6d TH |
334 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
335 | ||
98ac62de | 336 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
337 | /* board_ahci */ |
338 | { | |
1188c0d8 | 339 | .flags = AHCI_FLAG_COMMON, |
7da79312 | 340 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 341 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
342 | .port_ops = &ahci_ops, |
343 | }, | |
bf2af2a2 BJ |
344 | /* board_ahci_vt8251 */ |
345 | { | |
6949b914 | 346 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
417a1a6d | 347 | .flags = AHCI_FLAG_COMMON, |
bf2af2a2 | 348 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 349 | .udma_mask = ATA_UDMA6, |
ad616ffb | 350 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 351 | }, |
41669553 TH |
352 | /* board_ahci_ign_iferr */ |
353 | { | |
417a1a6d TH |
354 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
355 | .flags = AHCI_FLAG_COMMON, | |
41669553 | 356 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 357 | .udma_mask = ATA_UDMA6, |
41669553 TH |
358 | .port_ops = &ahci_ops, |
359 | }, | |
55a61604 CH |
360 | /* board_ahci_sb600 */ |
361 | { | |
417a1a6d | 362 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
4cde32fc | 363 | AHCI_HFLAG_32BIT_ONLY | |
a878539e | 364 | AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP), |
417a1a6d | 365 | .flags = AHCI_FLAG_COMMON, |
55a61604 | 366 | .pio_mask = 0x1f, /* pio0-4 */ |
469248ab | 367 | .udma_mask = ATA_UDMA6, |
55a61604 CH |
368 | .port_ops = &ahci_ops, |
369 | }, | |
cd70c266 JG |
370 | /* board_ahci_mv */ |
371 | { | |
417a1a6d TH |
372 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
373 | AHCI_HFLAG_MV_PATA), | |
cd70c266 | 374 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
417a1a6d | 375 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
cd70c266 JG |
376 | .pio_mask = 0x1f, /* pio0-4 */ |
377 | .udma_mask = ATA_UDMA6, | |
378 | .port_ops = &ahci_ops, | |
379 | }, | |
e39fc8c9 SH |
380 | /* board_ahci_sb700 */ |
381 | { | |
382 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | | |
383 | AHCI_HFLAG_NO_PMP), | |
384 | .flags = AHCI_FLAG_COMMON, | |
e39fc8c9 SH |
385 | .pio_mask = 0x1f, /* pio0-4 */ |
386 | .udma_mask = ATA_UDMA6, | |
387 | .port_ops = &ahci_ops, | |
388 | }, | |
1da177e4 LT |
389 | }; |
390 | ||
3b7d697d | 391 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 392 | /* Intel */ |
54bb3a94 JG |
393 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
394 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
395 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
396 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
397 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 398 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
399 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
400 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
401 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
402 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff TH |
403 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
404 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ | |
405 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ | |
406 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
407 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
408 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
409 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
410 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
411 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
412 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
413 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
414 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
415 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
416 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
417 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
418 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
419 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
420 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
421 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 JG |
422 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
423 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ | |
fe7fa31a | 424 | |
e34bb370 TH |
425 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
426 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
427 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
fe7fa31a JG |
428 | |
429 | /* ATI */ | |
c65ec1c2 | 430 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
431 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
432 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
433 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
434 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
435 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
436 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a JG |
437 | |
438 | /* VIA */ | |
54bb3a94 | 439 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 440 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
441 | |
442 | /* NVIDIA */ | |
54bb3a94 JG |
443 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
444 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
447 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
448 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
455 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
456 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
0522b286 PC |
463 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
464 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ | |
473 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ | |
474 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ | |
475 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ | |
476 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ | |
477 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ | |
478 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ | |
479 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ | |
480 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ | |
481 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ | |
482 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ | |
483 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ | |
484 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ | |
485 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ | |
486 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ | |
6ba86958 | 487 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
488 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ | |
489 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ | |
490 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ | |
7100819f PC |
491 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
492 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ | |
493 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ | |
494 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ | |
495 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ | |
496 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | |
497 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | |
498 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | |
70d562cf | 499 | { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */ |
500 | { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */ | |
501 | { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */ | |
502 | { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */ | |
503 | { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */ | |
504 | { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ | |
505 | { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ | |
506 | { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ | |
507 | { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */ | |
508 | { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */ | |
509 | { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */ | |
510 | { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */ | |
fe7fa31a | 511 | |
95916edd | 512 | /* SiS */ |
54bb3a94 JG |
513 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
514 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
515 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 516 | |
cd70c266 JG |
517 | /* Marvell */ |
518 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 519 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
cd70c266 | 520 | |
415ae2b5 JG |
521 | /* Generic, PCI class code for AHCI */ |
522 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 523 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 524 | |
1da177e4 LT |
525 | { } /* terminate list */ |
526 | }; | |
527 | ||
528 | ||
529 | static struct pci_driver ahci_pci_driver = { | |
530 | .name = DRV_NAME, | |
531 | .id_table = ahci_pci_tbl, | |
532 | .probe = ahci_init_one, | |
24dc5f33 | 533 | .remove = ata_pci_remove_one, |
438ac6d5 | 534 | #ifdef CONFIG_PM |
c1332875 TH |
535 | .suspend = ahci_pci_device_suspend, |
536 | .resume = ahci_pci_device_resume, | |
438ac6d5 | 537 | #endif |
1da177e4 LT |
538 | }; |
539 | ||
540 | ||
98fa4b60 TH |
541 | static inline int ahci_nr_ports(u32 cap) |
542 | { | |
543 | return (cap & 0x1f) + 1; | |
544 | } | |
545 | ||
dab632e8 JG |
546 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
547 | unsigned int port_no) | |
1da177e4 | 548 | { |
dab632e8 | 549 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
4447d351 | 550 | |
dab632e8 JG |
551 | return mmio + 0x100 + (port_no * 0x80); |
552 | } | |
553 | ||
554 | static inline void __iomem *ahci_port_base(struct ata_port *ap) | |
555 | { | |
556 | return __ahci_port_base(ap->host, ap->port_no); | |
1da177e4 LT |
557 | } |
558 | ||
b710a1f4 TH |
559 | static void ahci_enable_ahci(void __iomem *mmio) |
560 | { | |
561 | u32 tmp; | |
562 | ||
563 | /* turn on AHCI_EN */ | |
564 | tmp = readl(mmio + HOST_CTL); | |
565 | if (!(tmp & HOST_AHCI_EN)) { | |
566 | tmp |= HOST_AHCI_EN; | |
567 | writel(tmp, mmio + HOST_CTL); | |
568 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ | |
569 | WARN_ON(!(tmp & HOST_AHCI_EN)); | |
570 | } | |
571 | } | |
572 | ||
d447df14 TH |
573 | /** |
574 | * ahci_save_initial_config - Save and fixup initial config values | |
4447d351 | 575 | * @pdev: target PCI device |
4447d351 | 576 | * @hpriv: host private area to store config values |
d447df14 TH |
577 | * |
578 | * Some registers containing configuration info might be setup by | |
579 | * BIOS and might be cleared on reset. This function saves the | |
580 | * initial values of those registers into @hpriv such that they | |
581 | * can be restored after controller reset. | |
582 | * | |
583 | * If inconsistent, config values are fixed up by this function. | |
584 | * | |
585 | * LOCKING: | |
586 | * None. | |
587 | */ | |
4447d351 | 588 | static void ahci_save_initial_config(struct pci_dev *pdev, |
4447d351 | 589 | struct ahci_host_priv *hpriv) |
d447df14 | 590 | { |
4447d351 | 591 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
d447df14 | 592 | u32 cap, port_map; |
17199b18 | 593 | int i; |
c40e7cb8 | 594 | int mv; |
d447df14 | 595 | |
b710a1f4 TH |
596 | /* make sure AHCI mode is enabled before accessing CAP */ |
597 | ahci_enable_ahci(mmio); | |
598 | ||
d447df14 TH |
599 | /* Values prefixed with saved_ are written back to host after |
600 | * reset. Values without are used for driver operation. | |
601 | */ | |
602 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | |
603 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | |
604 | ||
274c1fde | 605 | /* some chips have errata preventing 64bit use */ |
417a1a6d | 606 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
c7a42156 TH |
607 | dev_printk(KERN_INFO, &pdev->dev, |
608 | "controller can't do 64bit DMA, forcing 32bit\n"); | |
609 | cap &= ~HOST_CAP_64; | |
610 | } | |
611 | ||
417a1a6d | 612 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
274c1fde TH |
613 | dev_printk(KERN_INFO, &pdev->dev, |
614 | "controller can't do NCQ, turning off CAP_NCQ\n"); | |
615 | cap &= ~HOST_CAP_NCQ; | |
616 | } | |
617 | ||
258cd846 | 618 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
6949b914 TH |
619 | dev_printk(KERN_INFO, &pdev->dev, |
620 | "controller can't do PMP, turning off CAP_PMP\n"); | |
621 | cap &= ~HOST_CAP_PMP; | |
622 | } | |
623 | ||
cd70c266 JG |
624 | /* |
625 | * Temporary Marvell 6145 hack: PATA port presence | |
626 | * is asserted through the standard AHCI port | |
627 | * presence register, as bit 4 (counting from 0) | |
628 | */ | |
417a1a6d | 629 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
630 | if (pdev->device == 0x6121) |
631 | mv = 0x3; | |
632 | else | |
633 | mv = 0xf; | |
cd70c266 JG |
634 | dev_printk(KERN_ERR, &pdev->dev, |
635 | "MV_AHCI HACK: port_map %x -> %x\n", | |
c40e7cb8 JAR |
636 | port_map, |
637 | port_map & mv); | |
cd70c266 | 638 | |
c40e7cb8 | 639 | port_map &= mv; |
cd70c266 JG |
640 | } |
641 | ||
17199b18 | 642 | /* cross check port_map and cap.n_ports */ |
7a234aff | 643 | if (port_map) { |
837f5f8f | 644 | int map_ports = 0; |
17199b18 | 645 | |
837f5f8f TH |
646 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
647 | if (port_map & (1 << i)) | |
648 | map_ports++; | |
17199b18 | 649 | |
837f5f8f TH |
650 | /* If PI has more ports than n_ports, whine, clear |
651 | * port_map and let it be generated from n_ports. | |
17199b18 | 652 | */ |
837f5f8f | 653 | if (map_ports > ahci_nr_ports(cap)) { |
4447d351 | 654 | dev_printk(KERN_WARNING, &pdev->dev, |
837f5f8f TH |
655 | "implemented port map (0x%x) contains more " |
656 | "ports than nr_ports (%u), using nr_ports\n", | |
657 | port_map, ahci_nr_ports(cap)); | |
7a234aff TH |
658 | port_map = 0; |
659 | } | |
660 | } | |
661 | ||
662 | /* fabricate port_map from cap.nr_ports */ | |
663 | if (!port_map) { | |
17199b18 | 664 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
7a234aff TH |
665 | dev_printk(KERN_WARNING, &pdev->dev, |
666 | "forcing PORTS_IMPL to 0x%x\n", port_map); | |
667 | ||
668 | /* write the fixed up value to the PI register */ | |
669 | hpriv->saved_port_map = port_map; | |
17199b18 TH |
670 | } |
671 | ||
d447df14 TH |
672 | /* record values to use during operation */ |
673 | hpriv->cap = cap; | |
674 | hpriv->port_map = port_map; | |
675 | } | |
676 | ||
677 | /** | |
678 | * ahci_restore_initial_config - Restore initial config | |
4447d351 | 679 | * @host: target ATA host |
d447df14 TH |
680 | * |
681 | * Restore initial config stored by ahci_save_initial_config(). | |
682 | * | |
683 | * LOCKING: | |
684 | * None. | |
685 | */ | |
4447d351 | 686 | static void ahci_restore_initial_config(struct ata_host *host) |
d447df14 | 687 | { |
4447d351 TH |
688 | struct ahci_host_priv *hpriv = host->private_data; |
689 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
690 | ||
d447df14 TH |
691 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
692 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | |
693 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
694 | } | |
695 | ||
203ef6c4 | 696 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 697 | { |
203ef6c4 TH |
698 | static const int offset[] = { |
699 | [SCR_STATUS] = PORT_SCR_STAT, | |
700 | [SCR_CONTROL] = PORT_SCR_CTL, | |
701 | [SCR_ERROR] = PORT_SCR_ERR, | |
702 | [SCR_ACTIVE] = PORT_SCR_ACT, | |
703 | [SCR_NOTIFICATION] = PORT_SCR_NTF, | |
704 | }; | |
705 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
1da177e4 | 706 | |
203ef6c4 TH |
707 | if (sc_reg < ARRAY_SIZE(offset) && |
708 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) | |
709 | return offset[sc_reg]; | |
da3dbb17 | 710 | return 0; |
1da177e4 LT |
711 | } |
712 | ||
203ef6c4 | 713 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 714 | { |
203ef6c4 TH |
715 | void __iomem *port_mmio = ahci_port_base(ap); |
716 | int offset = ahci_scr_offset(ap, sc_reg); | |
717 | ||
718 | if (offset) { | |
719 | *val = readl(port_mmio + offset); | |
720 | return 0; | |
1da177e4 | 721 | } |
203ef6c4 TH |
722 | return -EINVAL; |
723 | } | |
1da177e4 | 724 | |
203ef6c4 TH |
725 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
726 | { | |
727 | void __iomem *port_mmio = ahci_port_base(ap); | |
728 | int offset = ahci_scr_offset(ap, sc_reg); | |
729 | ||
730 | if (offset) { | |
731 | writel(val, port_mmio + offset); | |
732 | return 0; | |
733 | } | |
734 | return -EINVAL; | |
1da177e4 LT |
735 | } |
736 | ||
4447d351 | 737 | static void ahci_start_engine(struct ata_port *ap) |
7c76d1e8 | 738 | { |
4447d351 | 739 | void __iomem *port_mmio = ahci_port_base(ap); |
7c76d1e8 TH |
740 | u32 tmp; |
741 | ||
d8fcd116 | 742 | /* start DMA */ |
9f592056 | 743 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
744 | tmp |= PORT_CMD_START; |
745 | writel(tmp, port_mmio + PORT_CMD); | |
746 | readl(port_mmio + PORT_CMD); /* flush */ | |
747 | } | |
748 | ||
4447d351 | 749 | static int ahci_stop_engine(struct ata_port *ap) |
254950cd | 750 | { |
4447d351 | 751 | void __iomem *port_mmio = ahci_port_base(ap); |
254950cd TH |
752 | u32 tmp; |
753 | ||
754 | tmp = readl(port_mmio + PORT_CMD); | |
755 | ||
d8fcd116 | 756 | /* check if the HBA is idle */ |
254950cd TH |
757 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
758 | return 0; | |
759 | ||
d8fcd116 | 760 | /* setting HBA to idle */ |
254950cd TH |
761 | tmp &= ~PORT_CMD_START; |
762 | writel(tmp, port_mmio + PORT_CMD); | |
763 | ||
d8fcd116 | 764 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd | 765 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
2dcb407e | 766 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
d8fcd116 | 767 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
768 | return -EIO; |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
4447d351 | 773 | static void ahci_start_fis_rx(struct ata_port *ap) |
0be0aa98 | 774 | { |
4447d351 TH |
775 | void __iomem *port_mmio = ahci_port_base(ap); |
776 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
777 | struct ahci_port_priv *pp = ap->private_data; | |
0be0aa98 TH |
778 | u32 tmp; |
779 | ||
780 | /* set FIS registers */ | |
4447d351 TH |
781 | if (hpriv->cap & HOST_CAP_64) |
782 | writel((pp->cmd_slot_dma >> 16) >> 16, | |
783 | port_mmio + PORT_LST_ADDR_HI); | |
784 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
0be0aa98 | 785 | |
4447d351 TH |
786 | if (hpriv->cap & HOST_CAP_64) |
787 | writel((pp->rx_fis_dma >> 16) >> 16, | |
788 | port_mmio + PORT_FIS_ADDR_HI); | |
789 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
0be0aa98 TH |
790 | |
791 | /* enable FIS reception */ | |
792 | tmp = readl(port_mmio + PORT_CMD); | |
793 | tmp |= PORT_CMD_FIS_RX; | |
794 | writel(tmp, port_mmio + PORT_CMD); | |
795 | ||
796 | /* flush */ | |
797 | readl(port_mmio + PORT_CMD); | |
798 | } | |
799 | ||
4447d351 | 800 | static int ahci_stop_fis_rx(struct ata_port *ap) |
0be0aa98 | 801 | { |
4447d351 | 802 | void __iomem *port_mmio = ahci_port_base(ap); |
0be0aa98 TH |
803 | u32 tmp; |
804 | ||
805 | /* disable FIS reception */ | |
806 | tmp = readl(port_mmio + PORT_CMD); | |
807 | tmp &= ~PORT_CMD_FIS_RX; | |
808 | writel(tmp, port_mmio + PORT_CMD); | |
809 | ||
810 | /* wait for completion, spec says 500ms, give it 1000 */ | |
811 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
812 | PORT_CMD_FIS_ON, 10, 1000); | |
813 | if (tmp & PORT_CMD_FIS_ON) | |
814 | return -EBUSY; | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
4447d351 | 819 | static void ahci_power_up(struct ata_port *ap) |
0be0aa98 | 820 | { |
4447d351 TH |
821 | struct ahci_host_priv *hpriv = ap->host->private_data; |
822 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
823 | u32 cmd; |
824 | ||
825 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
826 | ||
827 | /* spin up device */ | |
4447d351 | 828 | if (hpriv->cap & HOST_CAP_SSS) { |
0be0aa98 TH |
829 | cmd |= PORT_CMD_SPIN_UP; |
830 | writel(cmd, port_mmio + PORT_CMD); | |
831 | } | |
832 | ||
833 | /* wake up link */ | |
834 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
835 | } | |
836 | ||
31556594 KCA |
837 | static void ahci_disable_alpm(struct ata_port *ap) |
838 | { | |
839 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
840 | void __iomem *port_mmio = ahci_port_base(ap); | |
841 | u32 cmd; | |
842 | struct ahci_port_priv *pp = ap->private_data; | |
843 | ||
844 | /* IPM bits should be disabled by libata-core */ | |
845 | /* get the existing command bits */ | |
846 | cmd = readl(port_mmio + PORT_CMD); | |
847 | ||
848 | /* disable ALPM and ASP */ | |
849 | cmd &= ~PORT_CMD_ASP; | |
850 | cmd &= ~PORT_CMD_ALPE; | |
851 | ||
852 | /* force the interface back to active */ | |
853 | cmd |= PORT_CMD_ICC_ACTIVE; | |
854 | ||
855 | /* write out new cmd value */ | |
856 | writel(cmd, port_mmio + PORT_CMD); | |
857 | cmd = readl(port_mmio + PORT_CMD); | |
858 | ||
859 | /* wait 10ms to be sure we've come out of any low power state */ | |
860 | msleep(10); | |
861 | ||
862 | /* clear out any PhyRdy stuff from interrupt status */ | |
863 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); | |
864 | ||
865 | /* go ahead and clean out PhyRdy Change from Serror too */ | |
866 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
867 | ||
868 | /* | |
869 | * Clear flag to indicate that we should ignore all PhyRdy | |
870 | * state changes | |
871 | */ | |
872 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; | |
873 | ||
874 | /* | |
875 | * Enable interrupts on Phy Ready. | |
876 | */ | |
877 | pp->intr_mask |= PORT_IRQ_PHYRDY; | |
878 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
879 | ||
880 | /* | |
881 | * don't change the link pm policy - we can be called | |
882 | * just to turn of link pm temporarily | |
883 | */ | |
884 | } | |
885 | ||
886 | static int ahci_enable_alpm(struct ata_port *ap, | |
887 | enum link_pm policy) | |
888 | { | |
889 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
890 | void __iomem *port_mmio = ahci_port_base(ap); | |
891 | u32 cmd; | |
892 | struct ahci_port_priv *pp = ap->private_data; | |
893 | u32 asp; | |
894 | ||
895 | /* Make sure the host is capable of link power management */ | |
896 | if (!(hpriv->cap & HOST_CAP_ALPM)) | |
897 | return -EINVAL; | |
898 | ||
899 | switch (policy) { | |
900 | case MAX_PERFORMANCE: | |
901 | case NOT_AVAILABLE: | |
902 | /* | |
903 | * if we came here with NOT_AVAILABLE, | |
904 | * it just means this is the first time we | |
905 | * have tried to enable - default to max performance, | |
906 | * and let the user go to lower power modes on request. | |
907 | */ | |
908 | ahci_disable_alpm(ap); | |
909 | return 0; | |
910 | case MIN_POWER: | |
911 | /* configure HBA to enter SLUMBER */ | |
912 | asp = PORT_CMD_ASP; | |
913 | break; | |
914 | case MEDIUM_POWER: | |
915 | /* configure HBA to enter PARTIAL */ | |
916 | asp = 0; | |
917 | break; | |
918 | default: | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
922 | /* | |
923 | * Disable interrupts on Phy Ready. This keeps us from | |
924 | * getting woken up due to spurious phy ready interrupts | |
925 | * TBD - Hot plug should be done via polling now, is | |
926 | * that even supported? | |
927 | */ | |
928 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; | |
929 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
930 | ||
931 | /* | |
932 | * Set a flag to indicate that we should ignore all PhyRdy | |
933 | * state changes since these can happen now whenever we | |
934 | * change link state | |
935 | */ | |
936 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; | |
937 | ||
938 | /* get the existing command bits */ | |
939 | cmd = readl(port_mmio + PORT_CMD); | |
940 | ||
941 | /* | |
942 | * Set ASP based on Policy | |
943 | */ | |
944 | cmd |= asp; | |
945 | ||
946 | /* | |
947 | * Setting this bit will instruct the HBA to aggressively | |
948 | * enter a lower power link state when it's appropriate and | |
949 | * based on the value set above for ASP | |
950 | */ | |
951 | cmd |= PORT_CMD_ALPE; | |
952 | ||
953 | /* write out new cmd value */ | |
954 | writel(cmd, port_mmio + PORT_CMD); | |
955 | cmd = readl(port_mmio + PORT_CMD); | |
956 | ||
957 | /* IPM bits should be set by libata-core */ | |
958 | return 0; | |
959 | } | |
960 | ||
438ac6d5 | 961 | #ifdef CONFIG_PM |
4447d351 | 962 | static void ahci_power_down(struct ata_port *ap) |
0be0aa98 | 963 | { |
4447d351 TH |
964 | struct ahci_host_priv *hpriv = ap->host->private_data; |
965 | void __iomem *port_mmio = ahci_port_base(ap); | |
0be0aa98 TH |
966 | u32 cmd, scontrol; |
967 | ||
4447d351 | 968 | if (!(hpriv->cap & HOST_CAP_SSS)) |
07c53dac | 969 | return; |
0be0aa98 | 970 | |
07c53dac TH |
971 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
972 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
973 | scontrol &= ~0xf; | |
974 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 975 | |
07c53dac TH |
976 | /* then set PxCMD.SUD to 0 */ |
977 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
978 | cmd &= ~PORT_CMD_SPIN_UP; | |
979 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 | 980 | } |
438ac6d5 | 981 | #endif |
0be0aa98 | 982 | |
df69c9c5 | 983 | static void ahci_start_port(struct ata_port *ap) |
0be0aa98 | 984 | { |
0be0aa98 | 985 | /* enable FIS reception */ |
4447d351 | 986 | ahci_start_fis_rx(ap); |
0be0aa98 TH |
987 | |
988 | /* enable DMA */ | |
4447d351 | 989 | ahci_start_engine(ap); |
0be0aa98 TH |
990 | } |
991 | ||
4447d351 | 992 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
0be0aa98 TH |
993 | { |
994 | int rc; | |
995 | ||
996 | /* disable DMA */ | |
4447d351 | 997 | rc = ahci_stop_engine(ap); |
0be0aa98 TH |
998 | if (rc) { |
999 | *emsg = "failed to stop engine"; | |
1000 | return rc; | |
1001 | } | |
1002 | ||
1003 | /* disable FIS reception */ | |
4447d351 | 1004 | rc = ahci_stop_fis_rx(ap); |
0be0aa98 TH |
1005 | if (rc) { |
1006 | *emsg = "failed stop FIS RX"; | |
1007 | return rc; | |
1008 | } | |
1009 | ||
0be0aa98 TH |
1010 | return 0; |
1011 | } | |
1012 | ||
4447d351 | 1013 | static int ahci_reset_controller(struct ata_host *host) |
d91542c1 | 1014 | { |
4447d351 | 1015 | struct pci_dev *pdev = to_pci_dev(host->dev); |
49f29090 | 1016 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 | 1017 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
d447df14 | 1018 | u32 tmp; |
d91542c1 | 1019 | |
3cc3eb11 JG |
1020 | /* we must be in AHCI mode, before using anything |
1021 | * AHCI-specific, such as HOST_RESET. | |
1022 | */ | |
b710a1f4 | 1023 | ahci_enable_ahci(mmio); |
3cc3eb11 JG |
1024 | |
1025 | /* global controller reset */ | |
a22e6444 TH |
1026 | if (!ahci_skip_host_reset) { |
1027 | tmp = readl(mmio + HOST_CTL); | |
1028 | if ((tmp & HOST_RESET) == 0) { | |
1029 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1030 | readl(mmio + HOST_CTL); /* flush */ | |
1031 | } | |
d91542c1 | 1032 | |
a22e6444 TH |
1033 | /* reset must complete within 1 second, or |
1034 | * the hardware should be considered fried. | |
1035 | */ | |
1036 | ssleep(1); | |
d91542c1 | 1037 | |
a22e6444 TH |
1038 | tmp = readl(mmio + HOST_CTL); |
1039 | if (tmp & HOST_RESET) { | |
1040 | dev_printk(KERN_ERR, host->dev, | |
1041 | "controller reset failed (0x%x)\n", tmp); | |
1042 | return -EIO; | |
1043 | } | |
d91542c1 | 1044 | |
a22e6444 TH |
1045 | /* turn on AHCI mode */ |
1046 | ahci_enable_ahci(mmio); | |
98fa4b60 | 1047 | |
a22e6444 TH |
1048 | /* Some registers might be cleared on reset. Restore |
1049 | * initial values. | |
1050 | */ | |
1051 | ahci_restore_initial_config(host); | |
1052 | } else | |
1053 | dev_printk(KERN_INFO, host->dev, | |
1054 | "skipping global host reset\n"); | |
d91542c1 TH |
1055 | |
1056 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
1057 | u16 tmp16; | |
1058 | ||
1059 | /* configure PCS */ | |
1060 | pci_read_config_word(pdev, 0x92, &tmp16); | |
49f29090 TH |
1061 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
1062 | tmp16 |= hpriv->port_map; | |
1063 | pci_write_config_word(pdev, 0x92, tmp16); | |
1064 | } | |
d91542c1 TH |
1065 | } |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
2bcd866b JG |
1070 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
1071 | int port_no, void __iomem *mmio, | |
1072 | void __iomem *port_mmio) | |
1073 | { | |
1074 | const char *emsg = NULL; | |
1075 | int rc; | |
1076 | u32 tmp; | |
1077 | ||
1078 | /* make sure port is not active */ | |
1079 | rc = ahci_deinit_port(ap, &emsg); | |
1080 | if (rc) | |
1081 | dev_printk(KERN_WARNING, &pdev->dev, | |
1082 | "%s (%d)\n", emsg, rc); | |
1083 | ||
1084 | /* clear SError */ | |
1085 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1086 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1087 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1088 | ||
1089 | /* clear port IRQ */ | |
1090 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1091 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1092 | if (tmp) | |
1093 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1094 | ||
1095 | writel(1 << port_no, mmio + HOST_IRQ_STAT); | |
1096 | } | |
1097 | ||
4447d351 | 1098 | static void ahci_init_controller(struct ata_host *host) |
d91542c1 | 1099 | { |
417a1a6d | 1100 | struct ahci_host_priv *hpriv = host->private_data; |
4447d351 TH |
1101 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1102 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
2bcd866b | 1103 | int i; |
cd70c266 | 1104 | void __iomem *port_mmio; |
d91542c1 | 1105 | u32 tmp; |
c40e7cb8 | 1106 | int mv; |
d91542c1 | 1107 | |
417a1a6d | 1108 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
c40e7cb8 JAR |
1109 | if (pdev->device == 0x6121) |
1110 | mv = 2; | |
1111 | else | |
1112 | mv = 4; | |
1113 | port_mmio = __ahci_port_base(host, mv); | |
cd70c266 JG |
1114 | |
1115 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1116 | ||
1117 | /* clear port IRQ */ | |
1118 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1119 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1120 | if (tmp) | |
1121 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1122 | } | |
1123 | ||
4447d351 TH |
1124 | for (i = 0; i < host->n_ports; i++) { |
1125 | struct ata_port *ap = host->ports[i]; | |
d91542c1 | 1126 | |
cd70c266 | 1127 | port_mmio = ahci_port_base(ap); |
4447d351 | 1128 | if (ata_port_is_dummy(ap)) |
d91542c1 | 1129 | continue; |
d91542c1 | 1130 | |
2bcd866b | 1131 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
d91542c1 TH |
1132 | } |
1133 | ||
1134 | tmp = readl(mmio + HOST_CTL); | |
1135 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1136 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1137 | tmp = readl(mmio + HOST_CTL); | |
1138 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1139 | } | |
1140 | ||
a878539e JG |
1141 | static void ahci_dev_config(struct ata_device *dev) |
1142 | { | |
1143 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; | |
1144 | ||
4cde32fc | 1145 | if (hpriv->flags & AHCI_HFLAG_SECT255) { |
a878539e | 1146 | dev->max_sectors = 255; |
4cde32fc JG |
1147 | ata_dev_printk(dev, KERN_INFO, |
1148 | "SB600 AHCI: limiting to 255 sectors per cmd\n"); | |
1149 | } | |
a878539e JG |
1150 | } |
1151 | ||
422b7595 | 1152 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 | 1153 | { |
4447d351 | 1154 | void __iomem *port_mmio = ahci_port_base(ap); |
1da177e4 | 1155 | struct ata_taskfile tf; |
422b7595 TH |
1156 | u32 tmp; |
1157 | ||
1158 | tmp = readl(port_mmio + PORT_SIG); | |
1159 | tf.lbah = (tmp >> 24) & 0xff; | |
1160 | tf.lbam = (tmp >> 16) & 0xff; | |
1161 | tf.lbal = (tmp >> 8) & 0xff; | |
1162 | tf.nsect = (tmp) & 0xff; | |
1163 | ||
1164 | return ata_dev_classify(&tf); | |
1165 | } | |
1166 | ||
12fad3f9 TH |
1167 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
1168 | u32 opts) | |
cc9278ed | 1169 | { |
12fad3f9 TH |
1170 | dma_addr_t cmd_tbl_dma; |
1171 | ||
1172 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
1173 | ||
1174 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
1175 | pp->cmd_slot[tag].status = 0; | |
1176 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
1177 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
1178 | } |
1179 | ||
d2e75dff | 1180 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
4658f79b | 1181 | { |
350756f6 | 1182 | void __iomem *port_mmio = ahci_port_base(ap); |
cca3974e | 1183 | struct ahci_host_priv *hpriv = ap->host->private_data; |
520d06f9 | 1184 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; |
bf2af2a2 | 1185 | u32 tmp; |
d2e75dff | 1186 | int busy, rc; |
bf2af2a2 | 1187 | |
d2e75dff | 1188 | /* do we need to kick the port? */ |
520d06f9 | 1189 | busy = status & (ATA_BUSY | ATA_DRQ); |
d2e75dff TH |
1190 | if (!busy && !force_restart) |
1191 | return 0; | |
1192 | ||
1193 | /* stop engine */ | |
1194 | rc = ahci_stop_engine(ap); | |
1195 | if (rc) | |
1196 | goto out_restart; | |
1197 | ||
1198 | /* need to do CLO? */ | |
1199 | if (!busy) { | |
1200 | rc = 0; | |
1201 | goto out_restart; | |
1202 | } | |
1203 | ||
1204 | if (!(hpriv->cap & HOST_CAP_CLO)) { | |
1205 | rc = -EOPNOTSUPP; | |
1206 | goto out_restart; | |
1207 | } | |
bf2af2a2 | 1208 | |
d2e75dff | 1209 | /* perform CLO */ |
bf2af2a2 BJ |
1210 | tmp = readl(port_mmio + PORT_CMD); |
1211 | tmp |= PORT_CMD_CLO; | |
1212 | writel(tmp, port_mmio + PORT_CMD); | |
1213 | ||
d2e75dff | 1214 | rc = 0; |
bf2af2a2 BJ |
1215 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
1216 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
1217 | if (tmp & PORT_CMD_CLO) | |
d2e75dff | 1218 | rc = -EIO; |
bf2af2a2 | 1219 | |
d2e75dff TH |
1220 | /* restart engine */ |
1221 | out_restart: | |
1222 | ahci_start_engine(ap); | |
1223 | return rc; | |
bf2af2a2 BJ |
1224 | } |
1225 | ||
91c4a2e0 TH |
1226 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
1227 | struct ata_taskfile *tf, int is_cmd, u16 flags, | |
1228 | unsigned long timeout_msec) | |
bf2af2a2 | 1229 | { |
91c4a2e0 | 1230 | const u32 cmd_fis_len = 5; /* five dwords */ |
4658f79b | 1231 | struct ahci_port_priv *pp = ap->private_data; |
4447d351 | 1232 | void __iomem *port_mmio = ahci_port_base(ap); |
91c4a2e0 TH |
1233 | u8 *fis = pp->cmd_tbl; |
1234 | u32 tmp; | |
1235 | ||
1236 | /* prep the command */ | |
1237 | ata_tf_to_fis(tf, pmp, is_cmd, fis); | |
1238 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); | |
1239 | ||
1240 | /* issue & wait */ | |
1241 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
1242 | ||
1243 | if (timeout_msec) { | |
1244 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, | |
1245 | 1, timeout_msec); | |
1246 | if (tmp & 0x1) { | |
1247 | ahci_kick_engine(ap, 1); | |
1248 | return -EBUSY; | |
1249 | } | |
1250 | } else | |
1251 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
a89611e8 TH |
1256 | static int ahci_check_ready(struct ata_link *link) |
1257 | { | |
350756f6 TH |
1258 | void __iomem *port_mmio = ahci_port_base(link->ap); |
1259 | u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; | |
a89611e8 TH |
1260 | |
1261 | if (!(status & ATA_BUSY)) | |
1262 | return 1; | |
1263 | return 0; | |
1264 | } | |
1265 | ||
cc0680a5 | 1266 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 | 1267 | int pmp, unsigned long deadline) |
91c4a2e0 | 1268 | { |
cc0680a5 | 1269 | struct ata_port *ap = link->ap; |
4658f79b | 1270 | const char *reason = NULL; |
2cbb79eb | 1271 | unsigned long now, msecs; |
4658f79b | 1272 | struct ata_taskfile tf; |
4658f79b TH |
1273 | int rc; |
1274 | ||
1275 | DPRINTK("ENTER\n"); | |
1276 | ||
cc0680a5 | 1277 | if (ata_link_offline(link)) { |
c2a65852 TH |
1278 | DPRINTK("PHY reports no device\n"); |
1279 | *class = ATA_DEV_NONE; | |
1280 | return 0; | |
1281 | } | |
1282 | ||
4658f79b | 1283 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
d2e75dff | 1284 | rc = ahci_kick_engine(ap, 1); |
994056d7 | 1285 | if (rc && rc != -EOPNOTSUPP) |
cc0680a5 | 1286 | ata_link_printk(link, KERN_WARNING, |
994056d7 | 1287 | "failed to reset engine (errno=%d)\n", rc); |
4658f79b | 1288 | |
cc0680a5 | 1289 | ata_tf_init(link->device, &tf); |
4658f79b TH |
1290 | |
1291 | /* issue the first D2H Register FIS */ | |
2cbb79eb TH |
1292 | msecs = 0; |
1293 | now = jiffies; | |
1294 | if (time_after(now, deadline)) | |
1295 | msecs = jiffies_to_msecs(deadline - now); | |
1296 | ||
4658f79b | 1297 | tf.ctl |= ATA_SRST; |
a9cf5e85 | 1298 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
91c4a2e0 | 1299 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
4658f79b TH |
1300 | rc = -EIO; |
1301 | reason = "1st FIS failed"; | |
1302 | goto fail; | |
1303 | } | |
1304 | ||
1305 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
1306 | msleep(1); | |
1307 | ||
1308 | /* issue the second D2H Register FIS */ | |
4658f79b | 1309 | tf.ctl &= ~ATA_SRST; |
a9cf5e85 | 1310 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
4658f79b | 1311 | |
705e76be | 1312 | /* wait for link to become ready */ |
a89611e8 | 1313 | rc = ata_wait_after_reset(link, deadline, ahci_check_ready); |
9b89391c TH |
1314 | /* link occupied, -ENODEV too is an error */ |
1315 | if (rc) { | |
1316 | reason = "device not ready"; | |
1317 | goto fail; | |
4658f79b | 1318 | } |
9b89391c | 1319 | *class = ahci_dev_classify(ap); |
4658f79b TH |
1320 | |
1321 | DPRINTK("EXIT, class=%u\n", *class); | |
1322 | return 0; | |
1323 | ||
4658f79b | 1324 | fail: |
cc0680a5 | 1325 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
1326 | return rc; |
1327 | } | |
1328 | ||
cc0680a5 | 1329 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
a9cf5e85 TH |
1330 | unsigned long deadline) |
1331 | { | |
7d50b60b TH |
1332 | int pmp = 0; |
1333 | ||
1334 | if (link->ap->flags & ATA_FLAG_PMP) | |
1335 | pmp = SATA_PMP_CTRL_PORT; | |
1336 | ||
1337 | return ahci_do_softreset(link, class, pmp, deadline); | |
a9cf5e85 TH |
1338 | } |
1339 | ||
cc0680a5 | 1340 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1341 | unsigned long deadline) |
422b7595 | 1342 | { |
9dadd45b | 1343 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
cc0680a5 | 1344 | struct ata_port *ap = link->ap; |
4296971d TH |
1345 | struct ahci_port_priv *pp = ap->private_data; |
1346 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1347 | struct ata_taskfile tf; | |
9dadd45b | 1348 | bool online; |
4bd00f6a TH |
1349 | int rc; |
1350 | ||
1351 | DPRINTK("ENTER\n"); | |
1da177e4 | 1352 | |
4447d351 | 1353 | ahci_stop_engine(ap); |
4296971d TH |
1354 | |
1355 | /* clear D2H reception area to properly wait for D2H FIS */ | |
cc0680a5 | 1356 | ata_tf_init(link->device, &tf); |
dfd7a3db | 1357 | tf.command = 0x80; |
9977126c | 1358 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
4296971d | 1359 | |
9dadd45b TH |
1360 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1361 | ahci_check_ready); | |
4296971d | 1362 | |
4447d351 | 1363 | ahci_start_engine(ap); |
1da177e4 | 1364 | |
9dadd45b | 1365 | if (online) |
4bd00f6a | 1366 | *class = ahci_dev_classify(ap); |
1da177e4 | 1367 | |
4bd00f6a TH |
1368 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
1369 | return rc; | |
1370 | } | |
1371 | ||
cc0680a5 | 1372 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 1373 | unsigned long deadline) |
ad616ffb | 1374 | { |
cc0680a5 | 1375 | struct ata_port *ap = link->ap; |
9dadd45b | 1376 | bool online; |
ad616ffb TH |
1377 | int rc; |
1378 | ||
1379 | DPRINTK("ENTER\n"); | |
1380 | ||
4447d351 | 1381 | ahci_stop_engine(ap); |
ad616ffb | 1382 | |
cc0680a5 | 1383 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
9dadd45b | 1384 | deadline, &online, NULL); |
ad616ffb | 1385 | |
4447d351 | 1386 | ahci_start_engine(ap); |
ad616ffb TH |
1387 | |
1388 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
1389 | ||
1390 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
1391 | * request follow-up softreset. | |
1392 | */ | |
9dadd45b | 1393 | return online ? -EAGAIN : rc; |
ad616ffb TH |
1394 | } |
1395 | ||
edc93052 TH |
1396 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
1397 | unsigned long deadline) | |
1398 | { | |
1399 | struct ata_port *ap = link->ap; | |
1400 | struct ahci_port_priv *pp = ap->private_data; | |
1401 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1402 | struct ata_taskfile tf; | |
9dadd45b | 1403 | bool online; |
edc93052 TH |
1404 | int rc; |
1405 | ||
1406 | ahci_stop_engine(ap); | |
1407 | ||
1408 | /* clear D2H reception area to properly wait for D2H FIS */ | |
1409 | ata_tf_init(link->device, &tf); | |
1410 | tf.command = 0x80; | |
1411 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
1412 | ||
1413 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), | |
9dadd45b | 1414 | deadline, &online, NULL); |
edc93052 TH |
1415 | |
1416 | ahci_start_engine(ap); | |
1417 | ||
edc93052 TH |
1418 | /* The pseudo configuration device on SIMG4726 attached to |
1419 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
1420 | * hardreset if no device is attached to the first downstream | |
1421 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
1422 | * work around this, wait for !BSY only briefly. If BSY isn't | |
1423 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
1424 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
1425 | * | |
1426 | * Wait for two seconds. Devices attached to downstream port | |
1427 | * which can't process the following IDENTIFY after this will | |
1428 | * have to be reset again. For most cases, this should | |
1429 | * suffice while making probing snappish enough. | |
1430 | */ | |
9dadd45b TH |
1431 | if (online) { |
1432 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
1433 | ahci_check_ready); | |
1434 | if (rc) | |
1435 | ahci_kick_engine(ap, 0); | |
1436 | } | |
9dadd45b | 1437 | return rc; |
edc93052 TH |
1438 | } |
1439 | ||
cc0680a5 | 1440 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
4bd00f6a | 1441 | { |
cc0680a5 | 1442 | struct ata_port *ap = link->ap; |
4447d351 | 1443 | void __iomem *port_mmio = ahci_port_base(ap); |
4bd00f6a TH |
1444 | u32 new_tmp, tmp; |
1445 | ||
203c75b8 | 1446 | ata_std_postreset(link, class); |
02eaa666 JG |
1447 | |
1448 | /* Make sure port's ATAPI bit is set appropriately */ | |
1449 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 1450 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
1451 | new_tmp |= PORT_CMD_ATAPI; |
1452 | else | |
1453 | new_tmp &= ~PORT_CMD_ATAPI; | |
1454 | if (new_tmp != tmp) { | |
1455 | writel(new_tmp, port_mmio + PORT_CMD); | |
1456 | readl(port_mmio + PORT_CMD); /* flush */ | |
1457 | } | |
1da177e4 LT |
1458 | } |
1459 | ||
7d50b60b TH |
1460 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
1461 | unsigned long deadline) | |
1462 | { | |
1463 | return ahci_do_softreset(link, class, link->pmp, deadline); | |
1464 | } | |
1465 | ||
12fad3f9 | 1466 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 1467 | { |
cedc9a47 | 1468 | struct scatterlist *sg; |
ff2aeb1e TH |
1469 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
1470 | unsigned int si; | |
1da177e4 LT |
1471 | |
1472 | VPRINTK("ENTER\n"); | |
1473 | ||
1474 | /* | |
1475 | * Next, the S/G list. | |
1476 | */ | |
ff2aeb1e | 1477 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
cedc9a47 JG |
1478 | dma_addr_t addr = sg_dma_address(sg); |
1479 | u32 sg_len = sg_dma_len(sg); | |
1480 | ||
ff2aeb1e TH |
1481 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
1482 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1483 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); | |
1da177e4 | 1484 | } |
828d09de | 1485 | |
ff2aeb1e | 1486 | return si; |
1da177e4 LT |
1487 | } |
1488 | ||
1489 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1490 | { | |
a0ea7328 JG |
1491 | struct ata_port *ap = qc->ap; |
1492 | struct ahci_port_priv *pp = ap->private_data; | |
405e66b3 | 1493 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
12fad3f9 | 1494 | void *cmd_tbl; |
1da177e4 LT |
1495 | u32 opts; |
1496 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1497 | unsigned int n_elem; |
1da177e4 | 1498 | |
1da177e4 LT |
1499 | /* |
1500 | * Fill in command table information. First, the header, | |
1501 | * a SATA Register - Host to Device command FIS. | |
1502 | */ | |
12fad3f9 TH |
1503 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1504 | ||
7d50b60b | 1505 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
cc9278ed | 1506 | if (is_atapi) { |
12fad3f9 TH |
1507 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1508 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1509 | } |
1da177e4 | 1510 | |
cc9278ed TH |
1511 | n_elem = 0; |
1512 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1513 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1514 | |
cc9278ed TH |
1515 | /* |
1516 | * Fill in command slot information. | |
1517 | */ | |
7d50b60b | 1518 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
cc9278ed TH |
1519 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
1520 | opts |= AHCI_CMD_WRITE; | |
1521 | if (is_atapi) | |
4b10e559 | 1522 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1523 | |
12fad3f9 | 1524 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1525 | } |
1526 | ||
78cd52d0 | 1527 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1528 | { |
417a1a6d | 1529 | struct ahci_host_priv *hpriv = ap->host->private_data; |
78cd52d0 | 1530 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1531 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
1532 | struct ata_link *link = NULL; | |
1533 | struct ata_queued_cmd *active_qc; | |
1534 | struct ata_eh_info *active_ehi; | |
78cd52d0 | 1535 | u32 serror; |
1da177e4 | 1536 | |
7d50b60b TH |
1537 | /* determine active link */ |
1538 | ata_port_for_each_link(link, ap) | |
1539 | if (ata_link_active(link)) | |
1540 | break; | |
1541 | if (!link) | |
1542 | link = &ap->link; | |
1543 | ||
1544 | active_qc = ata_qc_from_tag(ap, link->active_tag); | |
1545 | active_ehi = &link->eh_info; | |
1546 | ||
1547 | /* record irq stat */ | |
1548 | ata_ehi_clear_desc(host_ehi); | |
1549 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); | |
1da177e4 | 1550 | |
78cd52d0 | 1551 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
da3dbb17 | 1552 | ahci_scr_read(ap, SCR_ERROR, &serror); |
78cd52d0 | 1553 | ahci_scr_write(ap, SCR_ERROR, serror); |
7d50b60b | 1554 | host_ehi->serror |= serror; |
78cd52d0 | 1555 | |
41669553 | 1556 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
417a1a6d | 1557 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
41669553 TH |
1558 | irq_stat &= ~PORT_IRQ_IF_ERR; |
1559 | ||
55a61604 | 1560 | if (irq_stat & PORT_IRQ_TF_ERR) { |
7d50b60b TH |
1561 | /* If qc is active, charge it; otherwise, the active |
1562 | * link. There's no active qc on NCQ errors. It will | |
1563 | * be determined by EH by reading log page 10h. | |
1564 | */ | |
1565 | if (active_qc) | |
1566 | active_qc->err_mask |= AC_ERR_DEV; | |
1567 | else | |
1568 | active_ehi->err_mask |= AC_ERR_DEV; | |
1569 | ||
417a1a6d | 1570 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
7d50b60b TH |
1571 | host_ehi->serror &= ~SERR_INTERNAL; |
1572 | } | |
1573 | ||
1574 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1575 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1576 | ||
1577 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1578 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b TH |
1579 | ata_ehi_push_desc(active_ehi, |
1580 | "unknown FIS %08x %08x %08x %08x" , | |
1581 | unk[0], unk[1], unk[2], unk[3]); | |
1582 | } | |
1583 | ||
1584 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { | |
1585 | active_ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 1586 | active_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1587 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
55a61604 | 1588 | } |
78cd52d0 TH |
1589 | |
1590 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
7d50b60b | 1591 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
cf480626 | 1592 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1593 | ata_ehi_push_desc(host_ehi, "host bus error"); |
1da177e4 LT |
1594 | } |
1595 | ||
78cd52d0 | 1596 | if (irq_stat & PORT_IRQ_IF_ERR) { |
7d50b60b | 1597 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
cf480626 | 1598 | host_ehi->action |= ATA_EH_RESET; |
7d50b60b | 1599 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
78cd52d0 | 1600 | } |
1da177e4 | 1601 | |
78cd52d0 | 1602 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
7d50b60b TH |
1603 | ata_ehi_hotplugged(host_ehi); |
1604 | ata_ehi_push_desc(host_ehi, "%s", | |
1605 | irq_stat & PORT_IRQ_CONNECT ? | |
78cd52d0 TH |
1606 | "connection status changed" : "PHY RDY changed"); |
1607 | } | |
1608 | ||
78cd52d0 | 1609 | /* okay, let's hand over to EH */ |
a72ec4ce | 1610 | |
78cd52d0 TH |
1611 | if (irq_stat & PORT_IRQ_FREEZE) |
1612 | ata_port_freeze(ap); | |
1613 | else | |
1614 | ata_port_abort(ap); | |
1da177e4 LT |
1615 | } |
1616 | ||
df69c9c5 | 1617 | static void ahci_port_intr(struct ata_port *ap) |
1da177e4 | 1618 | { |
350756f6 | 1619 | void __iomem *port_mmio = ahci_port_base(ap); |
9af5c9c9 | 1620 | struct ata_eh_info *ehi = &ap->link.eh_info; |
0291f95f | 1621 | struct ahci_port_priv *pp = ap->private_data; |
5f226c6b | 1622 | struct ahci_host_priv *hpriv = ap->host->private_data; |
b06ce3e5 | 1623 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
12fad3f9 | 1624 | u32 status, qc_active; |
459ad688 | 1625 | int rc; |
1da177e4 LT |
1626 | |
1627 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1628 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1629 | ||
b06ce3e5 TH |
1630 | /* ignore BAD_PMP while resetting */ |
1631 | if (unlikely(resetting)) | |
1632 | status &= ~PORT_IRQ_BAD_PMP; | |
1633 | ||
31556594 KCA |
1634 | /* If we are getting PhyRdy, this is |
1635 | * just a power state change, we should | |
1636 | * clear out this, plus the PhyRdy/Comm | |
1637 | * Wake bits from Serror | |
1638 | */ | |
1639 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && | |
1640 | (status & PORT_IRQ_PHYRDY)) { | |
1641 | status &= ~PORT_IRQ_PHYRDY; | |
1642 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); | |
1643 | } | |
1644 | ||
78cd52d0 TH |
1645 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1646 | ahci_error_intr(ap, status); | |
1647 | return; | |
1da177e4 LT |
1648 | } |
1649 | ||
2f294968 | 1650 | if (status & PORT_IRQ_SDB_FIS) { |
5f226c6b TH |
1651 | /* If SNotification is available, leave notification |
1652 | * handling to sata_async_notification(). If not, | |
1653 | * emulate it by snooping SDB FIS RX area. | |
1654 | * | |
1655 | * Snooping FIS RX area is probably cheaper than | |
1656 | * poking SNotification but some constrollers which | |
1657 | * implement SNotification, ICH9 for example, don't | |
1658 | * store AN SDB FIS into receive area. | |
2f294968 | 1659 | */ |
5f226c6b | 1660 | if (hpriv->cap & HOST_CAP_SNTF) |
7d77b247 | 1661 | sata_async_notification(ap); |
5f226c6b TH |
1662 | else { |
1663 | /* If the 'N' bit in word 0 of the FIS is set, | |
1664 | * we just received asynchronous notification. | |
1665 | * Tell libata about it. | |
1666 | */ | |
1667 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; | |
1668 | u32 f0 = le32_to_cpu(f[0]); | |
1669 | ||
1670 | if (f0 & (1 << 15)) | |
1671 | sata_async_notification(ap); | |
1672 | } | |
2f294968 KCA |
1673 | } |
1674 | ||
7d50b60b TH |
1675 | /* pp->active_link is valid iff any command is in flight */ |
1676 | if (ap->qc_active && pp->active_link->sactive) | |
12fad3f9 TH |
1677 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
1678 | else | |
1679 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1680 | ||
79f97dad | 1681 | rc = ata_qc_complete_multiple(ap, qc_active); |
b06ce3e5 | 1682 | |
459ad688 TH |
1683 | /* while resetting, invalid completions are expected */ |
1684 | if (unlikely(rc < 0 && !resetting)) { | |
12fad3f9 | 1685 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1686 | ehi->action |= ATA_EH_RESET; |
12fad3f9 | 1687 | ata_port_freeze(ap); |
1da177e4 | 1688 | } |
1da177e4 LT |
1689 | } |
1690 | ||
7d12e780 | 1691 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1692 | { |
cca3974e | 1693 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1694 | struct ahci_host_priv *hpriv; |
1695 | unsigned int i, handled = 0; | |
ea6ba10b | 1696 | void __iomem *mmio; |
1da177e4 LT |
1697 | u32 irq_stat, irq_ack = 0; |
1698 | ||
1699 | VPRINTK("ENTER\n"); | |
1700 | ||
cca3974e | 1701 | hpriv = host->private_data; |
0d5ff566 | 1702 | mmio = host->iomap[AHCI_PCI_BAR]; |
1da177e4 LT |
1703 | |
1704 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1705 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1706 | irq_stat &= hpriv->port_map; | |
1707 | if (!irq_stat) | |
1708 | return IRQ_NONE; | |
1709 | ||
2dcb407e | 1710 | spin_lock(&host->lock); |
1da177e4 | 1711 | |
2dcb407e | 1712 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1713 | struct ata_port *ap; |
1da177e4 | 1714 | |
67846b30 JG |
1715 | if (!(irq_stat & (1 << i))) |
1716 | continue; | |
1717 | ||
cca3974e | 1718 | ap = host->ports[i]; |
67846b30 | 1719 | if (ap) { |
df69c9c5 | 1720 | ahci_port_intr(ap); |
67846b30 JG |
1721 | VPRINTK("port %u\n", i); |
1722 | } else { | |
1723 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1724 | if (ata_ratelimit()) |
cca3974e | 1725 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1726 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1727 | } |
67846b30 JG |
1728 | |
1729 | irq_ack |= (1 << i); | |
1da177e4 LT |
1730 | } |
1731 | ||
1732 | if (irq_ack) { | |
1733 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1734 | handled = 1; | |
1735 | } | |
1736 | ||
cca3974e | 1737 | spin_unlock(&host->lock); |
1da177e4 LT |
1738 | |
1739 | VPRINTK("EXIT\n"); | |
1740 | ||
1741 | return IRQ_RETVAL(handled); | |
1742 | } | |
1743 | ||
9a3d9eb0 | 1744 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1745 | { |
1746 | struct ata_port *ap = qc->ap; | |
4447d351 | 1747 | void __iomem *port_mmio = ahci_port_base(ap); |
7d50b60b TH |
1748 | struct ahci_port_priv *pp = ap->private_data; |
1749 | ||
1750 | /* Keep track of the currently active link. It will be used | |
1751 | * in completion path to determine whether NCQ phase is in | |
1752 | * progress. | |
1753 | */ | |
1754 | pp->active_link = qc->dev->link; | |
1da177e4 | 1755 | |
12fad3f9 TH |
1756 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1757 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1758 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1759 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
4c9bf4e7 TH |
1764 | static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
1765 | { | |
1766 | struct ahci_port_priv *pp = qc->ap->private_data; | |
1767 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
1768 | ||
1769 | ata_tf_from_fis(d2h_fis, &qc->result_tf); | |
1770 | return true; | |
1771 | } | |
1772 | ||
78cd52d0 TH |
1773 | static void ahci_freeze(struct ata_port *ap) |
1774 | { | |
4447d351 | 1775 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 TH |
1776 | |
1777 | /* turn IRQ off */ | |
1778 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1779 | } | |
1780 | ||
1781 | static void ahci_thaw(struct ata_port *ap) | |
1782 | { | |
0d5ff566 | 1783 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
4447d351 | 1784 | void __iomem *port_mmio = ahci_port_base(ap); |
78cd52d0 | 1785 | u32 tmp; |
a7384925 | 1786 | struct ahci_port_priv *pp = ap->private_data; |
78cd52d0 TH |
1787 | |
1788 | /* clear IRQ */ | |
1789 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1790 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
a718728f | 1791 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
78cd52d0 | 1792 | |
1c954a4d TH |
1793 | /* turn IRQ back on */ |
1794 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
78cd52d0 TH |
1795 | } |
1796 | ||
1797 | static void ahci_error_handler(struct ata_port *ap) | |
1798 | { | |
b51e9e5d | 1799 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1800 | /* restart engine */ |
4447d351 TH |
1801 | ahci_stop_engine(ap); |
1802 | ahci_start_engine(ap); | |
78cd52d0 TH |
1803 | } |
1804 | ||
a1efdaba | 1805 | sata_pmp_error_handler(ap); |
edc93052 TH |
1806 | } |
1807 | ||
78cd52d0 TH |
1808 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1809 | { | |
1810 | struct ata_port *ap = qc->ap; | |
1811 | ||
d2e75dff TH |
1812 | /* make DMA engine forget about the failed command */ |
1813 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1814 | ahci_kick_engine(ap, 1); | |
78cd52d0 TH |
1815 | } |
1816 | ||
7d50b60b TH |
1817 | static void ahci_pmp_attach(struct ata_port *ap) |
1818 | { | |
1819 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1820 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1821 | u32 cmd; |
1822 | ||
1823 | cmd = readl(port_mmio + PORT_CMD); | |
1824 | cmd |= PORT_CMD_PMP; | |
1825 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1826 | |
1827 | pp->intr_mask |= PORT_IRQ_BAD_PMP; | |
1828 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1829 | } |
1830 | ||
1831 | static void ahci_pmp_detach(struct ata_port *ap) | |
1832 | { | |
1833 | void __iomem *port_mmio = ahci_port_base(ap); | |
1c954a4d | 1834 | struct ahci_port_priv *pp = ap->private_data; |
7d50b60b TH |
1835 | u32 cmd; |
1836 | ||
1837 | cmd = readl(port_mmio + PORT_CMD); | |
1838 | cmd &= ~PORT_CMD_PMP; | |
1839 | writel(cmd, port_mmio + PORT_CMD); | |
1c954a4d TH |
1840 | |
1841 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; | |
1842 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); | |
7d50b60b TH |
1843 | } |
1844 | ||
028a2596 AD |
1845 | static int ahci_port_resume(struct ata_port *ap) |
1846 | { | |
1847 | ahci_power_up(ap); | |
1848 | ahci_start_port(ap); | |
1849 | ||
7d50b60b TH |
1850 | if (ap->nr_pmp_links) |
1851 | ahci_pmp_attach(ap); | |
1852 | else | |
1853 | ahci_pmp_detach(ap); | |
1854 | ||
028a2596 AD |
1855 | return 0; |
1856 | } | |
1857 | ||
438ac6d5 | 1858 | #ifdef CONFIG_PM |
c1332875 TH |
1859 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1860 | { | |
c1332875 TH |
1861 | const char *emsg = NULL; |
1862 | int rc; | |
1863 | ||
4447d351 | 1864 | rc = ahci_deinit_port(ap, &emsg); |
8e16f941 | 1865 | if (rc == 0) |
4447d351 | 1866 | ahci_power_down(ap); |
8e16f941 | 1867 | else { |
c1332875 | 1868 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
df69c9c5 | 1869 | ahci_start_port(ap); |
c1332875 TH |
1870 | } |
1871 | ||
1872 | return rc; | |
1873 | } | |
1874 | ||
c1332875 TH |
1875 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1876 | { | |
cca3974e | 1877 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1878 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
c1332875 TH |
1879 | u32 ctl; |
1880 | ||
3a2d5b70 | 1881 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
1882 | /* AHCI spec rev1.1 section 8.3.3: |
1883 | * Software must disable interrupts prior to requesting a | |
1884 | * transition of the HBA to D3 state. | |
1885 | */ | |
1886 | ctl = readl(mmio + HOST_CTL); | |
1887 | ctl &= ~HOST_IRQ_EN; | |
1888 | writel(ctl, mmio + HOST_CTL); | |
1889 | readl(mmio + HOST_CTL); /* flush */ | |
1890 | } | |
1891 | ||
1892 | return ata_pci_device_suspend(pdev, mesg); | |
1893 | } | |
1894 | ||
1895 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1896 | { | |
cca3974e | 1897 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
c1332875 TH |
1898 | int rc; |
1899 | ||
553c4aa6 TH |
1900 | rc = ata_pci_device_do_resume(pdev); |
1901 | if (rc) | |
1902 | return rc; | |
c1332875 TH |
1903 | |
1904 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
4447d351 | 1905 | rc = ahci_reset_controller(host); |
c1332875 TH |
1906 | if (rc) |
1907 | return rc; | |
1908 | ||
4447d351 | 1909 | ahci_init_controller(host); |
c1332875 TH |
1910 | } |
1911 | ||
cca3974e | 1912 | ata_host_resume(host); |
c1332875 TH |
1913 | |
1914 | return 0; | |
1915 | } | |
438ac6d5 | 1916 | #endif |
c1332875 | 1917 | |
254950cd TH |
1918 | static int ahci_port_start(struct ata_port *ap) |
1919 | { | |
cca3974e | 1920 | struct device *dev = ap->host->dev; |
254950cd | 1921 | struct ahci_port_priv *pp; |
254950cd TH |
1922 | void *mem; |
1923 | dma_addr_t mem_dma; | |
254950cd | 1924 | |
24dc5f33 | 1925 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
254950cd TH |
1926 | if (!pp) |
1927 | return -ENOMEM; | |
254950cd | 1928 | |
24dc5f33 TH |
1929 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
1930 | GFP_KERNEL); | |
1931 | if (!mem) | |
254950cd | 1932 | return -ENOMEM; |
254950cd TH |
1933 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
1934 | ||
1935 | /* | |
1936 | * First item in chunk of DMA memory: 32-slot command table, | |
1937 | * 32 bytes each in size | |
1938 | */ | |
1939 | pp->cmd_slot = mem; | |
1940 | pp->cmd_slot_dma = mem_dma; | |
1941 | ||
1942 | mem += AHCI_CMD_SLOT_SZ; | |
1943 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1944 | ||
1945 | /* | |
1946 | * Second item: Received-FIS area | |
1947 | */ | |
1948 | pp->rx_fis = mem; | |
1949 | pp->rx_fis_dma = mem_dma; | |
1950 | ||
1951 | mem += AHCI_RX_FIS_SZ; | |
1952 | mem_dma += AHCI_RX_FIS_SZ; | |
1953 | ||
1954 | /* | |
1955 | * Third item: data area for storing a single command | |
1956 | * and its scatter-gather table | |
1957 | */ | |
1958 | pp->cmd_tbl = mem; | |
1959 | pp->cmd_tbl_dma = mem_dma; | |
1960 | ||
a7384925 | 1961 | /* |
2dcb407e JG |
1962 | * Save off initial list of interrupts to be enabled. |
1963 | * This could be changed later | |
1964 | */ | |
a7384925 KCA |
1965 | pp->intr_mask = DEF_PORT_IRQ; |
1966 | ||
254950cd TH |
1967 | ap->private_data = pp; |
1968 | ||
df69c9c5 JG |
1969 | /* engage engines, captain */ |
1970 | return ahci_port_resume(ap); | |
254950cd TH |
1971 | } |
1972 | ||
1973 | static void ahci_port_stop(struct ata_port *ap) | |
1974 | { | |
0be0aa98 TH |
1975 | const char *emsg = NULL; |
1976 | int rc; | |
254950cd | 1977 | |
0be0aa98 | 1978 | /* de-initialize port */ |
4447d351 | 1979 | rc = ahci_deinit_port(ap, &emsg); |
0be0aa98 TH |
1980 | if (rc) |
1981 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1982 | } |
1983 | ||
4447d351 | 1984 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 1985 | { |
1da177e4 | 1986 | int rc; |
1da177e4 | 1987 | |
1da177e4 LT |
1988 | if (using_dac && |
1989 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1990 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1991 | if (rc) { | |
1992 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1993 | if (rc) { | |
a9524a76 JG |
1994 | dev_printk(KERN_ERR, &pdev->dev, |
1995 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1996 | return rc; |
1997 | } | |
1998 | } | |
1da177e4 LT |
1999 | } else { |
2000 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2001 | if (rc) { | |
a9524a76 JG |
2002 | dev_printk(KERN_ERR, &pdev->dev, |
2003 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
2004 | return rc; |
2005 | } | |
2006 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2007 | if (rc) { | |
a9524a76 JG |
2008 | dev_printk(KERN_ERR, &pdev->dev, |
2009 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
2010 | return rc; |
2011 | } | |
2012 | } | |
1da177e4 LT |
2013 | return 0; |
2014 | } | |
2015 | ||
4447d351 | 2016 | static void ahci_print_info(struct ata_host *host) |
1da177e4 | 2017 | { |
4447d351 TH |
2018 | struct ahci_host_priv *hpriv = host->private_data; |
2019 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2020 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
1da177e4 LT |
2021 | u32 vers, cap, impl, speed; |
2022 | const char *speed_s; | |
2023 | u16 cc; | |
2024 | const char *scc_s; | |
2025 | ||
2026 | vers = readl(mmio + HOST_VERSION); | |
2027 | cap = hpriv->cap; | |
2028 | impl = hpriv->port_map; | |
2029 | ||
2030 | speed = (cap >> 20) & 0xf; | |
2031 | if (speed == 1) | |
2032 | speed_s = "1.5"; | |
2033 | else if (speed == 2) | |
2034 | speed_s = "3"; | |
2035 | else | |
2036 | speed_s = "?"; | |
2037 | ||
2038 | pci_read_config_word(pdev, 0x0a, &cc); | |
c9f89475 | 2039 | if (cc == PCI_CLASS_STORAGE_IDE) |
1da177e4 | 2040 | scc_s = "IDE"; |
c9f89475 | 2041 | else if (cc == PCI_CLASS_STORAGE_SATA) |
1da177e4 | 2042 | scc_s = "SATA"; |
c9f89475 | 2043 | else if (cc == PCI_CLASS_STORAGE_RAID) |
1da177e4 LT |
2044 | scc_s = "RAID"; |
2045 | else | |
2046 | scc_s = "unknown"; | |
2047 | ||
a9524a76 JG |
2048 | dev_printk(KERN_INFO, &pdev->dev, |
2049 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 | 2050 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
2dcb407e | 2051 | , |
1da177e4 | 2052 | |
2dcb407e JG |
2053 | (vers >> 24) & 0xff, |
2054 | (vers >> 16) & 0xff, | |
2055 | (vers >> 8) & 0xff, | |
2056 | vers & 0xff, | |
1da177e4 LT |
2057 | |
2058 | ((cap >> 8) & 0x1f) + 1, | |
2059 | (cap & 0x1f) + 1, | |
2060 | speed_s, | |
2061 | impl, | |
2062 | scc_s); | |
2063 | ||
a9524a76 JG |
2064 | dev_printk(KERN_INFO, &pdev->dev, |
2065 | "flags: " | |
203ef6c4 TH |
2066 | "%s%s%s%s%s%s%s" |
2067 | "%s%s%s%s%s%s%s\n" | |
2dcb407e | 2068 | , |
1da177e4 LT |
2069 | |
2070 | cap & (1 << 31) ? "64bit " : "", | |
2071 | cap & (1 << 30) ? "ncq " : "", | |
203ef6c4 | 2072 | cap & (1 << 29) ? "sntf " : "", |
1da177e4 LT |
2073 | cap & (1 << 28) ? "ilck " : "", |
2074 | cap & (1 << 27) ? "stag " : "", | |
2075 | cap & (1 << 26) ? "pm " : "", | |
2076 | cap & (1 << 25) ? "led " : "", | |
2077 | ||
2078 | cap & (1 << 24) ? "clo " : "", | |
2079 | cap & (1 << 19) ? "nz " : "", | |
2080 | cap & (1 << 18) ? "only " : "", | |
2081 | cap & (1 << 17) ? "pmp " : "", | |
2082 | cap & (1 << 15) ? "pio " : "", | |
2083 | cap & (1 << 14) ? "slum " : "", | |
2084 | cap & (1 << 13) ? "part " : "" | |
2085 | ); | |
2086 | } | |
2087 | ||
edc93052 TH |
2088 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
2089 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
2090 | * support PMP and the 4726 either directly exports the device | |
2091 | * attached to the first downstream port or acts as a hardware storage | |
2092 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
2093 | * other configuration). | |
2094 | * | |
2095 | * When there's no device attached to the first downstream port of the | |
2096 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
2097 | * configure the 4726. However, ATA emulation of the device is very | |
2098 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
2099 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
2100 | * | |
2101 | * The following function works around the problem by always using | |
2102 | * hardreset on the port and not depending on receiving signature FIS | |
2103 | * afterward. If signature FIS isn't received soon, ATA class is | |
2104 | * assumed without follow-up softreset. | |
2105 | */ | |
2106 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
2107 | { | |
2108 | static struct dmi_system_id sysids[] = { | |
2109 | { | |
2110 | .ident = "P5W DH Deluxe", | |
2111 | .matches = { | |
2112 | DMI_MATCH(DMI_SYS_VENDOR, | |
2113 | "ASUSTEK COMPUTER INC"), | |
2114 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
2115 | }, | |
2116 | }, | |
2117 | { } | |
2118 | }; | |
2119 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
2120 | ||
2121 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
2122 | dmi_check_system(sysids)) { | |
2123 | struct ata_port *ap = host->ports[1]; | |
2124 | ||
2125 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " | |
2126 | "Deluxe on-board SIMG4726 workaround\n"); | |
2127 | ||
2128 | ap->ops = &ahci_p5wdh_ops; | |
2129 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
2130 | } | |
2131 | } | |
2132 | ||
24dc5f33 | 2133 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
2134 | { |
2135 | static int printed_version; | |
4447d351 TH |
2136 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
2137 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
24dc5f33 | 2138 | struct device *dev = &pdev->dev; |
1da177e4 | 2139 | struct ahci_host_priv *hpriv; |
4447d351 | 2140 | struct ata_host *host; |
837f5f8f | 2141 | int n_ports, i, rc; |
1da177e4 LT |
2142 | |
2143 | VPRINTK("ENTER\n"); | |
2144 | ||
12fad3f9 TH |
2145 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
2146 | ||
1da177e4 | 2147 | if (!printed_version++) |
a9524a76 | 2148 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 2149 | |
4447d351 | 2150 | /* acquire resources */ |
24dc5f33 | 2151 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
2152 | if (rc) |
2153 | return rc; | |
2154 | ||
dea55137 TH |
2155 | /* AHCI controllers often implement SFF compatible interface. |
2156 | * Grab all PCI BARs just in case. | |
2157 | */ | |
2158 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
0d5ff566 | 2159 | if (rc == -EBUSY) |
24dc5f33 | 2160 | pcim_pin_device(pdev); |
0d5ff566 | 2161 | if (rc) |
24dc5f33 | 2162 | return rc; |
1da177e4 | 2163 | |
c4f7792c TH |
2164 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
2165 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
2166 | u8 map; | |
2167 | ||
2168 | /* ICH6s share the same PCI ID for both piix and ahci | |
2169 | * modes. Enabling ahci mode while MAP indicates | |
2170 | * combined mode is a bad idea. Yield to ata_piix. | |
2171 | */ | |
2172 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
2173 | if (map & 0x3) { | |
2174 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " | |
2175 | "combined mode, can't enable AHCI mode\n"); | |
2176 | return -ENODEV; | |
2177 | } | |
2178 | } | |
2179 | ||
24dc5f33 TH |
2180 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
2181 | if (!hpriv) | |
2182 | return -ENOMEM; | |
417a1a6d TH |
2183 | hpriv->flags |= (unsigned long)pi.private_data; |
2184 | ||
2185 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) | |
2186 | pci_intx(pdev, 1); | |
1da177e4 | 2187 | |
4447d351 | 2188 | /* save initial config */ |
417a1a6d | 2189 | ahci_save_initial_config(pdev, hpriv); |
1da177e4 | 2190 | |
4447d351 | 2191 | /* prepare host */ |
274c1fde | 2192 | if (hpriv->cap & HOST_CAP_NCQ) |
4447d351 | 2193 | pi.flags |= ATA_FLAG_NCQ; |
1da177e4 | 2194 | |
7d50b60b TH |
2195 | if (hpriv->cap & HOST_CAP_PMP) |
2196 | pi.flags |= ATA_FLAG_PMP; | |
2197 | ||
837f5f8f TH |
2198 | /* CAP.NP sometimes indicate the index of the last enabled |
2199 | * port, at other times, that of the last possible port, so | |
2200 | * determining the maximum port number requires looking at | |
2201 | * both CAP.NP and port_map. | |
2202 | */ | |
2203 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
2204 | ||
2205 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
2206 | if (!host) |
2207 | return -ENOMEM; | |
2208 | host->iomap = pcim_iomap_table(pdev); | |
2209 | host->private_data = hpriv; | |
2210 | ||
2211 | for (i = 0; i < host->n_ports; i++) { | |
dab632e8 | 2212 | struct ata_port *ap = host->ports[i]; |
4447d351 | 2213 | |
cbcdd875 TH |
2214 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
2215 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
2216 | 0x100 + ap->port_no * 0x80, "port"); | |
2217 | ||
31556594 KCA |
2218 | /* set initial link pm policy */ |
2219 | ap->pm_policy = NOT_AVAILABLE; | |
2220 | ||
dab632e8 | 2221 | /* disabled/not-implemented port */ |
350756f6 | 2222 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 2223 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 2224 | } |
d447df14 | 2225 | |
edc93052 TH |
2226 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
2227 | ahci_p5wdh_workaround(host); | |
2228 | ||
4447d351 TH |
2229 | /* initialize adapter */ |
2230 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 2231 | if (rc) |
24dc5f33 | 2232 | return rc; |
1da177e4 | 2233 | |
4447d351 TH |
2234 | rc = ahci_reset_controller(host); |
2235 | if (rc) | |
2236 | return rc; | |
1da177e4 | 2237 | |
4447d351 TH |
2238 | ahci_init_controller(host); |
2239 | ahci_print_info(host); | |
1da177e4 | 2240 | |
4447d351 TH |
2241 | pci_set_master(pdev); |
2242 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
2243 | &ahci_sht); | |
907f4678 | 2244 | } |
1da177e4 LT |
2245 | |
2246 | static int __init ahci_init(void) | |
2247 | { | |
b7887196 | 2248 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
2249 | } |
2250 | ||
1da177e4 LT |
2251 | static void __exit ahci_exit(void) |
2252 | { | |
2253 | pci_unregister_driver(&ahci_pci_driver); | |
2254 | } | |
2255 | ||
2256 | ||
2257 | MODULE_AUTHOR("Jeff Garzik"); | |
2258 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
2259 | MODULE_LICENSE("GPL"); | |
2260 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 2261 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
2262 | |
2263 | module_init(ahci_init); | |
2264 | module_exit(ahci_exit); |