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Revert "AHCI: Optimize single IRQ interrupt processing"
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
67809f85 63 board_ahci_noncq,
441577ef 64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
cb85696d
JL		 86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
438ac6d5 90#ifdef CONFIG_PM
c1332875
TH		 91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 93#endif
ad616ffb 94
fad16e7a
TH		 95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
029cfd6b
TH		 99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
a1efdaba 101 .hardreset = ahci_vt8251_hardreset,
029cfd6b 102};
edc93052 103
029cfd6b
TH		 104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
a1efdaba 106 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 107};
108
98ac62de 109static const struct ata_port_info ahci_port_info[] = {
441577ef 110 /* by features */
facb8fa6 111 [board_ahci] = {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
facb8fa6 117 [board_ahci_ign_iferr] = {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
67809f85
LK		 124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
facb8fa6 131 [board_ahci_nosntf] = {
441577ef 132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 133 .flags = AHCI_FLAG_COMMON,
14bdef98 134 .pio_mask = ATA_PIO4,
469248ab 135 .udma_mask = ATA_UDMA6,
41669553
TH		 136 .port_ops = &ahci_ops,
137 },
facb8fa6 138 [board_ahci_yes_fbs] = {
5f173107
TH		 139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
441577ef 145 /* by chipsets */
facb8fa6 146 [board_ahci_mcp65] = {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
ae01b249 149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_mcp77] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
facb8fa6 161 [board_ahci_mcp89] = {
83f2b963 162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 163 .flags = AHCI_FLAG_COMMON,
14bdef98 164 .pio_mask = ATA_PIO4,
469248ab 165 .udma_mask = ATA_UDMA6,
441577ef 166 .port_ops = &ahci_ops,
55a61604 167 },
facb8fa6 168 [board_ahci_mv] = {
417a1a6d 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 172 .pio_mask = ATA_PIO4,
cd70c266
JG		 173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
facb8fa6 176 [board_ahci_sb600] = {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
facb8fa6 185 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
facb8fa6 192 [board_ahci_vt8251] = {
441577ef 193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_vt8251_ops,
1b677afd 198 },
1da177e4
LT		 199};
200
3b7d697d 201static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 202 /* Intel */
54bb3a94
JG		 203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 308 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
309 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
310 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
311 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
315 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
fe7fa31a 316
e34bb370
TH		 317 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
318 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
319 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 320 /* JMicron 362B and 362C have an AHCI function with IDE class code */
321 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
322 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 323
324 /* ATI */
c65ec1c2 325 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 326 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
331 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 332
e2dd90b1 333 /* AMD */
5deab536 334 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 335 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 336 /* AMD is using RAID class only for ahci controllers */
337 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
338 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
339
fe7fa31a 340 /* VIA */
54bb3a94 341 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 342 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 343
344 /* NVIDIA */
e297d99e
TH		 345 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 353 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
417 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
428 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 429
95916edd 430 /* SiS */
20e2de4a
TH		 431 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
432 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
433 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 434
318893e1
AR		 435 /* ST Microelectronics */
436 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
437
cd70c266
JG		 438 /* Marvell */
439 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 440 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 442 .class = PCI_CLASS_STORAGE_SATA_AHCI,
443 .class_mask = 0xffffff,
5f173107 444 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 446 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 447 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
448 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
449 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 451 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 452 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 453 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
454 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 455 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 457 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
459 .driver_data = board_ahci_yes_fbs },
69fd3157 460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 461 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 462 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
463 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 464 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
465 .driver_data = board_ahci_yes_fbs },
cd70c266 466
c77a036b
MN		 467 /* Promise */
468 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 469 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 470
c9703765 471 /* Asmedia */
7b4f6eca
AC		 472 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
473 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
474 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
475 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 476
67809f85
LK		 477 /*
478 * Samsung SSDs found on some macbooks. NCQ times out.
479 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
480 */
481 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
482
7f9c9f8e
HD		 483 /* Enmotus */
484 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
485
415ae2b5
JG		 486 /* Generic, PCI class code for AHCI */
487 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 488 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 489
1da177e4
LT		 490 { } /* terminate list */
491};
492
493
494static struct pci_driver ahci_pci_driver = {
495 .name = DRV_NAME,
496 .id_table = ahci_pci_tbl,
497 .probe = ahci_init_one,
24dc5f33 498 .remove = ata_pci_remove_one,
438ac6d5 499#ifdef CONFIG_PM
c1332875 500 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 501 .resume = ahci_pci_device_resume,
502#endif
503};
1da177e4 504
365cfa1e
AV		 505#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
506static int marvell_enable;
507#else
508static int marvell_enable = 1;
509#endif
510module_param(marvell_enable, int, 0644);
511MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 512
1da177e4 513
365cfa1e
AV		 514static void ahci_pci_save_initial_config(struct pci_dev *pdev,
515 struct ahci_host_priv *hpriv)
516{
517 unsigned int force_port_map = 0;
518 unsigned int mask_port_map = 0;
67846b30 519
365cfa1e
AV		 520 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
521 dev_info(&pdev->dev, "JMB361 has only one port\n");
522 force_port_map = 1;
1da177e4
LT		 523 }
524
365cfa1e
AV		 525 /*
526 * Temporary Marvell 6145 hack: PATA port presence
527 * is asserted through the standard AHCI port
528 * presence register, as bit 4 (counting from 0)
d28f87aa 529 */
365cfa1e
AV		 530 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
531 if (pdev->device == 0x6121)
532 mask_port_map = 0x3;
533 else
534 mask_port_map = 0xf;
535 dev_info(&pdev->dev,
536 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
537 }
1da177e4 538
725c7b57 539 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 540}
541
365cfa1e 542static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 543{
365cfa1e 544 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 545
365cfa1e 546 ahci_reset_controller(host);
1da177e4 547
365cfa1e
AV		 548 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
549 struct ahci_host_priv *hpriv = host->private_data;
550 u16 tmp16;
d6ef3153 551
365cfa1e
AV		 552 /* configure PCS */
553 pci_read_config_word(pdev, 0x92, &tmp16);
554 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
555 tmp16 |= hpriv->port_map;
556 pci_write_config_word(pdev, 0x92, tmp16);
557 }
d6ef3153
SH		 558 }
559
1da177e4
LT		 560 return 0;
561}
562
365cfa1e 563static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 564{
365cfa1e
AV		 565 struct ahci_host_priv *hpriv = host->private_data;
566 struct pci_dev *pdev = to_pci_dev(host->dev);
567 void __iomem *port_mmio;
78cd52d0 568 u32 tmp;
365cfa1e 569 int mv;
78cd52d0 570
365cfa1e
AV		 571 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
572 if (pdev->device == 0x6121)
573 mv = 2;
574 else
575 mv = 4;
576 port_mmio = __ahci_port_base(host, mv);
78cd52d0 577
365cfa1e 578 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 579
365cfa1e
AV		 580 /* clear port IRQ */
581 tmp = readl(port_mmio + PORT_IRQ_STAT);
582 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
583 if (tmp)
584 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 585 }
586
365cfa1e 587 ahci_init_controller(host);
edc93052
TH		 588}
589
365cfa1e
AV		 590static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline)
d6ef3153 592{
365cfa1e 593 struct ata_port *ap = link->ap;
039ece38 594 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 595 bool online;
d6ef3153
SH		 596 int rc;
597
365cfa1e 598 DPRINTK("ENTER\n");
d6ef3153 599
365cfa1e 600 ahci_stop_engine(ap);
d6ef3153 601
365cfa1e
AV		 602 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
603 deadline, &online, NULL);
d6ef3153 604
039ece38 605 hpriv->start_engine(ap);
d6ef3153 606
365cfa1e 607 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 608
365cfa1e
AV		 609 /* vt8251 doesn't clear BSY on signature FIS reception,
610 * request follow-up softreset.
611 */
612 return online ? -EAGAIN : rc;
7d50b60b
TH		 613}
614
365cfa1e
AV		 615static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline)
7d50b60b 617{
365cfa1e 618 struct ata_port *ap = link->ap;
1c954a4d 619 struct ahci_port_priv *pp = ap->private_data;
039ece38 620 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 621 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
622 struct ata_taskfile tf;
623 bool online;
624 int rc;
7d50b60b 625
365cfa1e 626 ahci_stop_engine(ap);
028a2596 627
365cfa1e
AV		 628 /* clear D2H reception area to properly wait for D2H FIS */
629 ata_tf_init(link->device, &tf);
9bbb1b0e 630 tf.command = ATA_BUSY;
365cfa1e 631 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 632
365cfa1e
AV		 633 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
634 deadline, &online, NULL);
028a2596 635
039ece38 636 hpriv->start_engine(ap);
c1332875 637
365cfa1e
AV		 638 /* The pseudo configuration device on SIMG4726 attached to
639 * ASUS P5W-DH Deluxe doesn't send signature FIS after
640 * hardreset if no device is attached to the first downstream
641 * port && the pseudo device locks up on SRST w/ PMP==0. To
642 * work around this, wait for !BSY only briefly. If BSY isn't
643 * cleared, perform CLO and proceed to IDENTIFY (achieved by
644 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
645 *
646 * Wait for two seconds. Devices attached to downstream port
647 * which can't process the following IDENTIFY after this will
648 * have to be reset again. For most cases, this should
649 * suffice while making probing snappish enough.
650 */
651 if (online) {
652 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
653 ahci_check_ready);
654 if (rc)
655 ahci_kick_engine(ap);
c1332875 656 }
c1332875
TH		 657 return rc;
658}
659
365cfa1e 660#ifdef CONFIG_PM
c1332875
TH		 661static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
662{
0a86e1c8 663 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 664 struct ahci_host_priv *hpriv = host->private_data;
d8993349 665 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 666 u32 ctl;
667
9b10ae86
TH		 668 if (mesg.event & PM_EVENT_SUSPEND &&
669 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 670 dev_err(&pdev->dev,
671 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 672 return -EIO;
673 }
674
3a2d5b70 675 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 676 /* AHCI spec rev1.1 section 8.3.3:
677 * Software must disable interrupts prior to requesting a
678 * transition of the HBA to D3 state.
679 */
680 ctl = readl(mmio + HOST_CTL);
681 ctl &= ~HOST_IRQ_EN;
682 writel(ctl, mmio + HOST_CTL);
683 readl(mmio + HOST_CTL); /* flush */
684 }
685
686 return ata_pci_device_suspend(pdev, mesg);
687}
688
689static int ahci_pci_device_resume(struct pci_dev *pdev)
690{
0a86e1c8 691 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 692 int rc;
693
553c4aa6
TH		 694 rc = ata_pci_device_do_resume(pdev);
695 if (rc)
696 return rc;
c1332875 697
cb85696d
JL		 698 /* Apple BIOS helpfully mangles the registers on resume */
699 if (is_mcp89_apple(pdev))
700 ahci_mcp89_apple_enable(pdev);
701
c1332875 702 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 703 rc = ahci_pci_reset_controller(host);
c1332875
TH		 704 if (rc)
705 return rc;
706
781d6550 707 ahci_pci_init_controller(host);
c1332875
TH		 708 }
709
cca3974e 710 ata_host_resume(host);
c1332875
TH		 711
712 return 0;
713}
438ac6d5 714#endif
c1332875 715
4447d351 716static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 717{
1da177e4 718 int rc;
1da177e4 719
318893e1
AR		 720 /*
721 * If the device fixup already set the dma_mask to some non-standard
722 * value, don't extend it here. This happens on STA2X11, for example.
723 */
724 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
725 return 0;
726
1da177e4 727 if (using_dac &&
6a35528a
YH		 728 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
729 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 730 if (rc) {
284901a9 731 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 732 if (rc) {
a44fec1f
JP		 733 dev_err(&pdev->dev,
734 "64-bit DMA enable failed\n");
1da177e4
LT		 735 return rc;
736 }
737 }
1da177e4 738 } else {
284901a9 739 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 740 if (rc) {
a44fec1f 741 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 742 return rc;
743 }
284901a9 744 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 745 if (rc) {
a44fec1f
JP		 746 dev_err(&pdev->dev,
747 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 748 return rc;
749 }
750 }
1da177e4
LT		 751 return 0;
752}
753
439fcaec
AV		 754static void ahci_pci_print_info(struct ata_host *host)
755{
756 struct pci_dev *pdev = to_pci_dev(host->dev);
757 u16 cc;
758 const char *scc_s;
759
760 pci_read_config_word(pdev, 0x0a, &cc);
761 if (cc == PCI_CLASS_STORAGE_IDE)
762 scc_s = "IDE";
763 else if (cc == PCI_CLASS_STORAGE_SATA)
764 scc_s = "SATA";
765 else if (cc == PCI_CLASS_STORAGE_RAID)
766 scc_s = "RAID";
767 else
768 scc_s = "unknown";
769
770 ahci_print_info(host, scc_s);
771}
772
edc93052
TH		 773/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
774 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
775 * support PMP and the 4726 either directly exports the device
776 * attached to the first downstream port or acts as a hardware storage
777 * controller and emulate a single ATA device (can be RAID 0/1 or some
778 * other configuration).
779 *
780 * When there's no device attached to the first downstream port of the
781 * 4726, "Config Disk" appears, which is a pseudo ATA device to
782 * configure the 4726. However, ATA emulation of the device is very
783 * lame. It doesn't send signature D2H Reg FIS after the initial
784 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
785 *
786 * The following function works around the problem by always using
787 * hardreset on the port and not depending on receiving signature FIS
788 * afterward. If signature FIS isn't received soon, ATA class is
789 * assumed without follow-up softreset.
790 */
791static void ahci_p5wdh_workaround(struct ata_host *host)
792{
1bd06867 793 static const struct dmi_system_id sysids[] = {
edc93052
TH		 794 {
795 .ident = "P5W DH Deluxe",
796 .matches = {
797 DMI_MATCH(DMI_SYS_VENDOR,
798 "ASUSTEK COMPUTER INC"),
799 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
800 },
801 },
802 { }
803 };
804 struct pci_dev *pdev = to_pci_dev(host->dev);
805
806 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
807 dmi_check_system(sysids)) {
808 struct ata_port *ap = host->ports[1];
809
a44fec1f
JP		 810 dev_info(&pdev->dev,
811 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 812
813 ap->ops = &ahci_p5wdh_ops;
814 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
815 }
816}
817
cb85696d
JL		 818/*
819 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
820 * booting in BIOS compatibility mode. We restore the registers but not ID.
821 */
822static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
823{
824 u32 val;
825
826 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
827
828 pci_read_config_dword(pdev, 0xf8, &val);
829 val |= 1 << 0x1b;
830 /* the following changes the device ID, but appears not to affect function */
831 /* val = (val & ~0xf0000000) | 0x80000000; */
832 pci_write_config_dword(pdev, 0xf8, val);
833
834 pci_read_config_dword(pdev, 0x54c, &val);
835 val |= 1 << 0xc;
836 pci_write_config_dword(pdev, 0x54c, val);
837
838 pci_read_config_dword(pdev, 0x4a4, &val);
839 val &= 0xff;
840 val |= 0x01060100;
841 pci_write_config_dword(pdev, 0x4a4, val);
842
843 pci_read_config_dword(pdev, 0x54c, &val);
844 val &= ~(1 << 0xc);
845 pci_write_config_dword(pdev, 0x54c, val);
846
847 pci_read_config_dword(pdev, 0xf8, &val);
848 val &= ~(1 << 0x1b);
849 pci_write_config_dword(pdev, 0xf8, val);
850}
851
852static bool is_mcp89_apple(struct pci_dev *pdev)
853{
854 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
855 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
856 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
857 pdev->subsystem_device == 0xcb89;
858}
859
2fcad9d2
TH		 860/* only some SB600 ahci controllers can do 64bit DMA */
861static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 862{
863 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 864 /*
865 * The oldest version known to be broken is 0901 and
866 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 867 * Enable 64bit DMA on 1501 and anything newer.
868 *
03d783bf
TH		 869 * Please read bko#9412 for more info.
870 */
58a09b38
SH		 871 {
872 .ident = "ASUS M2A-VM",
873 .matches = {
874 DMI_MATCH(DMI_BOARD_VENDOR,
875 "ASUSTeK Computer INC."),
876 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
877 },
03d783bf 878 .driver_data = "20071026", /* yyyymmdd */
58a09b38 879 },
e65cc194
MN		 880 /*
881 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
882 * support 64bit DMA.
883 *
884 * BIOS versions earlier than 1.5 had the Manufacturer DMI
885 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
886 * This spelling mistake was fixed in BIOS version 1.5, so
887 * 1.5 and later have the Manufacturer as
888 * "MICRO-STAR INTERNATIONAL CO.,LTD".
889 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
890 *
891 * BIOS versions earlier than 1.9 had a Board Product Name
892 * DMI field of "MS-7376". This was changed to be
893 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
894 * match on DMI_BOARD_NAME of "MS-7376".
895 */
896 {
897 .ident = "MSI K9A2 Platinum",
898 .matches = {
899 DMI_MATCH(DMI_BOARD_VENDOR,
900 "MICRO-STAR INTER"),
901 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
902 },
903 },
ff0173c1
MN		 904 /*
905 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
906 * 64bit DMA.
907 *
908 * This board also had the typo mentioned above in the
909 * Manufacturer DMI field (fixed in BIOS version 1.5), so
910 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
911 */
912 {
913 .ident = "MSI K9AGM2",
914 .matches = {
915 DMI_MATCH(DMI_BOARD_VENDOR,
916 "MICRO-STAR INTER"),
917 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
918 },
919 },
3c4aa91f
MN		 920 /*
921 * All BIOS versions for the Asus M3A support 64bit DMA.
922 * (all release versions from 0301 to 1206 were tested)
923 */
924 {
925 .ident = "ASUS M3A",
926 .matches = {
927 DMI_MATCH(DMI_BOARD_VENDOR,
928 "ASUSTeK Computer INC."),
929 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
930 },
931 },
58a09b38
SH		 932 { }
933 };
03d783bf 934 const struct dmi_system_id *match;
2fcad9d2
TH		 935 int year, month, date;
936 char buf[9];
58a09b38 937
03d783bf 938 match = dmi_first_match(sysids);
58a09b38 939 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 940 !match)
58a09b38
SH		 941 return false;
942
e65cc194
MN		 943 if (!match->driver_data)
944 goto enable_64bit;
945
2fcad9d2
TH		 946 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
947 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 948
e65cc194
MN		 949 if (strcmp(buf, match->driver_data) >= 0)
950 goto enable_64bit;
951 else {
a44fec1f
JP		 952 dev_warn(&pdev->dev,
953 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
954 match->ident);
2fcad9d2
TH		 955 return false;
956 }
e65cc194
MN		 957
958enable_64bit:
a44fec1f 959 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 960 return true;
58a09b38
SH		 961}
962
1fd68434
RW		 963static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
964{
965 static const struct dmi_system_id broken_systems[] = {
966 {
967 .ident = "HP Compaq nx6310",
968 .matches = {
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
971 },
972 /* PCI slot number of the controller */
973 .driver_data = (void *)0x1FUL,
974 },
d2f9c061
MR		 975 {
976 .ident = "HP Compaq 6720s",
977 .matches = {
978 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
979 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
980 },
981 /* PCI slot number of the controller */
982 .driver_data = (void *)0x1FUL,
983 },
1fd68434
RW		 984
985 { } /* terminate list */
986 };
987 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
988
989 if (dmi) {
990 unsigned long slot = (unsigned long)dmi->driver_data;
991 /* apply the quirk only to on-board controllers */
992 return slot == PCI_SLOT(pdev->devfn);
993 }
994
995 return false;
996}
997
9b10ae86
TH		 998static bool ahci_broken_suspend(struct pci_dev *pdev)
999{
1000 static const struct dmi_system_id sysids[] = {
1001 /*
1002 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1003 * to the harddisk doesn't become online after
1004 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1005 *
1006 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1007 *
1008 * Use dates instead of versions to match as HP is
1009 * apparently recycling both product and version
1010 * strings.
1011 *
1012 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1013 */
1014 {
1015 .ident = "dv4",
1016 .matches = {
1017 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1018 DMI_MATCH(DMI_PRODUCT_NAME,
1019 "HP Pavilion dv4 Notebook PC"),
1020 },
9deb3431 1021 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1022 },
1023 {
1024 .ident = "dv5",
1025 .matches = {
1026 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1027 DMI_MATCH(DMI_PRODUCT_NAME,
1028 "HP Pavilion dv5 Notebook PC"),
1029 },
9deb3431 1030 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1031 },
1032 {
1033 .ident = "dv6",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1036 DMI_MATCH(DMI_PRODUCT_NAME,
1037 "HP Pavilion dv6 Notebook PC"),
1038 },
9deb3431 1039 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1040 },
1041 {
1042 .ident = "HDX18",
1043 .matches = {
1044 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1045 DMI_MATCH(DMI_PRODUCT_NAME,
1046 "HP HDX18 Notebook PC"),
1047 },
9deb3431 1048 .driver_data = "20090430", /* F.23 */
9b10ae86 1049 },
cedc9bf9
TH		 1050 /*
1051 * Acer eMachines G725 has the same problem. BIOS
1052 * V1.03 is known to be broken. V3.04 is known to
25985edc 1053 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1054 * that we don't have much idea about. For now,
1055 * blacklist anything older than V3.04.
9deb3431
TH		 1056 *
1057 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1058 */
1059 {
1060 .ident = "G725",
1061 .matches = {
1062 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1064 },
9deb3431 1065 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1066 },
9b10ae86
TH		 1067 { } /* terminate list */
1068 };
1069 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1070 int year, month, date;
1071 char buf[9];
9b10ae86
TH		 1072
1073 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1074 return false;
1075
9deb3431
TH		 1076 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1077 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1078
9deb3431 1079 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1080}
1081
5594639a
TH		 1082static bool ahci_broken_online(struct pci_dev *pdev)
1083{
1084#define ENCODE_BUSDEVFN(bus, slot, func) \
1085 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1086 static const struct dmi_system_id sysids[] = {
1087 /*
1088 * There are several gigabyte boards which use
1089 * SIMG5723s configured as hardware RAID. Certain
1090 * 5723 firmware revisions shipped there keep the link
1091 * online but fail to answer properly to SRST or
1092 * IDENTIFY when no device is attached downstream
1093 * causing libata to retry quite a few times leading
1094 * to excessive detection delay.
1095 *
1096 * As these firmwares respond to the second reset try
1097 * with invalid device signature, considering unknown
1098 * sig as offline works around the problem acceptably.
1099 */
1100 {
1101 .ident = "EP45-DQ6",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "Gigabyte Technology Co., Ltd."),
1105 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1106 },
1107 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1108 },
1109 {
1110 .ident = "EP45-DS5",
1111 .matches = {
1112 DMI_MATCH(DMI_BOARD_VENDOR,
1113 "Gigabyte Technology Co., Ltd."),
1114 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1115 },
1116 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1117 },
1118 { } /* terminate list */
1119 };
1120#undef ENCODE_BUSDEVFN
1121 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1122 unsigned int val;
1123
1124 if (!dmi)
1125 return false;
1126
1127 val = (unsigned long)dmi->driver_data;
1128
1129 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1130}
1131
0cf4a7d6
JP		 1132static bool ahci_broken_devslp(struct pci_dev *pdev)
1133{
1134 /* device with broken DEVSLP but still showing SDS capability */
1135 static const struct pci_device_id ids[] = {
1136 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1137 {}
1138 };
1139
1140 return pci_match_id(ids, pdev);
1141}
1142
8e513217 1143#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1144static void ahci_gtf_filter_workaround(struct ata_host *host)
1145{
1146 static const struct dmi_system_id sysids[] = {
1147 /*
1148 * Aspire 3810T issues a bunch of SATA enable commands
1149 * via _GTF including an invalid one and one which is
1150 * rejected by the device. Among the successful ones
1151 * is FPDMA non-zero offset enable which when enabled
1152 * only on the drive side leads to NCQ command
1153 * failures. Filter it out.
1154 */
1155 {
1156 .ident = "Aspire 3810T",
1157 .matches = {
1158 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1159 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1160 },
1161 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1162 },
1163 { }
1164 };
1165 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1166 unsigned int filter;
1167 int i;
1168
1169 if (!dmi)
1170 return;
1171
1172 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1173 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1174 filter, dmi->ident);
f80ae7e4
TH		 1175
1176 for (i = 0; i < host->n_ports; i++) {
1177 struct ata_port *ap = host->ports[i];
1178 struct ata_link *link;
1179 struct ata_device *dev;
1180
1181 ata_for_each_link(link, ap, EDGE)
1182 ata_for_each_dev(dev, link, ALL)
1183 dev->gtf_filter |= filter;
1184 }
1185}
8e513217
MT		 1186#else
1187static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1188{}
1189#endif
f80ae7e4 1190
e1ba8459 1191static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1192 struct ahci_host_priv *hpriv)
5ca72c4f 1193{
ccf8f53c 1194 int rc, nvec;
5ca72c4f 1195
7b92b4f6
AG		 1196 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1197 goto intx;
1198
fc061d96
AG		 1199 nvec = pci_msi_vec_count(pdev);
1200 if (nvec < 0)
7b92b4f6
AG		 1201 goto intx;
1202
1203 /*
1204 * If number of MSIs is less than number of ports then Sharing Last
1205 * Message mode could be enforced. In this case assume that advantage
1206 * of multipe MSIs is negated and use single MSI mode instead.
1207 */
fc061d96 1208 if (nvec < n_ports)
7b92b4f6
AG		 1209 goto single_msi;
1210
ccf8f53c
AG		 1211 rc = pci_enable_msi_exact(pdev, nvec);
1212 if (rc == -ENOSPC)
fc40363b 1213 goto single_msi;
ccf8f53c 1214 else if (rc < 0)
fc061d96 1215 goto intx;
5ca72c4f 1216
ab0f9e78
AG		 1217 /* fallback to single MSI mode if the controller enforced MRSM mode */
1218 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1219 pci_disable_msi(pdev);
1220 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1221 goto single_msi;
1222 }
1223
c3ebd6a9
AG		 1224 if (nvec > 1)
1225 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1226
7b92b4f6
AG		 1227 return nvec;
1228
1229single_msi:
fc061d96 1230 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1231 goto intx;
1232 return 1;
1233
1234intx:
5ca72c4f
AG		 1235 pci_intx(pdev, 1);
1236 return 0;
1237}
1238
24dc5f33 1239static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1240{
e297d99e
TH		 1241 unsigned int board_id = ent->driver_data;
1242 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1243 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1244 struct device *dev = &pdev->dev;
1da177e4 1245 struct ahci_host_priv *hpriv;
4447d351 1246 struct ata_host *host;
c3ebd6a9 1247 int n_ports, i, rc;
318893e1 1248 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1249
1250 VPRINTK("ENTER\n");
1251
b429dd59 1252 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1253
06296a1e 1254 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1255
5b66c829
AC		 1256 /* The AHCI driver can only drive the SATA ports, the PATA driver
1257 can drive them all so if both drivers are selected make sure
1258 AHCI stays out of the way */
1259 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1260 return -ENODEV;
1261
cb85696d
JL		 1262 /* Apple BIOS on MCP89 prevents us using AHCI */
1263 if (is_mcp89_apple(pdev))
1264 ahci_mcp89_apple_enable(pdev);
c6353b45 1265
7a02267e
MN		 1266 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1267 * At the moment, we can only use the AHCI mode. Let the users know
1268 * that for SAS drives they're out of luck.
1269 */
1270 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1271 dev_info(&pdev->dev,
1272 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1273
7f9c9f8e 1274 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1275 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1276 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1277 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1278 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1279
e6b7e41c
CL		 1280 /*
1281 * The JMicron chip 361/363 contains one SATA controller and one
1282 * PATA controller,for powering on these both controllers, we must
1283 * follow the sequence one by one, otherwise one of them can not be
1284 * powered on successfully, so here we disable the async suspend
1285 * method for these chips.
1286 */
1287 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1288 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1289 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1290 device_disable_async_suspend(&pdev->dev);
1291
4447d351 1292 /* acquire resources */
24dc5f33 1293 rc = pcim_enable_device(pdev);
1da177e4
LT		 1294 if (rc)
1295 return rc;
1296
c4f7792c
TH		 1297 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1298 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1299 u8 map;
1300
1301 /* ICH6s share the same PCI ID for both piix and ahci
1302 * modes. Enabling ahci mode while MAP indicates
1303 * combined mode is a bad idea. Yield to ata_piix.
1304 */
1305 pci_read_config_byte(pdev, ICH_MAP, &map);
1306 if (map & 0x3) {
a44fec1f
JP		 1307 dev_info(&pdev->dev,
1308 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1309 return -ENODEV;
1310 }
1311 }
1312
6fec8871
PB		 1313 /* AHCI controllers often implement SFF compatible interface.
1314 * Grab all PCI BARs just in case.
1315 */
1316 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1317 if (rc == -EBUSY)
1318 pcim_pin_device(pdev);
1319 if (rc)
1320 return rc;
1321
24dc5f33
TH		 1322 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1323 if (!hpriv)
1324 return -ENOMEM;
417a1a6d
TH		 1325 hpriv->flags |= (unsigned long)pi.private_data;
1326
e297d99e
TH		 1327 /* MCP65 revision A1 and A2 can't do MSI */
1328 if (board_id == board_ahci_mcp65 &&
1329 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1330 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1331
e427fe04
SH		 1332 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1333 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1334 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1335
2fcad9d2
TH		 1336 /* only some SB600s can do 64bit DMA */
1337 if (ahci_sb600_enable_64bit(pdev))
1338 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1339
318893e1 1340 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1341
0cf4a7d6
JP		 1342 /* must set flag prior to save config in order to take effect */
1343 if (ahci_broken_devslp(pdev))
1344 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1345
4447d351 1346 /* save initial config */
394d6e53 1347 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1348
4447d351 1349 /* prepare host */
453d3131
RH		 1350 if (hpriv->cap & HOST_CAP_NCQ) {
1351 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1352 /*
1353 * Auto-activate optimization is supposed to be
1354 * supported on all AHCI controllers indicating NCQ
1355 * capability, but it seems to be broken on some
1356 * chipsets including NVIDIAs.
1357 */
1358 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1359 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1360
1361 /*
1362 * All AHCI controllers should be forward-compatible
1363 * with the new auxiliary field. This code should be
1364 * conditionalized if any buggy AHCI controllers are
1365 * encountered.
1366 */
1367 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1368 }
1da177e4 1369
7d50b60b
TH		 1370 if (hpriv->cap & HOST_CAP_PMP)
1371 pi.flags |= ATA_FLAG_PMP;
1372
0cbb0e77 1373 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1374
1fd68434
RW		 1375 if (ahci_broken_system_poweroff(pdev)) {
1376 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1377 dev_info(&pdev->dev,
1378 "quirky BIOS, skipping spindown on poweroff\n");
1379 }
1380
9b10ae86
TH		 1381 if (ahci_broken_suspend(pdev)) {
1382 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1383 dev_warn(&pdev->dev,
1384 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1385 }
1386
5594639a
TH		 1387 if (ahci_broken_online(pdev)) {
1388 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1389 dev_info(&pdev->dev,
1390 "online status unreliable, applying workaround\n");
1391 }
1392
837f5f8f
TH		 1393 /* CAP.NP sometimes indicate the index of the last enabled
1394 * port, at other times, that of the last possible port, so
1395 * determining the maximum port number requires looking at
1396 * both CAP.NP and port_map.
1397 */
1398 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1399
c3ebd6a9 1400 ahci_init_interrupts(pdev, n_ports, hpriv);
7b92b4f6 1401
837f5f8f 1402 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1403 if (!host)
1404 return -ENOMEM;
4447d351
TH		 1405 host->private_data = hpriv;
1406
f3d7f23f 1407 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1408 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1409 else
d2782d96 1410 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1411
18f7ba4c
KCA		 1412 if (pi.flags & ATA_FLAG_EM)
1413 ahci_reset_em(host);
1414
4447d351 1415 for (i = 0; i < host->n_ports; i++) {
dab632e8 1416 struct ata_port *ap = host->ports[i];
4447d351 1417
318893e1
AR		 1418 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1419 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1420 0x100 + ap->port_no * 0x80, "port");
1421
18f7ba4c
KCA		 1422 /* set enclosure management message type */
1423 if (ap->flags & ATA_FLAG_EM)
008dbd61 1424 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1425
1426
dab632e8 1427 /* disabled/not-implemented port */
350756f6 1428 if (!(hpriv->port_map & (1 << i)))
dab632e8 1429 ap->ops = &ata_dummy_port_ops;
4447d351 1430 }
d447df14 1431
edc93052
TH		 1432 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1433 ahci_p5wdh_workaround(host);
1434
f80ae7e4
TH		 1435 /* apply gtf filter quirk */
1436 ahci_gtf_filter_workaround(host);
1437
4447d351
TH		 1438 /* initialize adapter */
1439 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1440 if (rc)
24dc5f33 1441 return rc;
1da177e4 1442
3303040d 1443 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1444 if (rc)
1445 return rc;
1da177e4 1446
781d6550 1447 ahci_pci_init_controller(host);
439fcaec 1448 ahci_pci_print_info(host);
1da177e4 1449
4447d351 1450 pci_set_master(pdev);
5ca72c4f 1451
d1028e2f 1452 return ahci_host_activate(host, pdev->irq, &ahci_sht);
907f4678 1453}
1da177e4 1454
2fc75da0 1455module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1456
1457MODULE_AUTHOR("Jeff Garzik");
1458MODULE_DESCRIPTION("AHCI SATA low-level driver");
1459MODULE_LICENSE("GPL");
1460MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1461MODULE_VERSION(DRV_VERSION);
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