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[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 82static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
438ac6d5 86#ifdef CONFIG_PM
c1332875
TH		 87static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 89#endif
ad616ffb 90
fad16e7a
TH		 91static struct scsi_host_template ahci_sht = {
92 AHCI_SHT("ahci"),
93};
94
029cfd6b
TH		 95static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
a1efdaba 97 .hardreset = ahci_vt8251_hardreset,
029cfd6b 98};
edc93052 99
029cfd6b
TH		 100static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 103};
104
417a1a6d
TH		 105#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
4da646b7 109 [board_ahci] =
1da177e4 110 {
1188c0d8 111 .flags = AHCI_FLAG_COMMON,
14bdef98 112 .pio_mask = ATA_PIO4,
469248ab 113 .udma_mask = ATA_UDMA6,
1da177e4
LT		 114 .port_ops = &ahci_ops,
115 },
441577ef 116 [board_ahci_ign_iferr] =
bf2af2a2 117 {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
441577ef 124 [board_ahci_nosntf] =
41669553 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
41669553
TH		 130 .port_ops = &ahci_ops,
131 },
5f173107
TH		 132 [board_ahci_yes_fbs] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
441577ef
TH		 140 /* by chipsets */
141 [board_ahci_mcp65] =
55a61604 142 {
83f2b963
TH		 143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
144 AHCI_HFLAG_YES_NCQ),
ae01b249 145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_mcp77] =
151 {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp89] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 161 .flags = AHCI_FLAG_COMMON,
14bdef98 162 .pio_mask = ATA_PIO4,
469248ab 163 .udma_mask = ATA_UDMA6,
441577ef 164 .port_ops = &ahci_ops,
55a61604 165 },
4da646b7 166 [board_ahci_mv] =
cd70c266 167 {
417a1a6d 168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 171 .pio_mask = ATA_PIO4,
cd70c266
JG		 172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
441577ef 175 [board_ahci_sb600] =
e39fc8c9 176 {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
441577ef 185 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 186 {
441577ef 187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 192 },
441577ef 193 [board_ahci_vt8251] =
1b677afd 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_vt8251_ops,
1b677afd 200 },
1da177e4
LT		 201};
202
3b7d697d 203static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 204 /* Intel */
54bb3a94
JG		 205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 262 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
fe7fa31a 263
e34bb370
TH		 264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 267
268 /* ATI */
c65ec1c2 269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 276
e2dd90b1 277 /* AMD */
5deab536 278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
fe7fa31a 283 /* VIA */
54bb3a94 284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 286
287 /* NVIDIA */
e297d99e
TH		 288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 372
95916edd 373 /* SiS */
20e2de4a
TH		 374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 377
cd70c266
JG		 378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 381 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
5f173107 384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 385 { PCI_DEVICE(0x1b4b, 0x9125),
386 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 387 { PCI_DEVICE(0x1b4b, 0x91a3),
388 .driver_data = board_ahci_yes_fbs },
cd70c266 389
c77a036b
MN		 390 /* Promise */
391 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392
415ae2b5
JG		 393 /* Generic, PCI class code for AHCI */
394 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 395 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 396
1da177e4
LT		 397 { } /* terminate list */
398};
399
400
401static struct pci_driver ahci_pci_driver = {
402 .name = DRV_NAME,
403 .id_table = ahci_pci_tbl,
404 .probe = ahci_init_one,
24dc5f33 405 .remove = ata_pci_remove_one,
438ac6d5 406#ifdef CONFIG_PM
c1332875 407 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 408 .resume = ahci_pci_device_resume,
409#endif
410};
1da177e4 411
365cfa1e
AV		 412#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
413static int marvell_enable;
414#else
415static int marvell_enable = 1;
416#endif
417module_param(marvell_enable, int, 0644);
418MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 419
1da177e4 420
365cfa1e
AV		 421static void ahci_pci_save_initial_config(struct pci_dev *pdev,
422 struct ahci_host_priv *hpriv)
423{
424 unsigned int force_port_map = 0;
425 unsigned int mask_port_map = 0;
67846b30 426
365cfa1e
AV		 427 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
428 dev_info(&pdev->dev, "JMB361 has only one port\n");
429 force_port_map = 1;
1da177e4
LT		 430 }
431
365cfa1e
AV		 432 /*
433 * Temporary Marvell 6145 hack: PATA port presence
434 * is asserted through the standard AHCI port
435 * presence register, as bit 4 (counting from 0)
d28f87aa 436 */
365cfa1e
AV		 437 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
438 if (pdev->device == 0x6121)
439 mask_port_map = 0x3;
440 else
441 mask_port_map = 0xf;
442 dev_info(&pdev->dev,
443 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
444 }
1da177e4 445
365cfa1e
AV		 446 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
447 mask_port_map);
1da177e4
LT		 448}
449
365cfa1e 450static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 451{
365cfa1e 452 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 453
365cfa1e 454 ahci_reset_controller(host);
1da177e4 455
365cfa1e
AV		 456 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
457 struct ahci_host_priv *hpriv = host->private_data;
458 u16 tmp16;
d6ef3153 459
365cfa1e
AV		 460 /* configure PCS */
461 pci_read_config_word(pdev, 0x92, &tmp16);
462 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
463 tmp16 |= hpriv->port_map;
464 pci_write_config_word(pdev, 0x92, tmp16);
465 }
d6ef3153
SH		 466 }
467
1da177e4
LT		 468 return 0;
469}
470
365cfa1e 471static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 472{
365cfa1e
AV		 473 struct ahci_host_priv *hpriv = host->private_data;
474 struct pci_dev *pdev = to_pci_dev(host->dev);
475 void __iomem *port_mmio;
78cd52d0 476 u32 tmp;
365cfa1e 477 int mv;
78cd52d0 478
365cfa1e
AV		 479 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
480 if (pdev->device == 0x6121)
481 mv = 2;
482 else
483 mv = 4;
484 port_mmio = __ahci_port_base(host, mv);
78cd52d0 485
365cfa1e 486 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 487
365cfa1e
AV		 488 /* clear port IRQ */
489 tmp = readl(port_mmio + PORT_IRQ_STAT);
490 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 if (tmp)
492 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 493 }
494
365cfa1e 495 ahci_init_controller(host);
edc93052
TH		 496}
497
365cfa1e
AV		 498static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
499 unsigned long deadline)
d6ef3153 500{
365cfa1e
AV		 501 struct ata_port *ap = link->ap;
502 bool online;
d6ef3153
SH		 503 int rc;
504
365cfa1e 505 DPRINTK("ENTER\n");
d6ef3153 506
365cfa1e 507 ahci_stop_engine(ap);
d6ef3153 508
365cfa1e
AV		 509 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
510 deadline, &online, NULL);
d6ef3153
SH		 511
512 ahci_start_engine(ap);
d6ef3153 513
365cfa1e 514 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 515
365cfa1e
AV		 516 /* vt8251 doesn't clear BSY on signature FIS reception,
517 * request follow-up softreset.
518 */
519 return online ? -EAGAIN : rc;
7d50b60b
TH		 520}
521
365cfa1e
AV		 522static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
523 unsigned long deadline)
7d50b60b 524{
365cfa1e 525 struct ata_port *ap = link->ap;
1c954a4d 526 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 527 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
528 struct ata_taskfile tf;
529 bool online;
530 int rc;
7d50b60b 531
365cfa1e 532 ahci_stop_engine(ap);
028a2596 533
365cfa1e
AV		 534 /* clear D2H reception area to properly wait for D2H FIS */
535 ata_tf_init(link->device, &tf);
536 tf.command = 0x80;
537 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 538
365cfa1e
AV		 539 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
540 deadline, &online, NULL);
028a2596 541
365cfa1e 542 ahci_start_engine(ap);
c1332875 543
365cfa1e
AV		 544 /* The pseudo configuration device on SIMG4726 attached to
545 * ASUS P5W-DH Deluxe doesn't send signature FIS after
546 * hardreset if no device is attached to the first downstream
547 * port && the pseudo device locks up on SRST w/ PMP==0. To
548 * work around this, wait for !BSY only briefly. If BSY isn't
549 * cleared, perform CLO and proceed to IDENTIFY (achieved by
550 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
551 *
552 * Wait for two seconds. Devices attached to downstream port
553 * which can't process the following IDENTIFY after this will
554 * have to be reset again. For most cases, this should
555 * suffice while making probing snappish enough.
556 */
557 if (online) {
558 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
559 ahci_check_ready);
560 if (rc)
561 ahci_kick_engine(ap);
c1332875 562 }
c1332875
TH		 563 return rc;
564}
565
365cfa1e 566#ifdef CONFIG_PM
c1332875
TH		 567static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
568{
cca3974e 569 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 570 struct ahci_host_priv *hpriv = host->private_data;
d8993349 571 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 572 u32 ctl;
573
9b10ae86
TH		 574 if (mesg.event & PM_EVENT_SUSPEND &&
575 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 576 dev_err(&pdev->dev,
577 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 578 return -EIO;
579 }
580
3a2d5b70 581 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 582 /* AHCI spec rev1.1 section 8.3.3:
583 * Software must disable interrupts prior to requesting a
584 * transition of the HBA to D3 state.
585 */
586 ctl = readl(mmio + HOST_CTL);
587 ctl &= ~HOST_IRQ_EN;
588 writel(ctl, mmio + HOST_CTL);
589 readl(mmio + HOST_CTL); /* flush */
590 }
591
592 return ata_pci_device_suspend(pdev, mesg);
593}
594
595static int ahci_pci_device_resume(struct pci_dev *pdev)
596{
cca3974e 597 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 598 int rc;
599
553c4aa6
TH		 600 rc = ata_pci_device_do_resume(pdev);
601 if (rc)
602 return rc;
c1332875
TH		 603
604 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 605 rc = ahci_pci_reset_controller(host);
c1332875
TH		 606 if (rc)
607 return rc;
608
781d6550 609 ahci_pci_init_controller(host);
c1332875
TH		 610 }
611
cca3974e 612 ata_host_resume(host);
c1332875
TH		 613
614 return 0;
615}
438ac6d5 616#endif
c1332875 617
4447d351 618static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 619{
1da177e4 620 int rc;
1da177e4 621
1da177e4 622 if (using_dac &&
6a35528a
YH		 623 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
624 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 625 if (rc) {
284901a9 626 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 627 if (rc) {
a44fec1f
JP		 628 dev_err(&pdev->dev,
629 "64-bit DMA enable failed\n");
1da177e4
LT		 630 return rc;
631 }
632 }
1da177e4 633 } else {
284901a9 634 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 635 if (rc) {
a44fec1f 636 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 637 return rc;
638 }
284901a9 639 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 640 if (rc) {
a44fec1f
JP		 641 dev_err(&pdev->dev,
642 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 643 return rc;
644 }
645 }
1da177e4
LT		 646 return 0;
647}
648
439fcaec
AV		 649static void ahci_pci_print_info(struct ata_host *host)
650{
651 struct pci_dev *pdev = to_pci_dev(host->dev);
652 u16 cc;
653 const char *scc_s;
654
655 pci_read_config_word(pdev, 0x0a, &cc);
656 if (cc == PCI_CLASS_STORAGE_IDE)
657 scc_s = "IDE";
658 else if (cc == PCI_CLASS_STORAGE_SATA)
659 scc_s = "SATA";
660 else if (cc == PCI_CLASS_STORAGE_RAID)
661 scc_s = "RAID";
662 else
663 scc_s = "unknown";
664
665 ahci_print_info(host, scc_s);
666}
667
edc93052
TH		 668/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
669 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
670 * support PMP and the 4726 either directly exports the device
671 * attached to the first downstream port or acts as a hardware storage
672 * controller and emulate a single ATA device (can be RAID 0/1 or some
673 * other configuration).
674 *
675 * When there's no device attached to the first downstream port of the
676 * 4726, "Config Disk" appears, which is a pseudo ATA device to
677 * configure the 4726. However, ATA emulation of the device is very
678 * lame. It doesn't send signature D2H Reg FIS after the initial
679 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
680 *
681 * The following function works around the problem by always using
682 * hardreset on the port and not depending on receiving signature FIS
683 * afterward. If signature FIS isn't received soon, ATA class is
684 * assumed without follow-up softreset.
685 */
686static void ahci_p5wdh_workaround(struct ata_host *host)
687{
688 static struct dmi_system_id sysids[] = {
689 {
690 .ident = "P5W DH Deluxe",
691 .matches = {
692 DMI_MATCH(DMI_SYS_VENDOR,
693 "ASUSTEK COMPUTER INC"),
694 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
695 },
696 },
697 { }
698 };
699 struct pci_dev *pdev = to_pci_dev(host->dev);
700
701 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
702 dmi_check_system(sysids)) {
703 struct ata_port *ap = host->ports[1];
704
a44fec1f
JP		 705 dev_info(&pdev->dev,
706 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 707
708 ap->ops = &ahci_p5wdh_ops;
709 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
710 }
711}
712
2fcad9d2
TH		 713/* only some SB600 ahci controllers can do 64bit DMA */
714static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 715{
716 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 717 /*
718 * The oldest version known to be broken is 0901 and
719 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 720 * Enable 64bit DMA on 1501 and anything newer.
721 *
03d783bf
TH		 722 * Please read bko#9412 for more info.
723 */
58a09b38
SH		 724 {
725 .ident = "ASUS M2A-VM",
726 .matches = {
727 DMI_MATCH(DMI_BOARD_VENDOR,
728 "ASUSTeK Computer INC."),
729 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
730 },
03d783bf 731 .driver_data = "20071026", /* yyyymmdd */
58a09b38 732 },
e65cc194
MN		 733 /*
734 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
735 * support 64bit DMA.
736 *
737 * BIOS versions earlier than 1.5 had the Manufacturer DMI
738 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
739 * This spelling mistake was fixed in BIOS version 1.5, so
740 * 1.5 and later have the Manufacturer as
741 * "MICRO-STAR INTERNATIONAL CO.,LTD".
742 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
743 *
744 * BIOS versions earlier than 1.9 had a Board Product Name
745 * DMI field of "MS-7376". This was changed to be
746 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
747 * match on DMI_BOARD_NAME of "MS-7376".
748 */
749 {
750 .ident = "MSI K9A2 Platinum",
751 .matches = {
752 DMI_MATCH(DMI_BOARD_VENDOR,
753 "MICRO-STAR INTER"),
754 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
755 },
756 },
3c4aa91f
MN		 757 /*
758 * All BIOS versions for the Asus M3A support 64bit DMA.
759 * (all release versions from 0301 to 1206 were tested)
760 */
761 {
762 .ident = "ASUS M3A",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR,
765 "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
767 },
768 },
58a09b38
SH		 769 { }
770 };
03d783bf 771 const struct dmi_system_id *match;
2fcad9d2
TH		 772 int year, month, date;
773 char buf[9];
58a09b38 774
03d783bf 775 match = dmi_first_match(sysids);
58a09b38 776 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 777 !match)
58a09b38
SH		 778 return false;
779
e65cc194
MN		 780 if (!match->driver_data)
781 goto enable_64bit;
782
2fcad9d2
TH		 783 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
784 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 785
e65cc194
MN		 786 if (strcmp(buf, match->driver_data) >= 0)
787 goto enable_64bit;
788 else {
a44fec1f
JP		 789 dev_warn(&pdev->dev,
790 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
791 match->ident);
2fcad9d2
TH		 792 return false;
793 }
e65cc194
MN		 794
795enable_64bit:
a44fec1f 796 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 797 return true;
58a09b38
SH		 798}
799
1fd68434
RW		 800static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
801{
802 static const struct dmi_system_id broken_systems[] = {
803 {
804 .ident = "HP Compaq nx6310",
805 .matches = {
806 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
808 },
809 /* PCI slot number of the controller */
810 .driver_data = (void *)0x1FUL,
811 },
d2f9c061
MR		 812 {
813 .ident = "HP Compaq 6720s",
814 .matches = {
815 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
816 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
817 },
818 /* PCI slot number of the controller */
819 .driver_data = (void *)0x1FUL,
820 },
1fd68434
RW		 821
822 { } /* terminate list */
823 };
824 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
825
826 if (dmi) {
827 unsigned long slot = (unsigned long)dmi->driver_data;
828 /* apply the quirk only to on-board controllers */
829 return slot == PCI_SLOT(pdev->devfn);
830 }
831
832 return false;
833}
834
9b10ae86
TH		 835static bool ahci_broken_suspend(struct pci_dev *pdev)
836{
837 static const struct dmi_system_id sysids[] = {
838 /*
839 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
840 * to the harddisk doesn't become online after
841 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 842 *
843 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
844 *
845 * Use dates instead of versions to match as HP is
846 * apparently recycling both product and version
847 * strings.
848 *
849 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 850 */
851 {
852 .ident = "dv4",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
855 DMI_MATCH(DMI_PRODUCT_NAME,
856 "HP Pavilion dv4 Notebook PC"),
857 },
9deb3431 858 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 859 },
860 {
861 .ident = "dv5",
862 .matches = {
863 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
864 DMI_MATCH(DMI_PRODUCT_NAME,
865 "HP Pavilion dv5 Notebook PC"),
866 },
9deb3431 867 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 868 },
869 {
870 .ident = "dv6",
871 .matches = {
872 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
873 DMI_MATCH(DMI_PRODUCT_NAME,
874 "HP Pavilion dv6 Notebook PC"),
875 },
9deb3431 876 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 877 },
878 {
879 .ident = "HDX18",
880 .matches = {
881 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
882 DMI_MATCH(DMI_PRODUCT_NAME,
883 "HP HDX18 Notebook PC"),
884 },
9deb3431 885 .driver_data = "20090430", /* F.23 */
9b10ae86 886 },
cedc9bf9
TH		 887 /*
888 * Acer eMachines G725 has the same problem. BIOS
889 * V1.03 is known to be broken. V3.04 is known to
25985edc 890 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 891 * that we don't have much idea about. For now,
892 * blacklist anything older than V3.04.
9deb3431
TH		 893 *
894 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 895 */
896 {
897 .ident = "G725",
898 .matches = {
899 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
900 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
901 },
9deb3431 902 .driver_data = "20091216", /* V3.04 */
cedc9bf9 903 },
9b10ae86
TH		 904 { } /* terminate list */
905 };
906 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 907 int year, month, date;
908 char buf[9];
9b10ae86
TH		 909
910 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
911 return false;
912
9deb3431
TH		 913 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
914 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 915
9deb3431 916 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 917}
918
5594639a
TH		 919static bool ahci_broken_online(struct pci_dev *pdev)
920{
921#define ENCODE_BUSDEVFN(bus, slot, func) \
922 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
923 static const struct dmi_system_id sysids[] = {
924 /*
925 * There are several gigabyte boards which use
926 * SIMG5723s configured as hardware RAID. Certain
927 * 5723 firmware revisions shipped there keep the link
928 * online but fail to answer properly to SRST or
929 * IDENTIFY when no device is attached downstream
930 * causing libata to retry quite a few times leading
931 * to excessive detection delay.
932 *
933 * As these firmwares respond to the second reset try
934 * with invalid device signature, considering unknown
935 * sig as offline works around the problem acceptably.
936 */
937 {
938 .ident = "EP45-DQ6",
939 .matches = {
940 DMI_MATCH(DMI_BOARD_VENDOR,
941 "Gigabyte Technology Co., Ltd."),
942 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
943 },
944 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
945 },
946 {
947 .ident = "EP45-DS5",
948 .matches = {
949 DMI_MATCH(DMI_BOARD_VENDOR,
950 "Gigabyte Technology Co., Ltd."),
951 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
952 },
953 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
954 },
955 { } /* terminate list */
956 };
957#undef ENCODE_BUSDEVFN
958 const struct dmi_system_id *dmi = dmi_first_match(sysids);
959 unsigned int val;
960
961 if (!dmi)
962 return false;
963
964 val = (unsigned long)dmi->driver_data;
965
966 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
967}
968
8e513217 969#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 970static void ahci_gtf_filter_workaround(struct ata_host *host)
971{
972 static const struct dmi_system_id sysids[] = {
973 /*
974 * Aspire 3810T issues a bunch of SATA enable commands
975 * via _GTF including an invalid one and one which is
976 * rejected by the device. Among the successful ones
977 * is FPDMA non-zero offset enable which when enabled
978 * only on the drive side leads to NCQ command
979 * failures. Filter it out.
980 */
981 {
982 .ident = "Aspire 3810T",
983 .matches = {
984 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
986 },
987 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
988 },
989 { }
990 };
991 const struct dmi_system_id *dmi = dmi_first_match(sysids);
992 unsigned int filter;
993 int i;
994
995 if (!dmi)
996 return;
997
998 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 999 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1000 filter, dmi->ident);
f80ae7e4
TH		 1001
1002 for (i = 0; i < host->n_ports; i++) {
1003 struct ata_port *ap = host->ports[i];
1004 struct ata_link *link;
1005 struct ata_device *dev;
1006
1007 ata_for_each_link(link, ap, EDGE)
1008 ata_for_each_dev(dev, link, ALL)
1009 dev->gtf_filter |= filter;
1010 }
1011}
8e513217
MT		 1012#else
1013static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1014{}
1015#endif
f80ae7e4 1016
24dc5f33 1017static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1018{
e297d99e
TH		 1019 unsigned int board_id = ent->driver_data;
1020 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1021 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1022 struct device *dev = &pdev->dev;
1da177e4 1023 struct ahci_host_priv *hpriv;
4447d351 1024 struct ata_host *host;
837f5f8f 1025 int n_ports, i, rc;
1da177e4
LT		 1026
1027 VPRINTK("ENTER\n");
1028
b429dd59 1029 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1030
06296a1e 1031 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1032
5b66c829
AC		 1033 /* The AHCI driver can only drive the SATA ports, the PATA driver
1034 can drive them all so if both drivers are selected make sure
1035 AHCI stays out of the way */
1036 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1037 return -ENODEV;
1038
c6353b45
TH		 1039 /*
1040 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1041 * ahci, use ata_generic instead.
1042 */
1043 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1044 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1045 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1046 pdev->subsystem_device == 0xcb89)
1047 return -ENODEV;
1048
7a02267e
MN		 1049 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1050 * At the moment, we can only use the AHCI mode. Let the users know
1051 * that for SAS drives they're out of luck.
1052 */
1053 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1054 dev_info(&pdev->dev,
1055 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1056
4447d351 1057 /* acquire resources */
24dc5f33 1058 rc = pcim_enable_device(pdev);
1da177e4
LT		 1059 if (rc)
1060 return rc;
1061
dea55137
TH		 1062 /* AHCI controllers often implement SFF compatible interface.
1063 * Grab all PCI BARs just in case.
1064 */
1065 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1066 if (rc == -EBUSY)
24dc5f33 1067 pcim_pin_device(pdev);
0d5ff566 1068 if (rc)
24dc5f33 1069 return rc;
1da177e4 1070
c4f7792c
TH		 1071 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1072 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1073 u8 map;
1074
1075 /* ICH6s share the same PCI ID for both piix and ahci
1076 * modes. Enabling ahci mode while MAP indicates
1077 * combined mode is a bad idea. Yield to ata_piix.
1078 */
1079 pci_read_config_byte(pdev, ICH_MAP, &map);
1080 if (map & 0x3) {
a44fec1f
JP		 1081 dev_info(&pdev->dev,
1082 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1083 return -ENODEV;
1084 }
1085 }
1086
24dc5f33
TH		 1087 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1088 if (!hpriv)
1089 return -ENOMEM;
417a1a6d
TH		 1090 hpriv->flags |= (unsigned long)pi.private_data;
1091
e297d99e
TH		 1092 /* MCP65 revision A1 and A2 can't do MSI */
1093 if (board_id == board_ahci_mcp65 &&
1094 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1095 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1096
e427fe04
SH		 1097 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1098 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1099 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1100
2fcad9d2
TH		 1101 /* only some SB600s can do 64bit DMA */
1102 if (ahci_sb600_enable_64bit(pdev))
1103 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1104
31b239ad
TH		 1105 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1106 pci_intx(pdev, 1);
1da177e4 1107
d8993349
AV		 1108 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1109
4447d351 1110 /* save initial config */
394d6e53 1111 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1112
4447d351 1113 /* prepare host */
453d3131
RH		 1114 if (hpriv->cap & HOST_CAP_NCQ) {
1115 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1116 /*
1117 * Auto-activate optimization is supposed to be
1118 * supported on all AHCI controllers indicating NCQ
1119 * capability, but it seems to be broken on some
1120 * chipsets including NVIDIAs.
1121 */
1122 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1123 pi.flags |= ATA_FLAG_FPDMA_AA;
1124 }
1da177e4 1125
7d50b60b
TH		 1126 if (hpriv->cap & HOST_CAP_PMP)
1127 pi.flags |= ATA_FLAG_PMP;
1128
0cbb0e77 1129 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1130
1fd68434
RW		 1131 if (ahci_broken_system_poweroff(pdev)) {
1132 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1133 dev_info(&pdev->dev,
1134 "quirky BIOS, skipping spindown on poweroff\n");
1135 }
1136
9b10ae86
TH		 1137 if (ahci_broken_suspend(pdev)) {
1138 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1139 dev_warn(&pdev->dev,
1140 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1141 }
1142
5594639a
TH		 1143 if (ahci_broken_online(pdev)) {
1144 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1145 dev_info(&pdev->dev,
1146 "online status unreliable, applying workaround\n");
1147 }
1148
837f5f8f
TH		 1149 /* CAP.NP sometimes indicate the index of the last enabled
1150 * port, at other times, that of the last possible port, so
1151 * determining the maximum port number requires looking at
1152 * both CAP.NP and port_map.
1153 */
1154 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1155
1156 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1157 if (!host)
1158 return -ENOMEM;
4447d351
TH		 1159 host->private_data = hpriv;
1160
f3d7f23f 1161 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1162 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1163 else
1164 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1165
18f7ba4c
KCA		 1166 if (pi.flags & ATA_FLAG_EM)
1167 ahci_reset_em(host);
1168
4447d351 1169 for (i = 0; i < host->n_ports; i++) {
dab632e8 1170 struct ata_port *ap = host->ports[i];
4447d351 1171
cbcdd875
TH		 1172 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1173 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1174 0x100 + ap->port_no * 0x80, "port");
1175
18f7ba4c
KCA		 1176 /* set enclosure management message type */
1177 if (ap->flags & ATA_FLAG_EM)
008dbd61 1178 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1179
1180
dab632e8 1181 /* disabled/not-implemented port */
350756f6 1182 if (!(hpriv->port_map & (1 << i)))
dab632e8 1183 ap->ops = &ata_dummy_port_ops;
4447d351 1184 }
d447df14 1185
edc93052
TH		 1186 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1187 ahci_p5wdh_workaround(host);
1188
f80ae7e4
TH		 1189 /* apply gtf filter quirk */
1190 ahci_gtf_filter_workaround(host);
1191
4447d351
TH		 1192 /* initialize adapter */
1193 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1194 if (rc)
24dc5f33 1195 return rc;
1da177e4 1196
3303040d 1197 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1198 if (rc)
1199 return rc;
1da177e4 1200
781d6550 1201 ahci_pci_init_controller(host);
439fcaec 1202 ahci_pci_print_info(host);
1da177e4 1203
4447d351
TH		 1204 pci_set_master(pdev);
1205 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1206 &ahci_sht);
907f4678 1207}
1da177e4
LT		 1208
1209static int __init ahci_init(void)
1210{
b7887196 1211 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1212}
1213
1da177e4
LT		 1214static void __exit ahci_exit(void)
1215{
1216 pci_unregister_driver(&ahci_pci_driver);
1217}
1218
1219
1220MODULE_AUTHOR("Jeff Garzik");
1221MODULE_DESCRIPTION("AHCI SATA low-level driver");
1222MODULE_LICENSE("GPL");
1223MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1224MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1225
1226module_init(ahci_init);
1227module_exit(ahci_exit);
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