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ahci: implement PMP support
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
1da177e4 44#include <scsi/scsi_host.h>
193515d5 45#include <scsi/scsi_cmnd.h>
1da177e4 46#include <linux/libata.h>
1da177e4
LT		 47
48#define DRV_NAME "ahci"
7d50b60b 49#define DRV_VERSION "3.0"
1da177e4
LT		 50
51
52enum {
53 AHCI_PCI_BAR = 5,
648a88be 54 AHCI_MAX_PORTS = 32,
1da177e4
LT		 55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 57 AHCI_USE_CLUSTERING = 1,
12fad3f9 58 AHCI_MAX_CMDS = 32,
dd410ff1 59 AHCI_CMD_SZ = 32,
12fad3f9 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 61 AHCI_RX_FIS_SZ = 256,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
4b10e559 71 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
7a234aff
TH		 80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82 board_ahci_sb600 = 3,
83 board_ahci_mv = 4,
1da177e4
LT		 84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
0be0aa98 98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 99 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
78cd52d0
TH		 143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
4296971d 146 PORT_IRQ_PHYRDY |
7d50b60b
TH		 147 PORT_IRQ_UNK_FIS |
148 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
150 PORT_IRQ_TF_ERR |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 155
156 /* PORT_CMD bits */
02eaa666 157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 162 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
166
0be0aa98 167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 171
bf2af2a2 172 /* ap->flags bits */
4aeb0e32
TH		 173 AHCI_FLAG_NO_NCQ = (1 << 24),
174 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
55a61604 175 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
c7a42156 176 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
cd70c266
JG		 177 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
178 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
a7384925 179 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
1188c0d8
TH		 180
181 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
182 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2 183 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
0c88758b 184 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
1da177e4
LT		 185};
186
187struct ahci_cmd_hdr {
188 u32 opts;
189 u32 status;
190 u32 tbl_addr;
191 u32 tbl_addr_hi;
192 u32 reserved[4];
193};
194
195struct ahci_sg {
196 u32 addr;
197 u32 addr_hi;
198 u32 reserved;
199 u32 flags_size;
200};
201
202struct ahci_host_priv {
d447df14
TH		 203 u32 cap; /* cap to use */
204 u32 port_map; /* port map to use */
205 u32 saved_cap; /* saved initial cap */
206 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 207};
208
209struct ahci_port_priv {
7d50b60b 210 struct ata_link *active_link;
1da177e4
LT		 211 struct ahci_cmd_hdr *cmd_slot;
212 dma_addr_t cmd_slot_dma;
213 void *cmd_tbl;
214 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 215 void *rx_fis;
216 dma_addr_t rx_fis_dma;
0291f95f 217 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 218 unsigned int ncq_saw_d2h:1;
219 unsigned int ncq_saw_dmas:1;
afb2d552 220 unsigned int ncq_saw_sdb:1;
a7384925 221 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 222};
223
da3dbb17
TH		 224static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
225static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4 226static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 227static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 228static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 229static int ahci_port_start(struct ata_port *ap);
230static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 231static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
232static void ahci_qc_prep(struct ata_queued_cmd *qc);
233static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 234static void ahci_freeze(struct ata_port *ap);
235static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 236static void ahci_pmp_attach(struct ata_port *ap);
237static void ahci_pmp_detach(struct ata_port *ap);
238static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
239static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
78cd52d0 240static void ahci_error_handler(struct ata_port *ap);
ad616ffb 241static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 242static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 243static int ahci_port_resume(struct ata_port *ap);
dab632e8
JG		 244static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
245static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
246 u32 opts);
438ac6d5 247#ifdef CONFIG_PM
c1332875 248static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 249static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
250static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 251#endif
1da177e4 252
193515d5 253static struct scsi_host_template ahci_sht = {
1da177e4
LT		 254 .module = THIS_MODULE,
255 .name = DRV_NAME,
256 .ioctl = ata_scsi_ioctl,
257 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 258 .change_queue_depth = ata_scsi_change_queue_depth,
259 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 260 .this_id = ATA_SHT_THIS_ID,
261 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 262 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
263 .emulated = ATA_SHT_EMULATED,
264 .use_clustering = AHCI_USE_CLUSTERING,
265 .proc_name = DRV_NAME,
266 .dma_boundary = AHCI_DMA_BOUNDARY,
267 .slave_configure = ata_scsi_slave_config,
ccf68c34 268 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 269 .bios_param = ata_std_bios_param,
1da177e4
LT		 270};
271
057ace5e 272static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 273 .check_status = ahci_check_status,
274 .check_altstatus = ahci_check_status,
1da177e4
LT		 275 .dev_select = ata_noop_dev_select,
276
277 .tf_read = ahci_tf_read,
278
7d50b60b 279 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 280 .qc_prep = ahci_qc_prep,
281 .qc_issue = ahci_qc_issue,
282
1da177e4
LT		 283 .irq_clear = ahci_irq_clear,
284
285 .scr_read = ahci_scr_read,
286 .scr_write = ahci_scr_write,
287
78cd52d0
TH		 288 .freeze = ahci_freeze,
289 .thaw = ahci_thaw,
290
291 .error_handler = ahci_error_handler,
292 .post_internal_cmd = ahci_post_internal_cmd,
293
7d50b60b
TH		 294 .pmp_attach = ahci_pmp_attach,
295 .pmp_detach = ahci_pmp_detach,
296 .pmp_read = ahci_pmp_read,
297 .pmp_write = ahci_pmp_write,
298
438ac6d5 299#ifdef CONFIG_PM
c1332875
TH		 300 .port_suspend = ahci_port_suspend,
301 .port_resume = ahci_port_resume,
438ac6d5 302#endif
c1332875 303
1da177e4
LT		 304 .port_start = ahci_port_start,
305 .port_stop = ahci_port_stop,
1da177e4
LT		 306};
307
ad616ffb 308static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 309 .check_status = ahci_check_status,
310 .check_altstatus = ahci_check_status,
311 .dev_select = ata_noop_dev_select,
312
313 .tf_read = ahci_tf_read,
314
7d50b60b 315 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 316 .qc_prep = ahci_qc_prep,
317 .qc_issue = ahci_qc_issue,
318
ad616ffb
TH		 319 .irq_clear = ahci_irq_clear,
320
321 .scr_read = ahci_scr_read,
322 .scr_write = ahci_scr_write,
323
324 .freeze = ahci_freeze,
325 .thaw = ahci_thaw,
326
327 .error_handler = ahci_vt8251_error_handler,
328 .post_internal_cmd = ahci_post_internal_cmd,
329
7d50b60b
TH		 330 .pmp_attach = ahci_pmp_attach,
331 .pmp_detach = ahci_pmp_detach,
332 .pmp_read = ahci_pmp_read,
333 .pmp_write = ahci_pmp_write,
334
438ac6d5 335#ifdef CONFIG_PM
ad616ffb
TH		 336 .port_suspend = ahci_port_suspend,
337 .port_resume = ahci_port_resume,
438ac6d5 338#endif
ad616ffb
TH		 339
340 .port_start = ahci_port_start,
341 .port_stop = ahci_port_stop,
342};
343
98ac62de 344static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 345 /* board_ahci */
346 {
1188c0d8 347 .flags = AHCI_FLAG_COMMON,
0c88758b 348 .link_flags = AHCI_LFLAG_COMMON,
7da79312 349 .pio_mask = 0x1f, /* pio0-4 */
469248ab 350 .udma_mask = ATA_UDMA6,
1da177e4
LT		 351 .port_ops = &ahci_ops,
352 },
bf2af2a2
BJ		 353 /* board_ahci_vt8251 */
354 {
0c88758b
TH		 355 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
356 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
bf2af2a2 357 .pio_mask = 0x1f, /* pio0-4 */
469248ab 358 .udma_mask = ATA_UDMA6,
ad616ffb 359 .port_ops = &ahci_vt8251_ops,
bf2af2a2 360 },
41669553
TH		 361 /* board_ahci_ign_iferr */
362 {
1188c0d8 363 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
0c88758b 364 .link_flags = AHCI_LFLAG_COMMON,
41669553 365 .pio_mask = 0x1f, /* pio0-4 */
469248ab 366 .udma_mask = ATA_UDMA6,
41669553
TH		 367 .port_ops = &ahci_ops,
368 },
55a61604
CH		 369 /* board_ahci_sb600 */
370 {
1188c0d8 371 .flags = AHCI_FLAG_COMMON |
c7a42156
TH		 372 AHCI_FLAG_IGN_SERR_INTERNAL |
373 AHCI_FLAG_32BIT_ONLY,
0c88758b 374 .link_flags = AHCI_LFLAG_COMMON,
55a61604 375 .pio_mask = 0x1f, /* pio0-4 */
469248ab 376 .udma_mask = ATA_UDMA6,
55a61604
CH		 377 .port_ops = &ahci_ops,
378 },
cd70c266
JG		 379 /* board_ahci_mv */
380 {
381 .sht = &ahci_sht,
382 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
383 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
7a234aff
TH		 384 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
385 AHCI_FLAG_MV_PATA,
0c88758b 386 .link_flags = AHCI_LFLAG_COMMON,
cd70c266
JG		 387 .pio_mask = 0x1f, /* pio0-4 */
388 .udma_mask = ATA_UDMA6,
389 .port_ops = &ahci_ops,
390 },
1da177e4
LT		 391};
392
3b7d697d 393static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 394 /* Intel */
54bb3a94
JG		 395 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
396 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
397 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
398 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
399 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 400 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 401 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
402 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
403 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
404 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 405 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
406 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
407 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
408 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
409 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
410 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
414 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
415 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
416 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
417 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
419 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 422 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
423 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
fe7fa31a 424
e34bb370
TH		 425 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
426 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
427 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 428
429 /* ATI */
c65ec1c2 430 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
c69c0892 431 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
fe7fa31a
JG		 437
438 /* VIA */
54bb3a94 439 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 440 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 441
442 /* NVIDIA */
54bb3a94
JG		 443 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 447 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 455 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 463 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
fe7fa31a 487
95916edd 488 /* SiS */
54bb3a94
JG		 489 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
490 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
491 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 492
cd70c266
JG		 493 /* Marvell */
494 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
495
415ae2b5
JG		 496 /* Generic, PCI class code for AHCI */
497 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 498 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 499
1da177e4
LT		 500 { } /* terminate list */
501};
502
503
504static struct pci_driver ahci_pci_driver = {
505 .name = DRV_NAME,
506 .id_table = ahci_pci_tbl,
507 .probe = ahci_init_one,
24dc5f33 508 .remove = ata_pci_remove_one,
438ac6d5 509#ifdef CONFIG_PM
c1332875
TH		 510 .suspend = ahci_pci_device_suspend,
511 .resume = ahci_pci_device_resume,
438ac6d5 512#endif
1da177e4
LT		 513};
514
515
98fa4b60
TH		 516static inline int ahci_nr_ports(u32 cap)
517{
518 return (cap & 0x1f) + 1;
519}
520
dab632e8
JG		 521static inline void __iomem *__ahci_port_base(struct ata_host *host,
522 unsigned int port_no)
1da177e4 523{
dab632e8 524 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 525
dab632e8
JG		 526 return mmio + 0x100 + (port_no * 0x80);
527}
528
529static inline void __iomem *ahci_port_base(struct ata_port *ap)
530{
531 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 532}
533
d447df14
TH		 534/**
535 * ahci_save_initial_config - Save and fixup initial config values
4447d351
TH		 536 * @pdev: target PCI device
537 * @pi: associated ATA port info
538 * @hpriv: host private area to store config values
d447df14
TH		 539 *
540 * Some registers containing configuration info might be setup by
541 * BIOS and might be cleared on reset. This function saves the
542 * initial values of those registers into @hpriv such that they
543 * can be restored after controller reset.
544 *
545 * If inconsistent, config values are fixed up by this function.
546 *
547 * LOCKING:
548 * None.
549 */
4447d351
TH		 550static void ahci_save_initial_config(struct pci_dev *pdev,
551 const struct ata_port_info *pi,
552 struct ahci_host_priv *hpriv)
d447df14 553{
4447d351 554 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 555 u32 cap, port_map;
17199b18 556 int i;
d447df14
TH		 557
558 /* Values prefixed with saved_ are written back to host after
559 * reset. Values without are used for driver operation.
560 */
561 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
562 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
563
274c1fde 564 /* some chips have errata preventing 64bit use */
c7a42156
TH		 565 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
566 dev_printk(KERN_INFO, &pdev->dev,
567 "controller can't do 64bit DMA, forcing 32bit\n");
568 cap &= ~HOST_CAP_64;
569 }
570
274c1fde
TH		 571 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
572 dev_printk(KERN_INFO, &pdev->dev,
573 "controller can't do NCQ, turning off CAP_NCQ\n");
574 cap &= ~HOST_CAP_NCQ;
575 }
576
cd70c266
JG		 577 /*
578 * Temporary Marvell 6145 hack: PATA port presence
579 * is asserted through the standard AHCI port
580 * presence register, as bit 4 (counting from 0)
581 */
582 if (pi->flags & AHCI_FLAG_MV_PATA) {
583 dev_printk(KERN_ERR, &pdev->dev,
584 "MV_AHCI HACK: port_map %x -> %x\n",
585 hpriv->port_map,
586 hpriv->port_map & 0xf);
587
588 port_map &= 0xf;
589 }
590
17199b18 591 /* cross check port_map and cap.n_ports */
7a234aff 592 if (port_map) {
17199b18
TH		 593 u32 tmp_port_map = port_map;
594 int n_ports = ahci_nr_ports(cap);
595
596 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
597 if (tmp_port_map & (1 << i)) {
598 n_ports--;
599 tmp_port_map &= ~(1 << i);
600 }
601 }
602
7a234aff
TH		 603 /* If n_ports and port_map are inconsistent, whine and
604 * clear port_map and let it be generated from n_ports.
17199b18 605 */
7a234aff 606 if (n_ports || tmp_port_map) {
4447d351 607 dev_printk(KERN_WARNING, &pdev->dev,
17199b18 608 "nr_ports (%u) and implemented port map "
7a234aff 609 "(0x%x) don't match, using nr_ports\n",
17199b18 610 ahci_nr_ports(cap), port_map);
7a234aff
TH		 611 port_map = 0;
612 }
613 }
614
615 /* fabricate port_map from cap.nr_ports */
616 if (!port_map) {
17199b18 617 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 618 dev_printk(KERN_WARNING, &pdev->dev,
619 "forcing PORTS_IMPL to 0x%x\n", port_map);
620
621 /* write the fixed up value to the PI register */
622 hpriv->saved_port_map = port_map;
17199b18
TH		 623 }
624
d447df14
TH		 625 /* record values to use during operation */
626 hpriv->cap = cap;
627 hpriv->port_map = port_map;
628}
629
630/**
631 * ahci_restore_initial_config - Restore initial config
4447d351 632 * @host: target ATA host
d447df14
TH		 633 *
634 * Restore initial config stored by ahci_save_initial_config().
635 *
636 * LOCKING:
637 * None.
638 */
4447d351 639static void ahci_restore_initial_config(struct ata_host *host)
d447df14 640{
4447d351
TH		 641 struct ahci_host_priv *hpriv = host->private_data;
642 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
643
d447df14
TH		 644 writel(hpriv->saved_cap, mmio + HOST_CAP);
645 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
646 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
647}
648
203ef6c4 649static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 650{
203ef6c4
TH		 651 static const int offset[] = {
652 [SCR_STATUS] = PORT_SCR_STAT,
653 [SCR_CONTROL] = PORT_SCR_CTL,
654 [SCR_ERROR] = PORT_SCR_ERR,
655 [SCR_ACTIVE] = PORT_SCR_ACT,
656 [SCR_NOTIFICATION] = PORT_SCR_NTF,
657 };
658 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 659
203ef6c4
TH		 660 if (sc_reg < ARRAY_SIZE(offset) &&
661 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
662 return offset[sc_reg];
da3dbb17 663 return 0;
1da177e4
LT		 664}
665
203ef6c4 666static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 667{
203ef6c4
TH		 668 void __iomem *port_mmio = ahci_port_base(ap);
669 int offset = ahci_scr_offset(ap, sc_reg);
670
671 if (offset) {
672 *val = readl(port_mmio + offset);
673 return 0;
1da177e4 674 }
203ef6c4
TH		 675 return -EINVAL;
676}
1da177e4 677
203ef6c4
TH		 678static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
679{
680 void __iomem *port_mmio = ahci_port_base(ap);
681 int offset = ahci_scr_offset(ap, sc_reg);
682
683 if (offset) {
684 writel(val, port_mmio + offset);
685 return 0;
686 }
687 return -EINVAL;
1da177e4
LT		 688}
689
4447d351 690static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 691{
4447d351 692 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 693 u32 tmp;
694
d8fcd116 695 /* start DMA */
9f592056 696 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 697 tmp |= PORT_CMD_START;
698 writel(tmp, port_mmio + PORT_CMD);
699 readl(port_mmio + PORT_CMD); /* flush */
700}
701
4447d351 702static int ahci_stop_engine(struct ata_port *ap)
254950cd 703{
4447d351 704 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 705 u32 tmp;
706
707 tmp = readl(port_mmio + PORT_CMD);
708
d8fcd116 709 /* check if the HBA is idle */
254950cd
TH		 710 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
711 return 0;
712
d8fcd116 713 /* setting HBA to idle */
254950cd
TH		 714 tmp &= ~PORT_CMD_START;
715 writel(tmp, port_mmio + PORT_CMD);
716
d8fcd116 717 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 718 tmp = ata_wait_register(port_mmio + PORT_CMD,
719 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 720 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 721 return -EIO;
722
723 return 0;
724}
725
4447d351 726static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 727{
4447d351
TH		 728 void __iomem *port_mmio = ahci_port_base(ap);
729 struct ahci_host_priv *hpriv = ap->host->private_data;
730 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 731 u32 tmp;
732
733 /* set FIS registers */
4447d351
TH		 734 if (hpriv->cap & HOST_CAP_64)
735 writel((pp->cmd_slot_dma >> 16) >> 16,
736 port_mmio + PORT_LST_ADDR_HI);
737 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 738
4447d351
TH		 739 if (hpriv->cap & HOST_CAP_64)
740 writel((pp->rx_fis_dma >> 16) >> 16,
741 port_mmio + PORT_FIS_ADDR_HI);
742 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 743
744 /* enable FIS reception */
745 tmp = readl(port_mmio + PORT_CMD);
746 tmp |= PORT_CMD_FIS_RX;
747 writel(tmp, port_mmio + PORT_CMD);
748
749 /* flush */
750 readl(port_mmio + PORT_CMD);
751}
752
4447d351 753static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 754{
4447d351 755 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 756 u32 tmp;
757
758 /* disable FIS reception */
759 tmp = readl(port_mmio + PORT_CMD);
760 tmp &= ~PORT_CMD_FIS_RX;
761 writel(tmp, port_mmio + PORT_CMD);
762
763 /* wait for completion, spec says 500ms, give it 1000 */
764 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
765 PORT_CMD_FIS_ON, 10, 1000);
766 if (tmp & PORT_CMD_FIS_ON)
767 return -EBUSY;
768
769 return 0;
770}
771
4447d351 772static void ahci_power_up(struct ata_port *ap)
0be0aa98 773{
4447d351
TH		 774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 776 u32 cmd;
777
778 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
779
780 /* spin up device */
4447d351 781 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 782 cmd |= PORT_CMD_SPIN_UP;
783 writel(cmd, port_mmio + PORT_CMD);
784 }
785
786 /* wake up link */
787 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
788}
789
438ac6d5 790#ifdef CONFIG_PM
4447d351 791static void ahci_power_down(struct ata_port *ap)
0be0aa98 792{
4447d351
TH		 793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 795 u32 cmd, scontrol;
796
4447d351 797 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 798 return;
0be0aa98 799
07c53dac
TH		 800 /* put device into listen mode, first set PxSCTL.DET to 0 */
801 scontrol = readl(port_mmio + PORT_SCR_CTL);
802 scontrol &= ~0xf;
803 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 804
07c53dac
TH		 805 /* then set PxCMD.SUD to 0 */
806 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
807 cmd &= ~PORT_CMD_SPIN_UP;
808 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 809}
438ac6d5 810#endif
0be0aa98 811
df69c9c5 812static void ahci_start_port(struct ata_port *ap)
0be0aa98 813{
0be0aa98 814 /* enable FIS reception */
4447d351 815 ahci_start_fis_rx(ap);
0be0aa98
TH		 816
817 /* enable DMA */
4447d351 818 ahci_start_engine(ap);
0be0aa98
TH		 819}
820
4447d351 821static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 822{
823 int rc;
824
825 /* disable DMA */
4447d351 826 rc = ahci_stop_engine(ap);
0be0aa98
TH		 827 if (rc) {
828 *emsg = "failed to stop engine";
829 return rc;
830 }
831
832 /* disable FIS reception */
4447d351 833 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 834 if (rc) {
835 *emsg = "failed stop FIS RX";
836 return rc;
837 }
838
0be0aa98
TH		 839 return 0;
840}
841
4447d351 842static int ahci_reset_controller(struct ata_host *host)
d91542c1 843{
4447d351
TH		 844 struct pci_dev *pdev = to_pci_dev(host->dev);
845 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 846 u32 tmp;
d91542c1 847
3cc3eb11
JG		 848 /* we must be in AHCI mode, before using anything
849 * AHCI-specific, such as HOST_RESET.
850 */
d91542c1 851 tmp = readl(mmio + HOST_CTL);
3cc3eb11
JG		 852 if (!(tmp & HOST_AHCI_EN))
853 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
854
855 /* global controller reset */
d91542c1
TH		 856 if ((tmp & HOST_RESET) == 0) {
857 writel(tmp | HOST_RESET, mmio + HOST_CTL);
858 readl(mmio + HOST_CTL); /* flush */
859 }
860
861 /* reset must complete within 1 second, or
862 * the hardware should be considered fried.
863 */
864 ssleep(1);
865
866 tmp = readl(mmio + HOST_CTL);
867 if (tmp & HOST_RESET) {
4447d351 868 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 869 "controller reset failed (0x%x)\n", tmp);
870 return -EIO;
871 }
872
98fa4b60 873 /* turn on AHCI mode */
d91542c1
TH		 874 writel(HOST_AHCI_EN, mmio + HOST_CTL);
875 (void) readl(mmio + HOST_CTL); /* flush */
98fa4b60 876
d447df14 877 /* some registers might be cleared on reset. restore initial values */
4447d351 878 ahci_restore_initial_config(host);
d91542c1
TH		 879
880 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
881 u16 tmp16;
882
883 /* configure PCS */
884 pci_read_config_word(pdev, 0x92, &tmp16);
885 tmp16 |= 0xf;
886 pci_write_config_word(pdev, 0x92, tmp16);
887 }
888
889 return 0;
890}
891
2bcd866b
JG		 892static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
893 int port_no, void __iomem *mmio,
894 void __iomem *port_mmio)
895{
896 const char *emsg = NULL;
897 int rc;
898 u32 tmp;
899
900 /* make sure port is not active */
901 rc = ahci_deinit_port(ap, &emsg);
902 if (rc)
903 dev_printk(KERN_WARNING, &pdev->dev,
904 "%s (%d)\n", emsg, rc);
905
906 /* clear SError */
907 tmp = readl(port_mmio + PORT_SCR_ERR);
908 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
909 writel(tmp, port_mmio + PORT_SCR_ERR);
910
911 /* clear port IRQ */
912 tmp = readl(port_mmio + PORT_IRQ_STAT);
913 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
914 if (tmp)
915 writel(tmp, port_mmio + PORT_IRQ_STAT);
916
917 writel(1 << port_no, mmio + HOST_IRQ_STAT);
918}
919
4447d351 920static void ahci_init_controller(struct ata_host *host)
d91542c1 921{
4447d351
TH		 922 struct pci_dev *pdev = to_pci_dev(host->dev);
923 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 924 int i;
cd70c266 925 void __iomem *port_mmio;
d91542c1
TH		 926 u32 tmp;
927
cd70c266
JG		 928 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
929 port_mmio = __ahci_port_base(host, 4);
930
931 writel(0, port_mmio + PORT_IRQ_MASK);
932
933 /* clear port IRQ */
934 tmp = readl(port_mmio + PORT_IRQ_STAT);
935 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
936 if (tmp)
937 writel(tmp, port_mmio + PORT_IRQ_STAT);
938 }
939
4447d351
TH		 940 for (i = 0; i < host->n_ports; i++) {
941 struct ata_port *ap = host->ports[i];
d91542c1 942
cd70c266 943 port_mmio = ahci_port_base(ap);
4447d351 944 if (ata_port_is_dummy(ap))
d91542c1 945 continue;
d91542c1 946
2bcd866b 947 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 948 }
949
950 tmp = readl(mmio + HOST_CTL);
951 VPRINTK("HOST_CTL 0x%x\n", tmp);
952 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
953 tmp = readl(mmio + HOST_CTL);
954 VPRINTK("HOST_CTL 0x%x\n", tmp);
955}
956
422b7595 957static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 958{
4447d351 959 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 960 struct ata_taskfile tf;
422b7595
TH		 961 u32 tmp;
962
963 tmp = readl(port_mmio + PORT_SIG);
964 tf.lbah = (tmp >> 24) & 0xff;
965 tf.lbam = (tmp >> 16) & 0xff;
966 tf.lbal = (tmp >> 8) & 0xff;
967 tf.nsect = (tmp) & 0xff;
968
969 return ata_dev_classify(&tf);
970}
971
12fad3f9
TH		 972static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
973 u32 opts)
cc9278ed 974{
12fad3f9
TH		 975 dma_addr_t cmd_tbl_dma;
976
977 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
978
979 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
980 pp->cmd_slot[tag].status = 0;
981 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
982 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 983}
984
d2e75dff 985static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 986{
0d5ff566 987 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 988 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 989 u32 tmp;
d2e75dff 990 int busy, rc;
bf2af2a2 991
d2e75dff
TH		 992 /* do we need to kick the port? */
993 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
994 if (!busy && !force_restart)
995 return 0;
996
997 /* stop engine */
998 rc = ahci_stop_engine(ap);
999 if (rc)
1000 goto out_restart;
1001
1002 /* need to do CLO? */
1003 if (!busy) {
1004 rc = 0;
1005 goto out_restart;
1006 }
1007
1008 if (!(hpriv->cap & HOST_CAP_CLO)) {
1009 rc = -EOPNOTSUPP;
1010 goto out_restart;
1011 }
bf2af2a2 1012
d2e75dff 1013 /* perform CLO */
bf2af2a2
BJ		 1014 tmp = readl(port_mmio + PORT_CMD);
1015 tmp |= PORT_CMD_CLO;
1016 writel(tmp, port_mmio + PORT_CMD);
1017
d2e75dff 1018 rc = 0;
bf2af2a2
BJ		 1019 tmp = ata_wait_register(port_mmio + PORT_CMD,
1020 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1021 if (tmp & PORT_CMD_CLO)
d2e75dff 1022 rc = -EIO;
bf2af2a2 1023
d2e75dff
TH		 1024 /* restart engine */
1025 out_restart:
1026 ahci_start_engine(ap);
1027 return rc;
bf2af2a2
BJ		 1028}
1029
91c4a2e0
TH		 1030static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1031 struct ata_taskfile *tf, int is_cmd, u16 flags,
1032 unsigned long timeout_msec)
bf2af2a2 1033{
91c4a2e0 1034 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1035 struct ahci_port_priv *pp = ap->private_data;
4447d351 1036 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1037 u8 *fis = pp->cmd_tbl;
1038 u32 tmp;
1039
1040 /* prep the command */
1041 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1042 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1043
1044 /* issue & wait */
1045 writel(1, port_mmio + PORT_CMD_ISSUE);
1046
1047 if (timeout_msec) {
1048 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1049 1, timeout_msec);
1050 if (tmp & 0x1) {
1051 ahci_kick_engine(ap, 1);
1052 return -EBUSY;
1053 }
1054 } else
1055 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1056
1057 return 0;
1058}
1059
cc0680a5 1060static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1061 int pmp, unsigned long deadline)
91c4a2e0 1062{
cc0680a5 1063 struct ata_port *ap = link->ap;
4658f79b 1064 const char *reason = NULL;
2cbb79eb 1065 unsigned long now, msecs;
4658f79b 1066 struct ata_taskfile tf;
4658f79b
TH		 1067 int rc;
1068
1069 DPRINTK("ENTER\n");
1070
cc0680a5 1071 if (ata_link_offline(link)) {
c2a65852
TH		 1072 DPRINTK("PHY reports no device\n");
1073 *class = ATA_DEV_NONE;
1074 return 0;
1075 }
1076
4658f79b 1077 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff
TH		 1078 rc = ahci_kick_engine(ap, 1);
1079 if (rc)
cc0680a5 1080 ata_link_printk(link, KERN_WARNING,
d2e75dff 1081 "failed to reset engine (errno=%d)", rc);
4658f79b 1082
cc0680a5 1083 ata_tf_init(link->device, &tf);
4658f79b
TH		 1084
1085 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1086 msecs = 0;
1087 now = jiffies;
1088 if (time_after(now, deadline))
1089 msecs = jiffies_to_msecs(deadline - now);
1090
4658f79b 1091 tf.ctl |= ATA_SRST;
a9cf5e85 1092 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1093 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1094 rc = -EIO;
1095 reason = "1st FIS failed";
1096 goto fail;
1097 }
1098
1099 /* spec says at least 5us, but be generous and sleep for 1ms */
1100 msleep(1);
1101
1102 /* issue the second D2H Register FIS */
4658f79b 1103 tf.ctl &= ~ATA_SRST;
a9cf5e85 1104 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b
TH		 1105
1106 /* spec mandates ">= 2ms" before checking status.
1107 * We wait 150ms, because that was the magic delay used for
1108 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1109 * between when the ATA command register is written, and then
1110 * status is checked. Because waiting for "a while" before
1111 * checking status is fine, post SRST, we perform this magic
1112 * delay here as well.
1113 */
1114 msleep(150);
1115
9b89391c
TH		 1116 rc = ata_wait_ready(ap, deadline);
1117 /* link occupied, -ENODEV too is an error */
1118 if (rc) {
1119 reason = "device not ready";
1120 goto fail;
4658f79b 1121 }
9b89391c 1122 *class = ahci_dev_classify(ap);
4658f79b
TH		 1123
1124 DPRINTK("EXIT, class=%u\n", *class);
1125 return 0;
1126
4658f79b 1127 fail:
cc0680a5 1128 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1129 return rc;
1130}
1131
cc0680a5 1132static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1133 unsigned long deadline)
1134{
7d50b60b
TH		 1135 int pmp = 0;
1136
1137 if (link->ap->flags & ATA_FLAG_PMP)
1138 pmp = SATA_PMP_CTRL_PORT;
1139
1140 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1141}
1142
cc0680a5 1143static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1144 unsigned long deadline)
422b7595 1145{
cc0680a5 1146 struct ata_port *ap = link->ap;
4296971d
TH		 1147 struct ahci_port_priv *pp = ap->private_data;
1148 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1149 struct ata_taskfile tf;
4bd00f6a
TH		 1150 int rc;
1151
1152 DPRINTK("ENTER\n");
1da177e4 1153
4447d351 1154 ahci_stop_engine(ap);
4296971d
TH		 1155
1156 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1157 ata_tf_init(link->device, &tf);
dfd7a3db 1158 tf.command = 0x80;
9977126c 1159 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1160
cc0680a5 1161 rc = sata_std_hardreset(link, class, deadline);
4296971d 1162
4447d351 1163 ahci_start_engine(ap);
1da177e4 1164
cc0680a5 1165 if (rc == 0 && ata_link_online(link))
4bd00f6a 1166 *class = ahci_dev_classify(ap);
7d50b60b 1167 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1168 *class = ATA_DEV_NONE;
1da177e4 1169
4bd00f6a
TH		 1170 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1171 return rc;
1172}
1173
cc0680a5 1174static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1175 unsigned long deadline)
ad616ffb 1176{
cc0680a5 1177 struct ata_port *ap = link->ap;
da3dbb17 1178 u32 serror;
ad616ffb
TH		 1179 int rc;
1180
1181 DPRINTK("ENTER\n");
1182
4447d351 1183 ahci_stop_engine(ap);
ad616ffb 1184
cc0680a5 1185 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1186 deadline);
ad616ffb
TH		 1187
1188 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1189 ahci_scr_read(ap, SCR_ERROR, &serror);
1190 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1191
4447d351 1192 ahci_start_engine(ap);
ad616ffb
TH		 1193
1194 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1195
1196 /* vt8251 doesn't clear BSY on signature FIS reception,
1197 * request follow-up softreset.
1198 */
1199 return rc ?: -EAGAIN;
1200}
1201
cc0680a5 1202static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1203{
cc0680a5 1204 struct ata_port *ap = link->ap;
4447d351 1205 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1206 u32 new_tmp, tmp;
1207
cc0680a5 1208 ata_std_postreset(link, class);
02eaa666
JG		 1209
1210 /* Make sure port's ATAPI bit is set appropriately */
1211 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1212 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1213 new_tmp |= PORT_CMD_ATAPI;
1214 else
1215 new_tmp &= ~PORT_CMD_ATAPI;
1216 if (new_tmp != tmp) {
1217 writel(new_tmp, port_mmio + PORT_CMD);
1218 readl(port_mmio + PORT_CMD); /* flush */
1219 }
1da177e4
LT		 1220}
1221
7d50b60b
TH		 1222static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1223 unsigned long deadline)
1224{
1225 return ahci_do_softreset(link, class, link->pmp, deadline);
1226}
1227
1da177e4
LT		 1228static u8 ahci_check_status(struct ata_port *ap)
1229{
0d5ff566 1230 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1231
1232 return readl(mmio + PORT_TFDATA) & 0xFF;
1233}
1234
1da177e4
LT		 1235static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1236{
1237 struct ahci_port_priv *pp = ap->private_data;
1238 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1239
1240 ata_tf_from_fis(d2h_fis, tf);
1241}
1242
12fad3f9 1243static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1244{
cedc9a47
JG		 1245 struct scatterlist *sg;
1246 struct ahci_sg *ahci_sg;
828d09de 1247 unsigned int n_sg = 0;
1da177e4
LT		 1248
1249 VPRINTK("ENTER\n");
1250
1251 /*
1252 * Next, the S/G list.
1253 */
12fad3f9 1254 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 1255 ata_for_each_sg(sg, qc) {
1256 dma_addr_t addr = sg_dma_address(sg);
1257 u32 sg_len = sg_dma_len(sg);
1258
1259 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1260 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1261 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 1262
cedc9a47 1263 ahci_sg++;
828d09de 1264 n_sg++;
1da177e4 1265 }
828d09de
JG		 1266
1267 return n_sg;
1da177e4
LT		 1268}
1269
1270static void ahci_qc_prep(struct ata_queued_cmd *qc)
1271{
a0ea7328
JG		 1272 struct ata_port *ap = qc->ap;
1273 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 1274 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 1275 void *cmd_tbl;
1da177e4
LT		 1276 u32 opts;
1277 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1278 unsigned int n_elem;
1da177e4 1279
1da177e4
LT		 1280 /*
1281 * Fill in command table information. First, the header,
1282 * a SATA Register - Host to Device command FIS.
1283 */
12fad3f9
TH		 1284 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1285
7d50b60b 1286 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1287 if (is_atapi) {
12fad3f9
TH		 1288 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1289 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1290 }
1da177e4 1291
cc9278ed
TH		 1292 n_elem = 0;
1293 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1294 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1295
cc9278ed
TH		 1296 /*
1297 * Fill in command slot information.
1298 */
7d50b60b 1299 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1300 if (qc->tf.flags & ATA_TFLAG_WRITE)
1301 opts |= AHCI_CMD_WRITE;
1302 if (is_atapi)
4b10e559 1303 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1304
12fad3f9 1305 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1306}
1307
78cd52d0 1308static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1309{
78cd52d0 1310 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1311 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1312 struct ata_link *link = NULL;
1313 struct ata_queued_cmd *active_qc;
1314 struct ata_eh_info *active_ehi;
78cd52d0 1315 u32 serror;
1da177e4 1316
7d50b60b
TH		 1317 /* determine active link */
1318 ata_port_for_each_link(link, ap)
1319 if (ata_link_active(link))
1320 break;
1321 if (!link)
1322 link = &ap->link;
1323
1324 active_qc = ata_qc_from_tag(ap, link->active_tag);
1325 active_ehi = &link->eh_info;
1326
1327 /* record irq stat */
1328 ata_ehi_clear_desc(host_ehi);
1329 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1330
78cd52d0 1331 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1332 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1333 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1334 host_ehi->serror |= serror;
78cd52d0 1335
41669553
TH		 1336 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1337 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1338 irq_stat &= ~PORT_IRQ_IF_ERR;
1339
55a61604 1340 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1341 /* If qc is active, charge it; otherwise, the active
1342 * link. There's no active qc on NCQ errors. It will
1343 * be determined by EH by reading log page 10h.
1344 */
1345 if (active_qc)
1346 active_qc->err_mask |= AC_ERR_DEV;
1347 else
1348 active_ehi->err_mask |= AC_ERR_DEV;
1349
55a61604 1350 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1351 host_ehi->serror &= ~SERR_INTERNAL;
1352 }
1353
1354 if (irq_stat & PORT_IRQ_UNK_FIS) {
1355 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1356
1357 active_ehi->err_mask |= AC_ERR_HSM;
1358 active_ehi->action |= ATA_EH_SOFTRESET;
1359 ata_ehi_push_desc(active_ehi,
1360 "unknown FIS %08x %08x %08x %08x" ,
1361 unk[0], unk[1], unk[2], unk[3]);
1362 }
1363
1364 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1365 active_ehi->err_mask |= AC_ERR_HSM;
1366 active_ehi->action |= ATA_EH_SOFTRESET;
1367 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1368 }
78cd52d0
TH		 1369
1370 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b
TH		 1371 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1372 host_ehi->action |= ATA_EH_SOFTRESET;
1373 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1374 }
1375
78cd52d0 1376 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b
TH		 1377 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1378 host_ehi->action |= ATA_EH_SOFTRESET;
1379 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1380 }
1da177e4 1381
78cd52d0 1382 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1383 ata_ehi_hotplugged(host_ehi);
1384 ata_ehi_push_desc(host_ehi, "%s",
1385 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1386 "connection status changed" : "PHY RDY changed");
1387 }
1388
78cd52d0 1389 /* okay, let's hand over to EH */
a72ec4ce 1390
78cd52d0
TH		 1391 if (irq_stat & PORT_IRQ_FREEZE)
1392 ata_port_freeze(ap);
1393 else
1394 ata_port_abort(ap);
1da177e4
LT		 1395}
1396
df69c9c5 1397static void ahci_port_intr(struct ata_port *ap)
1da177e4 1398{
4447d351 1399 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1400 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1401 struct ahci_port_priv *pp = ap->private_data;
12fad3f9 1402 u32 status, qc_active;
0291f95f 1403 int rc, known_irq = 0;
1da177e4
LT		 1404
1405 status = readl(port_mmio + PORT_IRQ_STAT);
1406 writel(status, port_mmio + PORT_IRQ_STAT);
1407
78cd52d0
TH		 1408 if (unlikely(status & PORT_IRQ_ERROR)) {
1409 ahci_error_intr(ap, status);
1410 return;
1da177e4
LT		 1411 }
1412
2f294968 1413 if (status & PORT_IRQ_SDB_FIS) {
7d77b247
TH		 1414 /* If the 'N' bit in word 0 of the FIS is set, we just
1415 * received asynchronous notification. Tell libata
1416 * about it. Note that as the SDB FIS itself is
1417 * accessible, SNotification can be emulated by the
1418 * driver but don't bother for the time being.
2f294968
KCA		 1419 */
1420 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1421 u32 f0 = le32_to_cpu(f[0]);
1422
7d77b247
TH		 1423 if (f0 & (1 << 15))
1424 sata_async_notification(ap);
2f294968
KCA		 1425 }
1426
7d50b60b
TH		 1427 /* pp->active_link is valid iff any command is in flight */
1428 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1429 qc_active = readl(port_mmio + PORT_SCR_ACT);
1430 else
1431 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1432
1433 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1434 if (rc > 0)
1435 return;
1436 if (rc < 0) {
1437 ehi->err_mask |= AC_ERR_HSM;
1438 ehi->action |= ATA_EH_SOFTRESET;
1439 ata_port_freeze(ap);
1440 return;
1da177e4
LT		 1441 }
1442
2a3917a8
TH		 1443 /* hmmm... a spurious interupt */
1444
0291f95f
TH		 1445 /* if !NCQ, ignore. No modern ATA device has broken HSM
1446 * implementation for non-NCQ commands.
1447 */
9af5c9c9 1448 if (!ap->link.sactive)
12fad3f9
TH		 1449 return;
1450
0291f95f
TH		 1451 if (status & PORT_IRQ_D2H_REG_FIS) {
1452 if (!pp->ncq_saw_d2h)
1453 ata_port_printk(ap, KERN_INFO,
1454 "D2H reg with I during NCQ, "
1455 "this message won't be printed again\n");
1456 pp->ncq_saw_d2h = 1;
1457 known_irq = 1;
1458 }
1459
1460 if (status & PORT_IRQ_DMAS_FIS) {
1461 if (!pp->ncq_saw_dmas)
1462 ata_port_printk(ap, KERN_INFO,
1463 "DMAS FIS during NCQ, "
1464 "this message won't be printed again\n");
1465 pp->ncq_saw_dmas = 1;
1466 known_irq = 1;
1467 }
1468
a2bbd0c9 1469 if (status & PORT_IRQ_SDB_FIS) {
04d4f7a1 1470 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
0291f95f 1471
afb2d552
TH		 1472 if (le32_to_cpu(f[1])) {
1473 /* SDB FIS containing spurious completions
1474 * might be dangerous, whine and fail commands
1475 * with HSM violation. EH will turn off NCQ
1476 * after several such failures.
1477 */
1478 ata_ehi_push_desc(ehi,
1479 "spurious completions during NCQ "
1480 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1481 readl(port_mmio + PORT_CMD_ISSUE),
1482 readl(port_mmio + PORT_SCR_ACT),
1483 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1484 ehi->err_mask |= AC_ERR_HSM;
1485 ehi->action |= ATA_EH_SOFTRESET;
1486 ata_port_freeze(ap);
1487 } else {
1488 if (!pp->ncq_saw_sdb)
1489 ata_port_printk(ap, KERN_INFO,
1490 "spurious SDB FIS %08x:%08x during NCQ, "
1491 "this message won't be printed again\n",
1492 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1493 pp->ncq_saw_sdb = 1;
1494 }
0291f95f
TH		 1495 known_irq = 1;
1496 }
2a3917a8 1497
0291f95f 1498 if (!known_irq)
78cd52d0 1499 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
0291f95f 1500 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
9af5c9c9 1501 status, ap->link.active_tag, ap->link.sactive);
1da177e4
LT		 1502}
1503
1504static void ahci_irq_clear(struct ata_port *ap)
1505{
1506 /* TODO */
1507}
1508
7d12e780 1509static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1510{
cca3974e 1511 struct ata_host *host = dev_instance;
1da177e4
LT		 1512 struct ahci_host_priv *hpriv;
1513 unsigned int i, handled = 0;
ea6ba10b 1514 void __iomem *mmio;
1da177e4
LT		 1515 u32 irq_stat, irq_ack = 0;
1516
1517 VPRINTK("ENTER\n");
1518
cca3974e 1519 hpriv = host->private_data;
0d5ff566 1520 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1521
1522 /* sigh. 0xffffffff is a valid return from h/w */
1523 irq_stat = readl(mmio + HOST_IRQ_STAT);
1524 irq_stat &= hpriv->port_map;
1525 if (!irq_stat)
1526 return IRQ_NONE;
1527
cca3974e 1528 spin_lock(&host->lock);
1da177e4 1529
cca3974e 1530 for (i = 0; i < host->n_ports; i++) {
1da177e4 1531 struct ata_port *ap;
1da177e4 1532
67846b30
JG		 1533 if (!(irq_stat & (1 << i)))
1534 continue;
1535
cca3974e 1536 ap = host->ports[i];
67846b30 1537 if (ap) {
df69c9c5 1538 ahci_port_intr(ap);
67846b30
JG		 1539 VPRINTK("port %u\n", i);
1540 } else {
1541 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1542 if (ata_ratelimit())
cca3974e 1543 dev_printk(KERN_WARNING, host->dev,
a9524a76 1544 "interrupt on disabled port %u\n", i);
1da177e4 1545 }
67846b30
JG		 1546
1547 irq_ack |= (1 << i);
1da177e4
LT		 1548 }
1549
1550 if (irq_ack) {
1551 writel(irq_ack, mmio + HOST_IRQ_STAT);
1552 handled = 1;
1553 }
1554
cca3974e 1555 spin_unlock(&host->lock);
1da177e4
LT		 1556
1557 VPRINTK("EXIT\n");
1558
1559 return IRQ_RETVAL(handled);
1560}
1561
9a3d9eb0 1562static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1563{
1564 struct ata_port *ap = qc->ap;
4447d351 1565 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1566 struct ahci_port_priv *pp = ap->private_data;
1567
1568 /* Keep track of the currently active link. It will be used
1569 * in completion path to determine whether NCQ phase is in
1570 * progress.
1571 */
1572 pp->active_link = qc->dev->link;
1da177e4 1573
12fad3f9
TH		 1574 if (qc->tf.protocol == ATA_PROT_NCQ)
1575 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1576 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1577 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1578
1579 return 0;
1580}
1581
78cd52d0
TH		 1582static void ahci_freeze(struct ata_port *ap)
1583{
4447d351 1584 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1585
1586 /* turn IRQ off */
1587 writel(0, port_mmio + PORT_IRQ_MASK);
1588}
1589
1590static void ahci_thaw(struct ata_port *ap)
1591{
0d5ff566 1592 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1593 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1594 u32 tmp;
a7384925 1595 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1596
1597 /* clear IRQ */
1598 tmp = readl(port_mmio + PORT_IRQ_STAT);
1599 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1600 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1601
7d50b60b
TH		 1602 /* turn IRQ back on, ignore BAD_PMP if PMP isn't attached */
1603 tmp = pp->intr_mask;
1604 if (!ap->nr_pmp_links)
1605 tmp &= ~PORT_IRQ_BAD_PMP;
1606 writel(tmp, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1607}
1608
1609static void ahci_error_handler(struct ata_port *ap)
1610{
b51e9e5d 1611 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1612 /* restart engine */
4447d351
TH		 1613 ahci_stop_engine(ap);
1614 ahci_start_engine(ap);
78cd52d0
TH		 1615 }
1616
1617 /* perform recovery */
7d50b60b
TH		 1618 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1619 ahci_hardreset, ahci_postreset,
1620 sata_pmp_std_prereset, ahci_pmp_softreset,
1621 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1622}
1623
ad616ffb
TH		 1624static void ahci_vt8251_error_handler(struct ata_port *ap)
1625{
ad616ffb
TH		 1626 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1627 /* restart engine */
4447d351
TH		 1628 ahci_stop_engine(ap);
1629 ahci_start_engine(ap);
ad616ffb
TH		 1630 }
1631
1632 /* perform recovery */
1633 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1634 ahci_postreset);
1635}
1636
78cd52d0
TH		 1637static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1638{
1639 struct ata_port *ap = qc->ap;
1640
d2e75dff
TH		 1641 /* make DMA engine forget about the failed command */
1642 if (qc->flags & ATA_QCFLAG_FAILED)
1643 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1644}
1645
7d50b60b
TH		 1646static void ahci_pmp_attach(struct ata_port *ap)
1647{
1648 void __iomem *port_mmio = ahci_port_base(ap);
1649 u32 cmd;
1650
1651 cmd = readl(port_mmio + PORT_CMD);
1652 cmd |= PORT_CMD_PMP;
1653 writel(cmd, port_mmio + PORT_CMD);
1654}
1655
1656static void ahci_pmp_detach(struct ata_port *ap)
1657{
1658 void __iomem *port_mmio = ahci_port_base(ap);
1659 struct ahci_host_priv *hpriv = ap->host->private_data;
1660 unsigned long flags;
1661 u32 cmd;
1662
1663 cmd = readl(port_mmio + PORT_CMD);
1664 cmd &= ~PORT_CMD_PMP;
1665 writel(cmd, port_mmio + PORT_CMD);
1666
1667 if (hpriv->cap & HOST_CAP_NCQ) {
1668 spin_lock_irqsave(ap->lock, flags);
1669 ap->flags |= ATA_FLAG_NCQ;
1670 spin_unlock_irqrestore(ap->lock, flags);
1671 }
1672}
1673
1674static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
1675{
1676 struct ata_port *ap = dev->link->ap;
1677 struct ata_taskfile tf;
1678 int rc;
1679
1680 ahci_kick_engine(ap, 0);
1681
1682 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
1683 rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1684 SATA_PMP_SCR_TIMEOUT);
1685 if (rc == 0) {
1686 ahci_tf_read(ap, &tf);
1687 *r_val = sata_pmp_read_val(&tf);
1688 }
1689 return rc;
1690}
1691
1692static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
1693{
1694 struct ata_port *ap = dev->link->ap;
1695 struct ata_taskfile tf;
1696
1697 ahci_kick_engine(ap, 0);
1698
1699 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
1700 return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1701 SATA_PMP_SCR_TIMEOUT);
1702}
1703
028a2596
AD		 1704static int ahci_port_resume(struct ata_port *ap)
1705{
1706 ahci_power_up(ap);
1707 ahci_start_port(ap);
1708
7d50b60b
TH		 1709 if (ap->nr_pmp_links)
1710 ahci_pmp_attach(ap);
1711 else
1712 ahci_pmp_detach(ap);
1713
028a2596
AD		 1714 return 0;
1715}
1716
438ac6d5 1717#ifdef CONFIG_PM
c1332875
TH		 1718static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1719{
c1332875
TH		 1720 const char *emsg = NULL;
1721 int rc;
1722
4447d351 1723 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1724 if (rc == 0)
4447d351 1725 ahci_power_down(ap);
8e16f941 1726 else {
c1332875 1727 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1728 ahci_start_port(ap);
c1332875
TH		 1729 }
1730
1731 return rc;
1732}
1733
c1332875
TH		 1734static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1735{
cca3974e 1736 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1737 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1738 u32 ctl;
1739
1740 if (mesg.event == PM_EVENT_SUSPEND) {
1741 /* AHCI spec rev1.1 section 8.3.3:
1742 * Software must disable interrupts prior to requesting a
1743 * transition of the HBA to D3 state.
1744 */
1745 ctl = readl(mmio + HOST_CTL);
1746 ctl &= ~HOST_IRQ_EN;
1747 writel(ctl, mmio + HOST_CTL);
1748 readl(mmio + HOST_CTL); /* flush */
1749 }
1750
1751 return ata_pci_device_suspend(pdev, mesg);
1752}
1753
1754static int ahci_pci_device_resume(struct pci_dev *pdev)
1755{
cca3974e 1756 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1757 int rc;
1758
553c4aa6
TH		 1759 rc = ata_pci_device_do_resume(pdev);
1760 if (rc)
1761 return rc;
c1332875
TH		 1762
1763 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 1764 rc = ahci_reset_controller(host);
c1332875
TH		 1765 if (rc)
1766 return rc;
1767
4447d351 1768 ahci_init_controller(host);
c1332875
TH		 1769 }
1770
cca3974e 1771 ata_host_resume(host);
c1332875
TH		 1772
1773 return 0;
1774}
438ac6d5 1775#endif
c1332875 1776
254950cd
TH		 1777static int ahci_port_start(struct ata_port *ap)
1778{
cca3974e 1779 struct device *dev = ap->host->dev;
254950cd 1780 struct ahci_port_priv *pp;
254950cd
TH		 1781 void *mem;
1782 dma_addr_t mem_dma;
1783 int rc;
1784
24dc5f33 1785 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 1786 if (!pp)
1787 return -ENOMEM;
254950cd
TH		 1788
1789 rc = ata_pad_alloc(ap, dev);
24dc5f33 1790 if (rc)
254950cd 1791 return rc;
254950cd 1792
24dc5f33
TH		 1793 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1794 GFP_KERNEL);
1795 if (!mem)
254950cd 1796 return -ENOMEM;
254950cd
TH		 1797 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1798
1799 /*
1800 * First item in chunk of DMA memory: 32-slot command table,
1801 * 32 bytes each in size
1802 */
1803 pp->cmd_slot = mem;
1804 pp->cmd_slot_dma = mem_dma;
1805
1806 mem += AHCI_CMD_SLOT_SZ;
1807 mem_dma += AHCI_CMD_SLOT_SZ;
1808
1809 /*
1810 * Second item: Received-FIS area
1811 */
1812 pp->rx_fis = mem;
1813 pp->rx_fis_dma = mem_dma;
1814
1815 mem += AHCI_RX_FIS_SZ;
1816 mem_dma += AHCI_RX_FIS_SZ;
1817
1818 /*
1819 * Third item: data area for storing a single command
1820 * and its scatter-gather table
1821 */
1822 pp->cmd_tbl = mem;
1823 pp->cmd_tbl_dma = mem_dma;
1824
a7384925
KCA		 1825 /*
1826 * Save off initial list of interrupts to be enabled.
1827 * This could be changed later
1828 */
1829 pp->intr_mask = DEF_PORT_IRQ;
1830
254950cd
TH		 1831 ap->private_data = pp;
1832
df69c9c5
JG		 1833 /* engage engines, captain */
1834 return ahci_port_resume(ap);
254950cd
TH		 1835}
1836
1837static void ahci_port_stop(struct ata_port *ap)
1838{
0be0aa98
TH		 1839 const char *emsg = NULL;
1840 int rc;
254950cd 1841
0be0aa98 1842 /* de-initialize port */
4447d351 1843 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 1844 if (rc)
1845 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1846}
1847
4447d351 1848static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 1849{
1da177e4 1850 int rc;
1da177e4 1851
1da177e4
LT		 1852 if (using_dac &&
1853 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1854 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1855 if (rc) {
1856 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1857 if (rc) {
a9524a76
JG		 1858 dev_printk(KERN_ERR, &pdev->dev,
1859 "64-bit DMA enable failed\n");
1da177e4
LT		 1860 return rc;
1861 }
1862 }
1da177e4
LT		 1863 } else {
1864 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1865 if (rc) {
a9524a76
JG		 1866 dev_printk(KERN_ERR, &pdev->dev,
1867 "32-bit DMA enable failed\n");
1da177e4
LT		 1868 return rc;
1869 }
1870 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1871 if (rc) {
a9524a76
JG		 1872 dev_printk(KERN_ERR, &pdev->dev,
1873 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1874 return rc;
1875 }
1876 }
1da177e4
LT		 1877 return 0;
1878}
1879
4447d351 1880static void ahci_print_info(struct ata_host *host)
1da177e4 1881{
4447d351
TH		 1882 struct ahci_host_priv *hpriv = host->private_data;
1883 struct pci_dev *pdev = to_pci_dev(host->dev);
1884 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1885 u32 vers, cap, impl, speed;
1886 const char *speed_s;
1887 u16 cc;
1888 const char *scc_s;
1889
1890 vers = readl(mmio + HOST_VERSION);
1891 cap = hpriv->cap;
1892 impl = hpriv->port_map;
1893
1894 speed = (cap >> 20) & 0xf;
1895 if (speed == 1)
1896 speed_s = "1.5";
1897 else if (speed == 2)
1898 speed_s = "3";
1899 else
1900 speed_s = "?";
1901
1902 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 1903 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 1904 scc_s = "IDE";
c9f89475 1905 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 1906 scc_s = "SATA";
c9f89475 1907 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 1908 scc_s = "RAID";
1909 else
1910 scc_s = "unknown";
1911
a9524a76
JG		 1912 dev_printk(KERN_INFO, &pdev->dev,
1913 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1914 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1915 ,
1da177e4
LT		 1916
1917 (vers >> 24) & 0xff,
1918 (vers >> 16) & 0xff,
1919 (vers >> 8) & 0xff,
1920 vers & 0xff,
1921
1922 ((cap >> 8) & 0x1f) + 1,
1923 (cap & 0x1f) + 1,
1924 speed_s,
1925 impl,
1926 scc_s);
1927
a9524a76
JG		 1928 dev_printk(KERN_INFO, &pdev->dev,
1929 "flags: "
203ef6c4
TH		 1930 "%s%s%s%s%s%s%s"
1931 "%s%s%s%s%s%s%s\n"
1da177e4 1932 ,
1da177e4
LT		 1933
1934 cap & (1 << 31) ? "64bit " : "",
1935 cap & (1 << 30) ? "ncq " : "",
203ef6c4 1936 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 1937 cap & (1 << 28) ? "ilck " : "",
1938 cap & (1 << 27) ? "stag " : "",
1939 cap & (1 << 26) ? "pm " : "",
1940 cap & (1 << 25) ? "led " : "",
1941
1942 cap & (1 << 24) ? "clo " : "",
1943 cap & (1 << 19) ? "nz " : "",
1944 cap & (1 << 18) ? "only " : "",
1945 cap & (1 << 17) ? "pmp " : "",
1946 cap & (1 << 15) ? "pio " : "",
1947 cap & (1 << 14) ? "slum " : "",
1948 cap & (1 << 13) ? "part " : ""
1949 );
1950}
1951
24dc5f33 1952static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1953{
1954 static int printed_version;
4447d351
TH		 1955 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1956 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1957 struct device *dev = &pdev->dev;
1da177e4 1958 struct ahci_host_priv *hpriv;
4447d351
TH		 1959 struct ata_host *host;
1960 int i, rc;
1da177e4
LT		 1961
1962 VPRINTK("ENTER\n");
1963
12fad3f9
TH		 1964 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1965
1da177e4 1966 if (!printed_version++)
a9524a76 1967 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1968
4447d351 1969 /* acquire resources */
24dc5f33 1970 rc = pcim_enable_device(pdev);
1da177e4
LT		 1971 if (rc)
1972 return rc;
1973
0d5ff566
TH		 1974 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1975 if (rc == -EBUSY)
24dc5f33 1976 pcim_pin_device(pdev);
0d5ff566 1977 if (rc)
24dc5f33 1978 return rc;
1da177e4 1979
cd70c266 1980 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
907f4678 1981 pci_intx(pdev, 1);
1da177e4 1982
24dc5f33
TH		 1983 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1984 if (!hpriv)
1985 return -ENOMEM;
1da177e4 1986
4447d351
TH		 1987 /* save initial config */
1988 ahci_save_initial_config(pdev, &pi, hpriv);
1da177e4 1989
4447d351 1990 /* prepare host */
274c1fde 1991 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 1992 pi.flags |= ATA_FLAG_NCQ;
1da177e4 1993
7d50b60b
TH		 1994 if (hpriv->cap & HOST_CAP_PMP)
1995 pi.flags |= ATA_FLAG_PMP;
1996
4447d351
TH		 1997 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1998 if (!host)
1999 return -ENOMEM;
2000 host->iomap = pcim_iomap_table(pdev);
2001 host->private_data = hpriv;
2002
2003 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2004 struct ata_port *ap = host->ports[i];
2005 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2006
cbcdd875
TH		 2007 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2008 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2009 0x100 + ap->port_no * 0x80, "port");
2010
dab632e8 2011 /* standard SATA port setup */
203ef6c4 2012 if (hpriv->port_map & (1 << i))
4447d351 2013 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2014
2015 /* disabled/not-implemented port */
2016 else
2017 ap->ops = &ata_dummy_port_ops;
4447d351 2018 }
d447df14 2019
4447d351
TH		 2020 /* initialize adapter */
2021 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2022 if (rc)
24dc5f33 2023 return rc;
1da177e4 2024
4447d351
TH		 2025 rc = ahci_reset_controller(host);
2026 if (rc)
2027 return rc;
1da177e4 2028
4447d351
TH		 2029 ahci_init_controller(host);
2030 ahci_print_info(host);
1da177e4 2031
4447d351
TH		 2032 pci_set_master(pdev);
2033 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2034 &ahci_sht);
907f4678 2035}
1da177e4
LT		 2036
2037static int __init ahci_init(void)
2038{
b7887196 2039 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2040}
2041
1da177e4
LT		 2042static void __exit ahci_exit(void)
2043{
2044 pci_unregister_driver(&ahci_pci_driver);
2045}
2046
2047
2048MODULE_AUTHOR("Jeff Garzik");
2049MODULE_DESCRIPTION("AHCI SATA low-level driver");
2050MODULE_LICENSE("GPL");
2051MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2052MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2053
2054module_init(ahci_init);
2055module_exit(ahci_exit);
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